1 /*
2  * Copyright 2022 Advanced Micro Devices, Inc.
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice shall be included in
12  * all copies or substantial portions of the Software.
13  *
14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20  * OTHER DEALINGS IN THE SOFTWARE.
21  *
22  * Authors: AMD
23  *
24  */
25 
26 #include "dcn32_optc.h"
27 
28 #include "dcn30/dcn30_optc.h"
29 #include "dcn31/dcn31_optc.h"
30 #include "reg_helper.h"
31 #include "dc.h"
32 #include "dcn_calc_math.h"
33 #include "dc_dmub_srv.h"
34 
35 #define REG(reg)\
36 	optc1->tg_regs->reg
37 
38 #define CTX \
39 	optc1->base.ctx
40 
41 #undef FN
42 #define FN(reg_name, field_name) \
43 	optc1->tg_shift->field_name, optc1->tg_mask->field_name
44 
45 static void optc32_set_odm_combine(struct timing_generator *optc, int *opp_id, int opp_cnt,
46 		struct dc_crtc_timing *timing)
47 {
48 	struct optc *optc1 = DCN10TG_FROM_TG(optc);
49 	uint32_t memory_mask = 0;
50 	int h_active = timing->h_addressable + timing->h_border_left + timing->h_border_right;
51 	int mpcc_hactive = h_active / opp_cnt;
52 	/* Each memory instance is 2048x(32x2) bits to support half line of 4096 */
53 	int odm_mem_count = (h_active + 2047) / 2048;
54 
55 	/*
56 	 * display <= 4k : 2 memories + 2 pipes
57 	 * 4k < display <= 8k : 4 memories + 2 pipes
58 	 * 8k < display <= 12k : 6 memories + 4 pipes
59 	 */
60 	if (opp_cnt == 4) {
61 		if (odm_mem_count <= 2)
62 			memory_mask = 0x3;
63 		else if (odm_mem_count <= 4)
64 			memory_mask = 0xf;
65 		else
66 			memory_mask = 0x3f;
67 	} else {
68 		if (odm_mem_count <= 2)
69 			memory_mask = 0x1 << (opp_id[0] * 2) | 0x1 << (opp_id[1] * 2);
70 		else if (odm_mem_count <= 4)
71 			memory_mask = 0x3 << (opp_id[0] * 2) | 0x3 << (opp_id[1] * 2);
72 		else
73 			memory_mask = 0x77;
74 	}
75 
76 	REG_SET(OPTC_MEMORY_CONFIG, 0,
77 		OPTC_MEM_SEL, memory_mask);
78 
79 	if (opp_cnt == 2) {
80 		REG_SET_3(OPTC_DATA_SOURCE_SELECT, 0,
81 				OPTC_NUM_OF_INPUT_SEGMENT, 1,
82 				OPTC_SEG0_SRC_SEL, opp_id[0],
83 				OPTC_SEG1_SRC_SEL, opp_id[1]);
84 	} else if (opp_cnt == 4) {
85 		REG_SET_5(OPTC_DATA_SOURCE_SELECT, 0,
86 				OPTC_NUM_OF_INPUT_SEGMENT, 3,
87 				OPTC_SEG0_SRC_SEL, opp_id[0],
88 				OPTC_SEG1_SRC_SEL, opp_id[1],
89 				OPTC_SEG2_SRC_SEL, opp_id[2],
90 				OPTC_SEG3_SRC_SEL, opp_id[3]);
91 	}
92 
93 	REG_UPDATE(OPTC_WIDTH_CONTROL,
94 			OPTC_SEGMENT_WIDTH, mpcc_hactive);
95 
96 	REG_UPDATE(OTG_H_TIMING_CNTL,
97 			OTG_H_TIMING_DIV_MODE, opp_cnt - 1);
98 	optc1->opp_count = opp_cnt;
99 }
100 
101 void optc32_set_h_timing_div_manual_mode(struct timing_generator *optc, bool manual_mode)
102 {
103 	struct optc *optc1 = DCN10TG_FROM_TG(optc);
104 
105 	REG_UPDATE(OTG_H_TIMING_CNTL,
106 			OTG_H_TIMING_DIV_MODE_MANUAL, manual_mode ? 1 : 0);
107 }
108 /**
109  * optc32_enable_crtc() - Enable CRTC - call ASIC Control Object to enable Timing generator.
110  *
111  * @optc: timing_generator instance.
112  *
113  * Return: If CRTC is enabled, return true.
114  */
115 static bool optc32_enable_crtc(struct timing_generator *optc)
116 {
117 	struct optc *optc1 = DCN10TG_FROM_TG(optc);
118 
119 	/* opp instance for OTG, 1 to 1 mapping and odm will adjust */
120 	REG_UPDATE(OPTC_DATA_SOURCE_SELECT,
121 			OPTC_SEG0_SRC_SEL, optc->inst);
122 
123 	/* VTG enable first is for HW workaround */
124 	REG_UPDATE(CONTROL,
125 			VTG0_ENABLE, 1);
126 
127 	REG_SEQ_START();
128 
129 	/* Enable CRTC */
130 	REG_UPDATE_2(OTG_CONTROL,
131 			OTG_DISABLE_POINT_CNTL, 2,
132 			OTG_MASTER_EN, 1);
133 
134 	REG_SEQ_SUBMIT();
135 	REG_SEQ_WAIT_DONE();
136 
137 	return true;
138 }
139 
140 /* disable_crtc */
141 static bool optc32_disable_crtc(struct timing_generator *optc)
142 {
143 	struct optc *optc1 = DCN10TG_FROM_TG(optc);
144 
145 	REG_UPDATE_5(OPTC_DATA_SOURCE_SELECT,
146 			OPTC_SEG0_SRC_SEL, 0xf,
147 			OPTC_SEG1_SRC_SEL, 0xf,
148 			OPTC_SEG2_SRC_SEL, 0xf,
149 			OPTC_SEG3_SRC_SEL, 0xf,
150 			OPTC_NUM_OF_INPUT_SEGMENT, 0);
151 
152 	REG_UPDATE(OPTC_MEMORY_CONFIG,
153 			OPTC_MEM_SEL, 0);
154 
155 	/* disable otg request until end of the first line
156 	 * in the vertical blank region
157 	 */
158 	REG_UPDATE(OTG_CONTROL,
159 			OTG_MASTER_EN, 0);
160 
161 	REG_UPDATE(CONTROL,
162 			VTG0_ENABLE, 0);
163 
164 	/* CRTC disabled, so disable  clock. */
165 	REG_WAIT(OTG_CLOCK_CONTROL,
166 			OTG_BUSY, 0,
167 			1, 150000);
168 
169 	return true;
170 }
171 
172 static void optc32_phantom_crtc_post_enable(struct timing_generator *optc)
173 {
174 	struct optc *optc1 = DCN10TG_FROM_TG(optc);
175 
176 	/* Disable immediately. */
177 	REG_UPDATE_2(OTG_CONTROL, OTG_DISABLE_POINT_CNTL, 0, OTG_MASTER_EN, 0);
178 
179 	/* CRTC disabled, so disable  clock. */
180 	REG_WAIT(OTG_CLOCK_CONTROL, OTG_BUSY, 0, 1, 100000);
181 }
182 
183 static void optc32_disable_phantom_otg(struct timing_generator *optc)
184 {
185 	struct optc *optc1 = DCN10TG_FROM_TG(optc);
186 
187 	REG_UPDATE_5(OPTC_DATA_SOURCE_SELECT,
188 			OPTC_SEG0_SRC_SEL, 0xf,
189 			OPTC_SEG1_SRC_SEL, 0xf,
190 			OPTC_SEG2_SRC_SEL, 0xf,
191 			OPTC_SEG3_SRC_SEL, 0xf,
192 			OPTC_NUM_OF_INPUT_SEGMENT, 0);
193 
194 	REG_UPDATE(OTG_CONTROL, OTG_MASTER_EN, 0);
195 }
196 
197 static void optc32_set_odm_bypass(struct timing_generator *optc,
198 		const struct dc_crtc_timing *dc_crtc_timing)
199 {
200 	struct optc *optc1 = DCN10TG_FROM_TG(optc);
201 	enum h_timing_div_mode h_div = H_TIMING_NO_DIV;
202 
203 	REG_SET_5(OPTC_DATA_SOURCE_SELECT, 0,
204 			OPTC_NUM_OF_INPUT_SEGMENT, 0,
205 			OPTC_SEG0_SRC_SEL, optc->inst,
206 			OPTC_SEG1_SRC_SEL, 0xf,
207 			OPTC_SEG2_SRC_SEL, 0xf,
208 			OPTC_SEG3_SRC_SEL, 0xf
209 			);
210 
211 	h_div = optc1_is_two_pixels_per_containter(dc_crtc_timing);
212 	REG_UPDATE(OTG_H_TIMING_CNTL,
213 			OTG_H_TIMING_DIV_MODE, h_div);
214 
215 	REG_SET(OPTC_MEMORY_CONFIG, 0,
216 			OPTC_MEM_SEL, 0);
217 	optc1->opp_count = 1;
218 }
219 
220 static void optc32_setup_manual_trigger(struct timing_generator *optc)
221 {
222 	struct optc *optc1 = DCN10TG_FROM_TG(optc);
223 	struct dc *dc = optc->ctx->dc;
224 
225 	if (dc->caps.dmub_caps.mclk_sw && !dc->debug.disable_fams)
226 		dc_dmub_srv_set_drr_manual_trigger_cmd(dc, optc->inst);
227 	else {
228 		/*
229 		 * MIN_MASK_EN is gone and MASK is now always enabled.
230 		 *
231 		 * To get it to it work with manual trigger we need to make sure
232 		 * we program the correct bit.
233 		 */
234 		REG_UPDATE_4(OTG_V_TOTAL_CONTROL,
235 				OTG_V_TOTAL_MIN_SEL, 1,
236 				OTG_V_TOTAL_MAX_SEL, 1,
237 				OTG_FORCE_LOCK_ON_EVENT, 0,
238 				OTG_SET_V_TOTAL_MIN_MASK, (1 << 1)); /* TRIGA */
239 	}
240 }
241 
242 static void optc32_set_drr(
243 	struct timing_generator *optc,
244 	const struct drr_params *params)
245 {
246 	struct optc *optc1 = DCN10TG_FROM_TG(optc);
247 
248 	if (params != NULL &&
249 		params->vertical_total_max > 0 &&
250 		params->vertical_total_min > 0) {
251 
252 		if (params->vertical_total_mid != 0) {
253 
254 			REG_SET(OTG_V_TOTAL_MID, 0,
255 				OTG_V_TOTAL_MID, params->vertical_total_mid - 1);
256 
257 			REG_UPDATE_2(OTG_V_TOTAL_CONTROL,
258 					OTG_VTOTAL_MID_REPLACING_MAX_EN, 1,
259 					OTG_VTOTAL_MID_FRAME_NUM,
260 					(uint8_t)params->vertical_total_mid_frame_num);
261 
262 		}
263 
264 		optc->funcs->set_vtotal_min_max(optc, params->vertical_total_min - 1, params->vertical_total_max - 1);
265 	}
266 
267 	optc32_setup_manual_trigger(optc);
268 }
269 
270 static struct timing_generator_funcs dcn32_tg_funcs = {
271 		.validate_timing = optc1_validate_timing,
272 		.program_timing = optc1_program_timing,
273 		.setup_vertical_interrupt0 = optc1_setup_vertical_interrupt0,
274 		.setup_vertical_interrupt1 = optc1_setup_vertical_interrupt1,
275 		.setup_vertical_interrupt2 = optc1_setup_vertical_interrupt2,
276 		.program_global_sync = optc1_program_global_sync,
277 		.enable_crtc = optc32_enable_crtc,
278 		.disable_crtc = optc32_disable_crtc,
279 		.phantom_crtc_post_enable = optc32_phantom_crtc_post_enable,
280 		.disable_phantom_crtc = optc32_disable_phantom_otg,
281 		/* used by enable_timing_synchronization. Not need for FPGA */
282 		.is_counter_moving = optc1_is_counter_moving,
283 		.get_position = optc1_get_position,
284 		.get_frame_count = optc1_get_vblank_counter,
285 		.get_scanoutpos = optc1_get_crtc_scanoutpos,
286 		.get_otg_active_size = optc1_get_otg_active_size,
287 		.set_early_control = optc1_set_early_control,
288 		/* used by enable_timing_synchronization. Not need for FPGA */
289 		.wait_for_state = optc1_wait_for_state,
290 		.set_blank_color = optc3_program_blank_color,
291 		.did_triggered_reset_occur = optc1_did_triggered_reset_occur,
292 		.triplebuffer_lock = optc3_triplebuffer_lock,
293 		.triplebuffer_unlock = optc2_triplebuffer_unlock,
294 		.enable_reset_trigger = optc1_enable_reset_trigger,
295 		.enable_crtc_reset = optc1_enable_crtc_reset,
296 		.disable_reset_trigger = optc1_disable_reset_trigger,
297 		.lock = optc3_lock,
298 		.unlock = optc1_unlock,
299 		.lock_doublebuffer_enable = optc3_lock_doublebuffer_enable,
300 		.lock_doublebuffer_disable = optc3_lock_doublebuffer_disable,
301 		.enable_optc_clock = optc1_enable_optc_clock,
302 		.set_drr = optc32_set_drr,
303 		.get_last_used_drr_vtotal = optc2_get_last_used_drr_vtotal,
304 		.set_vtotal_min_max = optc3_set_vtotal_min_max,
305 		.set_static_screen_control = optc1_set_static_screen_control,
306 		.program_stereo = optc1_program_stereo,
307 		.is_stereo_left_eye = optc1_is_stereo_left_eye,
308 		.tg_init = optc3_tg_init,
309 		.is_tg_enabled = optc1_is_tg_enabled,
310 		.is_optc_underflow_occurred = optc1_is_optc_underflow_occurred,
311 		.clear_optc_underflow = optc1_clear_optc_underflow,
312 		.setup_global_swap_lock = NULL,
313 		.get_crc = optc1_get_crc,
314 		.configure_crc = optc1_configure_crc,
315 		.set_dsc_config = optc3_set_dsc_config,
316 		.get_dsc_status = optc2_get_dsc_status,
317 		.set_dwb_source = NULL,
318 		.set_odm_bypass = optc32_set_odm_bypass,
319 		.set_odm_combine = optc32_set_odm_combine,
320 		.set_h_timing_div_manual_mode = optc32_set_h_timing_div_manual_mode,
321 		.get_optc_source = optc2_get_optc_source,
322 		.set_out_mux = optc3_set_out_mux,
323 		.set_drr_trigger_window = optc3_set_drr_trigger_window,
324 		.set_vtotal_change_limit = optc3_set_vtotal_change_limit,
325 		.set_gsl = optc2_set_gsl,
326 		.set_gsl_source_select = optc2_set_gsl_source_select,
327 		.set_vtg_params = optc1_set_vtg_params,
328 		.program_manual_trigger = optc2_program_manual_trigger,
329 		.setup_manual_trigger = optc2_setup_manual_trigger,
330 		.get_hw_timing = optc1_get_hw_timing,
331 };
332 
333 void dcn32_timing_generator_init(struct optc *optc1)
334 {
335 	optc1->base.funcs = &dcn32_tg_funcs;
336 
337 	optc1->max_h_total = optc1->tg_mask->OTG_H_TOTAL + 1;
338 	optc1->max_v_total = optc1->tg_mask->OTG_V_TOTAL + 1;
339 
340 	optc1->min_h_blank = 32;
341 	optc1->min_v_blank = 3;
342 	optc1->min_v_blank_interlace = 5;
343 	optc1->min_h_sync_width = 4;
344 	optc1->min_v_sync_width = 1;
345 }
346 
347