1235c6763SAurabindo Pillai /* 2235c6763SAurabindo Pillai * Copyright 2022 Advanced Micro Devices, Inc. 3235c6763SAurabindo Pillai * 4235c6763SAurabindo Pillai * Permission is hereby granted, free of charge, to any person obtaining a 5235c6763SAurabindo Pillai * copy of this software and associated documentation files (the "Software"), 6235c6763SAurabindo Pillai * to deal in the Software without restriction, including without limitation 7235c6763SAurabindo Pillai * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8235c6763SAurabindo Pillai * and/or sell copies of the Software, and to permit persons to whom the 9235c6763SAurabindo Pillai * Software is furnished to do so, subject to the following conditions: 10235c6763SAurabindo Pillai * 11235c6763SAurabindo Pillai * The above copyright notice and this permission notice shall be included in 12235c6763SAurabindo Pillai * all copies or substantial portions of the Software. 13235c6763SAurabindo Pillai * 14235c6763SAurabindo Pillai * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15235c6763SAurabindo Pillai * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16235c6763SAurabindo Pillai * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17235c6763SAurabindo Pillai * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18235c6763SAurabindo Pillai * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19235c6763SAurabindo Pillai * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20235c6763SAurabindo Pillai * OTHER DEALINGS IN THE SOFTWARE. 21235c6763SAurabindo Pillai * 22235c6763SAurabindo Pillai * Authors: AMD 23235c6763SAurabindo Pillai * 24235c6763SAurabindo Pillai */ 25235c6763SAurabindo Pillai 26235c6763SAurabindo Pillai #include "dcn32_optc.h" 27235c6763SAurabindo Pillai 28235c6763SAurabindo Pillai #include "dcn30/dcn30_optc.h" 29319568d7SAlvin Lee #include "dcn31/dcn31_optc.h" 30235c6763SAurabindo Pillai #include "reg_helper.h" 31235c6763SAurabindo Pillai #include "dc.h" 32235c6763SAurabindo Pillai #include "dcn_calc_math.h" 33319568d7SAlvin Lee #include "dc_dmub_srv.h" 34235c6763SAurabindo Pillai 35235c6763SAurabindo Pillai #define REG(reg)\ 36235c6763SAurabindo Pillai optc1->tg_regs->reg 37235c6763SAurabindo Pillai 38235c6763SAurabindo Pillai #define CTX \ 39235c6763SAurabindo Pillai optc1->base.ctx 40235c6763SAurabindo Pillai 41235c6763SAurabindo Pillai #undef FN 42235c6763SAurabindo Pillai #define FN(reg_name, field_name) \ 43235c6763SAurabindo Pillai optc1->tg_shift->field_name, optc1->tg_mask->field_name 44235c6763SAurabindo Pillai 45235c6763SAurabindo Pillai static void optc32_set_odm_combine(struct timing_generator *optc, int *opp_id, int opp_cnt, 46235c6763SAurabindo Pillai struct dc_crtc_timing *timing) 47235c6763SAurabindo Pillai { 48235c6763SAurabindo Pillai struct optc *optc1 = DCN10TG_FROM_TG(optc); 49235c6763SAurabindo Pillai uint32_t memory_mask = 0; 50235c6763SAurabindo Pillai int h_active = timing->h_addressable + timing->h_border_left + timing->h_border_right; 51235c6763SAurabindo Pillai int mpcc_hactive = h_active / opp_cnt; 52235c6763SAurabindo Pillai /* Each memory instance is 2048x(32x2) bits to support half line of 4096 */ 53235c6763SAurabindo Pillai int odm_mem_count = (h_active + 2047) / 2048; 54235c6763SAurabindo Pillai 55235c6763SAurabindo Pillai /* 56235c6763SAurabindo Pillai * display <= 4k : 2 memories + 2 pipes 57235c6763SAurabindo Pillai * 4k < display <= 8k : 4 memories + 2 pipes 58235c6763SAurabindo Pillai * 8k < display <= 12k : 6 memories + 4 pipes 59235c6763SAurabindo Pillai */ 60235c6763SAurabindo Pillai if (opp_cnt == 4) { 61235c6763SAurabindo Pillai if (odm_mem_count <= 2) 62235c6763SAurabindo Pillai memory_mask = 0x3; 63235c6763SAurabindo Pillai else if (odm_mem_count <= 4) 64235c6763SAurabindo Pillai memory_mask = 0xf; 65235c6763SAurabindo Pillai else 66235c6763SAurabindo Pillai memory_mask = 0x3f; 67235c6763SAurabindo Pillai } else { 68235c6763SAurabindo Pillai if (odm_mem_count <= 2) 69235c6763SAurabindo Pillai memory_mask = 0x1 << (opp_id[0] * 2) | 0x1 << (opp_id[1] * 2); 70235c6763SAurabindo Pillai else if (odm_mem_count <= 4) 71235c6763SAurabindo Pillai memory_mask = 0x3 << (opp_id[0] * 2) | 0x3 << (opp_id[1] * 2); 72235c6763SAurabindo Pillai else 73235c6763SAurabindo Pillai memory_mask = 0x77; 74235c6763SAurabindo Pillai } 75235c6763SAurabindo Pillai 76235c6763SAurabindo Pillai REG_SET(OPTC_MEMORY_CONFIG, 0, 77235c6763SAurabindo Pillai OPTC_MEM_SEL, memory_mask); 78235c6763SAurabindo Pillai 79235c6763SAurabindo Pillai if (opp_cnt == 2) { 80235c6763SAurabindo Pillai REG_SET_3(OPTC_DATA_SOURCE_SELECT, 0, 81235c6763SAurabindo Pillai OPTC_NUM_OF_INPUT_SEGMENT, 1, 82235c6763SAurabindo Pillai OPTC_SEG0_SRC_SEL, opp_id[0], 83235c6763SAurabindo Pillai OPTC_SEG1_SRC_SEL, opp_id[1]); 84235c6763SAurabindo Pillai } else if (opp_cnt == 4) { 85235c6763SAurabindo Pillai REG_SET_5(OPTC_DATA_SOURCE_SELECT, 0, 86235c6763SAurabindo Pillai OPTC_NUM_OF_INPUT_SEGMENT, 3, 87235c6763SAurabindo Pillai OPTC_SEG0_SRC_SEL, opp_id[0], 88235c6763SAurabindo Pillai OPTC_SEG1_SRC_SEL, opp_id[1], 89235c6763SAurabindo Pillai OPTC_SEG2_SRC_SEL, opp_id[2], 90235c6763SAurabindo Pillai OPTC_SEG3_SRC_SEL, opp_id[3]); 91235c6763SAurabindo Pillai } 92235c6763SAurabindo Pillai 93235c6763SAurabindo Pillai REG_UPDATE(OPTC_WIDTH_CONTROL, 94235c6763SAurabindo Pillai OPTC_SEGMENT_WIDTH, mpcc_hactive); 95235c6763SAurabindo Pillai 96d3dfceb5SAurabindo Pillai REG_UPDATE(OTG_H_TIMING_CNTL, 97d3dfceb5SAurabindo Pillai OTG_H_TIMING_DIV_MODE, opp_cnt - 1); 98235c6763SAurabindo Pillai optc1->opp_count = opp_cnt; 99235c6763SAurabindo Pillai } 100235c6763SAurabindo Pillai 101d3dfceb5SAurabindo Pillai static void optc32_set_h_timing_div_manual_mode(struct timing_generator *optc, bool manual_mode) 102d3dfceb5SAurabindo Pillai { 103d3dfceb5SAurabindo Pillai struct optc *optc1 = DCN10TG_FROM_TG(optc); 104d3dfceb5SAurabindo Pillai 105d3dfceb5SAurabindo Pillai REG_UPDATE(OTG_H_TIMING_CNTL, 106d3dfceb5SAurabindo Pillai OTG_H_TIMING_DIV_MODE_MANUAL, manual_mode ? 1 : 0); 107d3dfceb5SAurabindo Pillai } 108235c6763SAurabindo Pillai /** 109235c6763SAurabindo Pillai * Enable CRTC 110235c6763SAurabindo Pillai * Enable CRTC - call ASIC Control Object to enable Timing generator. 111235c6763SAurabindo Pillai */ 112235c6763SAurabindo Pillai static bool optc32_enable_crtc(struct timing_generator *optc) 113235c6763SAurabindo Pillai { 114235c6763SAurabindo Pillai struct optc *optc1 = DCN10TG_FROM_TG(optc); 115235c6763SAurabindo Pillai 116235c6763SAurabindo Pillai /* opp instance for OTG, 1 to 1 mapping and odm will adjust */ 117235c6763SAurabindo Pillai REG_UPDATE(OPTC_DATA_SOURCE_SELECT, 118235c6763SAurabindo Pillai OPTC_SEG0_SRC_SEL, optc->inst); 119235c6763SAurabindo Pillai 120235c6763SAurabindo Pillai /* VTG enable first is for HW workaround */ 121235c6763SAurabindo Pillai REG_UPDATE(CONTROL, 122235c6763SAurabindo Pillai VTG0_ENABLE, 1); 123235c6763SAurabindo Pillai 124235c6763SAurabindo Pillai REG_SEQ_START(); 125235c6763SAurabindo Pillai 126235c6763SAurabindo Pillai /* Enable CRTC */ 127235c6763SAurabindo Pillai REG_UPDATE_2(OTG_CONTROL, 128235c6763SAurabindo Pillai OTG_DISABLE_POINT_CNTL, 2, 129235c6763SAurabindo Pillai OTG_MASTER_EN, 1); 130235c6763SAurabindo Pillai 131235c6763SAurabindo Pillai REG_SEQ_SUBMIT(); 132235c6763SAurabindo Pillai REG_SEQ_WAIT_DONE(); 133235c6763SAurabindo Pillai 134235c6763SAurabindo Pillai return true; 135235c6763SAurabindo Pillai } 136235c6763SAurabindo Pillai 137235c6763SAurabindo Pillai /* disable_crtc */ 138235c6763SAurabindo Pillai static bool optc32_disable_crtc(struct timing_generator *optc) 139235c6763SAurabindo Pillai { 140235c6763SAurabindo Pillai struct optc *optc1 = DCN10TG_FROM_TG(optc); 141235c6763SAurabindo Pillai 142235c6763SAurabindo Pillai /* disable otg request until end of the first line 143235c6763SAurabindo Pillai * in the vertical blank region 144235c6763SAurabindo Pillai */ 145235c6763SAurabindo Pillai REG_UPDATE(OTG_CONTROL, 146235c6763SAurabindo Pillai OTG_MASTER_EN, 0); 147235c6763SAurabindo Pillai 148235c6763SAurabindo Pillai REG_UPDATE(CONTROL, 149235c6763SAurabindo Pillai VTG0_ENABLE, 0); 150235c6763SAurabindo Pillai 151235c6763SAurabindo Pillai /* CRTC disabled, so disable clock. */ 152235c6763SAurabindo Pillai REG_WAIT(OTG_CLOCK_CONTROL, 153235c6763SAurabindo Pillai OTG_BUSY, 0, 154235c6763SAurabindo Pillai 1, 100000); 155235c6763SAurabindo Pillai 156235c6763SAurabindo Pillai return true; 157235c6763SAurabindo Pillai } 158235c6763SAurabindo Pillai 159*04206ff0SJiapeng Chong static void optc32_phantom_crtc_post_enable(struct timing_generator *optc) 160235c6763SAurabindo Pillai { 161235c6763SAurabindo Pillai struct optc *optc1 = DCN10TG_FROM_TG(optc); 162235c6763SAurabindo Pillai 163235c6763SAurabindo Pillai /* Disable immediately. */ 164235c6763SAurabindo Pillai REG_UPDATE_2(OTG_CONTROL, OTG_DISABLE_POINT_CNTL, 0, OTG_MASTER_EN, 0); 165235c6763SAurabindo Pillai 166235c6763SAurabindo Pillai /* CRTC disabled, so disable clock. */ 167235c6763SAurabindo Pillai REG_WAIT(OTG_CLOCK_CONTROL, OTG_BUSY, 0, 1, 100000); 168235c6763SAurabindo Pillai } 169235c6763SAurabindo Pillai 170d3dfceb5SAurabindo Pillai static void optc32_set_odm_bypass(struct timing_generator *optc, 171d3dfceb5SAurabindo Pillai const struct dc_crtc_timing *dc_crtc_timing) 172d3dfceb5SAurabindo Pillai { 173d3dfceb5SAurabindo Pillai struct optc *optc1 = DCN10TG_FROM_TG(optc); 174d3dfceb5SAurabindo Pillai enum h_timing_div_mode h_div = H_TIMING_NO_DIV; 175d3dfceb5SAurabindo Pillai 176d3dfceb5SAurabindo Pillai REG_SET_5(OPTC_DATA_SOURCE_SELECT, 0, 177d3dfceb5SAurabindo Pillai OPTC_NUM_OF_INPUT_SEGMENT, 0, 178d3dfceb5SAurabindo Pillai OPTC_SEG0_SRC_SEL, optc->inst, 179d3dfceb5SAurabindo Pillai OPTC_SEG1_SRC_SEL, 0xf, 180d3dfceb5SAurabindo Pillai OPTC_SEG2_SRC_SEL, 0xf, 181d3dfceb5SAurabindo Pillai OPTC_SEG3_SRC_SEL, 0xf 182d3dfceb5SAurabindo Pillai ); 183d3dfceb5SAurabindo Pillai 184d3dfceb5SAurabindo Pillai h_div = optc1_is_two_pixels_per_containter(dc_crtc_timing); 185d3dfceb5SAurabindo Pillai REG_UPDATE(OTG_H_TIMING_CNTL, 186d3dfceb5SAurabindo Pillai OTG_H_TIMING_DIV_MODE, h_div); 187d3dfceb5SAurabindo Pillai 188d3dfceb5SAurabindo Pillai REG_SET(OPTC_MEMORY_CONFIG, 0, 189d3dfceb5SAurabindo Pillai OPTC_MEM_SEL, 0); 190d3dfceb5SAurabindo Pillai optc1->opp_count = 1; 191d3dfceb5SAurabindo Pillai } 192d3dfceb5SAurabindo Pillai 193*04206ff0SJiapeng Chong static void optc32_setup_manual_trigger(struct timing_generator *optc) 194319568d7SAlvin Lee { 195319568d7SAlvin Lee struct optc *optc1 = DCN10TG_FROM_TG(optc); 196319568d7SAlvin Lee struct dc *dc = optc->ctx->dc; 197319568d7SAlvin Lee 198319568d7SAlvin Lee if (dc->caps.dmub_caps.mclk_sw && !dc->debug.disable_fams) 199319568d7SAlvin Lee dc_dmub_srv_set_drr_manual_trigger_cmd(dc, optc->inst); 200319568d7SAlvin Lee else { 201319568d7SAlvin Lee /* 202319568d7SAlvin Lee * MIN_MASK_EN is gone and MASK is now always enabled. 203319568d7SAlvin Lee * 204319568d7SAlvin Lee * To get it to it work with manual trigger we need to make sure 205319568d7SAlvin Lee * we program the correct bit. 206319568d7SAlvin Lee */ 207319568d7SAlvin Lee REG_UPDATE_4(OTG_V_TOTAL_CONTROL, 208319568d7SAlvin Lee OTG_V_TOTAL_MIN_SEL, 1, 209319568d7SAlvin Lee OTG_V_TOTAL_MAX_SEL, 1, 210319568d7SAlvin Lee OTG_FORCE_LOCK_ON_EVENT, 0, 211319568d7SAlvin Lee OTG_SET_V_TOTAL_MIN_MASK, (1 << 1)); /* TRIGA */ 212319568d7SAlvin Lee 213319568d7SAlvin Lee // Setup manual flow control for EOF via TRIG_A 214319568d7SAlvin Lee optc->funcs->setup_manual_trigger(optc); 215319568d7SAlvin Lee } 216319568d7SAlvin Lee } 217319568d7SAlvin Lee 218*04206ff0SJiapeng Chong static void optc32_set_drr( 219319568d7SAlvin Lee struct timing_generator *optc, 220319568d7SAlvin Lee const struct drr_params *params) 221319568d7SAlvin Lee { 222319568d7SAlvin Lee struct optc *optc1 = DCN10TG_FROM_TG(optc); 223319568d7SAlvin Lee 224319568d7SAlvin Lee if (params != NULL && 225319568d7SAlvin Lee params->vertical_total_max > 0 && 226319568d7SAlvin Lee params->vertical_total_min > 0) { 227319568d7SAlvin Lee 228319568d7SAlvin Lee if (params->vertical_total_mid != 0) { 229319568d7SAlvin Lee 230319568d7SAlvin Lee REG_SET(OTG_V_TOTAL_MID, 0, 231319568d7SAlvin Lee OTG_V_TOTAL_MID, params->vertical_total_mid - 1); 232319568d7SAlvin Lee 233319568d7SAlvin Lee REG_UPDATE_2(OTG_V_TOTAL_CONTROL, 234319568d7SAlvin Lee OTG_VTOTAL_MID_REPLACING_MAX_EN, 1, 235319568d7SAlvin Lee OTG_VTOTAL_MID_FRAME_NUM, 236319568d7SAlvin Lee (uint8_t)params->vertical_total_mid_frame_num); 237319568d7SAlvin Lee 238319568d7SAlvin Lee } 239319568d7SAlvin Lee 240319568d7SAlvin Lee optc->funcs->set_vtotal_min_max(optc, params->vertical_total_min - 1, params->vertical_total_max - 1); 241319568d7SAlvin Lee optc32_setup_manual_trigger(optc); 242319568d7SAlvin Lee } else { 243319568d7SAlvin Lee REG_UPDATE_4(OTG_V_TOTAL_CONTROL, 244319568d7SAlvin Lee OTG_SET_V_TOTAL_MIN_MASK, 0, 245319568d7SAlvin Lee OTG_V_TOTAL_MIN_SEL, 0, 246319568d7SAlvin Lee OTG_V_TOTAL_MAX_SEL, 0, 247319568d7SAlvin Lee OTG_FORCE_LOCK_ON_EVENT, 0); 248319568d7SAlvin Lee 249319568d7SAlvin Lee optc->funcs->set_vtotal_min_max(optc, 0, 0); 250319568d7SAlvin Lee } 251319568d7SAlvin Lee } 252235c6763SAurabindo Pillai 253235c6763SAurabindo Pillai static struct timing_generator_funcs dcn32_tg_funcs = { 254235c6763SAurabindo Pillai .validate_timing = optc1_validate_timing, 255235c6763SAurabindo Pillai .program_timing = optc1_program_timing, 256235c6763SAurabindo Pillai .setup_vertical_interrupt0 = optc1_setup_vertical_interrupt0, 257235c6763SAurabindo Pillai .setup_vertical_interrupt1 = optc1_setup_vertical_interrupt1, 258235c6763SAurabindo Pillai .setup_vertical_interrupt2 = optc1_setup_vertical_interrupt2, 259235c6763SAurabindo Pillai .program_global_sync = optc1_program_global_sync, 260235c6763SAurabindo Pillai .enable_crtc = optc32_enable_crtc, 261235c6763SAurabindo Pillai .disable_crtc = optc32_disable_crtc, 262235c6763SAurabindo Pillai .phantom_crtc_post_enable = optc32_phantom_crtc_post_enable, 263235c6763SAurabindo Pillai /* used by enable_timing_synchronization. Not need for FPGA */ 264235c6763SAurabindo Pillai .is_counter_moving = optc1_is_counter_moving, 265235c6763SAurabindo Pillai .get_position = optc1_get_position, 266235c6763SAurabindo Pillai .get_frame_count = optc1_get_vblank_counter, 267235c6763SAurabindo Pillai .get_scanoutpos = optc1_get_crtc_scanoutpos, 268235c6763SAurabindo Pillai .get_otg_active_size = optc1_get_otg_active_size, 269235c6763SAurabindo Pillai .set_early_control = optc1_set_early_control, 270235c6763SAurabindo Pillai /* used by enable_timing_synchronization. Not need for FPGA */ 271235c6763SAurabindo Pillai .wait_for_state = optc1_wait_for_state, 272235c6763SAurabindo Pillai .set_blank_color = optc3_program_blank_color, 273235c6763SAurabindo Pillai .did_triggered_reset_occur = optc1_did_triggered_reset_occur, 274235c6763SAurabindo Pillai .triplebuffer_lock = optc3_triplebuffer_lock, 275235c6763SAurabindo Pillai .triplebuffer_unlock = optc2_triplebuffer_unlock, 276235c6763SAurabindo Pillai .enable_reset_trigger = optc1_enable_reset_trigger, 277235c6763SAurabindo Pillai .enable_crtc_reset = optc1_enable_crtc_reset, 278235c6763SAurabindo Pillai .disable_reset_trigger = optc1_disable_reset_trigger, 279235c6763SAurabindo Pillai .lock = optc3_lock, 280235c6763SAurabindo Pillai .unlock = optc1_unlock, 281235c6763SAurabindo Pillai .lock_doublebuffer_enable = optc3_lock_doublebuffer_enable, 282235c6763SAurabindo Pillai .lock_doublebuffer_disable = optc3_lock_doublebuffer_disable, 283235c6763SAurabindo Pillai .enable_optc_clock = optc1_enable_optc_clock, 2849f5171ceSAlvin Lee .set_drr = optc32_set_drr, 285235c6763SAurabindo Pillai .get_last_used_drr_vtotal = optc2_get_last_used_drr_vtotal, 286bbb6e5aeSAlvin Lee .set_vtotal_min_max = optc3_set_vtotal_min_max, 287235c6763SAurabindo Pillai .set_static_screen_control = optc1_set_static_screen_control, 288235c6763SAurabindo Pillai .program_stereo = optc1_program_stereo, 289235c6763SAurabindo Pillai .is_stereo_left_eye = optc1_is_stereo_left_eye, 290235c6763SAurabindo Pillai .tg_init = optc3_tg_init, 291235c6763SAurabindo Pillai .is_tg_enabled = optc1_is_tg_enabled, 292235c6763SAurabindo Pillai .is_optc_underflow_occurred = optc1_is_optc_underflow_occurred, 293235c6763SAurabindo Pillai .clear_optc_underflow = optc1_clear_optc_underflow, 294235c6763SAurabindo Pillai .setup_global_swap_lock = NULL, 295235c6763SAurabindo Pillai .get_crc = optc1_get_crc, 296235c6763SAurabindo Pillai .configure_crc = optc1_configure_crc, 297235c6763SAurabindo Pillai .set_dsc_config = optc3_set_dsc_config, 298235c6763SAurabindo Pillai .get_dsc_status = optc2_get_dsc_status, 299235c6763SAurabindo Pillai .set_dwb_source = NULL, 300d3dfceb5SAurabindo Pillai .set_odm_bypass = optc32_set_odm_bypass, 301235c6763SAurabindo Pillai .set_odm_combine = optc32_set_odm_combine, 302d3dfceb5SAurabindo Pillai .set_h_timing_div_manual_mode = optc32_set_h_timing_div_manual_mode, 303235c6763SAurabindo Pillai .get_optc_source = optc2_get_optc_source, 304235c6763SAurabindo Pillai .set_out_mux = optc3_set_out_mux, 305235c6763SAurabindo Pillai .set_drr_trigger_window = optc3_set_drr_trigger_window, 306235c6763SAurabindo Pillai .set_vtotal_change_limit = optc3_set_vtotal_change_limit, 307235c6763SAurabindo Pillai .set_gsl = optc2_set_gsl, 308235c6763SAurabindo Pillai .set_gsl_source_select = optc2_set_gsl_source_select, 309235c6763SAurabindo Pillai .set_vtg_params = optc1_set_vtg_params, 310235c6763SAurabindo Pillai .program_manual_trigger = optc2_program_manual_trigger, 311235c6763SAurabindo Pillai .setup_manual_trigger = optc2_setup_manual_trigger, 312235c6763SAurabindo Pillai .get_hw_timing = optc1_get_hw_timing, 313235c6763SAurabindo Pillai }; 314235c6763SAurabindo Pillai 315235c6763SAurabindo Pillai void dcn32_timing_generator_init(struct optc *optc1) 316235c6763SAurabindo Pillai { 317235c6763SAurabindo Pillai optc1->base.funcs = &dcn32_tg_funcs; 318235c6763SAurabindo Pillai 319235c6763SAurabindo Pillai optc1->max_h_total = optc1->tg_mask->OTG_H_TOTAL + 1; 320235c6763SAurabindo Pillai optc1->max_v_total = optc1->tg_mask->OTG_V_TOTAL + 1; 321235c6763SAurabindo Pillai 322235c6763SAurabindo Pillai optc1->min_h_blank = 32; 323235c6763SAurabindo Pillai optc1->min_v_blank = 3; 324235c6763SAurabindo Pillai optc1->min_v_blank_interlace = 5; 325235c6763SAurabindo Pillai optc1->min_h_sync_width = 4; 326235c6763SAurabindo Pillai optc1->min_v_sync_width = 1; 327235c6763SAurabindo Pillai } 328235c6763SAurabindo Pillai 329