1 /* 2 * Copyright 2021 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #include "reg_helper.h" 27 #include "dcn30/dcn30_mpc.h" 28 #include "dcn30/dcn30_cm_common.h" 29 #include "dcn30/dcn30_mpc.h" 30 #include "basics/conversion.h" 31 #include "dcn10/dcn10_cm_common.h" 32 #include "dc.h" 33 34 #define REG(reg)\ 35 mpc30->mpc_regs->reg 36 37 #define CTX \ 38 mpc30->base.ctx 39 40 #undef FN 41 #define FN(reg_name, field_name) \ 42 mpc30->mpc_shift->field_name, mpc30->mpc_mask->field_name 43 44 45 static void mpc32_mpc_init(struct mpc *mpc) 46 { 47 struct dcn30_mpc *mpc30 = TO_DCN30_MPC(mpc); 48 int mpcc_id; 49 50 mpc1_mpc_init(mpc); 51 52 if (mpc->ctx->dc->debug.enable_mem_low_power.bits.mpc) { 53 if (mpc30->mpc_mask->MPCC_MCM_SHAPER_MEM_LOW_PWR_MODE && mpc30->mpc_mask->MPCC_MCM_3DLUT_MEM_LOW_PWR_MODE) { 54 for (mpcc_id = 0; mpcc_id < mpc30->num_mpcc; mpcc_id++) { 55 REG_UPDATE(MPCC_MCM_MEM_PWR_CTRL[mpcc_id], MPCC_MCM_SHAPER_MEM_LOW_PWR_MODE, 3); 56 REG_UPDATE(MPCC_MCM_MEM_PWR_CTRL[mpcc_id], MPCC_MCM_3DLUT_MEM_LOW_PWR_MODE, 3); 57 REG_UPDATE(MPCC_MCM_MEM_PWR_CTRL[mpcc_id], MPCC_MCM_1DLUT_MEM_LOW_PWR_MODE, 3); 58 } 59 } 60 if (mpc30->mpc_mask->MPCC_OGAM_MEM_LOW_PWR_MODE) { 61 for (mpcc_id = 0; mpcc_id < mpc30->num_mpcc; mpcc_id++) 62 REG_UPDATE(MPCC_MEM_PWR_CTRL[mpcc_id], MPCC_OGAM_MEM_LOW_PWR_MODE, 3); 63 } 64 } 65 } 66 67 68 static enum dc_lut_mode mpc32_get_shaper_current(struct mpc *mpc, uint32_t mpcc_id) 69 { 70 enum dc_lut_mode mode; 71 uint32_t state_mode; 72 struct dcn30_mpc *mpc30 = TO_DCN30_MPC(mpc); 73 74 REG_GET(MPCC_MCM_SHAPER_CONTROL[mpcc_id], 75 MPCC_MCM_SHAPER_MODE_CURRENT, &state_mode); 76 77 switch (state_mode) { 78 case 0: 79 mode = LUT_BYPASS; 80 break; 81 case 1: 82 mode = LUT_RAM_A; 83 break; 84 case 2: 85 mode = LUT_RAM_B; 86 break; 87 default: 88 mode = LUT_BYPASS; 89 break; 90 } 91 return mode; 92 } 93 94 95 static void mpc32_configure_shaper_lut( 96 struct mpc *mpc, 97 bool is_ram_a, 98 uint32_t mpcc_id) 99 { 100 struct dcn30_mpc *mpc30 = TO_DCN30_MPC(mpc); 101 102 REG_UPDATE(MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK[mpcc_id], 103 MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK, 7); 104 REG_UPDATE(MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK[mpcc_id], 105 MPCC_MCM_SHAPER_LUT_WRITE_SEL, is_ram_a == true ? 0:1); 106 REG_SET(MPCC_MCM_SHAPER_LUT_INDEX[mpcc_id], 0, MPCC_MCM_SHAPER_LUT_INDEX, 0); 107 } 108 109 110 static void mpc32_program_shaper_luta_settings( 111 struct mpc *mpc, 112 const struct pwl_params *params, 113 uint32_t mpcc_id) 114 { 115 const struct gamma_curve *curve; 116 struct dcn30_mpc *mpc30 = TO_DCN30_MPC(mpc); 117 118 REG_SET_2(MPCC_MCM_SHAPER_RAMA_START_CNTL_B[mpcc_id], 0, 119 MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_B, params->corner_points[0].blue.custom_float_x, 120 MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_B, 0); 121 REG_SET_2(MPCC_MCM_SHAPER_RAMA_START_CNTL_G[mpcc_id], 0, 122 MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_B, params->corner_points[0].green.custom_float_x, 123 MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_B, 0); 124 REG_SET_2(MPCC_MCM_SHAPER_RAMA_START_CNTL_R[mpcc_id], 0, 125 MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_B, params->corner_points[0].red.custom_float_x, 126 MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_B, 0); 127 128 REG_SET_2(MPCC_MCM_SHAPER_RAMA_END_CNTL_B[mpcc_id], 0, 129 MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_B, params->corner_points[1].blue.custom_float_x, 130 MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_BASE_B, params->corner_points[1].blue.custom_float_y); 131 REG_SET_2(MPCC_MCM_SHAPER_RAMA_END_CNTL_G[mpcc_id], 0, 132 MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_B, params->corner_points[1].green.custom_float_x, 133 MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_BASE_B, params->corner_points[1].green.custom_float_y); 134 REG_SET_2(MPCC_MCM_SHAPER_RAMA_END_CNTL_R[mpcc_id], 0, 135 MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_B, params->corner_points[1].red.custom_float_x, 136 MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_BASE_B, params->corner_points[1].red.custom_float_y); 137 138 curve = params->arr_curve_points; 139 REG_SET_4(MPCC_MCM_SHAPER_RAMA_REGION_0_1[mpcc_id], 0, 140 MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset, 141 MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num, 142 MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset, 143 MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num); 144 145 curve += 2; 146 REG_SET_4(MPCC_MCM_SHAPER_RAMA_REGION_2_3[mpcc_id], 0, 147 MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset, 148 MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num, 149 MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset, 150 MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num); 151 152 curve += 2; 153 REG_SET_4(MPCC_MCM_SHAPER_RAMA_REGION_4_5[mpcc_id], 0, 154 MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset, 155 MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num, 156 MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset, 157 MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num); 158 159 curve += 2; 160 REG_SET_4(MPCC_MCM_SHAPER_RAMA_REGION_6_7[mpcc_id], 0, 161 MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset, 162 MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num, 163 MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset, 164 MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num); 165 166 curve += 2; 167 REG_SET_4(MPCC_MCM_SHAPER_RAMA_REGION_8_9[mpcc_id], 0, 168 MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset, 169 MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num, 170 MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset, 171 MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num); 172 173 curve += 2; 174 REG_SET_4(MPCC_MCM_SHAPER_RAMA_REGION_10_11[mpcc_id], 0, 175 MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset, 176 MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num, 177 MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset, 178 MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num); 179 180 curve += 2; 181 REG_SET_4(MPCC_MCM_SHAPER_RAMA_REGION_12_13[mpcc_id], 0, 182 MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset, 183 MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num, 184 MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset, 185 MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num); 186 187 curve += 2; 188 REG_SET_4(MPCC_MCM_SHAPER_RAMA_REGION_14_15[mpcc_id], 0, 189 MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset, 190 MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num, 191 MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset, 192 MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num); 193 194 195 curve += 2; 196 REG_SET_4(MPCC_MCM_SHAPER_RAMA_REGION_16_17[mpcc_id], 0, 197 MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset, 198 MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num, 199 MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset, 200 MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num); 201 202 curve += 2; 203 REG_SET_4(MPCC_MCM_SHAPER_RAMA_REGION_18_19[mpcc_id], 0, 204 MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset, 205 MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num, 206 MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset, 207 MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num); 208 209 curve += 2; 210 REG_SET_4(MPCC_MCM_SHAPER_RAMA_REGION_20_21[mpcc_id], 0, 211 MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset, 212 MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num, 213 MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset, 214 MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num); 215 216 curve += 2; 217 REG_SET_4(MPCC_MCM_SHAPER_RAMA_REGION_22_23[mpcc_id], 0, 218 MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset, 219 MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num, 220 MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset, 221 MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num); 222 223 curve += 2; 224 REG_SET_4(MPCC_MCM_SHAPER_RAMA_REGION_24_25[mpcc_id], 0, 225 MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset, 226 MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num, 227 MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset, 228 MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num); 229 230 curve += 2; 231 REG_SET_4(MPCC_MCM_SHAPER_RAMA_REGION_26_27[mpcc_id], 0, 232 MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset, 233 MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num, 234 MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset, 235 MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num); 236 237 curve += 2; 238 REG_SET_4(MPCC_MCM_SHAPER_RAMA_REGION_28_29[mpcc_id], 0, 239 MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset, 240 MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num, 241 MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset, 242 MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num); 243 244 curve += 2; 245 REG_SET_4(MPCC_MCM_SHAPER_RAMA_REGION_30_31[mpcc_id], 0, 246 MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset, 247 MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num, 248 MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset, 249 MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num); 250 251 curve += 2; 252 REG_SET_4(MPCC_MCM_SHAPER_RAMA_REGION_32_33[mpcc_id], 0, 253 MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset, 254 MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num, 255 MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset, 256 MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num); 257 } 258 259 260 static void mpc32_program_shaper_lutb_settings( 261 struct mpc *mpc, 262 const struct pwl_params *params, 263 uint32_t mpcc_id) 264 { 265 const struct gamma_curve *curve; 266 struct dcn30_mpc *mpc30 = TO_DCN30_MPC(mpc); 267 268 REG_SET_2(MPCC_MCM_SHAPER_RAMB_START_CNTL_B[mpcc_id], 0, 269 MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_B, params->corner_points[0].blue.custom_float_x, 270 MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_B, 0); 271 REG_SET_2(MPCC_MCM_SHAPER_RAMB_START_CNTL_G[mpcc_id], 0, 272 MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_B, params->corner_points[0].green.custom_float_x, 273 MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_B, 0); 274 REG_SET_2(MPCC_MCM_SHAPER_RAMB_START_CNTL_R[mpcc_id], 0, 275 MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_B, params->corner_points[0].red.custom_float_x, 276 MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_B, 0); 277 278 REG_SET_2(MPCC_MCM_SHAPER_RAMB_END_CNTL_B[mpcc_id], 0, 279 MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_B, params->corner_points[1].blue.custom_float_x, 280 MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_BASE_B, params->corner_points[1].blue.custom_float_y); 281 REG_SET_2(MPCC_MCM_SHAPER_RAMB_END_CNTL_G[mpcc_id], 0, 282 MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_B, params->corner_points[1].green.custom_float_x, 283 MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_BASE_B, params->corner_points[1].green.custom_float_y); 284 REG_SET_2(MPCC_MCM_SHAPER_RAMB_END_CNTL_R[mpcc_id], 0, 285 MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_B, params->corner_points[1].red.custom_float_x, 286 MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_BASE_B, params->corner_points[1].red.custom_float_y); 287 288 curve = params->arr_curve_points; 289 REG_SET_4(MPCC_MCM_SHAPER_RAMB_REGION_0_1[mpcc_id], 0, 290 MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset, 291 MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num, 292 MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset, 293 MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num); 294 295 curve += 2; 296 REG_SET_4(MPCC_MCM_SHAPER_RAMB_REGION_2_3[mpcc_id], 0, 297 MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset, 298 MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num, 299 MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset, 300 MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num); 301 302 303 curve += 2; 304 REG_SET_4(MPCC_MCM_SHAPER_RAMB_REGION_4_5[mpcc_id], 0, 305 MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset, 306 MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num, 307 MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset, 308 MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num); 309 310 curve += 2; 311 REG_SET_4(MPCC_MCM_SHAPER_RAMB_REGION_6_7[mpcc_id], 0, 312 MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset, 313 MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num, 314 MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset, 315 MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num); 316 317 curve += 2; 318 REG_SET_4(MPCC_MCM_SHAPER_RAMB_REGION_8_9[mpcc_id], 0, 319 MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset, 320 MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num, 321 MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset, 322 MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num); 323 324 curve += 2; 325 REG_SET_4(MPCC_MCM_SHAPER_RAMB_REGION_10_11[mpcc_id], 0, 326 MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset, 327 MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num, 328 MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset, 329 MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num); 330 331 curve += 2; 332 REG_SET_4(MPCC_MCM_SHAPER_RAMB_REGION_12_13[mpcc_id], 0, 333 MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset, 334 MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num, 335 MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset, 336 MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num); 337 338 curve += 2; 339 REG_SET_4(MPCC_MCM_SHAPER_RAMB_REGION_14_15[mpcc_id], 0, 340 MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset, 341 MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num, 342 MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset, 343 MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num); 344 345 346 curve += 2; 347 REG_SET_4(MPCC_MCM_SHAPER_RAMB_REGION_16_17[mpcc_id], 0, 348 MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset, 349 MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num, 350 MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset, 351 MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num); 352 353 curve += 2; 354 REG_SET_4(MPCC_MCM_SHAPER_RAMB_REGION_18_19[mpcc_id], 0, 355 MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset, 356 MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num, 357 MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset, 358 MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num); 359 360 curve += 2; 361 REG_SET_4(MPCC_MCM_SHAPER_RAMB_REGION_20_21[mpcc_id], 0, 362 MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset, 363 MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num, 364 MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset, 365 MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num); 366 367 curve += 2; 368 REG_SET_4(MPCC_MCM_SHAPER_RAMB_REGION_22_23[mpcc_id], 0, 369 MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset, 370 MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num, 371 MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset, 372 MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num); 373 374 curve += 2; 375 REG_SET_4(MPCC_MCM_SHAPER_RAMB_REGION_24_25[mpcc_id], 0, 376 MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset, 377 MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num, 378 MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset, 379 MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num); 380 381 curve += 2; 382 REG_SET_4(MPCC_MCM_SHAPER_RAMB_REGION_26_27[mpcc_id], 0, 383 MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset, 384 MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num, 385 MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset, 386 MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num); 387 388 curve += 2; 389 REG_SET_4(MPCC_MCM_SHAPER_RAMB_REGION_28_29[mpcc_id], 0, 390 MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset, 391 MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num, 392 MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset, 393 MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num); 394 395 curve += 2; 396 REG_SET_4(MPCC_MCM_SHAPER_RAMB_REGION_30_31[mpcc_id], 0, 397 MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset, 398 MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num, 399 MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset, 400 MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num); 401 402 curve += 2; 403 REG_SET_4(MPCC_MCM_SHAPER_RAMB_REGION_32_33[mpcc_id], 0, 404 MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset, 405 MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num, 406 MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset, 407 MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num); 408 } 409 410 411 static void mpc32_program_shaper_lut( 412 struct mpc *mpc, 413 const struct pwl_result_data *rgb, 414 uint32_t num, 415 uint32_t mpcc_id) 416 { 417 uint32_t i, red, green, blue; 418 uint32_t red_delta, green_delta, blue_delta; 419 uint32_t red_value, green_value, blue_value; 420 421 struct dcn30_mpc *mpc30 = TO_DCN30_MPC(mpc); 422 423 for (i = 0 ; i < num; i++) { 424 425 red = rgb[i].red_reg; 426 green = rgb[i].green_reg; 427 blue = rgb[i].blue_reg; 428 429 red_delta = rgb[i].delta_red_reg; 430 green_delta = rgb[i].delta_green_reg; 431 blue_delta = rgb[i].delta_blue_reg; 432 433 red_value = ((red_delta & 0x3ff) << 14) | (red & 0x3fff); 434 green_value = ((green_delta & 0x3ff) << 14) | (green & 0x3fff); 435 blue_value = ((blue_delta & 0x3ff) << 14) | (blue & 0x3fff); 436 437 REG_SET(MPCC_MCM_SHAPER_LUT_DATA[mpcc_id], 0, MPCC_MCM_SHAPER_LUT_DATA, red_value); 438 REG_SET(MPCC_MCM_SHAPER_LUT_DATA[mpcc_id], 0, MPCC_MCM_SHAPER_LUT_DATA, green_value); 439 REG_SET(MPCC_MCM_SHAPER_LUT_DATA[mpcc_id], 0, MPCC_MCM_SHAPER_LUT_DATA, blue_value); 440 } 441 442 } 443 444 445 static void mpc32_power_on_shaper_3dlut( 446 struct mpc *mpc, 447 uint32_t mpcc_id, 448 bool power_on) 449 { 450 uint32_t power_status_shaper = 2; 451 uint32_t power_status_3dlut = 2; 452 struct dcn30_mpc *mpc30 = TO_DCN30_MPC(mpc); 453 int max_retries = 10; 454 455 REG_SET(MPCC_MCM_MEM_PWR_CTRL[mpcc_id], 0, 456 MPCC_MCM_3DLUT_MEM_PWR_DIS, power_on == true ? 1:0); 457 /* wait for memory to fully power up */ 458 if (power_on && mpc->ctx->dc->debug.enable_mem_low_power.bits.mpc) { 459 REG_WAIT(MPCC_MCM_MEM_PWR_CTRL[mpcc_id], MPCC_MCM_SHAPER_MEM_PWR_STATE, 0, 1, max_retries); 460 REG_WAIT(MPCC_MCM_MEM_PWR_CTRL[mpcc_id], MPCC_MCM_3DLUT_MEM_PWR_STATE, 0, 1, max_retries); 461 } 462 463 /*read status is not mandatory, it is just for debugging*/ 464 REG_GET(MPCC_MCM_MEM_PWR_CTRL[mpcc_id], MPCC_MCM_SHAPER_MEM_PWR_STATE, &power_status_shaper); 465 REG_GET(MPCC_MCM_MEM_PWR_CTRL[mpcc_id], MPCC_MCM_3DLUT_MEM_PWR_STATE, &power_status_3dlut); 466 467 if (power_status_shaper != 0 && power_on == true) 468 BREAK_TO_DEBUGGER(); 469 470 if (power_status_3dlut != 0 && power_on == true) 471 BREAK_TO_DEBUGGER(); 472 } 473 474 475 bool mpc32_program_shaper( 476 struct mpc *mpc, 477 const struct pwl_params *params, 478 uint32_t mpcc_id) 479 { 480 enum dc_lut_mode current_mode; 481 enum dc_lut_mode next_mode; 482 483 struct dcn30_mpc *mpc30 = TO_DCN30_MPC(mpc); 484 485 if (params == NULL) { 486 REG_SET(MPCC_MCM_SHAPER_CONTROL[mpcc_id], 0, MPCC_MCM_SHAPER_LUT_MODE, 0); 487 return false; 488 } 489 490 if (mpc->ctx->dc->debug.enable_mem_low_power.bits.mpc) 491 mpc32_power_on_shaper_3dlut(mpc, mpcc_id, true); 492 493 current_mode = mpc32_get_shaper_current(mpc, mpcc_id); 494 495 if (current_mode == LUT_BYPASS || current_mode == LUT_RAM_A) 496 next_mode = LUT_RAM_B; 497 else 498 next_mode = LUT_RAM_A; 499 500 mpc32_configure_shaper_lut(mpc, next_mode == LUT_RAM_A ? true:false, mpcc_id); 501 502 if (next_mode == LUT_RAM_A) 503 mpc32_program_shaper_luta_settings(mpc, params, mpcc_id); 504 else 505 mpc32_program_shaper_lutb_settings(mpc, params, mpcc_id); 506 507 mpc32_program_shaper_lut( 508 mpc, params->rgb_resulted, params->hw_points_num, mpcc_id); 509 510 REG_SET(MPCC_MCM_SHAPER_CONTROL[mpcc_id], 0, MPCC_MCM_SHAPER_LUT_MODE, next_mode == LUT_RAM_A ? 1:2); 511 mpc32_power_on_shaper_3dlut(mpc, mpcc_id, false); 512 513 return true; 514 } 515 516 517 static enum dc_lut_mode get3dlut_config( 518 struct mpc *mpc, 519 bool *is_17x17x17, 520 bool *is_12bits_color_channel, 521 int mpcc_id) 522 { 523 uint32_t i_mode, i_enable_10bits, lut_size; 524 enum dc_lut_mode mode; 525 struct dcn30_mpc *mpc30 = TO_DCN30_MPC(mpc); 526 527 REG_GET(MPCC_MCM_3DLUT_MODE[mpcc_id], 528 MPCC_MCM_3DLUT_MODE_CURRENT, &i_mode); 529 530 REG_GET(MPCC_MCM_3DLUT_READ_WRITE_CONTROL[mpcc_id], 531 MPCC_MCM_3DLUT_30BIT_EN, &i_enable_10bits); 532 533 switch (i_mode) { 534 case 0: 535 mode = LUT_BYPASS; 536 break; 537 case 1: 538 mode = LUT_RAM_A; 539 break; 540 case 2: 541 mode = LUT_RAM_B; 542 break; 543 default: 544 mode = LUT_BYPASS; 545 break; 546 } 547 if (i_enable_10bits > 0) 548 *is_12bits_color_channel = false; 549 else 550 *is_12bits_color_channel = true; 551 552 REG_GET(MPCC_MCM_3DLUT_MODE[mpcc_id], MPCC_MCM_3DLUT_SIZE, &lut_size); 553 554 if (lut_size == 0) 555 *is_17x17x17 = true; 556 else 557 *is_17x17x17 = false; 558 559 return mode; 560 } 561 562 563 static void mpc32_select_3dlut_ram( 564 struct mpc *mpc, 565 enum dc_lut_mode mode, 566 bool is_color_channel_12bits, 567 uint32_t mpcc_id) 568 { 569 struct dcn30_mpc *mpc30 = TO_DCN30_MPC(mpc); 570 571 REG_UPDATE_2(MPCC_MCM_3DLUT_READ_WRITE_CONTROL[mpcc_id], 572 MPCC_MCM_3DLUT_RAM_SEL, mode == LUT_RAM_A ? 0 : 1, 573 MPCC_MCM_3DLUT_30BIT_EN, is_color_channel_12bits == true ? 0:1); 574 } 575 576 577 static void mpc32_select_3dlut_ram_mask( 578 struct mpc *mpc, 579 uint32_t ram_selection_mask, 580 uint32_t mpcc_id) 581 { 582 struct dcn30_mpc *mpc30 = TO_DCN30_MPC(mpc); 583 584 REG_UPDATE(MPCC_MCM_3DLUT_READ_WRITE_CONTROL[mpcc_id], MPCC_MCM_3DLUT_WRITE_EN_MASK, 585 ram_selection_mask); 586 REG_SET(MPCC_MCM_3DLUT_INDEX[mpcc_id], 0, MPCC_MCM_3DLUT_INDEX, 0); 587 } 588 589 590 static void mpc32_set3dlut_ram12( 591 struct mpc *mpc, 592 const struct dc_rgb *lut, 593 uint32_t entries, 594 uint32_t mpcc_id) 595 { 596 uint32_t i, red, green, blue, red1, green1, blue1; 597 struct dcn30_mpc *mpc30 = TO_DCN30_MPC(mpc); 598 599 for (i = 0 ; i < entries; i += 2) { 600 red = lut[i].red<<4; 601 green = lut[i].green<<4; 602 blue = lut[i].blue<<4; 603 red1 = lut[i+1].red<<4; 604 green1 = lut[i+1].green<<4; 605 blue1 = lut[i+1].blue<<4; 606 607 REG_SET_2(MPCC_MCM_3DLUT_DATA[mpcc_id], 0, 608 MPCC_MCM_3DLUT_DATA0, red, 609 MPCC_MCM_3DLUT_DATA1, red1); 610 611 REG_SET_2(MPCC_MCM_3DLUT_DATA[mpcc_id], 0, 612 MPCC_MCM_3DLUT_DATA0, green, 613 MPCC_MCM_3DLUT_DATA1, green1); 614 615 REG_SET_2(MPCC_MCM_3DLUT_DATA[mpcc_id], 0, 616 MPCC_MCM_3DLUT_DATA0, blue, 617 MPCC_MCM_3DLUT_DATA1, blue1); 618 } 619 } 620 621 622 static void mpc32_set3dlut_ram10( 623 struct mpc *mpc, 624 const struct dc_rgb *lut, 625 uint32_t entries, 626 uint32_t mpcc_id) 627 { 628 uint32_t i, red, green, blue, value; 629 struct dcn30_mpc *mpc30 = TO_DCN30_MPC(mpc); 630 631 for (i = 0; i < entries; i++) { 632 red = lut[i].red; 633 green = lut[i].green; 634 blue = lut[i].blue; 635 //should we shift red 22bit and green 12? 636 value = (red<<20) | (green<<10) | blue; 637 638 REG_SET(MPCC_MCM_3DLUT_DATA_30BIT[mpcc_id], 0, MPCC_MCM_3DLUT_DATA_30BIT, value); 639 } 640 641 } 642 643 644 static void mpc32_set_3dlut_mode( 645 struct mpc *mpc, 646 enum dc_lut_mode mode, 647 bool is_color_channel_12bits, 648 bool is_lut_size17x17x17, 649 uint32_t mpcc_id) 650 { 651 uint32_t lut_mode; 652 struct dcn30_mpc *mpc30 = TO_DCN30_MPC(mpc); 653 654 if (mode == LUT_BYPASS) 655 lut_mode = 0; 656 else if (mode == LUT_RAM_A) 657 lut_mode = 1; 658 else 659 lut_mode = 2; 660 661 REG_UPDATE_2(MPCC_MCM_3DLUT_MODE[mpcc_id], 662 MPCC_MCM_3DLUT_MODE, lut_mode, 663 MPCC_MCM_3DLUT_SIZE, is_lut_size17x17x17 == true ? 0 : 1); 664 } 665 666 667 bool mpc32_program_3dlut( 668 struct mpc *mpc, 669 const struct tetrahedral_params *params, 670 int mpcc_id) 671 { 672 enum dc_lut_mode mode; 673 bool is_17x17x17; 674 bool is_12bits_color_channel; 675 const struct dc_rgb *lut0; 676 const struct dc_rgb *lut1; 677 const struct dc_rgb *lut2; 678 const struct dc_rgb *lut3; 679 int lut_size0; 680 int lut_size; 681 682 if (params == NULL) { 683 mpc32_set_3dlut_mode(mpc, LUT_BYPASS, false, false, mpcc_id); 684 return false; 685 } 686 mpc32_power_on_shaper_3dlut(mpc, mpcc_id, true); 687 688 mode = get3dlut_config(mpc, &is_17x17x17, &is_12bits_color_channel, mpcc_id); 689 690 if (mode == LUT_BYPASS || mode == LUT_RAM_B) 691 mode = LUT_RAM_A; 692 else 693 mode = LUT_RAM_B; 694 695 is_17x17x17 = !params->use_tetrahedral_9; 696 is_12bits_color_channel = params->use_12bits; 697 if (is_17x17x17) { 698 lut0 = params->tetrahedral_17.lut0; 699 lut1 = params->tetrahedral_17.lut1; 700 lut2 = params->tetrahedral_17.lut2; 701 lut3 = params->tetrahedral_17.lut3; 702 lut_size0 = sizeof(params->tetrahedral_17.lut0)/ 703 sizeof(params->tetrahedral_17.lut0[0]); 704 lut_size = sizeof(params->tetrahedral_17.lut1)/ 705 sizeof(params->tetrahedral_17.lut1[0]); 706 } else { 707 lut0 = params->tetrahedral_9.lut0; 708 lut1 = params->tetrahedral_9.lut1; 709 lut2 = params->tetrahedral_9.lut2; 710 lut3 = params->tetrahedral_9.lut3; 711 lut_size0 = sizeof(params->tetrahedral_9.lut0)/ 712 sizeof(params->tetrahedral_9.lut0[0]); 713 lut_size = sizeof(params->tetrahedral_9.lut1)/ 714 sizeof(params->tetrahedral_9.lut1[0]); 715 } 716 717 mpc32_select_3dlut_ram(mpc, mode, 718 is_12bits_color_channel, mpcc_id); 719 mpc32_select_3dlut_ram_mask(mpc, 0x1, mpcc_id); 720 if (is_12bits_color_channel) 721 mpc32_set3dlut_ram12(mpc, lut0, lut_size0, mpcc_id); 722 else 723 mpc32_set3dlut_ram10(mpc, lut0, lut_size0, mpcc_id); 724 725 mpc32_select_3dlut_ram_mask(mpc, 0x2, mpcc_id); 726 if (is_12bits_color_channel) 727 mpc32_set3dlut_ram12(mpc, lut1, lut_size, mpcc_id); 728 else 729 mpc32_set3dlut_ram10(mpc, lut1, lut_size, mpcc_id); 730 731 mpc32_select_3dlut_ram_mask(mpc, 0x4, mpcc_id); 732 if (is_12bits_color_channel) 733 mpc32_set3dlut_ram12(mpc, lut2, lut_size, mpcc_id); 734 else 735 mpc32_set3dlut_ram10(mpc, lut2, lut_size, mpcc_id); 736 737 mpc32_select_3dlut_ram_mask(mpc, 0x8, mpcc_id); 738 if (is_12bits_color_channel) 739 mpc32_set3dlut_ram12(mpc, lut3, lut_size, mpcc_id); 740 else 741 mpc32_set3dlut_ram10(mpc, lut3, lut_size, mpcc_id); 742 743 mpc32_set_3dlut_mode(mpc, mode, is_12bits_color_channel, 744 is_17x17x17, mpcc_id); 745 746 if (mpc->ctx->dc->debug.enable_mem_low_power.bits.mpc) 747 mpc32_power_on_shaper_3dlut(mpc, mpcc_id, false); 748 749 return true; 750 } 751 752 const struct mpc_funcs dcn32_mpc_funcs = { 753 .read_mpcc_state = mpc1_read_mpcc_state, 754 .insert_plane = mpc1_insert_plane, 755 .remove_mpcc = mpc1_remove_mpcc, 756 .mpc_init = mpc32_mpc_init, 757 .mpc_init_single_inst = mpc1_mpc_init_single_inst, 758 .update_blending = mpc2_update_blending, 759 .cursor_lock = mpc1_cursor_lock, 760 .get_mpcc_for_dpp = mpc1_get_mpcc_for_dpp, 761 .wait_for_idle = mpc2_assert_idle_mpcc, 762 .assert_mpcc_idle_before_connect = mpc2_assert_mpcc_idle_before_connect, 763 .init_mpcc_list_from_hw = mpc1_init_mpcc_list_from_hw, 764 .set_denorm = mpc3_set_denorm, 765 .set_denorm_clamp = mpc3_set_denorm_clamp, 766 .set_output_csc = mpc3_set_output_csc, 767 .set_ocsc_default = mpc3_set_ocsc_default, 768 .set_output_gamma = mpc3_set_output_gamma, 769 .insert_plane_to_secondary = NULL, 770 .remove_mpcc_from_secondary = NULL, 771 .set_dwb_mux = mpc3_set_dwb_mux, 772 .disable_dwb_mux = mpc3_disable_dwb_mux, 773 .is_dwb_idle = mpc3_is_dwb_idle, 774 .set_out_rate_control = mpc3_set_out_rate_control, 775 .set_gamut_remap = mpc3_set_gamut_remap, 776 .program_shaper = mpc32_program_shaper, 777 .program_3dlut = mpc32_program_3dlut, 778 .acquire_rmu = NULL, 779 .release_rmu = NULL, 780 .power_on_mpc_mem_pwr = mpc3_power_on_ogam_lut, 781 .get_mpc_out_mux = mpc1_get_mpc_out_mux, 782 .set_bg_color = mpc1_set_bg_color, 783 }; 784 785 786 void dcn32_mpc_construct(struct dcn30_mpc *mpc30, 787 struct dc_context *ctx, 788 const struct dcn30_mpc_registers *mpc_regs, 789 const struct dcn30_mpc_shift *mpc_shift, 790 const struct dcn30_mpc_mask *mpc_mask, 791 int num_mpcc, 792 int num_rmu) 793 { 794 int i; 795 796 mpc30->base.ctx = ctx; 797 798 mpc30->base.funcs = &dcn32_mpc_funcs; 799 800 mpc30->mpc_regs = mpc_regs; 801 mpc30->mpc_shift = mpc_shift; 802 mpc30->mpc_mask = mpc_mask; 803 804 mpc30->mpcc_in_use_mask = 0; 805 mpc30->num_mpcc = num_mpcc; 806 mpc30->num_rmu = num_rmu; 807 808 for (i = 0; i < MAX_MPCC; i++) 809 mpc3_init_mpcc(&mpc30->base.mpcc_array[i], i); 810 } 811