1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #ifndef __DC_HWSS_DCN32_H__ 27 #define __DC_HWSS_DCN32_H__ 28 29 #include "hw_sequencer_private.h" 30 31 struct dc; 32 33 void dcn32_dsc_pg_control( 34 struct dce_hwseq *hws, 35 unsigned int dsc_inst, 36 bool power_on); 37 38 void dcn32_enable_power_gating_plane( 39 struct dce_hwseq *hws, 40 bool enable); 41 42 void dcn32_hubp_pg_control(struct dce_hwseq *hws, unsigned int hubp_inst, bool power_on); 43 44 bool dcn32_apply_idle_power_optimizations(struct dc *dc, bool enable); 45 46 void dcn32_cab_for_ss_control(struct dc *dc, bool enable); 47 48 void dcn32_commit_subvp_config(struct dc *dc, struct dc_state *context); 49 50 bool dcn32_set_mcm_luts(struct pipe_ctx *pipe_ctx, 51 const struct dc_plane_state *plane_state); 52 53 bool dcn32_set_input_transfer_func(struct dc *dc, 54 struct pipe_ctx *pipe_ctx, 55 const struct dc_plane_state *plane_state); 56 57 bool dcn32_set_output_transfer_func(struct dc *dc, 58 struct pipe_ctx *pipe_ctx, 59 const struct dc_stream_state *stream); 60 61 void dcn32_init_hw(struct dc *dc); 62 63 void dcn32_program_mall_pipe_config(struct dc *dc, struct dc_state *context); 64 65 void dcn32_update_mall_sel(struct dc *dc, struct dc_state *context); 66 67 void dcn32_subvp_update_force_pstate(struct dc *dc, struct dc_state *context); 68 69 void dcn32_update_odm(struct dc *dc, struct dc_state *context, struct pipe_ctx *pipe_ctx); 70 71 unsigned int dcn32_calculate_dccg_k1_k2_values(struct pipe_ctx *pipe_ctx, unsigned int *k1_div, unsigned int *k2_div); 72 73 void dcn32_set_pixels_per_cycle(struct pipe_ctx *pipe_ctx); 74 75 void dcn32_subvp_pipe_control_lock(struct dc *dc, 76 struct dc_state *context, 77 bool lock, 78 bool should_lock_all_pipes, 79 struct pipe_ctx *top_pipe_to_program, 80 bool subvp_prev_use); 81 82 void dcn32_unblank_stream(struct pipe_ctx *pipe_ctx, 83 struct dc_link_settings *link_settings); 84 85 bool dcn32_is_dp_dig_pixel_rate_div_policy(struct pipe_ctx *pipe_ctx); 86 87 #endif /* __DC_HWSS_DCN32_H__ */ 88