1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 27 #include "dm_services.h" 28 #include "dm_helpers.h" 29 #include "core_types.h" 30 #include "resource.h" 31 #include "dccg.h" 32 #include "dce/dce_hwseq.h" 33 #include "dcn30/dcn30_cm_common.h" 34 #include "reg_helper.h" 35 #include "abm.h" 36 #include "hubp.h" 37 #include "dchubbub.h" 38 #include "timing_generator.h" 39 #include "opp.h" 40 #include "ipp.h" 41 #include "mpc.h" 42 #include "mcif_wb.h" 43 #include "dc_dmub_srv.h" 44 #include "link_hwss.h" 45 #include "dpcd_defs.h" 46 #include "dcn32_hwseq.h" 47 #include "clk_mgr.h" 48 #include "dsc.h" 49 #include "dcn20/dcn20_optc.h" 50 #include "dce/dmub_hw_lock_mgr.h" 51 #include "dcn32_resource.h" 52 #include "link.h" 53 54 #define DC_LOGGER_INIT(logger) 55 56 #define CTX \ 57 hws->ctx 58 #define REG(reg)\ 59 hws->regs->reg 60 #define DC_LOGGER \ 61 dc->ctx->logger 62 63 64 #undef FN 65 #define FN(reg_name, field_name) \ 66 hws->shifts->field_name, hws->masks->field_name 67 68 void dcn32_dsc_pg_control( 69 struct dce_hwseq *hws, 70 unsigned int dsc_inst, 71 bool power_on) 72 { 73 uint32_t power_gate = power_on ? 0 : 1; 74 uint32_t pwr_status = power_on ? 0 : 2; 75 uint32_t org_ip_request_cntl = 0; 76 77 if (hws->ctx->dc->debug.disable_dsc_power_gate) 78 return; 79 80 REG_GET(DC_IP_REQUEST_CNTL, IP_REQUEST_EN, &org_ip_request_cntl); 81 if (org_ip_request_cntl == 0) 82 REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 1); 83 84 switch (dsc_inst) { 85 case 0: /* DSC0 */ 86 REG_UPDATE(DOMAIN16_PG_CONFIG, 87 DOMAIN_POWER_GATE, power_gate); 88 89 REG_WAIT(DOMAIN16_PG_STATUS, 90 DOMAIN_PGFSM_PWR_STATUS, pwr_status, 91 1, 1000); 92 break; 93 case 1: /* DSC1 */ 94 REG_UPDATE(DOMAIN17_PG_CONFIG, 95 DOMAIN_POWER_GATE, power_gate); 96 97 REG_WAIT(DOMAIN17_PG_STATUS, 98 DOMAIN_PGFSM_PWR_STATUS, pwr_status, 99 1, 1000); 100 break; 101 case 2: /* DSC2 */ 102 REG_UPDATE(DOMAIN18_PG_CONFIG, 103 DOMAIN_POWER_GATE, power_gate); 104 105 REG_WAIT(DOMAIN18_PG_STATUS, 106 DOMAIN_PGFSM_PWR_STATUS, pwr_status, 107 1, 1000); 108 break; 109 case 3: /* DSC3 */ 110 REG_UPDATE(DOMAIN19_PG_CONFIG, 111 DOMAIN_POWER_GATE, power_gate); 112 113 REG_WAIT(DOMAIN19_PG_STATUS, 114 DOMAIN_PGFSM_PWR_STATUS, pwr_status, 115 1, 1000); 116 break; 117 default: 118 BREAK_TO_DEBUGGER(); 119 break; 120 } 121 122 if (org_ip_request_cntl == 0) 123 REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 0); 124 } 125 126 127 void dcn32_enable_power_gating_plane( 128 struct dce_hwseq *hws, 129 bool enable) 130 { 131 bool force_on = true; /* disable power gating */ 132 uint32_t org_ip_request_cntl = 0; 133 134 if (enable) 135 force_on = false; 136 137 REG_GET(DC_IP_REQUEST_CNTL, IP_REQUEST_EN, &org_ip_request_cntl); 138 if (org_ip_request_cntl == 0) 139 REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 1); 140 141 /* DCHUBP0/1/2/3 */ 142 REG_UPDATE(DOMAIN0_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on); 143 REG_UPDATE(DOMAIN1_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on); 144 REG_UPDATE(DOMAIN2_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on); 145 REG_UPDATE(DOMAIN3_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on); 146 147 /* DCS0/1/2/3 */ 148 REG_UPDATE(DOMAIN16_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on); 149 REG_UPDATE(DOMAIN17_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on); 150 REG_UPDATE(DOMAIN18_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on); 151 REG_UPDATE(DOMAIN19_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on); 152 153 if (org_ip_request_cntl == 0) 154 REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 0); 155 } 156 157 void dcn32_hubp_pg_control(struct dce_hwseq *hws, unsigned int hubp_inst, bool power_on) 158 { 159 uint32_t power_gate = power_on ? 0 : 1; 160 uint32_t pwr_status = power_on ? 0 : 2; 161 162 if (hws->ctx->dc->debug.disable_hubp_power_gate) 163 return; 164 165 if (REG(DOMAIN0_PG_CONFIG) == 0) 166 return; 167 168 switch (hubp_inst) { 169 case 0: 170 REG_SET(DOMAIN0_PG_CONFIG, 0, DOMAIN_POWER_GATE, power_gate); 171 REG_WAIT(DOMAIN0_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, pwr_status, 1, 1000); 172 break; 173 case 1: 174 REG_SET(DOMAIN1_PG_CONFIG, 0, DOMAIN_POWER_GATE, power_gate); 175 REG_WAIT(DOMAIN1_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, pwr_status, 1, 1000); 176 break; 177 case 2: 178 REG_SET(DOMAIN2_PG_CONFIG, 0, DOMAIN_POWER_GATE, power_gate); 179 REG_WAIT(DOMAIN2_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, pwr_status, 1, 1000); 180 break; 181 case 3: 182 REG_SET(DOMAIN3_PG_CONFIG, 0, DOMAIN_POWER_GATE, power_gate); 183 REG_WAIT(DOMAIN3_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, pwr_status, 1, 1000); 184 break; 185 default: 186 BREAK_TO_DEBUGGER(); 187 break; 188 } 189 } 190 191 static bool dcn32_check_no_memory_request_for_cab(struct dc *dc) 192 { 193 int i; 194 195 /* First, check no-memory-request case */ 196 for (i = 0; i < dc->current_state->stream_count; i++) { 197 if ((dc->current_state->stream_status[i].plane_count) && 198 (dc->current_state->streams[i]->link->psr_settings.psr_version == DC_PSR_VERSION_UNSUPPORTED)) 199 /* Fail eligibility on a visible stream */ 200 break; 201 } 202 203 if (i == dc->current_state->stream_count) 204 return true; 205 206 return false; 207 } 208 209 210 /* This function loops through every surface that needs to be cached in CAB for SS, 211 * and calculates the total number of ways required to store all surfaces (primary, 212 * meta, cursor). 213 */ 214 static uint32_t dcn32_calculate_cab_allocation(struct dc *dc, struct dc_state *ctx) 215 { 216 int i; 217 uint32_t num_ways = 0; 218 uint32_t mall_ss_size_bytes = 0; 219 220 mall_ss_size_bytes = ctx->bw_ctx.bw.dcn.mall_ss_size_bytes; 221 // TODO add additional logic for PSR active stream exclusion optimization 222 // mall_ss_psr_active_size_bytes = ctx->bw_ctx.bw.dcn.mall_ss_psr_active_size_bytes; 223 224 // Include cursor size for CAB allocation 225 for (i = 0; i < dc->res_pool->pipe_count; i++) { 226 struct pipe_ctx *pipe = &ctx->res_ctx.pipe_ctx[i]; 227 228 if (!pipe->stream || !pipe->plane_state) 229 continue; 230 231 mall_ss_size_bytes += dcn32_helper_calculate_mall_bytes_for_cursor(dc, pipe, false); 232 } 233 234 // Convert number of cache lines required to number of ways 235 if (dc->debug.force_mall_ss_num_ways > 0) { 236 num_ways = dc->debug.force_mall_ss_num_ways; 237 } else { 238 num_ways = dcn32_helper_mall_bytes_to_ways(dc, mall_ss_size_bytes); 239 } 240 241 return num_ways; 242 } 243 244 bool dcn32_apply_idle_power_optimizations(struct dc *dc, bool enable) 245 { 246 union dmub_rb_cmd cmd; 247 uint8_t i; 248 uint32_t ways; 249 int j; 250 bool mall_ss_unsupported = false; 251 struct dc_plane_state *plane = NULL; 252 253 if (!dc->ctx->dmub_srv) 254 return false; 255 256 for (i = 0; i < dc->current_state->stream_count; i++) { 257 /* MALL SS messaging is not supported with PSR at this time */ 258 if (dc->current_state->streams[i] != NULL && 259 dc->current_state->streams[i]->link->psr_settings.psr_version != DC_PSR_VERSION_UNSUPPORTED) 260 return false; 261 } 262 263 if (enable) { 264 if (dc->current_state) { 265 266 /* 1. Check no memory request case for CAB. 267 * If no memory request case, send CAB_ACTION NO_DF_REQ DMUB message 268 */ 269 if (dcn32_check_no_memory_request_for_cab(dc)) { 270 /* Enable no-memory-requests case */ 271 memset(&cmd, 0, sizeof(cmd)); 272 cmd.cab.header.type = DMUB_CMD__CAB_FOR_SS; 273 cmd.cab.header.sub_type = DMUB_CMD__CAB_NO_DCN_REQ; 274 cmd.cab.header.payload_bytes = sizeof(cmd.cab) - sizeof(cmd.cab.header); 275 276 dm_execute_dmub_cmd(dc->ctx, &cmd, DM_DMUB_WAIT_TYPE_NO_WAIT); 277 278 return true; 279 } 280 281 /* 2. Check if all surfaces can fit in CAB. 282 * If surfaces can fit into CAB, send CAB_ACTION_ALLOW DMUB message 283 * and configure HUBP's to fetch from MALL 284 */ 285 ways = dcn32_calculate_cab_allocation(dc, dc->current_state); 286 287 /* MALL not supported with Stereo3D or TMZ surface. If any plane is using stereo, 288 * or TMZ surface, don't try to enter MALL. 289 */ 290 for (i = 0; i < dc->current_state->stream_count; i++) { 291 for (j = 0; j < dc->current_state->stream_status[i].plane_count; j++) { 292 plane = dc->current_state->stream_status[i].plane_states[j]; 293 294 if (plane->address.type == PLN_ADDR_TYPE_GRPH_STEREO || 295 plane->address.tmz_surface) { 296 mall_ss_unsupported = true; 297 break; 298 } 299 } 300 if (mall_ss_unsupported) 301 break; 302 } 303 if (ways <= dc->caps.cache_num_ways && !mall_ss_unsupported) { 304 memset(&cmd, 0, sizeof(cmd)); 305 cmd.cab.header.type = DMUB_CMD__CAB_FOR_SS; 306 cmd.cab.header.sub_type = DMUB_CMD__CAB_DCN_SS_FIT_IN_CAB; 307 cmd.cab.header.payload_bytes = sizeof(cmd.cab) - sizeof(cmd.cab.header); 308 cmd.cab.cab_alloc_ways = (uint8_t)ways; 309 310 dm_execute_dmub_cmd(dc->ctx, &cmd, DM_DMUB_WAIT_TYPE_NO_WAIT); 311 312 return true; 313 } 314 315 } 316 return false; 317 } 318 319 /* Disable CAB */ 320 memset(&cmd, 0, sizeof(cmd)); 321 cmd.cab.header.type = DMUB_CMD__CAB_FOR_SS; 322 cmd.cab.header.sub_type = DMUB_CMD__CAB_NO_IDLE_OPTIMIZATION; 323 cmd.cab.header.payload_bytes = 324 sizeof(cmd.cab) - sizeof(cmd.cab.header); 325 326 dm_execute_dmub_cmd(dc->ctx, &cmd, DM_DMUB_WAIT_TYPE_WAIT); 327 328 return true; 329 } 330 331 /* Send DMCUB message with SubVP pipe info 332 * - For each pipe in context, populate payload with required SubVP information 333 * if the pipe is using SubVP for MCLK switch 334 * - This function must be called while the DMUB HW lock is acquired by driver 335 */ 336 void dcn32_commit_subvp_config(struct dc *dc, struct dc_state *context) 337 { 338 int i; 339 bool enable_subvp = false; 340 341 if (!dc->ctx || !dc->ctx->dmub_srv) 342 return; 343 344 for (i = 0; i < dc->res_pool->pipe_count; i++) { 345 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; 346 347 if (pipe_ctx->stream && pipe_ctx->stream->mall_stream_config.paired_stream && 348 pipe_ctx->stream->mall_stream_config.type == SUBVP_MAIN) { 349 // There is at least 1 SubVP pipe, so enable SubVP 350 enable_subvp = true; 351 break; 352 } 353 } 354 dc_dmub_setup_subvp_dmub_command(dc, context, enable_subvp); 355 } 356 357 /* Sub-Viewport DMUB lock needs to be acquired by driver whenever SubVP is active and: 358 * 1. Any full update for any SubVP main pipe 359 * 2. Any immediate flip for any SubVP pipe 360 * 3. Any flip for DRR pipe 361 * 4. If SubVP was previously in use (i.e. in old context) 362 */ 363 void dcn32_subvp_pipe_control_lock(struct dc *dc, 364 struct dc_state *context, 365 bool lock, 366 bool should_lock_all_pipes, 367 struct pipe_ctx *top_pipe_to_program, 368 bool subvp_prev_use) 369 { 370 unsigned int i = 0; 371 bool subvp_immediate_flip = false; 372 bool subvp_in_use = false; 373 struct pipe_ctx *pipe; 374 375 for (i = 0; i < dc->res_pool->pipe_count; i++) { 376 pipe = &context->res_ctx.pipe_ctx[i]; 377 378 if (pipe->stream && pipe->plane_state && pipe->stream->mall_stream_config.type == SUBVP_MAIN) { 379 subvp_in_use = true; 380 break; 381 } 382 } 383 384 if (top_pipe_to_program && top_pipe_to_program->stream && top_pipe_to_program->plane_state) { 385 if (top_pipe_to_program->stream->mall_stream_config.type == SUBVP_MAIN && 386 top_pipe_to_program->plane_state->flip_immediate) 387 subvp_immediate_flip = true; 388 } 389 390 // Don't need to lock for DRR VSYNC flips -- FW will wait for DRR pending update cleared. 391 if ((subvp_in_use && (should_lock_all_pipes || subvp_immediate_flip)) || (!subvp_in_use && subvp_prev_use)) { 392 union dmub_inbox0_cmd_lock_hw hw_lock_cmd = { 0 }; 393 394 if (!lock) { 395 for (i = 0; i < dc->res_pool->pipe_count; i++) { 396 pipe = &context->res_ctx.pipe_ctx[i]; 397 if (pipe->stream && pipe->plane_state && pipe->stream->mall_stream_config.type == SUBVP_MAIN && 398 should_lock_all_pipes) 399 pipe->stream_res.tg->funcs->wait_for_state(pipe->stream_res.tg, CRTC_STATE_VBLANK); 400 } 401 } 402 403 hw_lock_cmd.bits.command_code = DMUB_INBOX0_CMD__HW_LOCK; 404 hw_lock_cmd.bits.hw_lock_client = HW_LOCK_CLIENT_DRIVER; 405 hw_lock_cmd.bits.lock = lock; 406 hw_lock_cmd.bits.should_release = !lock; 407 dmub_hw_lock_mgr_inbox0_cmd(dc->ctx->dmub_srv, hw_lock_cmd); 408 } 409 } 410 411 void dcn32_subvp_pipe_control_lock_fast(union block_sequence_params *params) 412 { 413 struct dc *dc = params->subvp_pipe_control_lock_fast_params.dc; 414 bool lock = params->subvp_pipe_control_lock_fast_params.lock; 415 struct pipe_ctx *pipe_ctx = params->subvp_pipe_control_lock_fast_params.pipe_ctx; 416 bool subvp_immediate_flip = false; 417 418 if (pipe_ctx && pipe_ctx->stream && pipe_ctx->plane_state) { 419 if (pipe_ctx->stream->mall_stream_config.type == SUBVP_MAIN && 420 pipe_ctx->plane_state->flip_immediate) 421 subvp_immediate_flip = true; 422 } 423 424 // Don't need to lock for DRR VSYNC flips -- FW will wait for DRR pending update cleared. 425 if (subvp_immediate_flip) { 426 union dmub_inbox0_cmd_lock_hw hw_lock_cmd = { 0 }; 427 428 hw_lock_cmd.bits.command_code = DMUB_INBOX0_CMD__HW_LOCK; 429 hw_lock_cmd.bits.hw_lock_client = HW_LOCK_CLIENT_DRIVER; 430 hw_lock_cmd.bits.lock = lock; 431 hw_lock_cmd.bits.should_release = !lock; 432 dmub_hw_lock_mgr_inbox0_cmd(dc->ctx->dmub_srv, hw_lock_cmd); 433 } 434 } 435 436 bool dcn32_set_mpc_shaper_3dlut( 437 struct pipe_ctx *pipe_ctx, const struct dc_stream_state *stream) 438 { 439 struct dpp *dpp_base = pipe_ctx->plane_res.dpp; 440 int mpcc_id = pipe_ctx->plane_res.hubp->inst; 441 struct mpc *mpc = pipe_ctx->stream_res.opp->ctx->dc->res_pool->mpc; 442 bool result = false; 443 444 const struct pwl_params *shaper_lut = NULL; 445 //get the shaper lut params 446 if (stream->func_shaper) { 447 if (stream->func_shaper->type == TF_TYPE_HWPWL) 448 shaper_lut = &stream->func_shaper->pwl; 449 else if (stream->func_shaper->type == TF_TYPE_DISTRIBUTED_POINTS) { 450 cm_helper_translate_curve_to_hw_format(stream->ctx, 451 stream->func_shaper, 452 &dpp_base->shaper_params, true); 453 shaper_lut = &dpp_base->shaper_params; 454 } 455 } 456 457 if (stream->lut3d_func && 458 stream->lut3d_func->state.bits.initialized == 1) { 459 460 result = mpc->funcs->program_3dlut(mpc, 461 &stream->lut3d_func->lut_3d, 462 mpcc_id); 463 464 result = mpc->funcs->program_shaper(mpc, 465 shaper_lut, 466 mpcc_id); 467 } 468 469 return result; 470 } 471 472 bool dcn32_set_mcm_luts( 473 struct pipe_ctx *pipe_ctx, const struct dc_plane_state *plane_state) 474 { 475 struct dpp *dpp_base = pipe_ctx->plane_res.dpp; 476 int mpcc_id = pipe_ctx->plane_res.hubp->inst; 477 struct mpc *mpc = pipe_ctx->stream_res.opp->ctx->dc->res_pool->mpc; 478 bool result = true; 479 struct pwl_params *lut_params = NULL; 480 481 // 1D LUT 482 if (plane_state->blend_tf) { 483 if (plane_state->blend_tf->type == TF_TYPE_HWPWL) 484 lut_params = &plane_state->blend_tf->pwl; 485 else if (plane_state->blend_tf->type == TF_TYPE_DISTRIBUTED_POINTS) { 486 cm_helper_translate_curve_to_hw_format(plane_state->ctx, 487 plane_state->blend_tf, 488 &dpp_base->regamma_params, false); 489 lut_params = &dpp_base->regamma_params; 490 } 491 } 492 result = mpc->funcs->program_1dlut(mpc, lut_params, mpcc_id); 493 494 // Shaper 495 if (plane_state->in_shaper_func) { 496 if (plane_state->in_shaper_func->type == TF_TYPE_HWPWL) 497 lut_params = &plane_state->in_shaper_func->pwl; 498 else if (plane_state->in_shaper_func->type == TF_TYPE_DISTRIBUTED_POINTS) { 499 // TODO: dpp_base replace 500 ASSERT(false); 501 cm_helper_translate_curve_to_hw_format(plane_state->ctx, 502 plane_state->in_shaper_func, 503 &dpp_base->shaper_params, true); 504 lut_params = &dpp_base->shaper_params; 505 } 506 } 507 508 result = mpc->funcs->program_shaper(mpc, lut_params, mpcc_id); 509 510 // 3D 511 if (plane_state->lut3d_func && plane_state->lut3d_func->state.bits.initialized == 1) 512 result = mpc->funcs->program_3dlut(mpc, &plane_state->lut3d_func->lut_3d, mpcc_id); 513 else 514 result = mpc->funcs->program_3dlut(mpc, NULL, mpcc_id); 515 516 return result; 517 } 518 519 bool dcn32_set_input_transfer_func(struct dc *dc, 520 struct pipe_ctx *pipe_ctx, 521 const struct dc_plane_state *plane_state) 522 { 523 struct dce_hwseq *hws = dc->hwseq; 524 struct mpc *mpc = dc->res_pool->mpc; 525 struct dpp *dpp_base = pipe_ctx->plane_res.dpp; 526 527 enum dc_transfer_func_predefined tf; 528 bool result = true; 529 struct pwl_params *params = NULL; 530 531 if (mpc == NULL || plane_state == NULL) 532 return false; 533 534 tf = TRANSFER_FUNCTION_UNITY; 535 536 if (plane_state->in_transfer_func && 537 plane_state->in_transfer_func->type == TF_TYPE_PREDEFINED) 538 tf = plane_state->in_transfer_func->tf; 539 540 dpp_base->funcs->dpp_set_pre_degam(dpp_base, tf); 541 542 if (plane_state->in_transfer_func) { 543 if (plane_state->in_transfer_func->type == TF_TYPE_HWPWL) 544 params = &plane_state->in_transfer_func->pwl; 545 else if (plane_state->in_transfer_func->type == TF_TYPE_DISTRIBUTED_POINTS && 546 cm3_helper_translate_curve_to_hw_format(plane_state->in_transfer_func, 547 &dpp_base->degamma_params, false)) 548 params = &dpp_base->degamma_params; 549 } 550 551 dpp_base->funcs->dpp_program_gamcor_lut(dpp_base, params); 552 553 if (pipe_ctx->stream_res.opp && 554 pipe_ctx->stream_res.opp->ctx && 555 hws->funcs.set_mcm_luts) 556 result = hws->funcs.set_mcm_luts(pipe_ctx, plane_state); 557 558 return result; 559 } 560 561 bool dcn32_set_output_transfer_func(struct dc *dc, 562 struct pipe_ctx *pipe_ctx, 563 const struct dc_stream_state *stream) 564 { 565 int mpcc_id = pipe_ctx->plane_res.hubp->inst; 566 struct mpc *mpc = pipe_ctx->stream_res.opp->ctx->dc->res_pool->mpc; 567 struct pwl_params *params = NULL; 568 bool ret = false; 569 570 /* program OGAM or 3DLUT only for the top pipe*/ 571 if (resource_is_pipe_type(pipe_ctx, OPP_HEAD)) { 572 /*program shaper and 3dlut in MPC*/ 573 ret = dcn32_set_mpc_shaper_3dlut(pipe_ctx, stream); 574 if (ret == false && mpc->funcs->set_output_gamma && stream->out_transfer_func) { 575 if (stream->out_transfer_func->type == TF_TYPE_HWPWL) 576 params = &stream->out_transfer_func->pwl; 577 else if (pipe_ctx->stream->out_transfer_func->type == 578 TF_TYPE_DISTRIBUTED_POINTS && 579 cm3_helper_translate_curve_to_hw_format( 580 stream->out_transfer_func, 581 &mpc->blender_params, false)) 582 params = &mpc->blender_params; 583 /* there are no ROM LUTs in OUTGAM */ 584 if (stream->out_transfer_func->type == TF_TYPE_PREDEFINED) 585 BREAK_TO_DEBUGGER(); 586 } 587 } 588 589 mpc->funcs->set_output_gamma(mpc, mpcc_id, params); 590 return ret; 591 } 592 593 /* Program P-State force value according to if pipe is using SubVP / FPO or not: 594 * 1. Reset P-State force on all pipes first 595 * 2. For each main pipe, force P-State disallow (P-State allow moderated by DMUB) 596 */ 597 void dcn32_update_force_pstate(struct dc *dc, struct dc_state *context) 598 { 599 int i; 600 601 /* Unforce p-state for each pipe if it is not FPO or SubVP. 602 * For FPO and SubVP, if it's already forced disallow, leave 603 * it as disallow. 604 */ 605 for (i = 0; i < dc->res_pool->pipe_count; i++) { 606 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; 607 struct hubp *hubp = pipe->plane_res.hubp; 608 609 if (!pipe->stream || !(pipe->stream->mall_stream_config.type == SUBVP_MAIN || 610 pipe->stream->fpo_in_use)) { 611 if (hubp && hubp->funcs->hubp_update_force_pstate_disallow) 612 hubp->funcs->hubp_update_force_pstate_disallow(hubp, false); 613 } 614 615 /* Today only FPO uses cursor P-State force. Only clear cursor P-State force 616 * if it's not FPO. 617 */ 618 if (!pipe->stream || !pipe->stream->fpo_in_use) { 619 if (hubp && hubp->funcs->hubp_update_force_cursor_pstate_disallow) 620 hubp->funcs->hubp_update_force_cursor_pstate_disallow(hubp, false); 621 } 622 } 623 624 /* Loop through each pipe -- for each subvp main pipe force p-state allow equal to false. 625 */ 626 for (i = 0; i < dc->res_pool->pipe_count; i++) { 627 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; 628 struct hubp *hubp = pipe->plane_res.hubp; 629 630 if (pipe->stream && pipe->plane_state && pipe->stream->mall_stream_config.type == SUBVP_MAIN) { 631 if (hubp && hubp->funcs->hubp_update_force_pstate_disallow) 632 hubp->funcs->hubp_update_force_pstate_disallow(hubp, true); 633 } 634 635 if (pipe->stream && pipe->stream->fpo_in_use) { 636 if (hubp && hubp->funcs->hubp_update_force_pstate_disallow) 637 hubp->funcs->hubp_update_force_pstate_disallow(hubp, true); 638 /* For now only force cursor p-state disallow for FPO 639 * Needs to be added for subvp once FW side gets updated 640 */ 641 if (hubp && hubp->funcs->hubp_update_force_cursor_pstate_disallow) 642 hubp->funcs->hubp_update_force_cursor_pstate_disallow(hubp, true); 643 } 644 } 645 } 646 647 /* Update MALL_SEL register based on if pipe / plane 648 * is a phantom pipe, main pipe, and if using MALL 649 * for SS. 650 */ 651 void dcn32_update_mall_sel(struct dc *dc, struct dc_state *context) 652 { 653 int i; 654 unsigned int num_ways = dcn32_calculate_cab_allocation(dc, context); 655 bool cache_cursor = false; 656 657 for (i = 0; i < dc->res_pool->pipe_count; i++) { 658 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; 659 struct hubp *hubp = pipe->plane_res.hubp; 660 661 if (pipe->stream && pipe->plane_state && hubp && hubp->funcs->hubp_update_mall_sel) { 662 int cursor_size = hubp->curs_attr.pitch * hubp->curs_attr.height; 663 664 switch (hubp->curs_attr.color_format) { 665 case CURSOR_MODE_MONO: 666 cursor_size /= 2; 667 break; 668 case CURSOR_MODE_COLOR_1BIT_AND: 669 case CURSOR_MODE_COLOR_PRE_MULTIPLIED_ALPHA: 670 case CURSOR_MODE_COLOR_UN_PRE_MULTIPLIED_ALPHA: 671 cursor_size *= 4; 672 break; 673 674 case CURSOR_MODE_COLOR_64BIT_FP_PRE_MULTIPLIED: 675 case CURSOR_MODE_COLOR_64BIT_FP_UN_PRE_MULTIPLIED: 676 default: 677 cursor_size *= 8; 678 break; 679 } 680 681 if (cursor_size > 16384) 682 cache_cursor = true; 683 684 if (pipe->stream->mall_stream_config.type == SUBVP_PHANTOM) { 685 hubp->funcs->hubp_update_mall_sel(hubp, 1, false); 686 } else { 687 // MALL not supported with Stereo3D 688 hubp->funcs->hubp_update_mall_sel(hubp, 689 num_ways <= dc->caps.cache_num_ways && 690 pipe->stream->link->psr_settings.psr_version == DC_PSR_VERSION_UNSUPPORTED && 691 pipe->plane_state->address.type != PLN_ADDR_TYPE_GRPH_STEREO && 692 !pipe->plane_state->address.tmz_surface ? 2 : 0, 693 cache_cursor); 694 } 695 } 696 } 697 } 698 699 /* Program the sub-viewport pipe configuration after the main / phantom pipes 700 * have been programmed in hardware. 701 * 1. Update force P-State for all the main pipes (disallow P-state) 702 * 2. Update MALL_SEL register 703 * 3. Program FORCE_ONE_ROW_FOR_FRAME for main subvp pipes 704 */ 705 void dcn32_program_mall_pipe_config(struct dc *dc, struct dc_state *context) 706 { 707 int i; 708 struct dce_hwseq *hws = dc->hwseq; 709 710 // Don't force p-state disallow -- can't block dummy p-state 711 712 // Update MALL_SEL register for each pipe 713 if (hws && hws->funcs.update_mall_sel) 714 hws->funcs.update_mall_sel(dc, context); 715 716 // Program FORCE_ONE_ROW_FOR_FRAME and CURSOR_REQ_MODE for main subvp pipes 717 for (i = 0; i < dc->res_pool->pipe_count; i++) { 718 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; 719 struct hubp *hubp = pipe->plane_res.hubp; 720 721 if (pipe->stream && hubp && hubp->funcs->hubp_prepare_subvp_buffering) { 722 /* TODO - remove setting CURSOR_REQ_MODE to 0 for legacy cases 723 * - need to investigate single pipe MPO + SubVP case to 724 * see if CURSOR_REQ_MODE will be back to 1 for SubVP 725 * when it should be 0 for MPO 726 */ 727 if (pipe->stream->mall_stream_config.type == SUBVP_MAIN) { 728 hubp->funcs->hubp_prepare_subvp_buffering(hubp, true); 729 } 730 } 731 } 732 } 733 734 static void dcn32_initialize_min_clocks(struct dc *dc) 735 { 736 struct dc_clocks *clocks = &dc->current_state->bw_ctx.bw.dcn.clk; 737 738 clocks->dcfclk_deep_sleep_khz = DCN3_2_DCFCLK_DS_INIT_KHZ; 739 clocks->dcfclk_khz = dc->clk_mgr->bw_params->clk_table.entries[0].dcfclk_mhz * 1000; 740 clocks->socclk_khz = dc->clk_mgr->bw_params->clk_table.entries[0].socclk_mhz * 1000; 741 clocks->dramclk_khz = dc->clk_mgr->bw_params->clk_table.entries[0].memclk_mhz * 1000; 742 clocks->dppclk_khz = dc->clk_mgr->bw_params->clk_table.entries[0].dppclk_mhz * 1000; 743 clocks->ref_dtbclk_khz = dc->clk_mgr->bw_params->clk_table.entries[0].dtbclk_mhz * 1000; 744 clocks->fclk_p_state_change_support = true; 745 clocks->p_state_change_support = true; 746 if (dc->debug.disable_boot_optimizations) { 747 clocks->dispclk_khz = dc->clk_mgr->bw_params->clk_table.entries[0].dispclk_mhz * 1000; 748 } else { 749 /* Even though DPG_EN = 1 for the connected display, it still requires the 750 * correct timing so we cannot set DISPCLK to min freq or it could cause 751 * audio corruption. Read current DISPCLK from DENTIST and request the same 752 * freq to ensure that the timing is valid and unchanged. 753 */ 754 clocks->dispclk_khz = dc->clk_mgr->funcs->get_dispclk_from_dentist(dc->clk_mgr); 755 } 756 757 dc->clk_mgr->funcs->update_clocks( 758 dc->clk_mgr, 759 dc->current_state, 760 true); 761 } 762 763 void dcn32_init_hw(struct dc *dc) 764 { 765 struct abm **abms = dc->res_pool->multiple_abms; 766 struct dce_hwseq *hws = dc->hwseq; 767 struct dc_bios *dcb = dc->ctx->dc_bios; 768 struct resource_pool *res_pool = dc->res_pool; 769 int i; 770 int edp_num; 771 uint32_t backlight = MAX_BACKLIGHT_LEVEL; 772 773 if (dc->clk_mgr && dc->clk_mgr->funcs->init_clocks) 774 dc->clk_mgr->funcs->init_clocks(dc->clk_mgr); 775 776 // Initialize the dccg 777 if (res_pool->dccg->funcs->dccg_init) 778 res_pool->dccg->funcs->dccg_init(res_pool->dccg); 779 780 if (!dcb->funcs->is_accelerated_mode(dcb)) { 781 hws->funcs.bios_golden_init(dc); 782 hws->funcs.disable_vga(dc->hwseq); 783 } 784 785 // Set default OPTC memory power states 786 if (dc->debug.enable_mem_low_power.bits.optc) { 787 // Shutdown when unassigned and light sleep in VBLANK 788 REG_SET_2(ODM_MEM_PWR_CTRL3, 0, ODM_MEM_UNASSIGNED_PWR_MODE, 3, ODM_MEM_VBLANK_PWR_MODE, 1); 789 } 790 791 if (dc->debug.enable_mem_low_power.bits.vga) { 792 // Power down VGA memory 793 REG_UPDATE(MMHUBBUB_MEM_PWR_CNTL, VGA_MEM_PWR_FORCE, 1); 794 } 795 796 if (dc->ctx->dc_bios->fw_info_valid) { 797 res_pool->ref_clocks.xtalin_clock_inKhz = 798 dc->ctx->dc_bios->fw_info.pll_info.crystal_frequency; 799 800 if (res_pool->dccg && res_pool->hubbub) { 801 (res_pool->dccg->funcs->get_dccg_ref_freq)(res_pool->dccg, 802 dc->ctx->dc_bios->fw_info.pll_info.crystal_frequency, 803 &res_pool->ref_clocks.dccg_ref_clock_inKhz); 804 805 (res_pool->hubbub->funcs->get_dchub_ref_freq)(res_pool->hubbub, 806 res_pool->ref_clocks.dccg_ref_clock_inKhz, 807 &res_pool->ref_clocks.dchub_ref_clock_inKhz); 808 } else { 809 // Not all ASICs have DCCG sw component 810 res_pool->ref_clocks.dccg_ref_clock_inKhz = 811 res_pool->ref_clocks.xtalin_clock_inKhz; 812 res_pool->ref_clocks.dchub_ref_clock_inKhz = 813 res_pool->ref_clocks.xtalin_clock_inKhz; 814 } 815 } else 816 ASSERT_CRITICAL(false); 817 818 for (i = 0; i < dc->link_count; i++) { 819 /* Power up AND update implementation according to the 820 * required signal (which may be different from the 821 * default signal on connector). 822 */ 823 struct dc_link *link = dc->links[i]; 824 825 link->link_enc->funcs->hw_init(link->link_enc); 826 827 /* Check for enabled DIG to identify enabled display */ 828 if (link->link_enc->funcs->is_dig_enabled && 829 link->link_enc->funcs->is_dig_enabled(link->link_enc)) { 830 link->link_status.link_active = true; 831 link->phy_state.symclk_state = SYMCLK_ON_TX_ON; 832 if (link->link_enc->funcs->fec_is_active && 833 link->link_enc->funcs->fec_is_active(link->link_enc)) 834 link->fec_state = dc_link_fec_enabled; 835 } 836 } 837 838 /* enable_power_gating_plane before dsc_pg_control because 839 * FORCEON = 1 with hw default value on bootup, resume from s3 840 */ 841 if (hws->funcs.enable_power_gating_plane) 842 hws->funcs.enable_power_gating_plane(dc->hwseq, true); 843 844 /* we want to turn off all dp displays before doing detection */ 845 dc->link_srv->blank_all_dp_displays(dc); 846 847 /* If taking control over from VBIOS, we may want to optimize our first 848 * mode set, so we need to skip powering down pipes until we know which 849 * pipes we want to use. 850 * Otherwise, if taking control is not possible, we need to power 851 * everything down. 852 */ 853 if (dcb->funcs->is_accelerated_mode(dcb) || !dc->config.seamless_boot_edp_requested) { 854 /* Disable boot optimizations means power down everything including PHY, DIG, 855 * and OTG (i.e. the boot is not optimized because we do a full power down). 856 */ 857 if (dc->hwss.enable_accelerated_mode && dc->debug.disable_boot_optimizations) 858 dc->hwss.enable_accelerated_mode(dc, dc->current_state); 859 else 860 hws->funcs.init_pipes(dc, dc->current_state); 861 862 if (dc->res_pool->hubbub->funcs->allow_self_refresh_control) 863 dc->res_pool->hubbub->funcs->allow_self_refresh_control(dc->res_pool->hubbub, 864 !dc->res_pool->hubbub->ctx->dc->debug.disable_stutter); 865 866 dcn32_initialize_min_clocks(dc); 867 868 /* On HW init, allow idle optimizations after pipes have been turned off. 869 * 870 * In certain D3 cases (i.e. BOCO / BOMACO) it's possible that hardware state 871 * is reset (i.e. not in idle at the time hw init is called), but software state 872 * still has idle_optimizations = true, so we must disable idle optimizations first 873 * (i.e. set false), then re-enable (set true). 874 */ 875 dc_allow_idle_optimizations(dc, false); 876 dc_allow_idle_optimizations(dc, true); 877 } 878 879 /* In headless boot cases, DIG may be turned 880 * on which causes HW/SW discrepancies. 881 * To avoid this, power down hardware on boot 882 * if DIG is turned on and seamless boot not enabled 883 */ 884 if (!dc->config.seamless_boot_edp_requested) { 885 struct dc_link *edp_links[MAX_NUM_EDP]; 886 struct dc_link *edp_link; 887 888 dc_get_edp_links(dc, edp_links, &edp_num); 889 if (edp_num) { 890 for (i = 0; i < edp_num; i++) { 891 edp_link = edp_links[i]; 892 if (edp_link->link_enc->funcs->is_dig_enabled && 893 edp_link->link_enc->funcs->is_dig_enabled(edp_link->link_enc) && 894 dc->hwss.edp_backlight_control && 895 dc->hwss.power_down && 896 dc->hwss.edp_power_control) { 897 dc->hwss.edp_backlight_control(edp_link, false); 898 dc->hwss.power_down(dc); 899 dc->hwss.edp_power_control(edp_link, false); 900 } 901 } 902 } else { 903 for (i = 0; i < dc->link_count; i++) { 904 struct dc_link *link = dc->links[i]; 905 906 if (link->link_enc->funcs->is_dig_enabled && 907 link->link_enc->funcs->is_dig_enabled(link->link_enc) && 908 dc->hwss.power_down) { 909 dc->hwss.power_down(dc); 910 break; 911 } 912 913 } 914 } 915 } 916 917 for (i = 0; i < res_pool->audio_count; i++) { 918 struct audio *audio = res_pool->audios[i]; 919 920 audio->funcs->hw_init(audio); 921 } 922 923 for (i = 0; i < dc->link_count; i++) { 924 struct dc_link *link = dc->links[i]; 925 926 if (link->panel_cntl) 927 backlight = link->panel_cntl->funcs->hw_init(link->panel_cntl); 928 } 929 930 for (i = 0; i < dc->res_pool->pipe_count; i++) { 931 if (abms[i] != NULL && abms[i]->funcs != NULL) 932 abms[i]->funcs->abm_init(abms[i], backlight); 933 } 934 935 /* power AFMT HDMI memory TODO: may move to dis/en output save power*/ 936 REG_WRITE(DIO_MEM_PWR_CTRL, 0); 937 938 if (!dc->debug.disable_clock_gate) { 939 /* enable all DCN clock gating */ 940 REG_WRITE(DCCG_GATE_DISABLE_CNTL, 0); 941 942 REG_WRITE(DCCG_GATE_DISABLE_CNTL2, 0); 943 944 REG_UPDATE(DCFCLK_CNTL, DCFCLK_GATE_DIS, 0); 945 } 946 947 if (!dcb->funcs->is_accelerated_mode(dcb) && dc->res_pool->hubbub->funcs->init_watermarks) 948 dc->res_pool->hubbub->funcs->init_watermarks(dc->res_pool->hubbub); 949 950 if (dc->clk_mgr->funcs->notify_wm_ranges) 951 dc->clk_mgr->funcs->notify_wm_ranges(dc->clk_mgr); 952 953 if (dc->clk_mgr->funcs->set_hard_max_memclk && !dc->clk_mgr->dc_mode_softmax_enabled) 954 dc->clk_mgr->funcs->set_hard_max_memclk(dc->clk_mgr); 955 956 if (dc->res_pool->hubbub->funcs->force_pstate_change_control) 957 dc->res_pool->hubbub->funcs->force_pstate_change_control( 958 dc->res_pool->hubbub, false, false); 959 960 if (dc->res_pool->hubbub->funcs->init_crb) 961 dc->res_pool->hubbub->funcs->init_crb(dc->res_pool->hubbub); 962 963 if (dc->res_pool->hubbub->funcs->set_request_limit && dc->config.sdpif_request_limit_words_per_umc > 0) 964 dc->res_pool->hubbub->funcs->set_request_limit(dc->res_pool->hubbub, dc->ctx->dc_bios->vram_info.num_chans, dc->config.sdpif_request_limit_words_per_umc); 965 966 // Get DMCUB capabilities 967 if (dc->ctx->dmub_srv) { 968 dc_dmub_srv_query_caps_cmd(dc->ctx->dmub_srv); 969 dc->caps.dmub_caps.psr = dc->ctx->dmub_srv->dmub->feature_caps.psr; 970 dc->caps.dmub_caps.subvp_psr = dc->ctx->dmub_srv->dmub->feature_caps.subvp_psr_support; 971 dc->caps.dmub_caps.gecc_enable = dc->ctx->dmub_srv->dmub->feature_caps.gecc_enable; 972 dc->caps.dmub_caps.mclk_sw = dc->ctx->dmub_srv->dmub->feature_caps.fw_assisted_mclk_switch; 973 } 974 } 975 976 static int calc_mpc_flow_ctrl_cnt(const struct dc_stream_state *stream, 977 int opp_cnt) 978 { 979 bool hblank_halved = optc2_is_two_pixels_per_containter(&stream->timing); 980 int flow_ctrl_cnt; 981 982 if (opp_cnt >= 2) 983 hblank_halved = true; 984 985 flow_ctrl_cnt = stream->timing.h_total - stream->timing.h_addressable - 986 stream->timing.h_border_left - 987 stream->timing.h_border_right; 988 989 if (hblank_halved) 990 flow_ctrl_cnt /= 2; 991 992 /* ODM combine 4:1 case */ 993 if (opp_cnt == 4) 994 flow_ctrl_cnt /= 2; 995 996 return flow_ctrl_cnt; 997 } 998 999 static void update_dsc_on_stream(struct pipe_ctx *pipe_ctx, bool enable) 1000 { 1001 struct display_stream_compressor *dsc = pipe_ctx->stream_res.dsc; 1002 struct dc_stream_state *stream = pipe_ctx->stream; 1003 struct pipe_ctx *odm_pipe; 1004 int opp_cnt = 1; 1005 1006 ASSERT(dsc); 1007 for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) 1008 opp_cnt++; 1009 1010 if (enable) { 1011 struct dsc_config dsc_cfg; 1012 struct dsc_optc_config dsc_optc_cfg; 1013 enum optc_dsc_mode optc_dsc_mode; 1014 1015 /* Enable DSC hw block */ 1016 dsc_cfg.pic_width = (stream->timing.h_addressable + stream->timing.h_border_left + stream->timing.h_border_right) / opp_cnt; 1017 dsc_cfg.pic_height = stream->timing.v_addressable + stream->timing.v_border_top + stream->timing.v_border_bottom; 1018 dsc_cfg.pixel_encoding = stream->timing.pixel_encoding; 1019 dsc_cfg.color_depth = stream->timing.display_color_depth; 1020 dsc_cfg.is_odm = pipe_ctx->next_odm_pipe ? true : false; 1021 dsc_cfg.dc_dsc_cfg = stream->timing.dsc_cfg; 1022 ASSERT(dsc_cfg.dc_dsc_cfg.num_slices_h % opp_cnt == 0); 1023 dsc_cfg.dc_dsc_cfg.num_slices_h /= opp_cnt; 1024 1025 dsc->funcs->dsc_set_config(dsc, &dsc_cfg, &dsc_optc_cfg); 1026 dsc->funcs->dsc_enable(dsc, pipe_ctx->stream_res.opp->inst); 1027 for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) { 1028 struct display_stream_compressor *odm_dsc = odm_pipe->stream_res.dsc; 1029 1030 ASSERT(odm_dsc); 1031 odm_dsc->funcs->dsc_set_config(odm_dsc, &dsc_cfg, &dsc_optc_cfg); 1032 odm_dsc->funcs->dsc_enable(odm_dsc, odm_pipe->stream_res.opp->inst); 1033 } 1034 dsc_cfg.dc_dsc_cfg.num_slices_h *= opp_cnt; 1035 dsc_cfg.pic_width *= opp_cnt; 1036 1037 optc_dsc_mode = dsc_optc_cfg.is_pixel_format_444 ? OPTC_DSC_ENABLED_444 : OPTC_DSC_ENABLED_NATIVE_SUBSAMPLED; 1038 1039 /* Enable DSC in OPTC */ 1040 DC_LOG_DSC("Setting optc DSC config for tg instance %d:", pipe_ctx->stream_res.tg->inst); 1041 pipe_ctx->stream_res.tg->funcs->set_dsc_config(pipe_ctx->stream_res.tg, 1042 optc_dsc_mode, 1043 dsc_optc_cfg.bytes_per_pixel, 1044 dsc_optc_cfg.slice_width); 1045 } else { 1046 /* disable DSC in OPTC */ 1047 pipe_ctx->stream_res.tg->funcs->set_dsc_config( 1048 pipe_ctx->stream_res.tg, 1049 OPTC_DSC_DISABLED, 0, 0); 1050 1051 /* disable DSC block */ 1052 dsc->funcs->dsc_disable(pipe_ctx->stream_res.dsc); 1053 for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) { 1054 ASSERT(odm_pipe->stream_res.dsc); 1055 odm_pipe->stream_res.dsc->funcs->dsc_disable(odm_pipe->stream_res.dsc); 1056 } 1057 } 1058 } 1059 1060 /* 1061 * Given any pipe_ctx, return the total ODM combine factor, and optionally return 1062 * the OPPids which are used 1063 * */ 1064 static unsigned int get_odm_config(struct pipe_ctx *pipe_ctx, unsigned int *opp_instances) 1065 { 1066 unsigned int opp_count = 1; 1067 struct pipe_ctx *odm_pipe; 1068 1069 /* First get to the top pipe */ 1070 for (odm_pipe = pipe_ctx; odm_pipe->prev_odm_pipe; odm_pipe = odm_pipe->prev_odm_pipe) 1071 ; 1072 1073 /* First pipe is always used */ 1074 if (opp_instances) 1075 opp_instances[0] = odm_pipe->stream_res.opp->inst; 1076 1077 /* Find and count odm pipes, if any */ 1078 for (odm_pipe = odm_pipe->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) { 1079 if (opp_instances) 1080 opp_instances[opp_count] = odm_pipe->stream_res.opp->inst; 1081 opp_count++; 1082 } 1083 1084 return opp_count; 1085 } 1086 1087 void dcn32_update_odm(struct dc *dc, struct dc_state *context, struct pipe_ctx *pipe_ctx) 1088 { 1089 struct pipe_ctx *odm_pipe; 1090 int opp_cnt = 0; 1091 int opp_inst[MAX_PIPES] = {0}; 1092 bool rate_control_2x_pclk = (pipe_ctx->stream->timing.flags.INTERLACE || optc2_is_two_pixels_per_containter(&pipe_ctx->stream->timing)); 1093 struct mpc_dwb_flow_control flow_control; 1094 struct mpc *mpc = dc->res_pool->mpc; 1095 int i; 1096 1097 opp_cnt = get_odm_config(pipe_ctx, opp_inst); 1098 1099 if (opp_cnt > 1) 1100 pipe_ctx->stream_res.tg->funcs->set_odm_combine( 1101 pipe_ctx->stream_res.tg, 1102 opp_inst, opp_cnt, 1103 &pipe_ctx->stream->timing); 1104 else 1105 pipe_ctx->stream_res.tg->funcs->set_odm_bypass( 1106 pipe_ctx->stream_res.tg, &pipe_ctx->stream->timing); 1107 1108 rate_control_2x_pclk = rate_control_2x_pclk || opp_cnt > 1; 1109 flow_control.flow_ctrl_mode = 0; 1110 flow_control.flow_ctrl_cnt0 = 0x80; 1111 flow_control.flow_ctrl_cnt1 = calc_mpc_flow_ctrl_cnt(pipe_ctx->stream, opp_cnt); 1112 if (mpc->funcs->set_out_rate_control) { 1113 for (i = 0; i < opp_cnt; ++i) { 1114 mpc->funcs->set_out_rate_control( 1115 mpc, opp_inst[i], 1116 true, 1117 rate_control_2x_pclk, 1118 &flow_control); 1119 } 1120 } 1121 1122 for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) { 1123 odm_pipe->stream_res.opp->funcs->opp_pipe_clock_control( 1124 odm_pipe->stream_res.opp, 1125 true); 1126 } 1127 1128 if (pipe_ctx->stream_res.dsc) { 1129 struct pipe_ctx *current_pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[pipe_ctx->pipe_idx]; 1130 1131 update_dsc_on_stream(pipe_ctx, pipe_ctx->stream->timing.flags.DSC); 1132 1133 /* Check if no longer using pipe for ODM, then need to disconnect DSC for that pipe */ 1134 if (!pipe_ctx->next_odm_pipe && current_pipe_ctx->next_odm_pipe && 1135 current_pipe_ctx->next_odm_pipe->stream_res.dsc) { 1136 struct display_stream_compressor *dsc = current_pipe_ctx->next_odm_pipe->stream_res.dsc; 1137 /* disconnect DSC block from stream */ 1138 dsc->funcs->dsc_disconnect(dsc); 1139 } 1140 } 1141 } 1142 1143 unsigned int dcn32_calculate_dccg_k1_k2_values(struct pipe_ctx *pipe_ctx, unsigned int *k1_div, unsigned int *k2_div) 1144 { 1145 struct dc_stream_state *stream = pipe_ctx->stream; 1146 unsigned int odm_combine_factor = 0; 1147 bool two_pix_per_container = false; 1148 1149 two_pix_per_container = optc2_is_two_pixels_per_containter(&stream->timing); 1150 odm_combine_factor = get_odm_config(pipe_ctx, NULL); 1151 1152 if (stream->ctx->dc->link_srv->dp_is_128b_132b_signal(pipe_ctx)) { 1153 *k1_div = PIXEL_RATE_DIV_BY_1; 1154 *k2_div = PIXEL_RATE_DIV_BY_1; 1155 } else if (dc_is_hdmi_tmds_signal(stream->signal) || dc_is_dvi_signal(stream->signal)) { 1156 *k1_div = PIXEL_RATE_DIV_BY_1; 1157 if (stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR420) 1158 *k2_div = PIXEL_RATE_DIV_BY_2; 1159 else 1160 *k2_div = PIXEL_RATE_DIV_BY_4; 1161 } else if (dc_is_dp_signal(stream->signal) || dc_is_virtual_signal(stream->signal)) { 1162 if (two_pix_per_container) { 1163 *k1_div = PIXEL_RATE_DIV_BY_1; 1164 *k2_div = PIXEL_RATE_DIV_BY_2; 1165 } else { 1166 *k1_div = PIXEL_RATE_DIV_BY_1; 1167 *k2_div = PIXEL_RATE_DIV_BY_4; 1168 if ((odm_combine_factor == 2) || dcn32_is_dp_dig_pixel_rate_div_policy(pipe_ctx)) 1169 *k2_div = PIXEL_RATE_DIV_BY_2; 1170 } 1171 } 1172 1173 if ((*k1_div == PIXEL_RATE_DIV_NA) && (*k2_div == PIXEL_RATE_DIV_NA)) 1174 ASSERT(false); 1175 1176 return odm_combine_factor; 1177 } 1178 1179 void dcn32_set_pixels_per_cycle(struct pipe_ctx *pipe_ctx) 1180 { 1181 uint32_t pix_per_cycle = 1; 1182 uint32_t odm_combine_factor = 1; 1183 1184 if (!pipe_ctx || !pipe_ctx->stream || !pipe_ctx->stream_res.stream_enc) 1185 return; 1186 1187 odm_combine_factor = get_odm_config(pipe_ctx, NULL); 1188 if (optc2_is_two_pixels_per_containter(&pipe_ctx->stream->timing) || odm_combine_factor > 1 1189 || dcn32_is_dp_dig_pixel_rate_div_policy(pipe_ctx)) 1190 pix_per_cycle = 2; 1191 1192 if (pipe_ctx->stream_res.stream_enc->funcs->set_input_mode) 1193 pipe_ctx->stream_res.stream_enc->funcs->set_input_mode(pipe_ctx->stream_res.stream_enc, 1194 pix_per_cycle); 1195 } 1196 1197 void dcn32_resync_fifo_dccg_dio(struct dce_hwseq *hws, struct dc *dc, struct dc_state *context) 1198 { 1199 unsigned int i; 1200 struct pipe_ctx *pipe = NULL; 1201 bool otg_disabled[MAX_PIPES] = {false}; 1202 1203 for (i = 0; i < dc->res_pool->pipe_count; i++) { 1204 pipe = &dc->current_state->res_ctx.pipe_ctx[i]; 1205 1206 if (!resource_is_pipe_type(pipe, OTG_MASTER)) 1207 continue; 1208 1209 if ((pipe->stream->dpms_off || dc_is_virtual_signal(pipe->stream->signal)) 1210 && pipe->stream->mall_stream_config.type != SUBVP_PHANTOM) { 1211 pipe->stream_res.tg->funcs->disable_crtc(pipe->stream_res.tg); 1212 reset_sync_context_for_pipe(dc, context, i); 1213 otg_disabled[i] = true; 1214 } 1215 } 1216 1217 hws->ctx->dc->res_pool->dccg->funcs->trigger_dio_fifo_resync(hws->ctx->dc->res_pool->dccg); 1218 1219 for (i = 0; i < dc->res_pool->pipe_count; i++) { 1220 pipe = &dc->current_state->res_ctx.pipe_ctx[i]; 1221 1222 if (otg_disabled[i]) 1223 pipe->stream_res.tg->funcs->enable_crtc(pipe->stream_res.tg); 1224 } 1225 } 1226 1227 void dcn32_unblank_stream(struct pipe_ctx *pipe_ctx, 1228 struct dc_link_settings *link_settings) 1229 { 1230 struct encoder_unblank_param params = {0}; 1231 struct dc_stream_state *stream = pipe_ctx->stream; 1232 struct dc_link *link = stream->link; 1233 struct dce_hwseq *hws = link->dc->hwseq; 1234 struct pipe_ctx *odm_pipe; 1235 uint32_t pix_per_cycle = 1; 1236 1237 params.opp_cnt = 1; 1238 for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) 1239 params.opp_cnt++; 1240 1241 /* only 3 items below are used by unblank */ 1242 params.timing = pipe_ctx->stream->timing; 1243 1244 params.link_settings.link_rate = link_settings->link_rate; 1245 1246 if (link->dc->link_srv->dp_is_128b_132b_signal(pipe_ctx)) { 1247 /* TODO - DP2.0 HW: Set ODM mode in dp hpo encoder here */ 1248 pipe_ctx->stream_res.hpo_dp_stream_enc->funcs->dp_unblank( 1249 pipe_ctx->stream_res.hpo_dp_stream_enc, 1250 pipe_ctx->stream_res.tg->inst); 1251 } else if (dc_is_dp_signal(pipe_ctx->stream->signal)) { 1252 if (optc2_is_two_pixels_per_containter(&stream->timing) || params.opp_cnt > 1 1253 || dcn32_is_dp_dig_pixel_rate_div_policy(pipe_ctx)) { 1254 params.timing.pix_clk_100hz /= 2; 1255 pix_per_cycle = 2; 1256 } 1257 pipe_ctx->stream_res.stream_enc->funcs->dp_set_odm_combine( 1258 pipe_ctx->stream_res.stream_enc, pix_per_cycle > 1); 1259 pipe_ctx->stream_res.stream_enc->funcs->dp_unblank(link, pipe_ctx->stream_res.stream_enc, ¶ms); 1260 } 1261 1262 if (link->local_sink && link->local_sink->sink_signal == SIGNAL_TYPE_EDP) 1263 hws->funcs.edp_backlight_control(link, true); 1264 } 1265 1266 bool dcn32_is_dp_dig_pixel_rate_div_policy(struct pipe_ctx *pipe_ctx) 1267 { 1268 struct dc *dc = pipe_ctx->stream->ctx->dc; 1269 1270 if (!is_h_timing_divisible_by_2(pipe_ctx->stream)) 1271 return false; 1272 1273 if (dc_is_dp_signal(pipe_ctx->stream->signal) && !dc->link_srv->dp_is_128b_132b_signal(pipe_ctx) && 1274 dc->debug.enable_dp_dig_pixel_rate_div_policy) 1275 return true; 1276 return false; 1277 } 1278 1279 static void apply_symclk_on_tx_off_wa(struct dc_link *link) 1280 { 1281 /* There are use cases where SYMCLK is referenced by OTG. For instance 1282 * for TMDS signal, OTG relies SYMCLK even if TX video output is off. 1283 * However current link interface will power off PHY when disabling link 1284 * output. This will turn off SYMCLK generated by PHY. The workaround is 1285 * to identify such case where SYMCLK is still in use by OTG when we 1286 * power off PHY. When this is detected, we will temporarily power PHY 1287 * back on and move PHY's SYMCLK state to SYMCLK_ON_TX_OFF by calling 1288 * program_pix_clk interface. When OTG is disabled, we will then power 1289 * off PHY by calling disable link output again. 1290 * 1291 * In future dcn generations, we plan to rework transmitter control 1292 * interface so that we could have an option to set SYMCLK ON TX OFF 1293 * state in one step without this workaround 1294 */ 1295 1296 struct dc *dc = link->ctx->dc; 1297 struct pipe_ctx *pipe_ctx = NULL; 1298 uint8_t i; 1299 1300 if (link->phy_state.symclk_ref_cnts.otg > 0) { 1301 for (i = 0; i < MAX_PIPES; i++) { 1302 pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[i]; 1303 if (resource_is_pipe_type(pipe_ctx, OPP_HEAD) && pipe_ctx->stream->link == link) { 1304 pipe_ctx->clock_source->funcs->program_pix_clk( 1305 pipe_ctx->clock_source, 1306 &pipe_ctx->stream_res.pix_clk_params, 1307 dc->link_srv->dp_get_encoding_format( 1308 &pipe_ctx->link_config.dp_link_settings), 1309 &pipe_ctx->pll_settings); 1310 link->phy_state.symclk_state = SYMCLK_ON_TX_OFF; 1311 break; 1312 } 1313 } 1314 } 1315 } 1316 1317 void dcn32_disable_link_output(struct dc_link *link, 1318 const struct link_resource *link_res, 1319 enum signal_type signal) 1320 { 1321 struct dc *dc = link->ctx->dc; 1322 const struct link_hwss *link_hwss = get_link_hwss(link, link_res); 1323 struct dmcu *dmcu = dc->res_pool->dmcu; 1324 1325 if (signal == SIGNAL_TYPE_EDP && 1326 link->dc->hwss.edp_backlight_control) 1327 link->dc->hwss.edp_backlight_control(link, false); 1328 else if (dmcu != NULL && dmcu->funcs->lock_phy) 1329 dmcu->funcs->lock_phy(dmcu); 1330 1331 link_hwss->disable_link_output(link, link_res, signal); 1332 link->phy_state.symclk_state = SYMCLK_OFF_TX_OFF; 1333 1334 if (signal == SIGNAL_TYPE_EDP && 1335 link->dc->hwss.edp_backlight_control) 1336 link->dc->hwss.edp_power_control(link, false); 1337 else if (dmcu != NULL && dmcu->funcs->lock_phy) 1338 dmcu->funcs->unlock_phy(dmcu); 1339 1340 dc->link_srv->dp_trace_source_sequence(link, DPCD_SOURCE_SEQ_AFTER_DISABLE_LINK_PHY); 1341 1342 apply_symclk_on_tx_off_wa(link); 1343 } 1344 1345 /* For SubVP the main pipe can have a viewport position change 1346 * without a full update. In this case we must also update the 1347 * viewport positions for the phantom pipe accordingly. 1348 */ 1349 void dcn32_update_phantom_vp_position(struct dc *dc, 1350 struct dc_state *context, 1351 struct pipe_ctx *phantom_pipe) 1352 { 1353 uint32_t i; 1354 struct dc_plane_state *phantom_plane = phantom_pipe->plane_state; 1355 1356 for (i = 0; i < dc->res_pool->pipe_count; i++) { 1357 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; 1358 1359 if (pipe->stream && pipe->stream->mall_stream_config.type == SUBVP_MAIN && 1360 pipe->stream->mall_stream_config.paired_stream == phantom_pipe->stream) { 1361 if (pipe->plane_state && pipe->plane_state->update_flags.bits.position_change) { 1362 1363 phantom_plane->src_rect.x = pipe->plane_state->src_rect.x; 1364 phantom_plane->src_rect.y = pipe->plane_state->src_rect.y; 1365 phantom_plane->clip_rect.x = pipe->plane_state->clip_rect.x; 1366 phantom_plane->dst_rect.x = pipe->plane_state->dst_rect.x; 1367 phantom_plane->dst_rect.y = pipe->plane_state->dst_rect.y; 1368 1369 phantom_pipe->plane_state->update_flags.bits.position_change = 1; 1370 resource_build_scaling_params(phantom_pipe); 1371 return; 1372 } 1373 } 1374 } 1375 } 1376 1377 /* Treat the phantom pipe as if it needs to be fully enabled. 1378 * If the pipe was previously in use but not phantom, it would 1379 * have been disabled earlier in the sequence so we need to run 1380 * the full enable sequence. 1381 */ 1382 void dcn32_apply_update_flags_for_phantom(struct pipe_ctx *phantom_pipe) 1383 { 1384 phantom_pipe->update_flags.raw = 0; 1385 if (phantom_pipe->stream && phantom_pipe->stream->mall_stream_config.type == SUBVP_PHANTOM) { 1386 if (resource_is_pipe_type(phantom_pipe, DPP_PIPE)) { 1387 phantom_pipe->update_flags.bits.enable = 1; 1388 phantom_pipe->update_flags.bits.mpcc = 1; 1389 phantom_pipe->update_flags.bits.dppclk = 1; 1390 phantom_pipe->update_flags.bits.hubp_interdependent = 1; 1391 phantom_pipe->update_flags.bits.hubp_rq_dlg_ttu = 1; 1392 phantom_pipe->update_flags.bits.gamut_remap = 1; 1393 phantom_pipe->update_flags.bits.scaler = 1; 1394 phantom_pipe->update_flags.bits.viewport = 1; 1395 phantom_pipe->update_flags.bits.det_size = 1; 1396 if (resource_is_pipe_type(phantom_pipe, OTG_MASTER)) { 1397 phantom_pipe->update_flags.bits.odm = 1; 1398 phantom_pipe->update_flags.bits.global_sync = 1; 1399 } 1400 } 1401 } 1402 } 1403 1404 bool dcn32_dsc_pg_status( 1405 struct dce_hwseq *hws, 1406 unsigned int dsc_inst) 1407 { 1408 uint32_t pwr_status = 0; 1409 1410 switch (dsc_inst) { 1411 case 0: /* DSC0 */ 1412 REG_GET(DOMAIN16_PG_STATUS, 1413 DOMAIN_PGFSM_PWR_STATUS, &pwr_status); 1414 break; 1415 case 1: /* DSC1 */ 1416 1417 REG_GET(DOMAIN17_PG_STATUS, 1418 DOMAIN_PGFSM_PWR_STATUS, &pwr_status); 1419 break; 1420 case 2: /* DSC2 */ 1421 REG_GET(DOMAIN18_PG_STATUS, 1422 DOMAIN_PGFSM_PWR_STATUS, &pwr_status); 1423 break; 1424 case 3: /* DSC3 */ 1425 REG_GET(DOMAIN19_PG_STATUS, 1426 DOMAIN_PGFSM_PWR_STATUS, &pwr_status); 1427 break; 1428 default: 1429 BREAK_TO_DEBUGGER(); 1430 break; 1431 } 1432 1433 return pwr_status == 0; 1434 } 1435 1436 void dcn32_update_dsc_pg(struct dc *dc, 1437 struct dc_state *context, 1438 bool safe_to_disable) 1439 { 1440 struct dce_hwseq *hws = dc->hwseq; 1441 int i; 1442 1443 for (i = 0; i < dc->res_pool->res_cap->num_dsc; i++) { 1444 struct display_stream_compressor *dsc = dc->res_pool->dscs[i]; 1445 bool is_dsc_ungated = hws->funcs.dsc_pg_status(hws, dsc->inst); 1446 1447 if (context->res_ctx.is_dsc_acquired[i]) { 1448 if (!is_dsc_ungated) { 1449 hws->funcs.dsc_pg_control(hws, dsc->inst, true); 1450 } 1451 } else if (safe_to_disable) { 1452 if (is_dsc_ungated) { 1453 hws->funcs.dsc_pg_control(hws, dsc->inst, false); 1454 } 1455 } 1456 } 1457 } 1458 1459 void dcn32_enable_phantom_streams(struct dc *dc, struct dc_state *context) 1460 { 1461 unsigned int i; 1462 1463 for (i = 0; i < dc->res_pool->pipe_count; i++) { 1464 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; 1465 struct pipe_ctx *old_pipe = &dc->current_state->res_ctx.pipe_ctx[i]; 1466 1467 /* If an active, non-phantom pipe is being transitioned into a phantom 1468 * pipe, wait for the double buffer update to complete first before we do 1469 * ANY phantom pipe programming. 1470 */ 1471 if (pipe->stream && pipe->stream->mall_stream_config.type == SUBVP_PHANTOM && 1472 old_pipe->stream && old_pipe->stream->mall_stream_config.type != SUBVP_PHANTOM) { 1473 old_pipe->stream_res.tg->funcs->wait_for_state( 1474 old_pipe->stream_res.tg, 1475 CRTC_STATE_VBLANK); 1476 old_pipe->stream_res.tg->funcs->wait_for_state( 1477 old_pipe->stream_res.tg, 1478 CRTC_STATE_VACTIVE); 1479 } 1480 } 1481 for (i = 0; i < dc->res_pool->pipe_count; i++) { 1482 struct pipe_ctx *new_pipe = &context->res_ctx.pipe_ctx[i]; 1483 1484 if (new_pipe->stream && new_pipe->stream->mall_stream_config.type == SUBVP_PHANTOM) { 1485 // If old context or new context has phantom pipes, apply 1486 // the phantom timings now. We can't change the phantom 1487 // pipe configuration safely without driver acquiring 1488 // the DMCUB lock first. 1489 dc->hwss.apply_ctx_to_hw(dc, context); 1490 break; 1491 } 1492 } 1493 } 1494 1495 /* Blank pixel data during initialization */ 1496 void dcn32_init_blank( 1497 struct dc *dc, 1498 struct timing_generator *tg) 1499 { 1500 struct dce_hwseq *hws = dc->hwseq; 1501 enum dc_color_space color_space; 1502 struct tg_color black_color = {0}; 1503 struct output_pixel_processor *opp = NULL; 1504 struct output_pixel_processor *bottom_opp = NULL; 1505 uint32_t num_opps, opp_id_src0, opp_id_src1; 1506 uint32_t otg_active_width, otg_active_height; 1507 uint32_t i; 1508 1509 /* program opp dpg blank color */ 1510 color_space = COLOR_SPACE_SRGB; 1511 color_space_to_black_color(dc, color_space, &black_color); 1512 1513 /* get the OTG active size */ 1514 tg->funcs->get_otg_active_size(tg, 1515 &otg_active_width, 1516 &otg_active_height); 1517 1518 /* get the OPTC source */ 1519 tg->funcs->get_optc_source(tg, &num_opps, &opp_id_src0, &opp_id_src1); 1520 1521 if (opp_id_src0 >= dc->res_pool->res_cap->num_opp) { 1522 ASSERT(false); 1523 return; 1524 } 1525 1526 for (i = 0; i < dc->res_pool->res_cap->num_opp; i++) { 1527 if (dc->res_pool->opps[i] != NULL && dc->res_pool->opps[i]->inst == opp_id_src0) { 1528 opp = dc->res_pool->opps[i]; 1529 break; 1530 } 1531 } 1532 1533 if (num_opps == 2) { 1534 otg_active_width = otg_active_width / 2; 1535 1536 if (opp_id_src1 >= dc->res_pool->res_cap->num_opp) { 1537 ASSERT(false); 1538 return; 1539 } 1540 for (i = 0; i < dc->res_pool->res_cap->num_opp; i++) { 1541 if (dc->res_pool->opps[i] != NULL && dc->res_pool->opps[i]->inst == opp_id_src1) { 1542 bottom_opp = dc->res_pool->opps[i]; 1543 break; 1544 } 1545 } 1546 } 1547 1548 if (opp && opp->funcs->opp_set_disp_pattern_generator) 1549 opp->funcs->opp_set_disp_pattern_generator( 1550 opp, 1551 CONTROLLER_DP_TEST_PATTERN_SOLID_COLOR, 1552 CONTROLLER_DP_COLOR_SPACE_UDEFINED, 1553 COLOR_DEPTH_UNDEFINED, 1554 &black_color, 1555 otg_active_width, 1556 otg_active_height, 1557 0); 1558 1559 if (num_opps == 2) { 1560 if (bottom_opp && bottom_opp->funcs->opp_set_disp_pattern_generator) { 1561 bottom_opp->funcs->opp_set_disp_pattern_generator( 1562 bottom_opp, 1563 CONTROLLER_DP_TEST_PATTERN_SOLID_COLOR, 1564 CONTROLLER_DP_COLOR_SPACE_UDEFINED, 1565 COLOR_DEPTH_UNDEFINED, 1566 &black_color, 1567 otg_active_width, 1568 otg_active_height, 1569 0); 1570 hws->funcs.wait_for_blank_complete(bottom_opp); 1571 } 1572 } 1573 1574 if (opp) 1575 hws->funcs.wait_for_blank_complete(opp); 1576 } 1577 1578 void dcn32_blank_phantom(struct dc *dc, 1579 struct timing_generator *tg, 1580 int width, 1581 int height) 1582 { 1583 struct dce_hwseq *hws = dc->hwseq; 1584 enum dc_color_space color_space; 1585 struct tg_color black_color = {0}; 1586 struct output_pixel_processor *opp = NULL; 1587 uint32_t num_opps, opp_id_src0, opp_id_src1; 1588 uint32_t otg_active_width, otg_active_height; 1589 uint32_t i; 1590 1591 /* program opp dpg blank color */ 1592 color_space = COLOR_SPACE_SRGB; 1593 color_space_to_black_color(dc, color_space, &black_color); 1594 1595 otg_active_width = width; 1596 otg_active_height = height; 1597 1598 /* get the OPTC source */ 1599 tg->funcs->get_optc_source(tg, &num_opps, &opp_id_src0, &opp_id_src1); 1600 ASSERT(opp_id_src0 < dc->res_pool->res_cap->num_opp); 1601 1602 for (i = 0; i < dc->res_pool->res_cap->num_opp; i++) { 1603 if (dc->res_pool->opps[i] != NULL && dc->res_pool->opps[i]->inst == opp_id_src0) { 1604 opp = dc->res_pool->opps[i]; 1605 break; 1606 } 1607 } 1608 1609 if (opp && opp->funcs->opp_set_disp_pattern_generator) 1610 opp->funcs->opp_set_disp_pattern_generator( 1611 opp, 1612 CONTROLLER_DP_TEST_PATTERN_SOLID_COLOR, 1613 CONTROLLER_DP_COLOR_SPACE_UDEFINED, 1614 COLOR_DEPTH_UNDEFINED, 1615 &black_color, 1616 otg_active_width, 1617 otg_active_height, 1618 0); 1619 1620 if (tg->funcs->is_tg_enabled(tg)) 1621 hws->funcs.wait_for_blank_complete(opp); 1622 } 1623 1624 bool dcn32_is_pipe_topology_transition_seamless(struct dc *dc, 1625 const struct dc_state *cur_ctx, 1626 const struct dc_state *new_ctx) 1627 { 1628 int i; 1629 const struct pipe_ctx *cur_pipe, *new_pipe; 1630 bool is_seamless = true; 1631 1632 for (i = 0; i < dc->res_pool->pipe_count; i++) { 1633 cur_pipe = &cur_ctx->res_ctx.pipe_ctx[i]; 1634 new_pipe = &new_ctx->res_ctx.pipe_ctx[i]; 1635 1636 if (resource_is_pipe_type(cur_pipe, FREE_PIPE) || 1637 resource_is_pipe_type(new_pipe, FREE_PIPE)) 1638 /* adding or removing free pipes is always seamless */ 1639 continue; 1640 else if (resource_is_pipe_type(cur_pipe, OTG_MASTER)) { 1641 if (resource_is_pipe_type(new_pipe, OTG_MASTER)) 1642 if (cur_pipe->stream->stream_id == new_pipe->stream->stream_id) 1643 /* OTG master with the same stream is seamless */ 1644 continue; 1645 } else if (resource_is_pipe_type(cur_pipe, OPP_HEAD)) { 1646 if (resource_is_pipe_type(new_pipe, OPP_HEAD)) { 1647 if (cur_pipe->stream_res.tg == new_pipe->stream_res.tg) 1648 /* 1649 * OPP heads sharing the same timing 1650 * generator is seamless 1651 */ 1652 continue; 1653 } 1654 } else if (resource_is_pipe_type(cur_pipe, DPP_PIPE)) { 1655 if (resource_is_pipe_type(new_pipe, DPP_PIPE)) { 1656 if (cur_pipe->stream_res.opp == new_pipe->stream_res.opp) 1657 /* 1658 * DPP pipes sharing the same OPP head is 1659 * seamless 1660 */ 1661 continue; 1662 } 1663 } 1664 1665 /* 1666 * This pipe's transition doesn't fall under any seamless 1667 * conditions 1668 */ 1669 is_seamless = false; 1670 break; 1671 } 1672 1673 return is_seamless; 1674 } 1675