1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 27 #include "dm_services.h" 28 #include "dm_helpers.h" 29 #include "core_types.h" 30 #include "resource.h" 31 #include "dccg.h" 32 #include "dce/dce_hwseq.h" 33 #include "dcn30/dcn30_cm_common.h" 34 #include "reg_helper.h" 35 #include "abm.h" 36 #include "hubp.h" 37 #include "dchubbub.h" 38 #include "timing_generator.h" 39 #include "opp.h" 40 #include "ipp.h" 41 #include "mpc.h" 42 #include "mcif_wb.h" 43 #include "dc_dmub_srv.h" 44 #include "link_hwss.h" 45 #include "dpcd_defs.h" 46 #include "dcn32_hwseq.h" 47 #include "clk_mgr.h" 48 #include "dsc.h" 49 #include "dcn20/dcn20_optc.h" 50 #include "dmub_subvp_state.h" 51 #include "dce/dmub_hw_lock_mgr.h" 52 #include "dcn32_resource.h" 53 #include "link.h" 54 #include "dc_link_dp.h" 55 #include "dmub/inc/dmub_subvp_state.h" 56 57 #define DC_LOGGER_INIT(logger) 58 59 #define CTX \ 60 hws->ctx 61 #define REG(reg)\ 62 hws->regs->reg 63 #define DC_LOGGER \ 64 dc->ctx->logger 65 66 67 #undef FN 68 #define FN(reg_name, field_name) \ 69 hws->shifts->field_name, hws->masks->field_name 70 71 void dcn32_dsc_pg_control( 72 struct dce_hwseq *hws, 73 unsigned int dsc_inst, 74 bool power_on) 75 { 76 uint32_t power_gate = power_on ? 0 : 1; 77 uint32_t pwr_status = power_on ? 0 : 2; 78 uint32_t org_ip_request_cntl = 0; 79 80 if (hws->ctx->dc->debug.disable_dsc_power_gate) 81 return; 82 83 REG_GET(DC_IP_REQUEST_CNTL, IP_REQUEST_EN, &org_ip_request_cntl); 84 if (org_ip_request_cntl == 0) 85 REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 1); 86 87 switch (dsc_inst) { 88 case 0: /* DSC0 */ 89 REG_UPDATE(DOMAIN16_PG_CONFIG, 90 DOMAIN_POWER_GATE, power_gate); 91 92 REG_WAIT(DOMAIN16_PG_STATUS, 93 DOMAIN_PGFSM_PWR_STATUS, pwr_status, 94 1, 1000); 95 break; 96 case 1: /* DSC1 */ 97 REG_UPDATE(DOMAIN17_PG_CONFIG, 98 DOMAIN_POWER_GATE, power_gate); 99 100 REG_WAIT(DOMAIN17_PG_STATUS, 101 DOMAIN_PGFSM_PWR_STATUS, pwr_status, 102 1, 1000); 103 break; 104 case 2: /* DSC2 */ 105 REG_UPDATE(DOMAIN18_PG_CONFIG, 106 DOMAIN_POWER_GATE, power_gate); 107 108 REG_WAIT(DOMAIN18_PG_STATUS, 109 DOMAIN_PGFSM_PWR_STATUS, pwr_status, 110 1, 1000); 111 break; 112 case 3: /* DSC3 */ 113 REG_UPDATE(DOMAIN19_PG_CONFIG, 114 DOMAIN_POWER_GATE, power_gate); 115 116 REG_WAIT(DOMAIN19_PG_STATUS, 117 DOMAIN_PGFSM_PWR_STATUS, pwr_status, 118 1, 1000); 119 break; 120 default: 121 BREAK_TO_DEBUGGER(); 122 break; 123 } 124 125 if (org_ip_request_cntl == 0) 126 REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 0); 127 } 128 129 130 void dcn32_enable_power_gating_plane( 131 struct dce_hwseq *hws, 132 bool enable) 133 { 134 bool force_on = true; /* disable power gating */ 135 136 if (enable) 137 force_on = false; 138 139 /* DCHUBP0/1/2/3 */ 140 REG_UPDATE(DOMAIN0_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on); 141 REG_UPDATE(DOMAIN1_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on); 142 REG_UPDATE(DOMAIN2_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on); 143 REG_UPDATE(DOMAIN3_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on); 144 145 /* DCS0/1/2/3 */ 146 REG_UPDATE(DOMAIN16_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on); 147 REG_UPDATE(DOMAIN17_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on); 148 REG_UPDATE(DOMAIN18_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on); 149 REG_UPDATE(DOMAIN19_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on); 150 } 151 152 void dcn32_hubp_pg_control(struct dce_hwseq *hws, unsigned int hubp_inst, bool power_on) 153 { 154 uint32_t power_gate = power_on ? 0 : 1; 155 uint32_t pwr_status = power_on ? 0 : 2; 156 157 if (hws->ctx->dc->debug.disable_hubp_power_gate) 158 return; 159 160 if (REG(DOMAIN0_PG_CONFIG) == 0) 161 return; 162 163 switch (hubp_inst) { 164 case 0: 165 REG_SET(DOMAIN0_PG_CONFIG, 0, DOMAIN_POWER_GATE, power_gate); 166 REG_WAIT(DOMAIN0_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, pwr_status, 1, 1000); 167 break; 168 case 1: 169 REG_SET(DOMAIN1_PG_CONFIG, 0, DOMAIN_POWER_GATE, power_gate); 170 REG_WAIT(DOMAIN1_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, pwr_status, 1, 1000); 171 break; 172 case 2: 173 REG_SET(DOMAIN2_PG_CONFIG, 0, DOMAIN_POWER_GATE, power_gate); 174 REG_WAIT(DOMAIN2_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, pwr_status, 1, 1000); 175 break; 176 case 3: 177 REG_SET(DOMAIN3_PG_CONFIG, 0, DOMAIN_POWER_GATE, power_gate); 178 REG_WAIT(DOMAIN3_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, pwr_status, 1, 1000); 179 break; 180 default: 181 BREAK_TO_DEBUGGER(); 182 break; 183 } 184 } 185 186 static bool dcn32_check_no_memory_request_for_cab(struct dc *dc) 187 { 188 int i; 189 190 /* First, check no-memory-request case */ 191 for (i = 0; i < dc->current_state->stream_count; i++) { 192 if ((dc->current_state->stream_status[i].plane_count) && 193 (dc->current_state->streams[i]->link->psr_settings.psr_version == DC_PSR_VERSION_UNSUPPORTED)) 194 /* Fail eligibility on a visible stream */ 195 break; 196 } 197 198 if (i == dc->current_state->stream_count) 199 return true; 200 201 return false; 202 } 203 204 205 /* This function loops through every surface that needs to be cached in CAB for SS, 206 * and calculates the total number of ways required to store all surfaces (primary, 207 * meta, cursor). 208 */ 209 static uint32_t dcn32_calculate_cab_allocation(struct dc *dc, struct dc_state *ctx) 210 { 211 int i; 212 uint8_t num_ways = 0; 213 uint32_t mall_ss_size_bytes = 0; 214 215 mall_ss_size_bytes = ctx->bw_ctx.bw.dcn.mall_ss_size_bytes; 216 // TODO add additional logic for PSR active stream exclusion optimization 217 // mall_ss_psr_active_size_bytes = ctx->bw_ctx.bw.dcn.mall_ss_psr_active_size_bytes; 218 219 // Include cursor size for CAB allocation 220 for (i = 0; i < dc->res_pool->pipe_count; i++) { 221 struct pipe_ctx *pipe = &ctx->res_ctx.pipe_ctx[i]; 222 223 if (!pipe->stream || !pipe->plane_state) 224 continue; 225 226 mall_ss_size_bytes += dcn32_helper_calculate_mall_bytes_for_cursor(dc, pipe, false); 227 } 228 229 // Convert number of cache lines required to number of ways 230 if (dc->debug.force_mall_ss_num_ways > 0) { 231 num_ways = dc->debug.force_mall_ss_num_ways; 232 } else { 233 num_ways = dcn32_helper_mall_bytes_to_ways(dc, mall_ss_size_bytes); 234 } 235 236 return num_ways; 237 } 238 239 bool dcn32_apply_idle_power_optimizations(struct dc *dc, bool enable) 240 { 241 union dmub_rb_cmd cmd; 242 uint8_t ways, i; 243 int j; 244 bool mall_ss_unsupported = false; 245 struct dc_plane_state *plane = NULL; 246 247 if (!dc->ctx->dmub_srv) 248 return false; 249 250 for (i = 0; i < dc->current_state->stream_count; i++) { 251 /* MALL SS messaging is not supported with PSR at this time */ 252 if (dc->current_state->streams[i] != NULL && 253 dc->current_state->streams[i]->link->psr_settings.psr_version != DC_PSR_VERSION_UNSUPPORTED) 254 return false; 255 } 256 257 if (enable) { 258 if (dc->current_state) { 259 260 /* 1. Check no memory request case for CAB. 261 * If no memory request case, send CAB_ACTION NO_DF_REQ DMUB message 262 */ 263 if (dcn32_check_no_memory_request_for_cab(dc)) { 264 /* Enable no-memory-requests case */ 265 memset(&cmd, 0, sizeof(cmd)); 266 cmd.cab.header.type = DMUB_CMD__CAB_FOR_SS; 267 cmd.cab.header.sub_type = DMUB_CMD__CAB_NO_DCN_REQ; 268 cmd.cab.header.payload_bytes = sizeof(cmd.cab) - sizeof(cmd.cab.header); 269 270 dc_dmub_srv_cmd_queue(dc->ctx->dmub_srv, &cmd); 271 dc_dmub_srv_cmd_execute(dc->ctx->dmub_srv); 272 273 return true; 274 } 275 276 /* 2. Check if all surfaces can fit in CAB. 277 * If surfaces can fit into CAB, send CAB_ACTION_ALLOW DMUB message 278 * and configure HUBP's to fetch from MALL 279 */ 280 ways = dcn32_calculate_cab_allocation(dc, dc->current_state); 281 282 /* MALL not supported with Stereo3D or TMZ surface. If any plane is using stereo, 283 * or TMZ surface, don't try to enter MALL. 284 */ 285 for (i = 0; i < dc->current_state->stream_count; i++) { 286 for (j = 0; j < dc->current_state->stream_status[i].plane_count; j++) { 287 plane = dc->current_state->stream_status[i].plane_states[j]; 288 289 if (plane->address.type == PLN_ADDR_TYPE_GRPH_STEREO || 290 plane->address.tmz_surface) { 291 mall_ss_unsupported = true; 292 break; 293 } 294 } 295 if (mall_ss_unsupported) 296 break; 297 } 298 if (ways <= dc->caps.cache_num_ways && !mall_ss_unsupported) { 299 memset(&cmd, 0, sizeof(cmd)); 300 cmd.cab.header.type = DMUB_CMD__CAB_FOR_SS; 301 cmd.cab.header.sub_type = DMUB_CMD__CAB_DCN_SS_FIT_IN_CAB; 302 cmd.cab.header.payload_bytes = sizeof(cmd.cab) - sizeof(cmd.cab.header); 303 cmd.cab.cab_alloc_ways = ways; 304 305 dc_dmub_srv_cmd_queue(dc->ctx->dmub_srv, &cmd); 306 dc_dmub_srv_cmd_execute(dc->ctx->dmub_srv); 307 308 return true; 309 } 310 311 } 312 return false; 313 } 314 315 /* Disable CAB */ 316 memset(&cmd, 0, sizeof(cmd)); 317 cmd.cab.header.type = DMUB_CMD__CAB_FOR_SS; 318 cmd.cab.header.sub_type = DMUB_CMD__CAB_NO_IDLE_OPTIMIZATION; 319 cmd.cab.header.payload_bytes = 320 sizeof(cmd.cab) - sizeof(cmd.cab.header); 321 322 dc_dmub_srv_cmd_queue(dc->ctx->dmub_srv, &cmd); 323 dc_dmub_srv_cmd_execute(dc->ctx->dmub_srv); 324 dc_dmub_srv_wait_idle(dc->ctx->dmub_srv); 325 326 return true; 327 } 328 329 /* Send DMCUB message with SubVP pipe info 330 * - For each pipe in context, populate payload with required SubVP information 331 * if the pipe is using SubVP for MCLK switch 332 * - This function must be called while the DMUB HW lock is acquired by driver 333 */ 334 void dcn32_commit_subvp_config(struct dc *dc, struct dc_state *context) 335 { 336 int i; 337 bool enable_subvp = false; 338 339 if (!dc->ctx || !dc->ctx->dmub_srv) 340 return; 341 342 for (i = 0; i < dc->res_pool->pipe_count; i++) { 343 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; 344 345 if (pipe_ctx->stream && pipe_ctx->stream->mall_stream_config.paired_stream && 346 pipe_ctx->stream->mall_stream_config.type == SUBVP_MAIN) { 347 // There is at least 1 SubVP pipe, so enable SubVP 348 enable_subvp = true; 349 break; 350 } 351 } 352 dc_dmub_setup_subvp_dmub_command(dc, context, enable_subvp); 353 } 354 355 /* Sub-Viewport DMUB lock needs to be acquired by driver whenever SubVP is active and: 356 * 1. Any full update for any SubVP main pipe 357 * 2. Any immediate flip for any SubVP pipe 358 * 3. Any flip for DRR pipe 359 * 4. If SubVP was previously in use (i.e. in old context) 360 */ 361 void dcn32_subvp_pipe_control_lock(struct dc *dc, 362 struct dc_state *context, 363 bool lock, 364 bool should_lock_all_pipes, 365 struct pipe_ctx *top_pipe_to_program, 366 bool subvp_prev_use) 367 { 368 unsigned int i = 0; 369 bool subvp_immediate_flip = false; 370 bool subvp_in_use = false; 371 struct pipe_ctx *pipe; 372 373 for (i = 0; i < dc->res_pool->pipe_count; i++) { 374 pipe = &context->res_ctx.pipe_ctx[i]; 375 376 if (pipe->stream && pipe->plane_state && pipe->stream->mall_stream_config.type == SUBVP_MAIN) { 377 subvp_in_use = true; 378 break; 379 } 380 } 381 382 if (top_pipe_to_program && top_pipe_to_program->stream && top_pipe_to_program->plane_state) { 383 if (top_pipe_to_program->stream->mall_stream_config.type == SUBVP_MAIN && 384 top_pipe_to_program->plane_state->flip_immediate) 385 subvp_immediate_flip = true; 386 } 387 388 // Don't need to lock for DRR VSYNC flips -- FW will wait for DRR pending update cleared. 389 if ((subvp_in_use && (should_lock_all_pipes || subvp_immediate_flip)) || (!subvp_in_use && subvp_prev_use)) { 390 union dmub_inbox0_cmd_lock_hw hw_lock_cmd = { 0 }; 391 392 if (!lock) { 393 for (i = 0; i < dc->res_pool->pipe_count; i++) { 394 pipe = &context->res_ctx.pipe_ctx[i]; 395 if (pipe->stream && pipe->plane_state && pipe->stream->mall_stream_config.type == SUBVP_MAIN && 396 should_lock_all_pipes) 397 pipe->stream_res.tg->funcs->wait_for_state(pipe->stream_res.tg, CRTC_STATE_VBLANK); 398 } 399 } 400 401 hw_lock_cmd.bits.command_code = DMUB_INBOX0_CMD__HW_LOCK; 402 hw_lock_cmd.bits.hw_lock_client = HW_LOCK_CLIENT_DRIVER; 403 hw_lock_cmd.bits.lock = lock; 404 hw_lock_cmd.bits.should_release = !lock; 405 dmub_hw_lock_mgr_inbox0_cmd(dc->ctx->dmub_srv, hw_lock_cmd); 406 } 407 } 408 409 410 static bool dcn32_set_mpc_shaper_3dlut( 411 struct pipe_ctx *pipe_ctx, const struct dc_stream_state *stream) 412 { 413 struct dpp *dpp_base = pipe_ctx->plane_res.dpp; 414 int mpcc_id = pipe_ctx->plane_res.hubp->inst; 415 struct mpc *mpc = pipe_ctx->stream_res.opp->ctx->dc->res_pool->mpc; 416 bool result = false; 417 418 const struct pwl_params *shaper_lut = NULL; 419 //get the shaper lut params 420 if (stream->func_shaper) { 421 if (stream->func_shaper->type == TF_TYPE_HWPWL) 422 shaper_lut = &stream->func_shaper->pwl; 423 else if (stream->func_shaper->type == TF_TYPE_DISTRIBUTED_POINTS) { 424 cm_helper_translate_curve_to_hw_format( 425 stream->func_shaper, 426 &dpp_base->shaper_params, true); 427 shaper_lut = &dpp_base->shaper_params; 428 } 429 } 430 431 if (stream->lut3d_func && 432 stream->lut3d_func->state.bits.initialized == 1) { 433 434 result = mpc->funcs->program_3dlut(mpc, 435 &stream->lut3d_func->lut_3d, 436 mpcc_id); 437 438 result = mpc->funcs->program_shaper(mpc, 439 shaper_lut, 440 mpcc_id); 441 } 442 443 return result; 444 } 445 446 bool dcn32_set_mcm_luts( 447 struct pipe_ctx *pipe_ctx, const struct dc_plane_state *plane_state) 448 { 449 struct dpp *dpp_base = pipe_ctx->plane_res.dpp; 450 int mpcc_id = pipe_ctx->plane_res.hubp->inst; 451 struct mpc *mpc = pipe_ctx->stream_res.opp->ctx->dc->res_pool->mpc; 452 bool result = true; 453 struct pwl_params *lut_params = NULL; 454 455 // 1D LUT 456 if (plane_state->blend_tf) { 457 if (plane_state->blend_tf->type == TF_TYPE_HWPWL) 458 lut_params = &plane_state->blend_tf->pwl; 459 else if (plane_state->blend_tf->type == TF_TYPE_DISTRIBUTED_POINTS) { 460 cm_helper_translate_curve_to_hw_format( 461 plane_state->blend_tf, 462 &dpp_base->regamma_params, false); 463 lut_params = &dpp_base->regamma_params; 464 } 465 } 466 result = mpc->funcs->program_1dlut(mpc, lut_params, mpcc_id); 467 468 // Shaper 469 if (plane_state->in_shaper_func) { 470 if (plane_state->in_shaper_func->type == TF_TYPE_HWPWL) 471 lut_params = &plane_state->in_shaper_func->pwl; 472 else if (plane_state->in_shaper_func->type == TF_TYPE_DISTRIBUTED_POINTS) { 473 // TODO: dpp_base replace 474 ASSERT(false); 475 cm_helper_translate_curve_to_hw_format( 476 plane_state->in_shaper_func, 477 &dpp_base->shaper_params, true); 478 lut_params = &dpp_base->shaper_params; 479 } 480 } 481 482 result = mpc->funcs->program_shaper(mpc, lut_params, mpcc_id); 483 484 // 3D 485 if (plane_state->lut3d_func && plane_state->lut3d_func->state.bits.initialized == 1) 486 result = mpc->funcs->program_3dlut(mpc, &plane_state->lut3d_func->lut_3d, mpcc_id); 487 else 488 result = mpc->funcs->program_3dlut(mpc, NULL, mpcc_id); 489 490 return result; 491 } 492 493 bool dcn32_set_input_transfer_func(struct dc *dc, 494 struct pipe_ctx *pipe_ctx, 495 const struct dc_plane_state *plane_state) 496 { 497 struct dce_hwseq *hws = dc->hwseq; 498 struct mpc *mpc = dc->res_pool->mpc; 499 struct dpp *dpp_base = pipe_ctx->plane_res.dpp; 500 501 enum dc_transfer_func_predefined tf; 502 bool result = true; 503 struct pwl_params *params = NULL; 504 505 if (mpc == NULL || plane_state == NULL) 506 return false; 507 508 tf = TRANSFER_FUNCTION_UNITY; 509 510 if (plane_state->in_transfer_func && 511 plane_state->in_transfer_func->type == TF_TYPE_PREDEFINED) 512 tf = plane_state->in_transfer_func->tf; 513 514 dpp_base->funcs->dpp_set_pre_degam(dpp_base, tf); 515 516 if (plane_state->in_transfer_func) { 517 if (plane_state->in_transfer_func->type == TF_TYPE_HWPWL) 518 params = &plane_state->in_transfer_func->pwl; 519 else if (plane_state->in_transfer_func->type == TF_TYPE_DISTRIBUTED_POINTS && 520 cm3_helper_translate_curve_to_hw_format(plane_state->in_transfer_func, 521 &dpp_base->degamma_params, false)) 522 params = &dpp_base->degamma_params; 523 } 524 525 dpp_base->funcs->dpp_program_gamcor_lut(dpp_base, params); 526 527 if (pipe_ctx->stream_res.opp && 528 pipe_ctx->stream_res.opp->ctx && 529 hws->funcs.set_mcm_luts) 530 result = hws->funcs.set_mcm_luts(pipe_ctx, plane_state); 531 532 return result; 533 } 534 535 bool dcn32_set_output_transfer_func(struct dc *dc, 536 struct pipe_ctx *pipe_ctx, 537 const struct dc_stream_state *stream) 538 { 539 int mpcc_id = pipe_ctx->plane_res.hubp->inst; 540 struct mpc *mpc = pipe_ctx->stream_res.opp->ctx->dc->res_pool->mpc; 541 struct pwl_params *params = NULL; 542 bool ret = false; 543 544 /* program OGAM or 3DLUT only for the top pipe*/ 545 if (pipe_ctx->top_pipe == NULL) { 546 /*program shaper and 3dlut in MPC*/ 547 ret = dcn32_set_mpc_shaper_3dlut(pipe_ctx, stream); 548 if (ret == false && mpc->funcs->set_output_gamma && stream->out_transfer_func) { 549 if (stream->out_transfer_func->type == TF_TYPE_HWPWL) 550 params = &stream->out_transfer_func->pwl; 551 else if (pipe_ctx->stream->out_transfer_func->type == 552 TF_TYPE_DISTRIBUTED_POINTS && 553 cm3_helper_translate_curve_to_hw_format( 554 stream->out_transfer_func, 555 &mpc->blender_params, false)) 556 params = &mpc->blender_params; 557 /* there are no ROM LUTs in OUTGAM */ 558 if (stream->out_transfer_func->type == TF_TYPE_PREDEFINED) 559 BREAK_TO_DEBUGGER(); 560 } 561 } 562 563 mpc->funcs->set_output_gamma(mpc, mpcc_id, params); 564 return ret; 565 } 566 567 /* Program P-State force value according to if pipe is using SubVP or not: 568 * 1. Reset P-State force on all pipes first 569 * 2. For each main pipe, force P-State disallow (P-State allow moderated by DMUB) 570 */ 571 void dcn32_subvp_update_force_pstate(struct dc *dc, struct dc_state *context) 572 { 573 int i; 574 int num_subvp = 0; 575 /* Unforce p-state for each pipe 576 */ 577 for (i = 0; i < dc->res_pool->pipe_count; i++) { 578 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; 579 struct hubp *hubp = pipe->plane_res.hubp; 580 581 if (hubp && hubp->funcs->hubp_update_force_pstate_disallow) 582 hubp->funcs->hubp_update_force_pstate_disallow(hubp, false); 583 if (pipe->stream && pipe->stream->mall_stream_config.type == SUBVP_MAIN) 584 num_subvp++; 585 } 586 587 if (num_subvp == 0) 588 return; 589 590 /* Loop through each pipe -- for each subvp main pipe force p-state allow equal to false. 591 */ 592 for (i = 0; i < dc->res_pool->pipe_count; i++) { 593 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; 594 595 if (pipe->stream && pipe->plane_state && (pipe->stream->mall_stream_config.type == SUBVP_MAIN)) { 596 struct hubp *hubp = pipe->plane_res.hubp; 597 598 if (hubp && hubp->funcs->hubp_update_force_pstate_disallow) 599 hubp->funcs->hubp_update_force_pstate_disallow(hubp, true); 600 } 601 } 602 } 603 604 /* Update MALL_SEL register based on if pipe / plane 605 * is a phantom pipe, main pipe, and if using MALL 606 * for SS. 607 */ 608 void dcn32_update_mall_sel(struct dc *dc, struct dc_state *context) 609 { 610 int i; 611 unsigned int num_ways = dcn32_calculate_cab_allocation(dc, context); 612 bool cache_cursor = false; 613 614 for (i = 0; i < dc->res_pool->pipe_count; i++) { 615 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; 616 struct hubp *hubp = pipe->plane_res.hubp; 617 618 if (pipe->stream && pipe->plane_state && hubp && hubp->funcs->hubp_update_mall_sel) { 619 int cursor_size = hubp->curs_attr.pitch * hubp->curs_attr.height; 620 621 switch (hubp->curs_attr.color_format) { 622 case CURSOR_MODE_MONO: 623 cursor_size /= 2; 624 break; 625 case CURSOR_MODE_COLOR_1BIT_AND: 626 case CURSOR_MODE_COLOR_PRE_MULTIPLIED_ALPHA: 627 case CURSOR_MODE_COLOR_UN_PRE_MULTIPLIED_ALPHA: 628 cursor_size *= 4; 629 break; 630 631 case CURSOR_MODE_COLOR_64BIT_FP_PRE_MULTIPLIED: 632 case CURSOR_MODE_COLOR_64BIT_FP_UN_PRE_MULTIPLIED: 633 default: 634 cursor_size *= 8; 635 break; 636 } 637 638 if (cursor_size > 16384) 639 cache_cursor = true; 640 641 if (pipe->stream->mall_stream_config.type == SUBVP_PHANTOM) { 642 hubp->funcs->hubp_update_mall_sel(hubp, 1, false); 643 } else { 644 // MALL not supported with Stereo3D 645 hubp->funcs->hubp_update_mall_sel(hubp, 646 num_ways <= dc->caps.cache_num_ways && 647 pipe->stream->link->psr_settings.psr_version == DC_PSR_VERSION_UNSUPPORTED && 648 pipe->plane_state->address.type != PLN_ADDR_TYPE_GRPH_STEREO && 649 !pipe->plane_state->address.tmz_surface ? 2 : 0, 650 cache_cursor); 651 } 652 } 653 } 654 } 655 656 /* Program the sub-viewport pipe configuration after the main / phantom pipes 657 * have been programmed in hardware. 658 * 1. Update force P-State for all the main pipes (disallow P-state) 659 * 2. Update MALL_SEL register 660 * 3. Program FORCE_ONE_ROW_FOR_FRAME for main subvp pipes 661 */ 662 void dcn32_program_mall_pipe_config(struct dc *dc, struct dc_state *context) 663 { 664 int i; 665 struct dce_hwseq *hws = dc->hwseq; 666 667 // Don't force p-state disallow -- can't block dummy p-state 668 669 // Update MALL_SEL register for each pipe 670 if (hws && hws->funcs.update_mall_sel) 671 hws->funcs.update_mall_sel(dc, context); 672 673 //update subvp force pstate 674 if (hws && hws->funcs.subvp_update_force_pstate) 675 dc->hwseq->funcs.subvp_update_force_pstate(dc, context); 676 677 // Program FORCE_ONE_ROW_FOR_FRAME and CURSOR_REQ_MODE for main subvp pipes 678 for (i = 0; i < dc->res_pool->pipe_count; i++) { 679 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; 680 struct hubp *hubp = pipe->plane_res.hubp; 681 682 if (pipe->stream && hubp && hubp->funcs->hubp_prepare_subvp_buffering) { 683 /* TODO - remove setting CURSOR_REQ_MODE to 0 for legacy cases 684 * - need to investigate single pipe MPO + SubVP case to 685 * see if CURSOR_REQ_MODE will be back to 1 for SubVP 686 * when it should be 0 for MPO 687 */ 688 if (pipe->stream->mall_stream_config.type == SUBVP_MAIN) { 689 hubp->funcs->hubp_prepare_subvp_buffering(hubp, true); 690 } 691 } 692 } 693 } 694 695 static void dcn32_initialize_min_clocks(struct dc *dc) 696 { 697 struct dc_clocks *clocks = &dc->current_state->bw_ctx.bw.dcn.clk; 698 699 clocks->dcfclk_deep_sleep_khz = DCN3_2_DCFCLK_DS_INIT_KHZ; 700 clocks->dcfclk_khz = dc->clk_mgr->bw_params->clk_table.entries[0].dcfclk_mhz * 1000; 701 clocks->socclk_khz = dc->clk_mgr->bw_params->clk_table.entries[0].socclk_mhz * 1000; 702 clocks->dramclk_khz = dc->clk_mgr->bw_params->clk_table.entries[0].memclk_mhz * 1000; 703 clocks->dppclk_khz = dc->clk_mgr->bw_params->clk_table.entries[0].dppclk_mhz * 1000; 704 clocks->dispclk_khz = dc->clk_mgr->bw_params->clk_table.entries[0].dispclk_mhz * 1000; 705 clocks->ref_dtbclk_khz = dc->clk_mgr->bw_params->clk_table.entries[0].dtbclk_mhz * 1000; 706 clocks->fclk_p_state_change_support = true; 707 clocks->p_state_change_support = true; 708 709 dc->clk_mgr->funcs->update_clocks( 710 dc->clk_mgr, 711 dc->current_state, 712 true); 713 } 714 715 void dcn32_init_hw(struct dc *dc) 716 { 717 struct abm **abms = dc->res_pool->multiple_abms; 718 struct dce_hwseq *hws = dc->hwseq; 719 struct dc_bios *dcb = dc->ctx->dc_bios; 720 struct resource_pool *res_pool = dc->res_pool; 721 int i; 722 int edp_num; 723 uint32_t backlight = MAX_BACKLIGHT_LEVEL; 724 725 if (dc->clk_mgr && dc->clk_mgr->funcs->init_clocks) 726 dc->clk_mgr->funcs->init_clocks(dc->clk_mgr); 727 728 // Initialize the dccg 729 if (res_pool->dccg->funcs->dccg_init) 730 res_pool->dccg->funcs->dccg_init(res_pool->dccg); 731 732 if (!dcb->funcs->is_accelerated_mode(dcb)) { 733 hws->funcs.bios_golden_init(dc); 734 hws->funcs.disable_vga(dc->hwseq); 735 } 736 737 // Set default OPTC memory power states 738 if (dc->debug.enable_mem_low_power.bits.optc) { 739 // Shutdown when unassigned and light sleep in VBLANK 740 REG_SET_2(ODM_MEM_PWR_CTRL3, 0, ODM_MEM_UNASSIGNED_PWR_MODE, 3, ODM_MEM_VBLANK_PWR_MODE, 1); 741 } 742 743 if (dc->debug.enable_mem_low_power.bits.vga) { 744 // Power down VGA memory 745 REG_UPDATE(MMHUBBUB_MEM_PWR_CNTL, VGA_MEM_PWR_FORCE, 1); 746 } 747 748 if (dc->ctx->dc_bios->fw_info_valid) { 749 res_pool->ref_clocks.xtalin_clock_inKhz = 750 dc->ctx->dc_bios->fw_info.pll_info.crystal_frequency; 751 752 if (res_pool->dccg && res_pool->hubbub) { 753 (res_pool->dccg->funcs->get_dccg_ref_freq)(res_pool->dccg, 754 dc->ctx->dc_bios->fw_info.pll_info.crystal_frequency, 755 &res_pool->ref_clocks.dccg_ref_clock_inKhz); 756 757 (res_pool->hubbub->funcs->get_dchub_ref_freq)(res_pool->hubbub, 758 res_pool->ref_clocks.dccg_ref_clock_inKhz, 759 &res_pool->ref_clocks.dchub_ref_clock_inKhz); 760 } else { 761 // Not all ASICs have DCCG sw component 762 res_pool->ref_clocks.dccg_ref_clock_inKhz = 763 res_pool->ref_clocks.xtalin_clock_inKhz; 764 res_pool->ref_clocks.dchub_ref_clock_inKhz = 765 res_pool->ref_clocks.xtalin_clock_inKhz; 766 } 767 } else 768 ASSERT_CRITICAL(false); 769 770 for (i = 0; i < dc->link_count; i++) { 771 /* Power up AND update implementation according to the 772 * required signal (which may be different from the 773 * default signal on connector). 774 */ 775 struct dc_link *link = dc->links[i]; 776 777 link->link_enc->funcs->hw_init(link->link_enc); 778 779 /* Check for enabled DIG to identify enabled display */ 780 if (link->link_enc->funcs->is_dig_enabled && 781 link->link_enc->funcs->is_dig_enabled(link->link_enc)) { 782 link->link_status.link_active = true; 783 link->phy_state.symclk_state = SYMCLK_ON_TX_ON; 784 if (link->link_enc->funcs->fec_is_active && 785 link->link_enc->funcs->fec_is_active(link->link_enc)) 786 link->fec_state = dc_link_fec_enabled; 787 } 788 } 789 790 /* Power gate DSCs */ 791 for (i = 0; i < res_pool->res_cap->num_dsc; i++) 792 if (hws->funcs.dsc_pg_control != NULL) 793 hws->funcs.dsc_pg_control(hws, res_pool->dscs[i]->inst, false); 794 795 /* we want to turn off all dp displays before doing detection */ 796 dc_link_blank_all_dp_displays(dc); 797 798 /* If taking control over from VBIOS, we may want to optimize our first 799 * mode set, so we need to skip powering down pipes until we know which 800 * pipes we want to use. 801 * Otherwise, if taking control is not possible, we need to power 802 * everything down. 803 */ 804 if (dcb->funcs->is_accelerated_mode(dcb) || !dc->config.seamless_boot_edp_requested) { 805 hws->funcs.init_pipes(dc, dc->current_state); 806 if (dc->res_pool->hubbub->funcs->allow_self_refresh_control) 807 dc->res_pool->hubbub->funcs->allow_self_refresh_control(dc->res_pool->hubbub, 808 !dc->res_pool->hubbub->ctx->dc->debug.disable_stutter); 809 810 dcn32_initialize_min_clocks(dc); 811 812 /* On HW init, allow idle optimizations after pipes have been turned off. 813 * 814 * In certain D3 cases (i.e. BOCO / BOMACO) it's possible that hardware state 815 * is reset (i.e. not in idle at the time hw init is called), but software state 816 * still has idle_optimizations = true, so we must disable idle optimizations first 817 * (i.e. set false), then re-enable (set true). 818 */ 819 dc_allow_idle_optimizations(dc, false); 820 dc_allow_idle_optimizations(dc, true); 821 } 822 823 /* In headless boot cases, DIG may be turned 824 * on which causes HW/SW discrepancies. 825 * To avoid this, power down hardware on boot 826 * if DIG is turned on and seamless boot not enabled 827 */ 828 if (!dc->config.seamless_boot_edp_requested) { 829 struct dc_link *edp_links[MAX_NUM_EDP]; 830 struct dc_link *edp_link; 831 832 get_edp_links(dc, edp_links, &edp_num); 833 if (edp_num) { 834 for (i = 0; i < edp_num; i++) { 835 edp_link = edp_links[i]; 836 if (edp_link->link_enc->funcs->is_dig_enabled && 837 edp_link->link_enc->funcs->is_dig_enabled(edp_link->link_enc) && 838 dc->hwss.edp_backlight_control && 839 dc->hwss.power_down && 840 dc->hwss.edp_power_control) { 841 dc->hwss.edp_backlight_control(edp_link, false); 842 dc->hwss.power_down(dc); 843 dc->hwss.edp_power_control(edp_link, false); 844 } 845 } 846 } else { 847 for (i = 0; i < dc->link_count; i++) { 848 struct dc_link *link = dc->links[i]; 849 850 if (link->link_enc->funcs->is_dig_enabled && 851 link->link_enc->funcs->is_dig_enabled(link->link_enc) && 852 dc->hwss.power_down) { 853 dc->hwss.power_down(dc); 854 break; 855 } 856 857 } 858 } 859 } 860 861 for (i = 0; i < res_pool->audio_count; i++) { 862 struct audio *audio = res_pool->audios[i]; 863 864 audio->funcs->hw_init(audio); 865 } 866 867 for (i = 0; i < dc->link_count; i++) { 868 struct dc_link *link = dc->links[i]; 869 870 if (link->panel_cntl) 871 backlight = link->panel_cntl->funcs->hw_init(link->panel_cntl); 872 } 873 874 for (i = 0; i < dc->res_pool->pipe_count; i++) { 875 if (abms[i] != NULL && abms[i]->funcs != NULL) 876 abms[i]->funcs->abm_init(abms[i], backlight); 877 } 878 879 /* power AFMT HDMI memory TODO: may move to dis/en output save power*/ 880 REG_WRITE(DIO_MEM_PWR_CTRL, 0); 881 882 if (!dc->debug.disable_clock_gate) { 883 /* enable all DCN clock gating */ 884 REG_WRITE(DCCG_GATE_DISABLE_CNTL, 0); 885 886 REG_WRITE(DCCG_GATE_DISABLE_CNTL2, 0); 887 888 REG_UPDATE(DCFCLK_CNTL, DCFCLK_GATE_DIS, 0); 889 } 890 if (hws->funcs.enable_power_gating_plane) 891 hws->funcs.enable_power_gating_plane(dc->hwseq, true); 892 893 if (!dcb->funcs->is_accelerated_mode(dcb) && dc->res_pool->hubbub->funcs->init_watermarks) 894 dc->res_pool->hubbub->funcs->init_watermarks(dc->res_pool->hubbub); 895 896 if (dc->clk_mgr->funcs->notify_wm_ranges) 897 dc->clk_mgr->funcs->notify_wm_ranges(dc->clk_mgr); 898 899 if (dc->clk_mgr->funcs->set_hard_max_memclk) 900 dc->clk_mgr->funcs->set_hard_max_memclk(dc->clk_mgr); 901 902 if (dc->res_pool->hubbub->funcs->force_pstate_change_control) 903 dc->res_pool->hubbub->funcs->force_pstate_change_control( 904 dc->res_pool->hubbub, false, false); 905 906 if (dc->res_pool->hubbub->funcs->init_crb) 907 dc->res_pool->hubbub->funcs->init_crb(dc->res_pool->hubbub); 908 909 if (dc->res_pool->hubbub->funcs->set_request_limit && dc->config.sdpif_request_limit_words_per_umc > 0) 910 dc->res_pool->hubbub->funcs->set_request_limit(dc->res_pool->hubbub, dc->ctx->dc_bios->vram_info.num_chans, dc->config.sdpif_request_limit_words_per_umc); 911 912 // Get DMCUB capabilities 913 if (dc->ctx->dmub_srv) { 914 dc_dmub_srv_query_caps_cmd(dc->ctx->dmub_srv->dmub); 915 dc->caps.dmub_caps.psr = dc->ctx->dmub_srv->dmub->feature_caps.psr; 916 } 917 } 918 919 static int calc_mpc_flow_ctrl_cnt(const struct dc_stream_state *stream, 920 int opp_cnt) 921 { 922 bool hblank_halved = optc2_is_two_pixels_per_containter(&stream->timing); 923 int flow_ctrl_cnt; 924 925 if (opp_cnt >= 2) 926 hblank_halved = true; 927 928 flow_ctrl_cnt = stream->timing.h_total - stream->timing.h_addressable - 929 stream->timing.h_border_left - 930 stream->timing.h_border_right; 931 932 if (hblank_halved) 933 flow_ctrl_cnt /= 2; 934 935 /* ODM combine 4:1 case */ 936 if (opp_cnt == 4) 937 flow_ctrl_cnt /= 2; 938 939 return flow_ctrl_cnt; 940 } 941 942 static void update_dsc_on_stream(struct pipe_ctx *pipe_ctx, bool enable) 943 { 944 struct display_stream_compressor *dsc = pipe_ctx->stream_res.dsc; 945 struct dc_stream_state *stream = pipe_ctx->stream; 946 struct pipe_ctx *odm_pipe; 947 int opp_cnt = 1; 948 949 ASSERT(dsc); 950 for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) 951 opp_cnt++; 952 953 if (enable) { 954 struct dsc_config dsc_cfg; 955 struct dsc_optc_config dsc_optc_cfg; 956 enum optc_dsc_mode optc_dsc_mode; 957 958 /* Enable DSC hw block */ 959 dsc_cfg.pic_width = (stream->timing.h_addressable + stream->timing.h_border_left + stream->timing.h_border_right) / opp_cnt; 960 dsc_cfg.pic_height = stream->timing.v_addressable + stream->timing.v_border_top + stream->timing.v_border_bottom; 961 dsc_cfg.pixel_encoding = stream->timing.pixel_encoding; 962 dsc_cfg.color_depth = stream->timing.display_color_depth; 963 dsc_cfg.is_odm = pipe_ctx->next_odm_pipe ? true : false; 964 dsc_cfg.dc_dsc_cfg = stream->timing.dsc_cfg; 965 ASSERT(dsc_cfg.dc_dsc_cfg.num_slices_h % opp_cnt == 0); 966 dsc_cfg.dc_dsc_cfg.num_slices_h /= opp_cnt; 967 968 dsc->funcs->dsc_set_config(dsc, &dsc_cfg, &dsc_optc_cfg); 969 dsc->funcs->dsc_enable(dsc, pipe_ctx->stream_res.opp->inst); 970 for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) { 971 struct display_stream_compressor *odm_dsc = odm_pipe->stream_res.dsc; 972 973 ASSERT(odm_dsc); 974 odm_dsc->funcs->dsc_set_config(odm_dsc, &dsc_cfg, &dsc_optc_cfg); 975 odm_dsc->funcs->dsc_enable(odm_dsc, odm_pipe->stream_res.opp->inst); 976 } 977 dsc_cfg.dc_dsc_cfg.num_slices_h *= opp_cnt; 978 dsc_cfg.pic_width *= opp_cnt; 979 980 optc_dsc_mode = dsc_optc_cfg.is_pixel_format_444 ? OPTC_DSC_ENABLED_444 : OPTC_DSC_ENABLED_NATIVE_SUBSAMPLED; 981 982 /* Enable DSC in OPTC */ 983 DC_LOG_DSC("Setting optc DSC config for tg instance %d:", pipe_ctx->stream_res.tg->inst); 984 pipe_ctx->stream_res.tg->funcs->set_dsc_config(pipe_ctx->stream_res.tg, 985 optc_dsc_mode, 986 dsc_optc_cfg.bytes_per_pixel, 987 dsc_optc_cfg.slice_width); 988 } else { 989 /* disable DSC in OPTC */ 990 pipe_ctx->stream_res.tg->funcs->set_dsc_config( 991 pipe_ctx->stream_res.tg, 992 OPTC_DSC_DISABLED, 0, 0); 993 994 /* disable DSC block */ 995 dsc->funcs->dsc_disable(pipe_ctx->stream_res.dsc); 996 for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) { 997 ASSERT(odm_pipe->stream_res.dsc); 998 odm_pipe->stream_res.dsc->funcs->dsc_disable(odm_pipe->stream_res.dsc); 999 } 1000 } 1001 } 1002 1003 /* 1004 * Given any pipe_ctx, return the total ODM combine factor, and optionally return 1005 * the OPPids which are used 1006 * */ 1007 static unsigned int get_odm_config(struct pipe_ctx *pipe_ctx, unsigned int *opp_instances) 1008 { 1009 unsigned int opp_count = 1; 1010 struct pipe_ctx *odm_pipe; 1011 1012 /* First get to the top pipe */ 1013 for (odm_pipe = pipe_ctx; odm_pipe->prev_odm_pipe; odm_pipe = odm_pipe->prev_odm_pipe) 1014 ; 1015 1016 /* First pipe is always used */ 1017 if (opp_instances) 1018 opp_instances[0] = odm_pipe->stream_res.opp->inst; 1019 1020 /* Find and count odm pipes, if any */ 1021 for (odm_pipe = odm_pipe->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) { 1022 if (opp_instances) 1023 opp_instances[opp_count] = odm_pipe->stream_res.opp->inst; 1024 opp_count++; 1025 } 1026 1027 return opp_count; 1028 } 1029 1030 void dcn32_update_odm(struct dc *dc, struct dc_state *context, struct pipe_ctx *pipe_ctx) 1031 { 1032 struct pipe_ctx *odm_pipe; 1033 int opp_cnt = 0; 1034 int opp_inst[MAX_PIPES] = {0}; 1035 bool rate_control_2x_pclk = (pipe_ctx->stream->timing.flags.INTERLACE || optc2_is_two_pixels_per_containter(&pipe_ctx->stream->timing)); 1036 struct mpc_dwb_flow_control flow_control; 1037 struct mpc *mpc = dc->res_pool->mpc; 1038 int i; 1039 1040 opp_cnt = get_odm_config(pipe_ctx, opp_inst); 1041 1042 if (opp_cnt > 1) 1043 pipe_ctx->stream_res.tg->funcs->set_odm_combine( 1044 pipe_ctx->stream_res.tg, 1045 opp_inst, opp_cnt, 1046 &pipe_ctx->stream->timing); 1047 else 1048 pipe_ctx->stream_res.tg->funcs->set_odm_bypass( 1049 pipe_ctx->stream_res.tg, &pipe_ctx->stream->timing); 1050 1051 rate_control_2x_pclk = rate_control_2x_pclk || opp_cnt > 1; 1052 flow_control.flow_ctrl_mode = 0; 1053 flow_control.flow_ctrl_cnt0 = 0x80; 1054 flow_control.flow_ctrl_cnt1 = calc_mpc_flow_ctrl_cnt(pipe_ctx->stream, opp_cnt); 1055 if (mpc->funcs->set_out_rate_control) { 1056 for (i = 0; i < opp_cnt; ++i) { 1057 mpc->funcs->set_out_rate_control( 1058 mpc, opp_inst[i], 1059 true, 1060 rate_control_2x_pclk, 1061 &flow_control); 1062 } 1063 } 1064 1065 for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) { 1066 odm_pipe->stream_res.opp->funcs->opp_pipe_clock_control( 1067 odm_pipe->stream_res.opp, 1068 true); 1069 } 1070 1071 if (pipe_ctx->stream_res.dsc) { 1072 struct pipe_ctx *current_pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[pipe_ctx->pipe_idx]; 1073 1074 update_dsc_on_stream(pipe_ctx, pipe_ctx->stream->timing.flags.DSC); 1075 1076 /* Check if no longer using pipe for ODM, then need to disconnect DSC for that pipe */ 1077 if (!pipe_ctx->next_odm_pipe && current_pipe_ctx->next_odm_pipe && 1078 current_pipe_ctx->next_odm_pipe->stream_res.dsc) { 1079 struct display_stream_compressor *dsc = current_pipe_ctx->next_odm_pipe->stream_res.dsc; 1080 /* disconnect DSC block from stream */ 1081 dsc->funcs->dsc_disconnect(dsc); 1082 } 1083 } 1084 } 1085 1086 unsigned int dcn32_calculate_dccg_k1_k2_values(struct pipe_ctx *pipe_ctx, unsigned int *k1_div, unsigned int *k2_div) 1087 { 1088 struct dc_stream_state *stream = pipe_ctx->stream; 1089 unsigned int odm_combine_factor = 0; 1090 bool two_pix_per_container = false; 1091 1092 // For phantom pipes, use the same programming as the main pipes 1093 if (pipe_ctx->stream->mall_stream_config.type == SUBVP_PHANTOM) { 1094 stream = pipe_ctx->stream->mall_stream_config.paired_stream; 1095 } 1096 two_pix_per_container = optc2_is_two_pixels_per_containter(&stream->timing); 1097 odm_combine_factor = get_odm_config(pipe_ctx, NULL); 1098 1099 if (link_is_dp_128b_132b_signal(pipe_ctx)) { 1100 *k1_div = PIXEL_RATE_DIV_BY_1; 1101 *k2_div = PIXEL_RATE_DIV_BY_1; 1102 } else if (dc_is_hdmi_tmds_signal(pipe_ctx->stream->signal) || dc_is_dvi_signal(pipe_ctx->stream->signal)) { 1103 *k1_div = PIXEL_RATE_DIV_BY_1; 1104 if (stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR420) 1105 *k2_div = PIXEL_RATE_DIV_BY_2; 1106 else 1107 *k2_div = PIXEL_RATE_DIV_BY_4; 1108 } else if (dc_is_dp_signal(pipe_ctx->stream->signal) || dc_is_virtual_signal(pipe_ctx->stream->signal)) { 1109 if (two_pix_per_container) { 1110 *k1_div = PIXEL_RATE_DIV_BY_1; 1111 *k2_div = PIXEL_RATE_DIV_BY_2; 1112 } else { 1113 *k1_div = PIXEL_RATE_DIV_BY_1; 1114 *k2_div = PIXEL_RATE_DIV_BY_4; 1115 if ((odm_combine_factor == 2) || dcn32_is_dp_dig_pixel_rate_div_policy(pipe_ctx)) 1116 *k2_div = PIXEL_RATE_DIV_BY_2; 1117 } 1118 } 1119 1120 if ((*k1_div == PIXEL_RATE_DIV_NA) && (*k2_div == PIXEL_RATE_DIV_NA)) 1121 ASSERT(false); 1122 1123 return odm_combine_factor; 1124 } 1125 1126 void dcn32_set_pixels_per_cycle(struct pipe_ctx *pipe_ctx) 1127 { 1128 uint32_t pix_per_cycle = 1; 1129 uint32_t odm_combine_factor = 1; 1130 1131 if (!pipe_ctx || !pipe_ctx->stream || !pipe_ctx->stream_res.stream_enc) 1132 return; 1133 1134 odm_combine_factor = get_odm_config(pipe_ctx, NULL); 1135 if (optc2_is_two_pixels_per_containter(&pipe_ctx->stream->timing) || odm_combine_factor > 1 1136 || dcn32_is_dp_dig_pixel_rate_div_policy(pipe_ctx)) 1137 pix_per_cycle = 2; 1138 1139 if (pipe_ctx->stream_res.stream_enc->funcs->set_input_mode) 1140 pipe_ctx->stream_res.stream_enc->funcs->set_input_mode(pipe_ctx->stream_res.stream_enc, 1141 pix_per_cycle); 1142 } 1143 1144 void dcn32_unblank_stream(struct pipe_ctx *pipe_ctx, 1145 struct dc_link_settings *link_settings) 1146 { 1147 struct encoder_unblank_param params = {0}; 1148 struct dc_stream_state *stream = pipe_ctx->stream; 1149 struct dc_link *link = stream->link; 1150 struct dce_hwseq *hws = link->dc->hwseq; 1151 struct pipe_ctx *odm_pipe; 1152 uint32_t pix_per_cycle = 1; 1153 1154 params.opp_cnt = 1; 1155 for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) 1156 params.opp_cnt++; 1157 1158 /* only 3 items below are used by unblank */ 1159 params.timing = pipe_ctx->stream->timing; 1160 1161 params.link_settings.link_rate = link_settings->link_rate; 1162 1163 if (link_is_dp_128b_132b_signal(pipe_ctx)) { 1164 /* TODO - DP2.0 HW: Set ODM mode in dp hpo encoder here */ 1165 pipe_ctx->stream_res.hpo_dp_stream_enc->funcs->dp_unblank( 1166 pipe_ctx->stream_res.hpo_dp_stream_enc, 1167 pipe_ctx->stream_res.tg->inst); 1168 } else if (dc_is_dp_signal(pipe_ctx->stream->signal)) { 1169 if (optc2_is_two_pixels_per_containter(&stream->timing) || params.opp_cnt > 1 1170 || dcn32_is_dp_dig_pixel_rate_div_policy(pipe_ctx)) { 1171 params.timing.pix_clk_100hz /= 2; 1172 pix_per_cycle = 2; 1173 } 1174 pipe_ctx->stream_res.stream_enc->funcs->dp_set_odm_combine( 1175 pipe_ctx->stream_res.stream_enc, pix_per_cycle > 1); 1176 pipe_ctx->stream_res.stream_enc->funcs->dp_unblank(link, pipe_ctx->stream_res.stream_enc, ¶ms); 1177 } 1178 1179 if (link->local_sink && link->local_sink->sink_signal == SIGNAL_TYPE_EDP) 1180 hws->funcs.edp_backlight_control(link, true); 1181 } 1182 1183 bool dcn32_is_dp_dig_pixel_rate_div_policy(struct pipe_ctx *pipe_ctx) 1184 { 1185 struct dc *dc = pipe_ctx->stream->ctx->dc; 1186 1187 if (!is_h_timing_divisible_by_2(pipe_ctx->stream)) 1188 return false; 1189 1190 if (dc_is_dp_signal(pipe_ctx->stream->signal) && !link_is_dp_128b_132b_signal(pipe_ctx) && 1191 dc->debug.enable_dp_dig_pixel_rate_div_policy) 1192 return true; 1193 return false; 1194 } 1195 1196 static void apply_symclk_on_tx_off_wa(struct dc_link *link) 1197 { 1198 /* There are use cases where SYMCLK is referenced by OTG. For instance 1199 * for TMDS signal, OTG relies SYMCLK even if TX video output is off. 1200 * However current link interface will power off PHY when disabling link 1201 * output. This will turn off SYMCLK generated by PHY. The workaround is 1202 * to identify such case where SYMCLK is still in use by OTG when we 1203 * power off PHY. When this is detected, we will temporarily power PHY 1204 * back on and move PHY's SYMCLK state to SYMCLK_ON_TX_OFF by calling 1205 * program_pix_clk interface. When OTG is disabled, we will then power 1206 * off PHY by calling disable link output again. 1207 * 1208 * In future dcn generations, we plan to rework transmitter control 1209 * interface so that we could have an option to set SYMCLK ON TX OFF 1210 * state in one step without this workaround 1211 */ 1212 1213 struct dc *dc = link->ctx->dc; 1214 struct pipe_ctx *pipe_ctx = NULL; 1215 uint8_t i; 1216 1217 if (link->phy_state.symclk_ref_cnts.otg > 0) { 1218 for (i = 0; i < MAX_PIPES; i++) { 1219 pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[i]; 1220 if (pipe_ctx->stream && pipe_ctx->stream->link == link && pipe_ctx->top_pipe == NULL) { 1221 pipe_ctx->clock_source->funcs->program_pix_clk( 1222 pipe_ctx->clock_source, 1223 &pipe_ctx->stream_res.pix_clk_params, 1224 link_dp_get_encoding_format(&pipe_ctx->link_config.dp_link_settings), 1225 &pipe_ctx->pll_settings); 1226 link->phy_state.symclk_state = SYMCLK_ON_TX_OFF; 1227 break; 1228 } 1229 } 1230 } 1231 } 1232 1233 void dcn32_disable_link_output(struct dc_link *link, 1234 const struct link_resource *link_res, 1235 enum signal_type signal) 1236 { 1237 struct dc *dc = link->ctx->dc; 1238 const struct link_hwss *link_hwss = get_link_hwss(link, link_res); 1239 struct dmcu *dmcu = dc->res_pool->dmcu; 1240 1241 if (signal == SIGNAL_TYPE_EDP && 1242 link->dc->hwss.edp_backlight_control) 1243 link->dc->hwss.edp_backlight_control(link, false); 1244 else if (dmcu != NULL && dmcu->funcs->lock_phy) 1245 dmcu->funcs->lock_phy(dmcu); 1246 1247 link_hwss->disable_link_output(link, link_res, signal); 1248 link->phy_state.symclk_state = SYMCLK_OFF_TX_OFF; 1249 1250 if (signal == SIGNAL_TYPE_EDP && 1251 link->dc->hwss.edp_backlight_control) 1252 link->dc->hwss.edp_power_control(link, false); 1253 else if (dmcu != NULL && dmcu->funcs->lock_phy) 1254 dmcu->funcs->unlock_phy(dmcu); 1255 1256 dp_source_sequence_trace(link, DPCD_SOURCE_SEQ_AFTER_DISABLE_LINK_PHY); 1257 1258 apply_symclk_on_tx_off_wa(link); 1259 } 1260 1261 /* For SubVP the main pipe can have a viewport position change 1262 * without a full update. In this case we must also update the 1263 * viewport positions for the phantom pipe accordingly. 1264 */ 1265 void dcn32_update_phantom_vp_position(struct dc *dc, 1266 struct dc_state *context, 1267 struct pipe_ctx *phantom_pipe) 1268 { 1269 uint32_t i; 1270 struct dc_plane_state *phantom_plane = phantom_pipe->plane_state; 1271 1272 for (i = 0; i < dc->res_pool->pipe_count; i++) { 1273 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; 1274 1275 if (pipe->stream && pipe->stream->mall_stream_config.type == SUBVP_MAIN && 1276 pipe->stream->mall_stream_config.paired_stream == phantom_pipe->stream) { 1277 if (pipe->plane_state && pipe->plane_state->update_flags.bits.position_change) { 1278 1279 phantom_plane->src_rect.x = pipe->plane_state->src_rect.x; 1280 phantom_plane->src_rect.y = pipe->plane_state->src_rect.y; 1281 phantom_plane->clip_rect.x = pipe->plane_state->clip_rect.x; 1282 phantom_plane->dst_rect.x = pipe->plane_state->dst_rect.x; 1283 phantom_plane->dst_rect.y = pipe->plane_state->dst_rect.y; 1284 1285 phantom_pipe->plane_state->update_flags.bits.position_change = 1; 1286 resource_build_scaling_params(phantom_pipe); 1287 return; 1288 } 1289 } 1290 } 1291 } 1292 1293 /* Treat the phantom pipe as if it needs to be fully enabled. 1294 * If the pipe was previously in use but not phantom, it would 1295 * have been disabled earlier in the sequence so we need to run 1296 * the full enable sequence. 1297 */ 1298 void dcn32_apply_update_flags_for_phantom(struct pipe_ctx *phantom_pipe) 1299 { 1300 phantom_pipe->update_flags.raw = 0; 1301 if (phantom_pipe->stream && phantom_pipe->stream->mall_stream_config.type == SUBVP_PHANTOM) { 1302 if (phantom_pipe->stream && phantom_pipe->plane_state) { 1303 phantom_pipe->update_flags.bits.enable = 1; 1304 phantom_pipe->update_flags.bits.mpcc = 1; 1305 phantom_pipe->update_flags.bits.dppclk = 1; 1306 phantom_pipe->update_flags.bits.hubp_interdependent = 1; 1307 phantom_pipe->update_flags.bits.hubp_rq_dlg_ttu = 1; 1308 phantom_pipe->update_flags.bits.gamut_remap = 1; 1309 phantom_pipe->update_flags.bits.scaler = 1; 1310 phantom_pipe->update_flags.bits.viewport = 1; 1311 phantom_pipe->update_flags.bits.det_size = 1; 1312 if (!phantom_pipe->top_pipe && !phantom_pipe->prev_odm_pipe) { 1313 phantom_pipe->update_flags.bits.odm = 1; 1314 phantom_pipe->update_flags.bits.global_sync = 1; 1315 } 1316 } 1317 } 1318 } 1319 1320 bool dcn32_dsc_pg_status( 1321 struct dce_hwseq *hws, 1322 unsigned int dsc_inst) 1323 { 1324 uint32_t pwr_status = 0; 1325 1326 switch (dsc_inst) { 1327 case 0: /* DSC0 */ 1328 REG_GET(DOMAIN16_PG_STATUS, 1329 DOMAIN_PGFSM_PWR_STATUS, &pwr_status); 1330 break; 1331 case 1: /* DSC1 */ 1332 1333 REG_GET(DOMAIN17_PG_STATUS, 1334 DOMAIN_PGFSM_PWR_STATUS, &pwr_status); 1335 break; 1336 case 2: /* DSC2 */ 1337 REG_GET(DOMAIN18_PG_STATUS, 1338 DOMAIN_PGFSM_PWR_STATUS, &pwr_status); 1339 break; 1340 case 3: /* DSC3 */ 1341 REG_GET(DOMAIN19_PG_STATUS, 1342 DOMAIN_PGFSM_PWR_STATUS, &pwr_status); 1343 break; 1344 default: 1345 BREAK_TO_DEBUGGER(); 1346 break; 1347 } 1348 1349 return pwr_status == 0; 1350 } 1351 1352 void dcn32_update_dsc_pg(struct dc *dc, 1353 struct dc_state *context, 1354 bool safe_to_disable) 1355 { 1356 struct dce_hwseq *hws = dc->hwseq; 1357 int i; 1358 1359 for (i = 0; i < dc->res_pool->res_cap->num_dsc; i++) { 1360 struct display_stream_compressor *dsc = dc->res_pool->dscs[i]; 1361 bool is_dsc_ungated = hws->funcs.dsc_pg_status(hws, dsc->inst); 1362 1363 if (context->res_ctx.is_dsc_acquired[i]) { 1364 if (!is_dsc_ungated) { 1365 hws->funcs.dsc_pg_control(hws, dsc->inst, true); 1366 } 1367 } else if (safe_to_disable) { 1368 if (is_dsc_ungated) { 1369 hws->funcs.dsc_pg_control(hws, dsc->inst, false); 1370 } 1371 } 1372 } 1373 } 1374 1375 void dcn32_enable_phantom_streams(struct dc *dc, struct dc_state *context) 1376 { 1377 unsigned int i; 1378 1379 for (i = 0; i < dc->res_pool->pipe_count; i++) { 1380 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; 1381 struct pipe_ctx *old_pipe = &dc->current_state->res_ctx.pipe_ctx[i]; 1382 1383 /* If an active, non-phantom pipe is being transitioned into a phantom 1384 * pipe, wait for the double buffer update to complete first before we do 1385 * ANY phantom pipe programming. 1386 */ 1387 if (pipe->stream && pipe->stream->mall_stream_config.type == SUBVP_PHANTOM && 1388 old_pipe->stream && old_pipe->stream->mall_stream_config.type != SUBVP_PHANTOM) { 1389 old_pipe->stream_res.tg->funcs->wait_for_state( 1390 old_pipe->stream_res.tg, 1391 CRTC_STATE_VBLANK); 1392 old_pipe->stream_res.tg->funcs->wait_for_state( 1393 old_pipe->stream_res.tg, 1394 CRTC_STATE_VACTIVE); 1395 } 1396 } 1397 for (i = 0; i < dc->res_pool->pipe_count; i++) { 1398 struct pipe_ctx *new_pipe = &context->res_ctx.pipe_ctx[i]; 1399 1400 if (new_pipe->stream && new_pipe->stream->mall_stream_config.type == SUBVP_PHANTOM) { 1401 // If old context or new context has phantom pipes, apply 1402 // the phantom timings now. We can't change the phantom 1403 // pipe configuration safely without driver acquiring 1404 // the DMCUB lock first. 1405 dc->hwss.apply_ctx_to_hw(dc, context); 1406 break; 1407 } 1408 } 1409 } 1410