1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 27 #include "dm_services.h" 28 #include "dm_helpers.h" 29 #include "core_types.h" 30 #include "resource.h" 31 #include "dccg.h" 32 #include "dce/dce_hwseq.h" 33 #include "dcn30/dcn30_cm_common.h" 34 #include "reg_helper.h" 35 #include "abm.h" 36 #include "hubp.h" 37 #include "dchubbub.h" 38 #include "timing_generator.h" 39 #include "opp.h" 40 #include "ipp.h" 41 #include "mpc.h" 42 #include "mcif_wb.h" 43 #include "dc_dmub_srv.h" 44 #include "link_hwss.h" 45 #include "dpcd_defs.h" 46 #include "dcn32_hwseq.h" 47 #include "clk_mgr.h" 48 #include "dsc.h" 49 #include "dcn20/dcn20_optc.h" 50 #include "dmub_subvp_state.h" 51 #include "dce/dmub_hw_lock_mgr.h" 52 #include "dcn32_resource.h" 53 #include "dc_link_dp.h" 54 #include "dmub/inc/dmub_subvp_state.h" 55 56 #define DC_LOGGER_INIT(logger) 57 58 #define CTX \ 59 hws->ctx 60 #define REG(reg)\ 61 hws->regs->reg 62 #define DC_LOGGER \ 63 dc->ctx->logger 64 65 66 #undef FN 67 #define FN(reg_name, field_name) \ 68 hws->shifts->field_name, hws->masks->field_name 69 70 void dcn32_dsc_pg_control( 71 struct dce_hwseq *hws, 72 unsigned int dsc_inst, 73 bool power_on) 74 { 75 uint32_t power_gate = power_on ? 0 : 1; 76 uint32_t pwr_status = power_on ? 0 : 2; 77 uint32_t org_ip_request_cntl = 0; 78 79 if (hws->ctx->dc->debug.disable_dsc_power_gate) 80 return; 81 82 REG_GET(DC_IP_REQUEST_CNTL, IP_REQUEST_EN, &org_ip_request_cntl); 83 if (org_ip_request_cntl == 0) 84 REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 1); 85 86 switch (dsc_inst) { 87 case 0: /* DSC0 */ 88 REG_UPDATE(DOMAIN16_PG_CONFIG, 89 DOMAIN_POWER_GATE, power_gate); 90 91 REG_WAIT(DOMAIN16_PG_STATUS, 92 DOMAIN_PGFSM_PWR_STATUS, pwr_status, 93 1, 1000); 94 break; 95 case 1: /* DSC1 */ 96 REG_UPDATE(DOMAIN17_PG_CONFIG, 97 DOMAIN_POWER_GATE, power_gate); 98 99 REG_WAIT(DOMAIN17_PG_STATUS, 100 DOMAIN_PGFSM_PWR_STATUS, pwr_status, 101 1, 1000); 102 break; 103 case 2: /* DSC2 */ 104 REG_UPDATE(DOMAIN18_PG_CONFIG, 105 DOMAIN_POWER_GATE, power_gate); 106 107 REG_WAIT(DOMAIN18_PG_STATUS, 108 DOMAIN_PGFSM_PWR_STATUS, pwr_status, 109 1, 1000); 110 break; 111 case 3: /* DSC3 */ 112 REG_UPDATE(DOMAIN19_PG_CONFIG, 113 DOMAIN_POWER_GATE, power_gate); 114 115 REG_WAIT(DOMAIN19_PG_STATUS, 116 DOMAIN_PGFSM_PWR_STATUS, pwr_status, 117 1, 1000); 118 break; 119 default: 120 BREAK_TO_DEBUGGER(); 121 break; 122 } 123 124 if (org_ip_request_cntl == 0) 125 REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 0); 126 } 127 128 129 void dcn32_enable_power_gating_plane( 130 struct dce_hwseq *hws, 131 bool enable) 132 { 133 bool force_on = true; /* disable power gating */ 134 135 if (enable) 136 force_on = false; 137 138 /* DCHUBP0/1/2/3 */ 139 REG_UPDATE(DOMAIN0_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on); 140 REG_UPDATE(DOMAIN1_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on); 141 REG_UPDATE(DOMAIN2_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on); 142 REG_UPDATE(DOMAIN3_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on); 143 144 /* DCS0/1/2/3 */ 145 REG_UPDATE(DOMAIN16_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on); 146 REG_UPDATE(DOMAIN17_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on); 147 REG_UPDATE(DOMAIN18_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on); 148 REG_UPDATE(DOMAIN19_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on); 149 } 150 151 void dcn32_hubp_pg_control(struct dce_hwseq *hws, unsigned int hubp_inst, bool power_on) 152 { 153 uint32_t power_gate = power_on ? 0 : 1; 154 uint32_t pwr_status = power_on ? 0 : 2; 155 156 if (hws->ctx->dc->debug.disable_hubp_power_gate) 157 return; 158 159 if (REG(DOMAIN0_PG_CONFIG) == 0) 160 return; 161 162 switch (hubp_inst) { 163 case 0: 164 REG_SET(DOMAIN0_PG_CONFIG, 0, DOMAIN_POWER_GATE, power_gate); 165 REG_WAIT(DOMAIN0_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, pwr_status, 1, 1000); 166 break; 167 case 1: 168 REG_SET(DOMAIN1_PG_CONFIG, 0, DOMAIN_POWER_GATE, power_gate); 169 REG_WAIT(DOMAIN1_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, pwr_status, 1, 1000); 170 break; 171 case 2: 172 REG_SET(DOMAIN2_PG_CONFIG, 0, DOMAIN_POWER_GATE, power_gate); 173 REG_WAIT(DOMAIN2_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, pwr_status, 1, 1000); 174 break; 175 case 3: 176 REG_SET(DOMAIN3_PG_CONFIG, 0, DOMAIN_POWER_GATE, power_gate); 177 REG_WAIT(DOMAIN3_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, pwr_status, 1, 1000); 178 break; 179 default: 180 BREAK_TO_DEBUGGER(); 181 break; 182 } 183 } 184 185 static bool dcn32_check_no_memory_request_for_cab(struct dc *dc) 186 { 187 int i; 188 189 /* First, check no-memory-request case */ 190 for (i = 0; i < dc->current_state->stream_count; i++) { 191 if (dc->current_state->stream_status[i].plane_count) 192 /* Fail eligibility on a visible stream */ 193 break; 194 } 195 196 if (i == dc->current_state->stream_count) 197 return true; 198 199 return false; 200 } 201 202 203 /* This function loops through every surface that needs to be cached in CAB for SS, 204 * and calculates the total number of ways required to store all surfaces (primary, 205 * meta, cursor). 206 */ 207 static uint32_t dcn32_calculate_cab_allocation(struct dc *dc, struct dc_state *ctx) 208 { 209 int i, j; 210 struct dc_stream_state *stream = NULL; 211 struct dc_plane_state *plane = NULL; 212 uint32_t cursor_size = 0; 213 uint32_t total_lines = 0; 214 uint32_t lines_per_way = 0; 215 uint8_t num_ways = 0; 216 uint8_t bytes_per_pixel = 0; 217 uint8_t cursor_bpp = 0; 218 uint16_t mblk_width = 0; 219 uint16_t mblk_height = 0; 220 uint16_t mall_alloc_width_blk_aligned = 0; 221 uint16_t mall_alloc_height_blk_aligned = 0; 222 uint16_t num_mblks = 0; 223 uint32_t bytes_in_mall = 0; 224 uint32_t cache_lines_used = 0; 225 uint32_t cache_lines_per_plane = 0; 226 227 for (i = 0; i < dc->res_pool->pipe_count; i++) { 228 struct pipe_ctx *pipe = &dc->current_state->res_ctx.pipe_ctx[i]; 229 230 if (!pipe->stream || !pipe->plane_state || 231 pipe->stream->link->psr_settings.psr_version != DC_PSR_VERSION_UNSUPPORTED || 232 pipe->stream->mall_stream_config.type == SUBVP_PHANTOM) 233 continue; 234 235 bytes_per_pixel = pipe->plane_state->format >= SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616 ? 8 : 4; 236 mblk_width = DCN3_2_MBLK_WIDTH; 237 mblk_height = bytes_per_pixel == 4 ? DCN3_2_MBLK_HEIGHT_4BPE : DCN3_2_MBLK_HEIGHT_8BPE; 238 239 /* full_vp_width_blk_aligned = FLOOR(vp_x_start + full_vp_width + blk_width - 1, blk_width) - 240 * FLOOR(vp_x_start, blk_width) 241 * 242 * mall_alloc_width_blk_aligned_l/c = full_vp_width_blk_aligned_l/c 243 */ 244 mall_alloc_width_blk_aligned = ((pipe->plane_res.scl_data.viewport.x + 245 pipe->plane_res.scl_data.viewport.width + mblk_width - 1) / mblk_width * mblk_width) - 246 (pipe->plane_res.scl_data.viewport.x / mblk_width * mblk_width); 247 248 /* full_vp_height_blk_aligned = FLOOR(vp_y_start + full_vp_height + blk_height - 1, blk_height) - 249 * FLOOR(vp_y_start, blk_height) 250 * 251 * mall_alloc_height_blk_aligned_l/c = full_vp_height_blk_aligned_l/c 252 */ 253 mall_alloc_height_blk_aligned = ((pipe->plane_res.scl_data.viewport.y + 254 pipe->plane_res.scl_data.viewport.height + mblk_height - 1) / mblk_height * mblk_height) - 255 (pipe->plane_res.scl_data.viewport.y / mblk_height * mblk_height); 256 257 num_mblks = ((mall_alloc_width_blk_aligned + mblk_width - 1) / mblk_width) * 258 ((mall_alloc_height_blk_aligned + mblk_height - 1) / mblk_height); 259 260 /* For DCC: 261 * meta_num_mblk = CEILING(full_mblk_width_ub_l*full_mblk_height_ub_l*Bpe/256/mblk_bytes, 1) 262 */ 263 if (pipe->plane_state->dcc.enable) 264 num_mblks += (mall_alloc_width_blk_aligned * mall_alloc_width_blk_aligned * bytes_per_pixel + 265 (256 * DCN3_2_MALL_MBLK_SIZE_BYTES) - 1) / (256 * DCN3_2_MALL_MBLK_SIZE_BYTES); 266 267 bytes_in_mall = num_mblks * DCN3_2_MALL_MBLK_SIZE_BYTES; 268 269 /* (cache lines used is total bytes / cache_line size. Add +2 for worst case alignment 270 * (MALL is 64-byte aligned) 271 */ 272 cache_lines_per_plane = bytes_in_mall / dc->caps.cache_line_size + 2; 273 cache_lines_used += cache_lines_per_plane; 274 } 275 276 // Include cursor size for CAB allocation 277 for (j = 0; j < dc->res_pool->pipe_count; j++) { 278 struct pipe_ctx *pipe = &ctx->res_ctx.pipe_ctx[j]; 279 struct hubp *hubp = pipe->plane_res.hubp; 280 281 if (pipe->stream && pipe->plane_state && hubp) 282 /* Find the cursor plane and use the exact size instead of 283 using the max for calculation */ 284 285 if (hubp->curs_attr.width > 0) { 286 cursor_size = hubp->curs_attr.pitch * hubp->curs_attr.height; 287 288 switch (pipe->stream->cursor_attributes.color_format) { 289 case CURSOR_MODE_MONO: 290 cursor_size /= 2; 291 cursor_bpp = 4; 292 break; 293 case CURSOR_MODE_COLOR_1BIT_AND: 294 case CURSOR_MODE_COLOR_PRE_MULTIPLIED_ALPHA: 295 case CURSOR_MODE_COLOR_UN_PRE_MULTIPLIED_ALPHA: 296 cursor_size *= 4; 297 cursor_bpp = 4; 298 break; 299 300 case CURSOR_MODE_COLOR_64BIT_FP_PRE_MULTIPLIED: 301 case CURSOR_MODE_COLOR_64BIT_FP_UN_PRE_MULTIPLIED: 302 cursor_size *= 8; 303 cursor_bpp = 8; 304 break; 305 } 306 307 if (pipe->stream->cursor_position.enable && !dc->debug.alloc_extra_way_for_cursor && 308 cursor_size > 16384) { 309 /* cursor_num_mblk = CEILING(num_cursors*cursor_width*cursor_width*cursor_Bpe/mblk_bytes, 1) 310 */ 311 cache_lines_used += (((cursor_size + DCN3_2_MALL_MBLK_SIZE_BYTES - 1) / 312 DCN3_2_MALL_MBLK_SIZE_BYTES) * DCN3_2_MALL_MBLK_SIZE_BYTES) / 313 dc->caps.cache_line_size + 2; 314 } 315 break; 316 } 317 } 318 319 // Convert number of cache lines required to number of ways 320 total_lines = dc->caps.max_cab_allocation_bytes / dc->caps.cache_line_size; 321 lines_per_way = total_lines / dc->caps.cache_num_ways; 322 num_ways = cache_lines_used / lines_per_way; 323 324 if (cache_lines_used % lines_per_way > 0) 325 num_ways++; 326 327 for (i = 0; i < ctx->stream_count; i++) { 328 stream = ctx->streams[i]; 329 for (j = 0; j < ctx->stream_status[i].plane_count; j++) { 330 plane = ctx->stream_status[i].plane_states[j]; 331 332 if (stream->cursor_position.enable && plane && 333 dc->debug.alloc_extra_way_for_cursor && 334 cursor_size > 16384) { 335 /* Cursor caching is not supported since it won't be on the same line. 336 * So we need an extra line to accommodate it. With large cursors and a single 4k monitor 337 * this case triggers corruption. If we're at the edge, then dont trigger display refresh 338 * from MALL. We only need to cache cursor if its greater that 64x64 at 4 bpp. 339 */ 340 num_ways++; 341 /* We only expect one cursor plane */ 342 break; 343 } 344 } 345 } 346 if (dc->debug.force_mall_ss_num_ways > 0) { 347 num_ways = dc->debug.force_mall_ss_num_ways; 348 } 349 return num_ways; 350 } 351 352 bool dcn32_apply_idle_power_optimizations(struct dc *dc, bool enable) 353 { 354 union dmub_rb_cmd cmd; 355 uint8_t ways, i; 356 int j; 357 bool mall_ss_unsupported = false; 358 struct dc_plane_state *plane = NULL; 359 360 if (!dc->ctx->dmub_srv) 361 return false; 362 363 if (enable) { 364 if (dc->current_state) { 365 366 /* 1. Check no memory request case for CAB. 367 * If no memory request case, send CAB_ACTION NO_DF_REQ DMUB message 368 */ 369 if (dcn32_check_no_memory_request_for_cab(dc)) { 370 /* Enable no-memory-requests case */ 371 memset(&cmd, 0, sizeof(cmd)); 372 cmd.cab.header.type = DMUB_CMD__CAB_FOR_SS; 373 cmd.cab.header.sub_type = DMUB_CMD__CAB_NO_DCN_REQ; 374 cmd.cab.header.payload_bytes = sizeof(cmd.cab) - sizeof(cmd.cab.header); 375 376 dc_dmub_srv_cmd_queue(dc->ctx->dmub_srv, &cmd); 377 dc_dmub_srv_cmd_execute(dc->ctx->dmub_srv); 378 379 return true; 380 } 381 382 /* 2. Check if all surfaces can fit in CAB. 383 * If surfaces can fit into CAB, send CAB_ACTION_ALLOW DMUB message 384 * and configure HUBP's to fetch from MALL 385 */ 386 ways = dcn32_calculate_cab_allocation(dc, dc->current_state); 387 388 /* MALL not supported with Stereo3D or TMZ surface. If any plane is using stereo, 389 * or TMZ surface, don't try to enter MALL. 390 */ 391 for (i = 0; i < dc->current_state->stream_count; i++) { 392 for (j = 0; j < dc->current_state->stream_status[i].plane_count; j++) { 393 plane = dc->current_state->stream_status[i].plane_states[j]; 394 395 if (plane->address.type == PLN_ADDR_TYPE_GRPH_STEREO || 396 plane->address.tmz_surface) { 397 mall_ss_unsupported = true; 398 break; 399 } 400 } 401 if (mall_ss_unsupported) 402 break; 403 } 404 if (ways <= dc->caps.cache_num_ways && !mall_ss_unsupported) { 405 memset(&cmd, 0, sizeof(cmd)); 406 cmd.cab.header.type = DMUB_CMD__CAB_FOR_SS; 407 cmd.cab.header.sub_type = DMUB_CMD__CAB_DCN_SS_FIT_IN_CAB; 408 cmd.cab.header.payload_bytes = sizeof(cmd.cab) - sizeof(cmd.cab.header); 409 cmd.cab.cab_alloc_ways = ways; 410 411 dc_dmub_srv_cmd_queue(dc->ctx->dmub_srv, &cmd); 412 dc_dmub_srv_cmd_execute(dc->ctx->dmub_srv); 413 414 return true; 415 } 416 417 } 418 return false; 419 } 420 421 /* Disable CAB */ 422 memset(&cmd, 0, sizeof(cmd)); 423 cmd.cab.header.type = DMUB_CMD__CAB_FOR_SS; 424 cmd.cab.header.sub_type = DMUB_CMD__CAB_NO_IDLE_OPTIMIZATION; 425 cmd.cab.header.payload_bytes = 426 sizeof(cmd.cab) - sizeof(cmd.cab.header); 427 428 dc_dmub_srv_cmd_queue(dc->ctx->dmub_srv, &cmd); 429 dc_dmub_srv_cmd_execute(dc->ctx->dmub_srv); 430 dc_dmub_srv_wait_idle(dc->ctx->dmub_srv); 431 432 return true; 433 } 434 435 /* Send DMCUB message with SubVP pipe info 436 * - For each pipe in context, populate payload with required SubVP information 437 * if the pipe is using SubVP for MCLK switch 438 * - This function must be called while the DMUB HW lock is acquired by driver 439 */ 440 void dcn32_commit_subvp_config(struct dc *dc, struct dc_state *context) 441 { 442 int i; 443 bool enable_subvp = false; 444 445 if (!dc->ctx || !dc->ctx->dmub_srv) 446 return; 447 448 for (i = 0; i < dc->res_pool->pipe_count; i++) { 449 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; 450 451 if (pipe_ctx->stream && pipe_ctx->stream->mall_stream_config.paired_stream && 452 pipe_ctx->stream->mall_stream_config.type == SUBVP_MAIN) { 453 // There is at least 1 SubVP pipe, so enable SubVP 454 enable_subvp = true; 455 break; 456 } 457 } 458 dc_dmub_setup_subvp_dmub_command(dc, context, enable_subvp); 459 } 460 461 /* Sub-Viewport DMUB lock needs to be acquired by driver whenever SubVP is active and: 462 * 1. Any full update for any SubVP main pipe 463 * 2. Any immediate flip for any SubVP pipe 464 * 3. Any flip for DRR pipe 465 * 4. If SubVP was previously in use (i.e. in old context) 466 */ 467 void dcn32_subvp_pipe_control_lock(struct dc *dc, 468 struct dc_state *context, 469 bool lock, 470 bool should_lock_all_pipes, 471 struct pipe_ctx *top_pipe_to_program, 472 bool subvp_prev_use) 473 { 474 unsigned int i = 0; 475 bool subvp_immediate_flip = false; 476 bool subvp_in_use = false; 477 struct pipe_ctx *pipe; 478 479 for (i = 0; i < dc->res_pool->pipe_count; i++) { 480 pipe = &context->res_ctx.pipe_ctx[i]; 481 482 if (pipe->stream && pipe->plane_state && pipe->stream->mall_stream_config.type == SUBVP_MAIN) { 483 subvp_in_use = true; 484 break; 485 } 486 } 487 488 if (top_pipe_to_program && top_pipe_to_program->stream && top_pipe_to_program->plane_state) { 489 if (top_pipe_to_program->stream->mall_stream_config.type == SUBVP_MAIN && 490 top_pipe_to_program->plane_state->flip_immediate) 491 subvp_immediate_flip = true; 492 } 493 494 // Don't need to lock for DRR VSYNC flips -- FW will wait for DRR pending update cleared. 495 if ((subvp_in_use && (should_lock_all_pipes || subvp_immediate_flip)) || (!subvp_in_use && subvp_prev_use)) { 496 union dmub_inbox0_cmd_lock_hw hw_lock_cmd = { 0 }; 497 498 if (!lock) { 499 for (i = 0; i < dc->res_pool->pipe_count; i++) { 500 pipe = &context->res_ctx.pipe_ctx[i]; 501 if (pipe->stream && pipe->plane_state && pipe->stream->mall_stream_config.type == SUBVP_MAIN && 502 should_lock_all_pipes) 503 pipe->stream_res.tg->funcs->wait_for_state(pipe->stream_res.tg, CRTC_STATE_VBLANK); 504 } 505 } 506 507 hw_lock_cmd.bits.command_code = DMUB_INBOX0_CMD__HW_LOCK; 508 hw_lock_cmd.bits.hw_lock_client = HW_LOCK_CLIENT_DRIVER; 509 hw_lock_cmd.bits.lock = lock; 510 hw_lock_cmd.bits.should_release = !lock; 511 dmub_hw_lock_mgr_inbox0_cmd(dc->ctx->dmub_srv, hw_lock_cmd); 512 } 513 } 514 515 516 static bool dcn32_set_mpc_shaper_3dlut( 517 struct pipe_ctx *pipe_ctx, const struct dc_stream_state *stream) 518 { 519 struct dpp *dpp_base = pipe_ctx->plane_res.dpp; 520 int mpcc_id = pipe_ctx->plane_res.hubp->inst; 521 struct mpc *mpc = pipe_ctx->stream_res.opp->ctx->dc->res_pool->mpc; 522 bool result = false; 523 524 const struct pwl_params *shaper_lut = NULL; 525 //get the shaper lut params 526 if (stream->func_shaper) { 527 if (stream->func_shaper->type == TF_TYPE_HWPWL) 528 shaper_lut = &stream->func_shaper->pwl; 529 else if (stream->func_shaper->type == TF_TYPE_DISTRIBUTED_POINTS) { 530 cm_helper_translate_curve_to_hw_format( 531 stream->func_shaper, 532 &dpp_base->shaper_params, true); 533 shaper_lut = &dpp_base->shaper_params; 534 } 535 } 536 537 if (stream->lut3d_func && 538 stream->lut3d_func->state.bits.initialized == 1) { 539 540 result = mpc->funcs->program_3dlut(mpc, 541 &stream->lut3d_func->lut_3d, 542 mpcc_id); 543 544 result = mpc->funcs->program_shaper(mpc, 545 shaper_lut, 546 mpcc_id); 547 } 548 549 return result; 550 } 551 552 bool dcn32_set_mcm_luts( 553 struct pipe_ctx *pipe_ctx, const struct dc_plane_state *plane_state) 554 { 555 struct dpp *dpp_base = pipe_ctx->plane_res.dpp; 556 int mpcc_id = pipe_ctx->plane_res.hubp->inst; 557 struct mpc *mpc = pipe_ctx->stream_res.opp->ctx->dc->res_pool->mpc; 558 bool result = true; 559 struct pwl_params *lut_params = NULL; 560 561 // 1D LUT 562 if (plane_state->blend_tf) { 563 if (plane_state->blend_tf->type == TF_TYPE_HWPWL) 564 lut_params = &plane_state->blend_tf->pwl; 565 else if (plane_state->blend_tf->type == TF_TYPE_DISTRIBUTED_POINTS) { 566 cm_helper_translate_curve_to_hw_format( 567 plane_state->blend_tf, 568 &dpp_base->regamma_params, false); 569 lut_params = &dpp_base->regamma_params; 570 } 571 } 572 result = mpc->funcs->program_1dlut(mpc, lut_params, mpcc_id); 573 574 // Shaper 575 if (plane_state->in_shaper_func) { 576 if (plane_state->in_shaper_func->type == TF_TYPE_HWPWL) 577 lut_params = &plane_state->in_shaper_func->pwl; 578 else if (plane_state->in_shaper_func->type == TF_TYPE_DISTRIBUTED_POINTS) { 579 // TODO: dpp_base replace 580 ASSERT(false); 581 cm_helper_translate_curve_to_hw_format( 582 plane_state->in_shaper_func, 583 &dpp_base->shaper_params, true); 584 lut_params = &dpp_base->shaper_params; 585 } 586 } 587 588 result = mpc->funcs->program_shaper(mpc, lut_params, mpcc_id); 589 590 // 3D 591 if (plane_state->lut3d_func && plane_state->lut3d_func->state.bits.initialized == 1) 592 result = mpc->funcs->program_3dlut(mpc, &plane_state->lut3d_func->lut_3d, mpcc_id); 593 else 594 result = mpc->funcs->program_3dlut(mpc, NULL, mpcc_id); 595 596 return result; 597 } 598 599 bool dcn32_set_input_transfer_func(struct dc *dc, 600 struct pipe_ctx *pipe_ctx, 601 const struct dc_plane_state *plane_state) 602 { 603 struct dce_hwseq *hws = dc->hwseq; 604 struct mpc *mpc = dc->res_pool->mpc; 605 struct dpp *dpp_base = pipe_ctx->plane_res.dpp; 606 607 enum dc_transfer_func_predefined tf; 608 bool result = true; 609 struct pwl_params *params = NULL; 610 611 if (mpc == NULL || plane_state == NULL) 612 return false; 613 614 tf = TRANSFER_FUNCTION_UNITY; 615 616 if (plane_state->in_transfer_func && 617 plane_state->in_transfer_func->type == TF_TYPE_PREDEFINED) 618 tf = plane_state->in_transfer_func->tf; 619 620 dpp_base->funcs->dpp_set_pre_degam(dpp_base, tf); 621 622 if (plane_state->in_transfer_func) { 623 if (plane_state->in_transfer_func->type == TF_TYPE_HWPWL) 624 params = &plane_state->in_transfer_func->pwl; 625 else if (plane_state->in_transfer_func->type == TF_TYPE_DISTRIBUTED_POINTS && 626 cm3_helper_translate_curve_to_hw_format(plane_state->in_transfer_func, 627 &dpp_base->degamma_params, false)) 628 params = &dpp_base->degamma_params; 629 } 630 631 dpp_base->funcs->dpp_program_gamcor_lut(dpp_base, params); 632 633 if (pipe_ctx->stream_res.opp && 634 pipe_ctx->stream_res.opp->ctx && 635 hws->funcs.set_mcm_luts) 636 result = hws->funcs.set_mcm_luts(pipe_ctx, plane_state); 637 638 return result; 639 } 640 641 bool dcn32_set_output_transfer_func(struct dc *dc, 642 struct pipe_ctx *pipe_ctx, 643 const struct dc_stream_state *stream) 644 { 645 int mpcc_id = pipe_ctx->plane_res.hubp->inst; 646 struct mpc *mpc = pipe_ctx->stream_res.opp->ctx->dc->res_pool->mpc; 647 struct pwl_params *params = NULL; 648 bool ret = false; 649 650 /* program OGAM or 3DLUT only for the top pipe*/ 651 if (pipe_ctx->top_pipe == NULL) { 652 /*program shaper and 3dlut in MPC*/ 653 ret = dcn32_set_mpc_shaper_3dlut(pipe_ctx, stream); 654 if (ret == false && mpc->funcs->set_output_gamma && stream->out_transfer_func) { 655 if (stream->out_transfer_func->type == TF_TYPE_HWPWL) 656 params = &stream->out_transfer_func->pwl; 657 else if (pipe_ctx->stream->out_transfer_func->type == 658 TF_TYPE_DISTRIBUTED_POINTS && 659 cm3_helper_translate_curve_to_hw_format( 660 stream->out_transfer_func, 661 &mpc->blender_params, false)) 662 params = &mpc->blender_params; 663 /* there are no ROM LUTs in OUTGAM */ 664 if (stream->out_transfer_func->type == TF_TYPE_PREDEFINED) 665 BREAK_TO_DEBUGGER(); 666 } 667 } 668 669 mpc->funcs->set_output_gamma(mpc, mpcc_id, params); 670 return ret; 671 } 672 673 /* Program P-State force value according to if pipe is using SubVP or not: 674 * 1. Reset P-State force on all pipes first 675 * 2. For each main pipe, force P-State disallow (P-State allow moderated by DMUB) 676 */ 677 void dcn32_subvp_update_force_pstate(struct dc *dc, struct dc_state *context) 678 { 679 int i; 680 int num_subvp = 0; 681 /* Unforce p-state for each pipe 682 */ 683 for (i = 0; i < dc->res_pool->pipe_count; i++) { 684 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; 685 struct hubp *hubp = pipe->plane_res.hubp; 686 687 if (hubp && hubp->funcs->hubp_update_force_pstate_disallow) 688 hubp->funcs->hubp_update_force_pstate_disallow(hubp, false); 689 if (pipe->stream && pipe->stream->mall_stream_config.type == SUBVP_MAIN) 690 num_subvp++; 691 } 692 693 if (num_subvp == 0) 694 return; 695 696 /* Loop through each pipe -- for each subvp main pipe force p-state allow equal to false. 697 */ 698 for (i = 0; i < dc->res_pool->pipe_count; i++) { 699 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; 700 701 // For SubVP + DRR, also force disallow on the DRR pipe 702 // (We will force allow in the DMUB sequence -- some DRR timings by default won't allow P-State so we have 703 // to force once the vblank is stretched). 704 if (pipe->stream && pipe->plane_state && (pipe->stream->mall_stream_config.type == SUBVP_MAIN || 705 (pipe->stream->mall_stream_config.type == SUBVP_NONE && pipe->stream->ignore_msa_timing_param))) { 706 struct hubp *hubp = pipe->plane_res.hubp; 707 708 if (hubp && hubp->funcs->hubp_update_force_pstate_disallow) 709 hubp->funcs->hubp_update_force_pstate_disallow(hubp, true); 710 } 711 } 712 } 713 714 /* Update MALL_SEL register based on if pipe / plane 715 * is a phantom pipe, main pipe, and if using MALL 716 * for SS. 717 */ 718 void dcn32_update_mall_sel(struct dc *dc, struct dc_state *context) 719 { 720 int i; 721 unsigned int num_ways = dcn32_calculate_cab_allocation(dc, context); 722 bool cache_cursor = false; 723 724 for (i = 0; i < dc->res_pool->pipe_count; i++) { 725 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; 726 struct hubp *hubp = pipe->plane_res.hubp; 727 728 if (pipe->stream && pipe->plane_state && hubp && hubp->funcs->hubp_update_mall_sel) { 729 int cursor_size = hubp->curs_attr.pitch * hubp->curs_attr.height; 730 731 switch (hubp->curs_attr.color_format) { 732 case CURSOR_MODE_MONO: 733 cursor_size /= 2; 734 break; 735 case CURSOR_MODE_COLOR_1BIT_AND: 736 case CURSOR_MODE_COLOR_PRE_MULTIPLIED_ALPHA: 737 case CURSOR_MODE_COLOR_UN_PRE_MULTIPLIED_ALPHA: 738 cursor_size *= 4; 739 break; 740 741 case CURSOR_MODE_COLOR_64BIT_FP_PRE_MULTIPLIED: 742 case CURSOR_MODE_COLOR_64BIT_FP_UN_PRE_MULTIPLIED: 743 default: 744 cursor_size *= 8; 745 break; 746 } 747 748 if (cursor_size > 16384) 749 cache_cursor = true; 750 751 if (pipe->stream->mall_stream_config.type == SUBVP_PHANTOM) { 752 hubp->funcs->hubp_update_mall_sel(hubp, 1, false); 753 } else { 754 // MALL not supported with Stereo3D 755 hubp->funcs->hubp_update_mall_sel(hubp, 756 num_ways <= dc->caps.cache_num_ways && 757 pipe->stream->link->psr_settings.psr_version == DC_PSR_VERSION_UNSUPPORTED && 758 pipe->plane_state->address.type != PLN_ADDR_TYPE_GRPH_STEREO && 759 !pipe->plane_state->address.tmz_surface ? 2 : 0, 760 cache_cursor); 761 } 762 } 763 } 764 } 765 766 /* Program the sub-viewport pipe configuration after the main / phantom pipes 767 * have been programmed in hardware. 768 * 1. Update force P-State for all the main pipes (disallow P-state) 769 * 2. Update MALL_SEL register 770 * 3. Program FORCE_ONE_ROW_FOR_FRAME for main subvp pipes 771 */ 772 void dcn32_program_mall_pipe_config(struct dc *dc, struct dc_state *context) 773 { 774 int i; 775 struct dce_hwseq *hws = dc->hwseq; 776 777 // Don't force p-state disallow -- can't block dummy p-state 778 779 // Update MALL_SEL register for each pipe 780 if (hws && hws->funcs.update_mall_sel) 781 hws->funcs.update_mall_sel(dc, context); 782 783 // Program FORCE_ONE_ROW_FOR_FRAME and CURSOR_REQ_MODE for main subvp pipes 784 for (i = 0; i < dc->res_pool->pipe_count; i++) { 785 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; 786 struct hubp *hubp = pipe->plane_res.hubp; 787 788 if (pipe->stream && hubp && hubp->funcs->hubp_prepare_subvp_buffering) { 789 /* TODO - remove setting CURSOR_REQ_MODE to 0 for legacy cases 790 * - need to investigate single pipe MPO + SubVP case to 791 * see if CURSOR_REQ_MODE will be back to 1 for SubVP 792 * when it should be 0 for MPO 793 */ 794 if (pipe->stream->mall_stream_config.type == SUBVP_MAIN) { 795 hubp->funcs->hubp_prepare_subvp_buffering(hubp, true); 796 } 797 } 798 } 799 } 800 801 void dcn32_init_hw(struct dc *dc) 802 { 803 struct abm **abms = dc->res_pool->multiple_abms; 804 struct dce_hwseq *hws = dc->hwseq; 805 struct dc_bios *dcb = dc->ctx->dc_bios; 806 struct resource_pool *res_pool = dc->res_pool; 807 int i; 808 int edp_num; 809 uint32_t backlight = MAX_BACKLIGHT_LEVEL; 810 811 if (dc->clk_mgr && dc->clk_mgr->funcs->init_clocks) 812 dc->clk_mgr->funcs->init_clocks(dc->clk_mgr); 813 814 // Initialize the dccg 815 if (res_pool->dccg->funcs->dccg_init) 816 res_pool->dccg->funcs->dccg_init(res_pool->dccg); 817 818 if (!dcb->funcs->is_accelerated_mode(dcb)) { 819 hws->funcs.bios_golden_init(dc); 820 hws->funcs.disable_vga(dc->hwseq); 821 } 822 823 // Set default OPTC memory power states 824 if (dc->debug.enable_mem_low_power.bits.optc) { 825 // Shutdown when unassigned and light sleep in VBLANK 826 REG_SET_2(ODM_MEM_PWR_CTRL3, 0, ODM_MEM_UNASSIGNED_PWR_MODE, 3, ODM_MEM_VBLANK_PWR_MODE, 1); 827 } 828 829 if (dc->debug.enable_mem_low_power.bits.vga) { 830 // Power down VGA memory 831 REG_UPDATE(MMHUBBUB_MEM_PWR_CNTL, VGA_MEM_PWR_FORCE, 1); 832 } 833 834 if (dc->ctx->dc_bios->fw_info_valid) { 835 res_pool->ref_clocks.xtalin_clock_inKhz = 836 dc->ctx->dc_bios->fw_info.pll_info.crystal_frequency; 837 838 if (res_pool->dccg && res_pool->hubbub) { 839 (res_pool->dccg->funcs->get_dccg_ref_freq)(res_pool->dccg, 840 dc->ctx->dc_bios->fw_info.pll_info.crystal_frequency, 841 &res_pool->ref_clocks.dccg_ref_clock_inKhz); 842 843 (res_pool->hubbub->funcs->get_dchub_ref_freq)(res_pool->hubbub, 844 res_pool->ref_clocks.dccg_ref_clock_inKhz, 845 &res_pool->ref_clocks.dchub_ref_clock_inKhz); 846 } else { 847 // Not all ASICs have DCCG sw component 848 res_pool->ref_clocks.dccg_ref_clock_inKhz = 849 res_pool->ref_clocks.xtalin_clock_inKhz; 850 res_pool->ref_clocks.dchub_ref_clock_inKhz = 851 res_pool->ref_clocks.xtalin_clock_inKhz; 852 } 853 } else 854 ASSERT_CRITICAL(false); 855 856 for (i = 0; i < dc->link_count; i++) { 857 /* Power up AND update implementation according to the 858 * required signal (which may be different from the 859 * default signal on connector). 860 */ 861 struct dc_link *link = dc->links[i]; 862 863 link->link_enc->funcs->hw_init(link->link_enc); 864 865 /* Check for enabled DIG to identify enabled display */ 866 if (link->link_enc->funcs->is_dig_enabled && 867 link->link_enc->funcs->is_dig_enabled(link->link_enc)) { 868 link->link_status.link_active = true; 869 link->phy_state.symclk_state = SYMCLK_ON_TX_ON; 870 if (link->link_enc->funcs->fec_is_active && 871 link->link_enc->funcs->fec_is_active(link->link_enc)) 872 link->fec_state = dc_link_fec_enabled; 873 } 874 } 875 876 /* Power gate DSCs */ 877 for (i = 0; i < res_pool->res_cap->num_dsc; i++) 878 if (hws->funcs.dsc_pg_control != NULL) 879 hws->funcs.dsc_pg_control(hws, res_pool->dscs[i]->inst, false); 880 881 /* we want to turn off all dp displays before doing detection */ 882 dc_link_blank_all_dp_displays(dc); 883 884 /* If taking control over from VBIOS, we may want to optimize our first 885 * mode set, so we need to skip powering down pipes until we know which 886 * pipes we want to use. 887 * Otherwise, if taking control is not possible, we need to power 888 * everything down. 889 */ 890 if (dcb->funcs->is_accelerated_mode(dcb) || !dc->config.seamless_boot_edp_requested) { 891 hws->funcs.init_pipes(dc, dc->current_state); 892 if (dc->res_pool->hubbub->funcs->allow_self_refresh_control) 893 dc->res_pool->hubbub->funcs->allow_self_refresh_control(dc->res_pool->hubbub, 894 !dc->res_pool->hubbub->ctx->dc->debug.disable_stutter); 895 } 896 897 /* In headless boot cases, DIG may be turned 898 * on which causes HW/SW discrepancies. 899 * To avoid this, power down hardware on boot 900 * if DIG is turned on and seamless boot not enabled 901 */ 902 if (!dc->config.seamless_boot_edp_requested) { 903 struct dc_link *edp_links[MAX_NUM_EDP]; 904 struct dc_link *edp_link; 905 906 get_edp_links(dc, edp_links, &edp_num); 907 if (edp_num) { 908 for (i = 0; i < edp_num; i++) { 909 edp_link = edp_links[i]; 910 if (edp_link->link_enc->funcs->is_dig_enabled && 911 edp_link->link_enc->funcs->is_dig_enabled(edp_link->link_enc) && 912 dc->hwss.edp_backlight_control && 913 dc->hwss.power_down && 914 dc->hwss.edp_power_control) { 915 dc->hwss.edp_backlight_control(edp_link, false); 916 dc->hwss.power_down(dc); 917 dc->hwss.edp_power_control(edp_link, false); 918 } 919 } 920 } else { 921 for (i = 0; i < dc->link_count; i++) { 922 struct dc_link *link = dc->links[i]; 923 924 if (link->link_enc->funcs->is_dig_enabled && 925 link->link_enc->funcs->is_dig_enabled(link->link_enc) && 926 dc->hwss.power_down) { 927 dc->hwss.power_down(dc); 928 break; 929 } 930 931 } 932 } 933 } 934 935 for (i = 0; i < res_pool->audio_count; i++) { 936 struct audio *audio = res_pool->audios[i]; 937 938 audio->funcs->hw_init(audio); 939 } 940 941 for (i = 0; i < dc->link_count; i++) { 942 struct dc_link *link = dc->links[i]; 943 944 if (link->panel_cntl) 945 backlight = link->panel_cntl->funcs->hw_init(link->panel_cntl); 946 } 947 948 for (i = 0; i < dc->res_pool->pipe_count; i++) { 949 if (abms[i] != NULL && abms[i]->funcs != NULL) 950 abms[i]->funcs->abm_init(abms[i], backlight); 951 } 952 953 /* power AFMT HDMI memory TODO: may move to dis/en output save power*/ 954 REG_WRITE(DIO_MEM_PWR_CTRL, 0); 955 956 if (!dc->debug.disable_clock_gate) { 957 /* enable all DCN clock gating */ 958 REG_WRITE(DCCG_GATE_DISABLE_CNTL, 0); 959 960 REG_WRITE(DCCG_GATE_DISABLE_CNTL2, 0); 961 962 REG_UPDATE(DCFCLK_CNTL, DCFCLK_GATE_DIS, 0); 963 } 964 if (hws->funcs.enable_power_gating_plane) 965 hws->funcs.enable_power_gating_plane(dc->hwseq, true); 966 967 if (!dcb->funcs->is_accelerated_mode(dcb) && dc->res_pool->hubbub->funcs->init_watermarks) 968 dc->res_pool->hubbub->funcs->init_watermarks(dc->res_pool->hubbub); 969 970 if (dc->clk_mgr->funcs->notify_wm_ranges) 971 dc->clk_mgr->funcs->notify_wm_ranges(dc->clk_mgr); 972 973 if (dc->clk_mgr->funcs->set_hard_max_memclk) 974 dc->clk_mgr->funcs->set_hard_max_memclk(dc->clk_mgr); 975 976 if (dc->res_pool->hubbub->funcs->force_pstate_change_control) 977 dc->res_pool->hubbub->funcs->force_pstate_change_control( 978 dc->res_pool->hubbub, false, false); 979 980 if (dc->res_pool->hubbub->funcs->init_crb) 981 dc->res_pool->hubbub->funcs->init_crb(dc->res_pool->hubbub); 982 983 // Get DMCUB capabilities 984 if (dc->ctx->dmub_srv) { 985 dc_dmub_srv_query_caps_cmd(dc->ctx->dmub_srv->dmub); 986 dc->caps.dmub_caps.psr = dc->ctx->dmub_srv->dmub->feature_caps.psr; 987 } 988 989 /* Enable support for ODM and windowed MPO if policy flag is set */ 990 if (dc->debug.enable_single_display_2to1_odm_policy) 991 dc->config.enable_windowed_mpo_odm = true; 992 } 993 994 static int calc_mpc_flow_ctrl_cnt(const struct dc_stream_state *stream, 995 int opp_cnt) 996 { 997 bool hblank_halved = optc2_is_two_pixels_per_containter(&stream->timing); 998 int flow_ctrl_cnt; 999 1000 if (opp_cnt >= 2) 1001 hblank_halved = true; 1002 1003 flow_ctrl_cnt = stream->timing.h_total - stream->timing.h_addressable - 1004 stream->timing.h_border_left - 1005 stream->timing.h_border_right; 1006 1007 if (hblank_halved) 1008 flow_ctrl_cnt /= 2; 1009 1010 /* ODM combine 4:1 case */ 1011 if (opp_cnt == 4) 1012 flow_ctrl_cnt /= 2; 1013 1014 return flow_ctrl_cnt; 1015 } 1016 1017 static void update_dsc_on_stream(struct pipe_ctx *pipe_ctx, bool enable) 1018 { 1019 struct display_stream_compressor *dsc = pipe_ctx->stream_res.dsc; 1020 struct dc_stream_state *stream = pipe_ctx->stream; 1021 struct pipe_ctx *odm_pipe; 1022 int opp_cnt = 1; 1023 1024 ASSERT(dsc); 1025 for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) 1026 opp_cnt++; 1027 1028 if (enable) { 1029 struct dsc_config dsc_cfg; 1030 struct dsc_optc_config dsc_optc_cfg; 1031 enum optc_dsc_mode optc_dsc_mode; 1032 1033 /* Enable DSC hw block */ 1034 dsc_cfg.pic_width = (stream->timing.h_addressable + stream->timing.h_border_left + stream->timing.h_border_right) / opp_cnt; 1035 dsc_cfg.pic_height = stream->timing.v_addressable + stream->timing.v_border_top + stream->timing.v_border_bottom; 1036 dsc_cfg.pixel_encoding = stream->timing.pixel_encoding; 1037 dsc_cfg.color_depth = stream->timing.display_color_depth; 1038 dsc_cfg.is_odm = pipe_ctx->next_odm_pipe ? true : false; 1039 dsc_cfg.dc_dsc_cfg = stream->timing.dsc_cfg; 1040 ASSERT(dsc_cfg.dc_dsc_cfg.num_slices_h % opp_cnt == 0); 1041 dsc_cfg.dc_dsc_cfg.num_slices_h /= opp_cnt; 1042 1043 dsc->funcs->dsc_set_config(dsc, &dsc_cfg, &dsc_optc_cfg); 1044 dsc->funcs->dsc_enable(dsc, pipe_ctx->stream_res.opp->inst); 1045 for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) { 1046 struct display_stream_compressor *odm_dsc = odm_pipe->stream_res.dsc; 1047 1048 ASSERT(odm_dsc); 1049 odm_dsc->funcs->dsc_set_config(odm_dsc, &dsc_cfg, &dsc_optc_cfg); 1050 odm_dsc->funcs->dsc_enable(odm_dsc, odm_pipe->stream_res.opp->inst); 1051 } 1052 dsc_cfg.dc_dsc_cfg.num_slices_h *= opp_cnt; 1053 dsc_cfg.pic_width *= opp_cnt; 1054 1055 optc_dsc_mode = dsc_optc_cfg.is_pixel_format_444 ? OPTC_DSC_ENABLED_444 : OPTC_DSC_ENABLED_NATIVE_SUBSAMPLED; 1056 1057 /* Enable DSC in OPTC */ 1058 DC_LOG_DSC("Setting optc DSC config for tg instance %d:", pipe_ctx->stream_res.tg->inst); 1059 pipe_ctx->stream_res.tg->funcs->set_dsc_config(pipe_ctx->stream_res.tg, 1060 optc_dsc_mode, 1061 dsc_optc_cfg.bytes_per_pixel, 1062 dsc_optc_cfg.slice_width); 1063 } else { 1064 /* disable DSC in OPTC */ 1065 pipe_ctx->stream_res.tg->funcs->set_dsc_config( 1066 pipe_ctx->stream_res.tg, 1067 OPTC_DSC_DISABLED, 0, 0); 1068 1069 /* disable DSC block */ 1070 dsc->funcs->dsc_disable(pipe_ctx->stream_res.dsc); 1071 for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) { 1072 ASSERT(odm_pipe->stream_res.dsc); 1073 odm_pipe->stream_res.dsc->funcs->dsc_disable(odm_pipe->stream_res.dsc); 1074 } 1075 } 1076 } 1077 1078 /* 1079 * Given any pipe_ctx, return the total ODM combine factor, and optionally return 1080 * the OPPids which are used 1081 * */ 1082 static unsigned int get_odm_config(struct pipe_ctx *pipe_ctx, unsigned int *opp_instances) 1083 { 1084 unsigned int opp_count = 1; 1085 struct pipe_ctx *odm_pipe; 1086 1087 /* First get to the top pipe */ 1088 for (odm_pipe = pipe_ctx; odm_pipe->prev_odm_pipe; odm_pipe = odm_pipe->prev_odm_pipe) 1089 ; 1090 1091 /* First pipe is always used */ 1092 if (opp_instances) 1093 opp_instances[0] = odm_pipe->stream_res.opp->inst; 1094 1095 /* Find and count odm pipes, if any */ 1096 for (odm_pipe = odm_pipe->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) { 1097 if (opp_instances) 1098 opp_instances[opp_count] = odm_pipe->stream_res.opp->inst; 1099 opp_count++; 1100 } 1101 1102 return opp_count; 1103 } 1104 1105 void dcn32_update_odm(struct dc *dc, struct dc_state *context, struct pipe_ctx *pipe_ctx) 1106 { 1107 struct pipe_ctx *odm_pipe; 1108 int opp_cnt = 0; 1109 int opp_inst[MAX_PIPES] = {0}; 1110 bool rate_control_2x_pclk = (pipe_ctx->stream->timing.flags.INTERLACE || optc2_is_two_pixels_per_containter(&pipe_ctx->stream->timing)); 1111 struct mpc_dwb_flow_control flow_control; 1112 struct mpc *mpc = dc->res_pool->mpc; 1113 int i; 1114 1115 opp_cnt = get_odm_config(pipe_ctx, opp_inst); 1116 1117 if (opp_cnt > 1) 1118 pipe_ctx->stream_res.tg->funcs->set_odm_combine( 1119 pipe_ctx->stream_res.tg, 1120 opp_inst, opp_cnt, 1121 &pipe_ctx->stream->timing); 1122 else 1123 pipe_ctx->stream_res.tg->funcs->set_odm_bypass( 1124 pipe_ctx->stream_res.tg, &pipe_ctx->stream->timing); 1125 1126 rate_control_2x_pclk = rate_control_2x_pclk || opp_cnt > 1; 1127 flow_control.flow_ctrl_mode = 0; 1128 flow_control.flow_ctrl_cnt0 = 0x80; 1129 flow_control.flow_ctrl_cnt1 = calc_mpc_flow_ctrl_cnt(pipe_ctx->stream, opp_cnt); 1130 if (mpc->funcs->set_out_rate_control) { 1131 for (i = 0; i < opp_cnt; ++i) { 1132 mpc->funcs->set_out_rate_control( 1133 mpc, opp_inst[i], 1134 true, 1135 rate_control_2x_pclk, 1136 &flow_control); 1137 } 1138 } 1139 1140 for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) { 1141 odm_pipe->stream_res.opp->funcs->opp_pipe_clock_control( 1142 odm_pipe->stream_res.opp, 1143 true); 1144 } 1145 1146 if (pipe_ctx->stream_res.dsc) { 1147 struct pipe_ctx *current_pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[pipe_ctx->pipe_idx]; 1148 1149 update_dsc_on_stream(pipe_ctx, pipe_ctx->stream->timing.flags.DSC); 1150 1151 /* Check if no longer using pipe for ODM, then need to disconnect DSC for that pipe */ 1152 if (!pipe_ctx->next_odm_pipe && current_pipe_ctx->next_odm_pipe && 1153 current_pipe_ctx->next_odm_pipe->stream_res.dsc) { 1154 struct display_stream_compressor *dsc = current_pipe_ctx->next_odm_pipe->stream_res.dsc; 1155 /* disconnect DSC block from stream */ 1156 dsc->funcs->dsc_disconnect(dsc); 1157 } 1158 } 1159 } 1160 1161 unsigned int dcn32_calculate_dccg_k1_k2_values(struct pipe_ctx *pipe_ctx, unsigned int *k1_div, unsigned int *k2_div) 1162 { 1163 struct dc_stream_state *stream = pipe_ctx->stream; 1164 unsigned int odm_combine_factor = 0; 1165 bool two_pix_per_container = false; 1166 1167 // For phantom pipes, use the same programming as the main pipes 1168 if (pipe_ctx->stream->mall_stream_config.type == SUBVP_PHANTOM) { 1169 stream = pipe_ctx->stream->mall_stream_config.paired_stream; 1170 } 1171 two_pix_per_container = optc2_is_two_pixels_per_containter(&stream->timing); 1172 odm_combine_factor = get_odm_config(pipe_ctx, NULL); 1173 1174 if (pipe_ctx->stream->signal == SIGNAL_TYPE_VIRTUAL) 1175 return odm_combine_factor; 1176 1177 if (is_dp_128b_132b_signal(pipe_ctx)) { 1178 *k2_div = PIXEL_RATE_DIV_BY_1; 1179 } else if (dc_is_hdmi_tmds_signal(pipe_ctx->stream->signal) || dc_is_dvi_signal(pipe_ctx->stream->signal)) { 1180 *k1_div = PIXEL_RATE_DIV_BY_1; 1181 if (stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR420) 1182 *k2_div = PIXEL_RATE_DIV_BY_2; 1183 else 1184 *k2_div = PIXEL_RATE_DIV_BY_4; 1185 } else if (dc_is_dp_signal(pipe_ctx->stream->signal)) { 1186 if (two_pix_per_container) { 1187 *k1_div = PIXEL_RATE_DIV_BY_1; 1188 *k2_div = PIXEL_RATE_DIV_BY_2; 1189 } else { 1190 *k1_div = PIXEL_RATE_DIV_BY_1; 1191 *k2_div = PIXEL_RATE_DIV_BY_4; 1192 if ((odm_combine_factor == 2) || dcn32_is_dp_dig_pixel_rate_div_policy(pipe_ctx)) 1193 *k2_div = PIXEL_RATE_DIV_BY_2; 1194 } 1195 } 1196 1197 if ((*k1_div == PIXEL_RATE_DIV_NA) && (*k2_div == PIXEL_RATE_DIV_NA)) 1198 ASSERT(false); 1199 1200 return odm_combine_factor; 1201 } 1202 1203 void dcn32_set_pixels_per_cycle(struct pipe_ctx *pipe_ctx) 1204 { 1205 uint32_t pix_per_cycle = 1; 1206 uint32_t odm_combine_factor = 1; 1207 1208 if (!pipe_ctx || !pipe_ctx->stream || !pipe_ctx->stream_res.stream_enc) 1209 return; 1210 1211 odm_combine_factor = get_odm_config(pipe_ctx, NULL); 1212 if (optc2_is_two_pixels_per_containter(&pipe_ctx->stream->timing) || odm_combine_factor > 1 1213 || dcn32_is_dp_dig_pixel_rate_div_policy(pipe_ctx)) 1214 pix_per_cycle = 2; 1215 1216 if (pipe_ctx->stream_res.stream_enc->funcs->set_input_mode) 1217 pipe_ctx->stream_res.stream_enc->funcs->set_input_mode(pipe_ctx->stream_res.stream_enc, 1218 pix_per_cycle); 1219 } 1220 1221 void dcn32_unblank_stream(struct pipe_ctx *pipe_ctx, 1222 struct dc_link_settings *link_settings) 1223 { 1224 struct encoder_unblank_param params = {0}; 1225 struct dc_stream_state *stream = pipe_ctx->stream; 1226 struct dc_link *link = stream->link; 1227 struct dce_hwseq *hws = link->dc->hwseq; 1228 struct pipe_ctx *odm_pipe; 1229 uint32_t pix_per_cycle = 1; 1230 1231 params.opp_cnt = 1; 1232 for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) 1233 params.opp_cnt++; 1234 1235 /* only 3 items below are used by unblank */ 1236 params.timing = pipe_ctx->stream->timing; 1237 1238 params.link_settings.link_rate = link_settings->link_rate; 1239 1240 if (is_dp_128b_132b_signal(pipe_ctx)) { 1241 /* TODO - DP2.0 HW: Set ODM mode in dp hpo encoder here */ 1242 pipe_ctx->stream_res.hpo_dp_stream_enc->funcs->dp_unblank( 1243 pipe_ctx->stream_res.hpo_dp_stream_enc, 1244 pipe_ctx->stream_res.tg->inst); 1245 } else if (dc_is_dp_signal(pipe_ctx->stream->signal)) { 1246 if (optc2_is_two_pixels_per_containter(&stream->timing) || params.opp_cnt > 1 1247 || dcn32_is_dp_dig_pixel_rate_div_policy(pipe_ctx)) { 1248 params.timing.pix_clk_100hz /= 2; 1249 pix_per_cycle = 2; 1250 } 1251 pipe_ctx->stream_res.stream_enc->funcs->dp_set_odm_combine( 1252 pipe_ctx->stream_res.stream_enc, pix_per_cycle > 1); 1253 pipe_ctx->stream_res.stream_enc->funcs->dp_unblank(link, pipe_ctx->stream_res.stream_enc, ¶ms); 1254 } 1255 1256 if (link->local_sink && link->local_sink->sink_signal == SIGNAL_TYPE_EDP) 1257 hws->funcs.edp_backlight_control(link, true); 1258 } 1259 1260 bool dcn32_is_dp_dig_pixel_rate_div_policy(struct pipe_ctx *pipe_ctx) 1261 { 1262 struct dc *dc = pipe_ctx->stream->ctx->dc; 1263 1264 if (!is_h_timing_divisible_by_2(pipe_ctx->stream)) 1265 return false; 1266 1267 if (dc_is_dp_signal(pipe_ctx->stream->signal) && !is_dp_128b_132b_signal(pipe_ctx) && 1268 dc->debug.enable_dp_dig_pixel_rate_div_policy) 1269 return true; 1270 return false; 1271 } 1272 1273 static void apply_symclk_on_tx_off_wa(struct dc_link *link) 1274 { 1275 /* There are use cases where SYMCLK is referenced by OTG. For instance 1276 * for TMDS signal, OTG relies SYMCLK even if TX video output is off. 1277 * However current link interface will power off PHY when disabling link 1278 * output. This will turn off SYMCLK generated by PHY. The workaround is 1279 * to identify such case where SYMCLK is still in use by OTG when we 1280 * power off PHY. When this is detected, we will temporarily power PHY 1281 * back on and move PHY's SYMCLK state to SYMCLK_ON_TX_OFF by calling 1282 * program_pix_clk interface. When OTG is disabled, we will then power 1283 * off PHY by calling disable link output again. 1284 * 1285 * In future dcn generations, we plan to rework transmitter control 1286 * interface so that we could have an option to set SYMCLK ON TX OFF 1287 * state in one step without this workaround 1288 */ 1289 1290 struct dc *dc = link->ctx->dc; 1291 struct pipe_ctx *pipe_ctx = NULL; 1292 uint8_t i; 1293 1294 if (link->phy_state.symclk_ref_cnts.otg > 0) { 1295 for (i = 0; i < MAX_PIPES; i++) { 1296 pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[i]; 1297 if (pipe_ctx->stream && pipe_ctx->stream->link == link && pipe_ctx->top_pipe == NULL) { 1298 pipe_ctx->clock_source->funcs->program_pix_clk( 1299 pipe_ctx->clock_source, 1300 &pipe_ctx->stream_res.pix_clk_params, 1301 dp_get_link_encoding_format(&pipe_ctx->link_config.dp_link_settings), 1302 &pipe_ctx->pll_settings); 1303 link->phy_state.symclk_state = SYMCLK_ON_TX_OFF; 1304 break; 1305 } 1306 } 1307 } 1308 } 1309 1310 void dcn32_disable_link_output(struct dc_link *link, 1311 const struct link_resource *link_res, 1312 enum signal_type signal) 1313 { 1314 struct dc *dc = link->ctx->dc; 1315 const struct link_hwss *link_hwss = get_link_hwss(link, link_res); 1316 struct dmcu *dmcu = dc->res_pool->dmcu; 1317 1318 if (signal == SIGNAL_TYPE_EDP && 1319 link->dc->hwss.edp_backlight_control) 1320 link->dc->hwss.edp_backlight_control(link, false); 1321 else if (dmcu != NULL && dmcu->funcs->lock_phy) 1322 dmcu->funcs->lock_phy(dmcu); 1323 1324 link_hwss->disable_link_output(link, link_res, signal); 1325 link->phy_state.symclk_state = SYMCLK_OFF_TX_OFF; 1326 1327 if (signal == SIGNAL_TYPE_EDP && 1328 link->dc->hwss.edp_backlight_control) 1329 link->dc->hwss.edp_power_control(link, false); 1330 else if (dmcu != NULL && dmcu->funcs->lock_phy) 1331 dmcu->funcs->unlock_phy(dmcu); 1332 1333 dp_source_sequence_trace(link, DPCD_SOURCE_SEQ_AFTER_DISABLE_LINK_PHY); 1334 1335 apply_symclk_on_tx_off_wa(link); 1336 } 1337 1338 /* For SubVP the main pipe can have a viewport position change 1339 * without a full update. In this case we must also update the 1340 * viewport positions for the phantom pipe accordingly. 1341 */ 1342 void dcn32_update_phantom_vp_position(struct dc *dc, 1343 struct dc_state *context, 1344 struct pipe_ctx *phantom_pipe) 1345 { 1346 uint32_t i; 1347 struct dc_plane_state *phantom_plane = phantom_pipe->plane_state; 1348 1349 for (i = 0; i < dc->res_pool->pipe_count; i++) { 1350 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; 1351 1352 if (pipe->stream && pipe->stream->mall_stream_config.type == SUBVP_MAIN && 1353 pipe->stream->mall_stream_config.paired_stream == phantom_pipe->stream) { 1354 if (pipe->plane_state && pipe->plane_state->update_flags.bits.position_change) { 1355 1356 phantom_plane->src_rect.x = pipe->plane_state->src_rect.x; 1357 phantom_plane->src_rect.y = pipe->plane_state->src_rect.y; 1358 phantom_plane->clip_rect.x = pipe->plane_state->clip_rect.x; 1359 phantom_plane->dst_rect.x = pipe->plane_state->dst_rect.x; 1360 phantom_plane->dst_rect.y = pipe->plane_state->dst_rect.y; 1361 1362 phantom_pipe->plane_state->update_flags.bits.position_change = 1; 1363 resource_build_scaling_params(phantom_pipe); 1364 return; 1365 } 1366 } 1367 } 1368 } 1369 1370 bool dcn32_dsc_pg_status( 1371 struct dce_hwseq *hws, 1372 unsigned int dsc_inst) 1373 { 1374 uint32_t pwr_status = 0; 1375 1376 switch (dsc_inst) { 1377 case 0: /* DSC0 */ 1378 REG_GET(DOMAIN16_PG_STATUS, 1379 DOMAIN_PGFSM_PWR_STATUS, &pwr_status); 1380 break; 1381 case 1: /* DSC1 */ 1382 1383 REG_GET(DOMAIN17_PG_STATUS, 1384 DOMAIN_PGFSM_PWR_STATUS, &pwr_status); 1385 break; 1386 case 2: /* DSC2 */ 1387 REG_GET(DOMAIN18_PG_STATUS, 1388 DOMAIN_PGFSM_PWR_STATUS, &pwr_status); 1389 break; 1390 case 3: /* DSC3 */ 1391 REG_GET(DOMAIN19_PG_STATUS, 1392 DOMAIN_PGFSM_PWR_STATUS, &pwr_status); 1393 break; 1394 default: 1395 BREAK_TO_DEBUGGER(); 1396 break; 1397 } 1398 1399 return pwr_status == 0; 1400 } 1401 1402 void dcn32_update_dsc_pg(struct dc *dc, 1403 struct dc_state *context, 1404 bool safe_to_disable) 1405 { 1406 struct dce_hwseq *hws = dc->hwseq; 1407 int i; 1408 1409 for (i = 0; i < dc->res_pool->res_cap->num_dsc; i++) { 1410 struct display_stream_compressor *dsc = dc->res_pool->dscs[i]; 1411 bool is_dsc_ungated = hws->funcs.dsc_pg_status(hws, dsc->inst); 1412 1413 if (context->res_ctx.is_dsc_acquired[i]) { 1414 if (!is_dsc_ungated) { 1415 hws->funcs.dsc_pg_control(hws, dsc->inst, true); 1416 } 1417 } else if (safe_to_disable) { 1418 if (is_dsc_ungated) { 1419 hws->funcs.dsc_pg_control(hws, dsc->inst, false); 1420 } 1421 } 1422 } 1423 } 1424