1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 27 #include "dm_services.h" 28 #include "dm_helpers.h" 29 #include "core_types.h" 30 #include "resource.h" 31 #include "dccg.h" 32 #include "dce/dce_hwseq.h" 33 #include "dcn30/dcn30_cm_common.h" 34 #include "reg_helper.h" 35 #include "abm.h" 36 #include "hubp.h" 37 #include "dchubbub.h" 38 #include "timing_generator.h" 39 #include "opp.h" 40 #include "ipp.h" 41 #include "mpc.h" 42 #include "mcif_wb.h" 43 #include "dc_dmub_srv.h" 44 #include "link_hwss.h" 45 #include "dpcd_defs.h" 46 #include "dcn32_hwseq.h" 47 #include "clk_mgr.h" 48 #include "dsc.h" 49 #include "dcn20/dcn20_optc.h" 50 #include "dmub_subvp_state.h" 51 #include "dce/dmub_hw_lock_mgr.h" 52 #include "dcn32_resource.h" 53 #include "dc_link_dp.h" 54 #include "dmub/inc/dmub_subvp_state.h" 55 56 #define DC_LOGGER_INIT(logger) 57 58 #define CTX \ 59 hws->ctx 60 #define REG(reg)\ 61 hws->regs->reg 62 #define DC_LOGGER \ 63 dc->ctx->logger 64 65 66 #undef FN 67 #define FN(reg_name, field_name) \ 68 hws->shifts->field_name, hws->masks->field_name 69 70 void dcn32_dsc_pg_control( 71 struct dce_hwseq *hws, 72 unsigned int dsc_inst, 73 bool power_on) 74 { 75 uint32_t power_gate = power_on ? 0 : 1; 76 uint32_t pwr_status = power_on ? 0 : 2; 77 uint32_t org_ip_request_cntl = 0; 78 79 if (hws->ctx->dc->debug.disable_dsc_power_gate) 80 return; 81 82 REG_GET(DC_IP_REQUEST_CNTL, IP_REQUEST_EN, &org_ip_request_cntl); 83 if (org_ip_request_cntl == 0) 84 REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 1); 85 86 switch (dsc_inst) { 87 case 0: /* DSC0 */ 88 REG_UPDATE(DOMAIN16_PG_CONFIG, 89 DOMAIN_POWER_GATE, power_gate); 90 91 REG_WAIT(DOMAIN16_PG_STATUS, 92 DOMAIN_PGFSM_PWR_STATUS, pwr_status, 93 1, 1000); 94 break; 95 case 1: /* DSC1 */ 96 REG_UPDATE(DOMAIN17_PG_CONFIG, 97 DOMAIN_POWER_GATE, power_gate); 98 99 REG_WAIT(DOMAIN17_PG_STATUS, 100 DOMAIN_PGFSM_PWR_STATUS, pwr_status, 101 1, 1000); 102 break; 103 case 2: /* DSC2 */ 104 REG_UPDATE(DOMAIN18_PG_CONFIG, 105 DOMAIN_POWER_GATE, power_gate); 106 107 REG_WAIT(DOMAIN18_PG_STATUS, 108 DOMAIN_PGFSM_PWR_STATUS, pwr_status, 109 1, 1000); 110 break; 111 case 3: /* DSC3 */ 112 REG_UPDATE(DOMAIN19_PG_CONFIG, 113 DOMAIN_POWER_GATE, power_gate); 114 115 REG_WAIT(DOMAIN19_PG_STATUS, 116 DOMAIN_PGFSM_PWR_STATUS, pwr_status, 117 1, 1000); 118 break; 119 default: 120 BREAK_TO_DEBUGGER(); 121 break; 122 } 123 124 if (org_ip_request_cntl == 0) 125 REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 0); 126 } 127 128 129 void dcn32_enable_power_gating_plane( 130 struct dce_hwseq *hws, 131 bool enable) 132 { 133 bool force_on = true; /* disable power gating */ 134 135 if (enable) 136 force_on = false; 137 138 /* DCHUBP0/1/2/3 */ 139 REG_UPDATE(DOMAIN0_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on); 140 REG_UPDATE(DOMAIN1_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on); 141 REG_UPDATE(DOMAIN2_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on); 142 REG_UPDATE(DOMAIN3_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on); 143 144 /* DCS0/1/2/3 */ 145 REG_UPDATE(DOMAIN16_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on); 146 REG_UPDATE(DOMAIN17_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on); 147 REG_UPDATE(DOMAIN18_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on); 148 REG_UPDATE(DOMAIN19_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on); 149 } 150 151 void dcn32_hubp_pg_control(struct dce_hwseq *hws, unsigned int hubp_inst, bool power_on) 152 { 153 uint32_t power_gate = power_on ? 0 : 1; 154 uint32_t pwr_status = power_on ? 0 : 2; 155 156 if (hws->ctx->dc->debug.disable_hubp_power_gate) 157 return; 158 159 if (REG(DOMAIN0_PG_CONFIG) == 0) 160 return; 161 162 switch (hubp_inst) { 163 case 0: 164 REG_SET(DOMAIN0_PG_CONFIG, 0, DOMAIN_POWER_GATE, power_gate); 165 REG_WAIT(DOMAIN0_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, pwr_status, 1, 1000); 166 break; 167 case 1: 168 REG_SET(DOMAIN1_PG_CONFIG, 0, DOMAIN_POWER_GATE, power_gate); 169 REG_WAIT(DOMAIN1_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, pwr_status, 1, 1000); 170 break; 171 case 2: 172 REG_SET(DOMAIN2_PG_CONFIG, 0, DOMAIN_POWER_GATE, power_gate); 173 REG_WAIT(DOMAIN2_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, pwr_status, 1, 1000); 174 break; 175 case 3: 176 REG_SET(DOMAIN3_PG_CONFIG, 0, DOMAIN_POWER_GATE, power_gate); 177 REG_WAIT(DOMAIN3_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, pwr_status, 1, 1000); 178 break; 179 default: 180 BREAK_TO_DEBUGGER(); 181 break; 182 } 183 } 184 185 static bool dcn32_check_no_memory_request_for_cab(struct dc *dc) 186 { 187 int i; 188 189 /* First, check no-memory-request case */ 190 for (i = 0; i < dc->current_state->stream_count; i++) { 191 if ((dc->current_state->stream_status[i].plane_count) && 192 (dc->current_state->streams[i]->link->psr_settings.psr_version == DC_PSR_VERSION_UNSUPPORTED)) 193 /* Fail eligibility on a visible stream */ 194 break; 195 } 196 197 if (i == dc->current_state->stream_count) 198 return true; 199 200 return false; 201 } 202 203 204 /* This function loops through every surface that needs to be cached in CAB for SS, 205 * and calculates the total number of ways required to store all surfaces (primary, 206 * meta, cursor). 207 */ 208 static uint32_t dcn32_calculate_cab_allocation(struct dc *dc, struct dc_state *ctx) 209 { 210 int i, j; 211 struct dc_stream_state *stream = NULL; 212 struct dc_plane_state *plane = NULL; 213 uint32_t cursor_size = 0; 214 uint32_t total_lines = 0; 215 uint32_t lines_per_way = 0; 216 uint8_t num_ways = 0; 217 uint8_t bytes_per_pixel = 0; 218 uint8_t cursor_bpp = 0; 219 uint16_t mblk_width = 0; 220 uint16_t mblk_height = 0; 221 uint16_t mall_alloc_width_blk_aligned = 0; 222 uint16_t mall_alloc_height_blk_aligned = 0; 223 uint16_t num_mblks = 0; 224 uint32_t bytes_in_mall = 0; 225 uint32_t cache_lines_used = 0; 226 uint32_t cache_lines_per_plane = 0; 227 228 for (i = 0; i < dc->res_pool->pipe_count; i++) { 229 struct pipe_ctx *pipe = &dc->current_state->res_ctx.pipe_ctx[i]; 230 231 /* If PSR is supported on an eDP panel that's connected, but that panel is 232 * not in PSR at the time of trying to enter MALL SS, we have to include it 233 * in the static screen CAB calculation 234 */ 235 if (!pipe->stream || !pipe->plane_state || 236 (pipe->stream->link->psr_settings.psr_version != DC_PSR_VERSION_UNSUPPORTED && 237 pipe->stream->link->psr_settings.psr_allow_active) || 238 pipe->stream->mall_stream_config.type == SUBVP_PHANTOM) 239 continue; 240 241 bytes_per_pixel = pipe->plane_state->format >= SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616 ? 8 : 4; 242 mblk_width = DCN3_2_MBLK_WIDTH; 243 mblk_height = bytes_per_pixel == 4 ? DCN3_2_MBLK_HEIGHT_4BPE : DCN3_2_MBLK_HEIGHT_8BPE; 244 245 /* full_vp_width_blk_aligned = FLOOR(vp_x_start + full_vp_width + blk_width - 1, blk_width) - 246 * FLOOR(vp_x_start, blk_width) 247 * 248 * mall_alloc_width_blk_aligned_l/c = full_vp_width_blk_aligned_l/c 249 */ 250 mall_alloc_width_blk_aligned = ((pipe->plane_res.scl_data.viewport.x + 251 pipe->plane_res.scl_data.viewport.width + mblk_width - 1) / mblk_width * mblk_width) - 252 (pipe->plane_res.scl_data.viewport.x / mblk_width * mblk_width); 253 254 /* full_vp_height_blk_aligned = FLOOR(vp_y_start + full_vp_height + blk_height - 1, blk_height) - 255 * FLOOR(vp_y_start, blk_height) 256 * 257 * mall_alloc_height_blk_aligned_l/c = full_vp_height_blk_aligned_l/c 258 */ 259 mall_alloc_height_blk_aligned = ((pipe->plane_res.scl_data.viewport.y + 260 pipe->plane_res.scl_data.viewport.height + mblk_height - 1) / mblk_height * mblk_height) - 261 (pipe->plane_res.scl_data.viewport.y / mblk_height * mblk_height); 262 263 num_mblks = ((mall_alloc_width_blk_aligned + mblk_width - 1) / mblk_width) * 264 ((mall_alloc_height_blk_aligned + mblk_height - 1) / mblk_height); 265 266 /*For DCC: 267 * meta_num_mblk = CEILING(meta_pitch*full_vp_height*Bpe/256/mblk_bytes, 1) 268 */ 269 if (pipe->plane_state->dcc.enable) 270 num_mblks += (pipe->plane_state->dcc.meta_pitch * pipe->plane_res.scl_data.viewport.height * bytes_per_pixel + 271 (256 * DCN3_2_MALL_MBLK_SIZE_BYTES) - 1) / (256 * DCN3_2_MALL_MBLK_SIZE_BYTES); 272 273 bytes_in_mall = num_mblks * DCN3_2_MALL_MBLK_SIZE_BYTES; 274 275 /* (cache lines used is total bytes / cache_line size. Add +2 for worst case alignment 276 * (MALL is 64-byte aligned) 277 */ 278 cache_lines_per_plane = bytes_in_mall / dc->caps.cache_line_size + 2; 279 cache_lines_used += cache_lines_per_plane; 280 } 281 282 // Include cursor size for CAB allocation 283 for (j = 0; j < dc->res_pool->pipe_count; j++) { 284 struct pipe_ctx *pipe = &ctx->res_ctx.pipe_ctx[j]; 285 struct hubp *hubp = pipe->plane_res.hubp; 286 287 if (pipe->stream && pipe->plane_state && hubp) 288 /* Find the cursor plane and use the exact size instead of 289 using the max for calculation */ 290 291 if (hubp->curs_attr.width > 0) { 292 cursor_size = hubp->curs_attr.pitch * hubp->curs_attr.height; 293 294 switch (pipe->stream->cursor_attributes.color_format) { 295 case CURSOR_MODE_MONO: 296 cursor_size /= 2; 297 cursor_bpp = 4; 298 break; 299 case CURSOR_MODE_COLOR_1BIT_AND: 300 case CURSOR_MODE_COLOR_PRE_MULTIPLIED_ALPHA: 301 case CURSOR_MODE_COLOR_UN_PRE_MULTIPLIED_ALPHA: 302 cursor_size *= 4; 303 cursor_bpp = 4; 304 break; 305 306 case CURSOR_MODE_COLOR_64BIT_FP_PRE_MULTIPLIED: 307 case CURSOR_MODE_COLOR_64BIT_FP_UN_PRE_MULTIPLIED: 308 cursor_size *= 8; 309 cursor_bpp = 8; 310 break; 311 } 312 313 if (pipe->stream->cursor_position.enable && !dc->debug.alloc_extra_way_for_cursor && 314 cursor_size > 16384) { 315 /* cursor_num_mblk = CEILING(num_cursors*cursor_width*cursor_width*cursor_Bpe/mblk_bytes, 1) 316 */ 317 cache_lines_used += (((cursor_size + DCN3_2_MALL_MBLK_SIZE_BYTES - 1) / 318 DCN3_2_MALL_MBLK_SIZE_BYTES) * DCN3_2_MALL_MBLK_SIZE_BYTES) / 319 dc->caps.cache_line_size + 2; 320 break; 321 } 322 } 323 } 324 325 // Convert number of cache lines required to number of ways 326 total_lines = dc->caps.max_cab_allocation_bytes / dc->caps.cache_line_size; 327 lines_per_way = total_lines / dc->caps.cache_num_ways; 328 num_ways = cache_lines_used / lines_per_way; 329 330 if (cache_lines_used % lines_per_way > 0) 331 num_ways++; 332 333 for (i = 0; i < ctx->stream_count; i++) { 334 stream = ctx->streams[i]; 335 for (j = 0; j < ctx->stream_status[i].plane_count; j++) { 336 plane = ctx->stream_status[i].plane_states[j]; 337 338 if (stream->cursor_position.enable && plane && 339 dc->debug.alloc_extra_way_for_cursor && 340 cursor_size > 16384) { 341 /* Cursor caching is not supported since it won't be on the same line. 342 * So we need an extra line to accommodate it. With large cursors and a single 4k monitor 343 * this case triggers corruption. If we're at the edge, then dont trigger display refresh 344 * from MALL. We only need to cache cursor if its greater that 64x64 at 4 bpp. 345 */ 346 num_ways++; 347 /* We only expect one cursor plane */ 348 break; 349 } 350 } 351 } 352 if (dc->debug.force_mall_ss_num_ways > 0) { 353 num_ways = dc->debug.force_mall_ss_num_ways; 354 } 355 return num_ways; 356 } 357 358 bool dcn32_apply_idle_power_optimizations(struct dc *dc, bool enable) 359 { 360 union dmub_rb_cmd cmd; 361 uint8_t ways, i; 362 int j; 363 bool mall_ss_unsupported = false; 364 struct dc_plane_state *plane = NULL; 365 366 if (!dc->ctx->dmub_srv) 367 return false; 368 369 if (enable) { 370 if (dc->current_state) { 371 372 /* 1. Check no memory request case for CAB. 373 * If no memory request case, send CAB_ACTION NO_DF_REQ DMUB message 374 */ 375 if (dcn32_check_no_memory_request_for_cab(dc)) { 376 /* Enable no-memory-requests case */ 377 memset(&cmd, 0, sizeof(cmd)); 378 cmd.cab.header.type = DMUB_CMD__CAB_FOR_SS; 379 cmd.cab.header.sub_type = DMUB_CMD__CAB_NO_DCN_REQ; 380 cmd.cab.header.payload_bytes = sizeof(cmd.cab) - sizeof(cmd.cab.header); 381 382 dc_dmub_srv_cmd_queue(dc->ctx->dmub_srv, &cmd); 383 dc_dmub_srv_cmd_execute(dc->ctx->dmub_srv); 384 385 return true; 386 } 387 388 /* 2. Check if all surfaces can fit in CAB. 389 * If surfaces can fit into CAB, send CAB_ACTION_ALLOW DMUB message 390 * and configure HUBP's to fetch from MALL 391 */ 392 ways = dcn32_calculate_cab_allocation(dc, dc->current_state); 393 394 /* MALL not supported with Stereo3D or TMZ surface. If any plane is using stereo, 395 * or TMZ surface, don't try to enter MALL. 396 */ 397 for (i = 0; i < dc->current_state->stream_count; i++) { 398 for (j = 0; j < dc->current_state->stream_status[i].plane_count; j++) { 399 plane = dc->current_state->stream_status[i].plane_states[j]; 400 401 if (plane->address.type == PLN_ADDR_TYPE_GRPH_STEREO || 402 plane->address.tmz_surface) { 403 mall_ss_unsupported = true; 404 break; 405 } 406 } 407 if (mall_ss_unsupported) 408 break; 409 } 410 if (ways <= dc->caps.cache_num_ways && !mall_ss_unsupported) { 411 memset(&cmd, 0, sizeof(cmd)); 412 cmd.cab.header.type = DMUB_CMD__CAB_FOR_SS; 413 cmd.cab.header.sub_type = DMUB_CMD__CAB_DCN_SS_FIT_IN_CAB; 414 cmd.cab.header.payload_bytes = sizeof(cmd.cab) - sizeof(cmd.cab.header); 415 cmd.cab.cab_alloc_ways = ways; 416 417 dc_dmub_srv_cmd_queue(dc->ctx->dmub_srv, &cmd); 418 dc_dmub_srv_cmd_execute(dc->ctx->dmub_srv); 419 420 return true; 421 } 422 423 } 424 return false; 425 } 426 427 /* Disable CAB */ 428 memset(&cmd, 0, sizeof(cmd)); 429 cmd.cab.header.type = DMUB_CMD__CAB_FOR_SS; 430 cmd.cab.header.sub_type = DMUB_CMD__CAB_NO_IDLE_OPTIMIZATION; 431 cmd.cab.header.payload_bytes = 432 sizeof(cmd.cab) - sizeof(cmd.cab.header); 433 434 dc_dmub_srv_cmd_queue(dc->ctx->dmub_srv, &cmd); 435 dc_dmub_srv_cmd_execute(dc->ctx->dmub_srv); 436 dc_dmub_srv_wait_idle(dc->ctx->dmub_srv); 437 438 return true; 439 } 440 441 /* Send DMCUB message with SubVP pipe info 442 * - For each pipe in context, populate payload with required SubVP information 443 * if the pipe is using SubVP for MCLK switch 444 * - This function must be called while the DMUB HW lock is acquired by driver 445 */ 446 void dcn32_commit_subvp_config(struct dc *dc, struct dc_state *context) 447 { 448 int i; 449 bool enable_subvp = false; 450 451 if (!dc->ctx || !dc->ctx->dmub_srv) 452 return; 453 454 for (i = 0; i < dc->res_pool->pipe_count; i++) { 455 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; 456 457 if (pipe_ctx->stream && pipe_ctx->stream->mall_stream_config.paired_stream && 458 pipe_ctx->stream->mall_stream_config.type == SUBVP_MAIN) { 459 // There is at least 1 SubVP pipe, so enable SubVP 460 enable_subvp = true; 461 break; 462 } 463 } 464 dc_dmub_setup_subvp_dmub_command(dc, context, enable_subvp); 465 } 466 467 /* Sub-Viewport DMUB lock needs to be acquired by driver whenever SubVP is active and: 468 * 1. Any full update for any SubVP main pipe 469 * 2. Any immediate flip for any SubVP pipe 470 * 3. Any flip for DRR pipe 471 * 4. If SubVP was previously in use (i.e. in old context) 472 */ 473 void dcn32_subvp_pipe_control_lock(struct dc *dc, 474 struct dc_state *context, 475 bool lock, 476 bool should_lock_all_pipes, 477 struct pipe_ctx *top_pipe_to_program, 478 bool subvp_prev_use) 479 { 480 unsigned int i = 0; 481 bool subvp_immediate_flip = false; 482 bool subvp_in_use = false; 483 struct pipe_ctx *pipe; 484 485 for (i = 0; i < dc->res_pool->pipe_count; i++) { 486 pipe = &context->res_ctx.pipe_ctx[i]; 487 488 if (pipe->stream && pipe->plane_state && pipe->stream->mall_stream_config.type == SUBVP_MAIN) { 489 subvp_in_use = true; 490 break; 491 } 492 } 493 494 if (top_pipe_to_program && top_pipe_to_program->stream && top_pipe_to_program->plane_state) { 495 if (top_pipe_to_program->stream->mall_stream_config.type == SUBVP_MAIN && 496 top_pipe_to_program->plane_state->flip_immediate) 497 subvp_immediate_flip = true; 498 } 499 500 // Don't need to lock for DRR VSYNC flips -- FW will wait for DRR pending update cleared. 501 if ((subvp_in_use && (should_lock_all_pipes || subvp_immediate_flip)) || (!subvp_in_use && subvp_prev_use)) { 502 union dmub_inbox0_cmd_lock_hw hw_lock_cmd = { 0 }; 503 504 if (!lock) { 505 for (i = 0; i < dc->res_pool->pipe_count; i++) { 506 pipe = &context->res_ctx.pipe_ctx[i]; 507 if (pipe->stream && pipe->plane_state && pipe->stream->mall_stream_config.type == SUBVP_MAIN && 508 should_lock_all_pipes) 509 pipe->stream_res.tg->funcs->wait_for_state(pipe->stream_res.tg, CRTC_STATE_VBLANK); 510 } 511 } 512 513 hw_lock_cmd.bits.command_code = DMUB_INBOX0_CMD__HW_LOCK; 514 hw_lock_cmd.bits.hw_lock_client = HW_LOCK_CLIENT_DRIVER; 515 hw_lock_cmd.bits.lock = lock; 516 hw_lock_cmd.bits.should_release = !lock; 517 dmub_hw_lock_mgr_inbox0_cmd(dc->ctx->dmub_srv, hw_lock_cmd); 518 } 519 } 520 521 522 static bool dcn32_set_mpc_shaper_3dlut( 523 struct pipe_ctx *pipe_ctx, const struct dc_stream_state *stream) 524 { 525 struct dpp *dpp_base = pipe_ctx->plane_res.dpp; 526 int mpcc_id = pipe_ctx->plane_res.hubp->inst; 527 struct mpc *mpc = pipe_ctx->stream_res.opp->ctx->dc->res_pool->mpc; 528 bool result = false; 529 530 const struct pwl_params *shaper_lut = NULL; 531 //get the shaper lut params 532 if (stream->func_shaper) { 533 if (stream->func_shaper->type == TF_TYPE_HWPWL) 534 shaper_lut = &stream->func_shaper->pwl; 535 else if (stream->func_shaper->type == TF_TYPE_DISTRIBUTED_POINTS) { 536 cm_helper_translate_curve_to_hw_format( 537 stream->func_shaper, 538 &dpp_base->shaper_params, true); 539 shaper_lut = &dpp_base->shaper_params; 540 } 541 } 542 543 if (stream->lut3d_func && 544 stream->lut3d_func->state.bits.initialized == 1) { 545 546 result = mpc->funcs->program_3dlut(mpc, 547 &stream->lut3d_func->lut_3d, 548 mpcc_id); 549 550 result = mpc->funcs->program_shaper(mpc, 551 shaper_lut, 552 mpcc_id); 553 } 554 555 return result; 556 } 557 558 bool dcn32_set_mcm_luts( 559 struct pipe_ctx *pipe_ctx, const struct dc_plane_state *plane_state) 560 { 561 struct dpp *dpp_base = pipe_ctx->plane_res.dpp; 562 int mpcc_id = pipe_ctx->plane_res.hubp->inst; 563 struct mpc *mpc = pipe_ctx->stream_res.opp->ctx->dc->res_pool->mpc; 564 bool result = true; 565 struct pwl_params *lut_params = NULL; 566 567 // 1D LUT 568 if (plane_state->blend_tf) { 569 if (plane_state->blend_tf->type == TF_TYPE_HWPWL) 570 lut_params = &plane_state->blend_tf->pwl; 571 else if (plane_state->blend_tf->type == TF_TYPE_DISTRIBUTED_POINTS) { 572 cm_helper_translate_curve_to_hw_format( 573 plane_state->blend_tf, 574 &dpp_base->regamma_params, false); 575 lut_params = &dpp_base->regamma_params; 576 } 577 } 578 result = mpc->funcs->program_1dlut(mpc, lut_params, mpcc_id); 579 580 // Shaper 581 if (plane_state->in_shaper_func) { 582 if (plane_state->in_shaper_func->type == TF_TYPE_HWPWL) 583 lut_params = &plane_state->in_shaper_func->pwl; 584 else if (plane_state->in_shaper_func->type == TF_TYPE_DISTRIBUTED_POINTS) { 585 // TODO: dpp_base replace 586 ASSERT(false); 587 cm_helper_translate_curve_to_hw_format( 588 plane_state->in_shaper_func, 589 &dpp_base->shaper_params, true); 590 lut_params = &dpp_base->shaper_params; 591 } 592 } 593 594 result = mpc->funcs->program_shaper(mpc, lut_params, mpcc_id); 595 596 // 3D 597 if (plane_state->lut3d_func && plane_state->lut3d_func->state.bits.initialized == 1) 598 result = mpc->funcs->program_3dlut(mpc, &plane_state->lut3d_func->lut_3d, mpcc_id); 599 else 600 result = mpc->funcs->program_3dlut(mpc, NULL, mpcc_id); 601 602 return result; 603 } 604 605 bool dcn32_set_input_transfer_func(struct dc *dc, 606 struct pipe_ctx *pipe_ctx, 607 const struct dc_plane_state *plane_state) 608 { 609 struct dce_hwseq *hws = dc->hwseq; 610 struct mpc *mpc = dc->res_pool->mpc; 611 struct dpp *dpp_base = pipe_ctx->plane_res.dpp; 612 613 enum dc_transfer_func_predefined tf; 614 bool result = true; 615 struct pwl_params *params = NULL; 616 617 if (mpc == NULL || plane_state == NULL) 618 return false; 619 620 tf = TRANSFER_FUNCTION_UNITY; 621 622 if (plane_state->in_transfer_func && 623 plane_state->in_transfer_func->type == TF_TYPE_PREDEFINED) 624 tf = plane_state->in_transfer_func->tf; 625 626 dpp_base->funcs->dpp_set_pre_degam(dpp_base, tf); 627 628 if (plane_state->in_transfer_func) { 629 if (plane_state->in_transfer_func->type == TF_TYPE_HWPWL) 630 params = &plane_state->in_transfer_func->pwl; 631 else if (plane_state->in_transfer_func->type == TF_TYPE_DISTRIBUTED_POINTS && 632 cm3_helper_translate_curve_to_hw_format(plane_state->in_transfer_func, 633 &dpp_base->degamma_params, false)) 634 params = &dpp_base->degamma_params; 635 } 636 637 dpp_base->funcs->dpp_program_gamcor_lut(dpp_base, params); 638 639 if (pipe_ctx->stream_res.opp && 640 pipe_ctx->stream_res.opp->ctx && 641 hws->funcs.set_mcm_luts) 642 result = hws->funcs.set_mcm_luts(pipe_ctx, plane_state); 643 644 return result; 645 } 646 647 bool dcn32_set_output_transfer_func(struct dc *dc, 648 struct pipe_ctx *pipe_ctx, 649 const struct dc_stream_state *stream) 650 { 651 int mpcc_id = pipe_ctx->plane_res.hubp->inst; 652 struct mpc *mpc = pipe_ctx->stream_res.opp->ctx->dc->res_pool->mpc; 653 struct pwl_params *params = NULL; 654 bool ret = false; 655 656 /* program OGAM or 3DLUT only for the top pipe*/ 657 if (pipe_ctx->top_pipe == NULL) { 658 /*program shaper and 3dlut in MPC*/ 659 ret = dcn32_set_mpc_shaper_3dlut(pipe_ctx, stream); 660 if (ret == false && mpc->funcs->set_output_gamma && stream->out_transfer_func) { 661 if (stream->out_transfer_func->type == TF_TYPE_HWPWL) 662 params = &stream->out_transfer_func->pwl; 663 else if (pipe_ctx->stream->out_transfer_func->type == 664 TF_TYPE_DISTRIBUTED_POINTS && 665 cm3_helper_translate_curve_to_hw_format( 666 stream->out_transfer_func, 667 &mpc->blender_params, false)) 668 params = &mpc->blender_params; 669 /* there are no ROM LUTs in OUTGAM */ 670 if (stream->out_transfer_func->type == TF_TYPE_PREDEFINED) 671 BREAK_TO_DEBUGGER(); 672 } 673 } 674 675 mpc->funcs->set_output_gamma(mpc, mpcc_id, params); 676 return ret; 677 } 678 679 /* Program P-State force value according to if pipe is using SubVP or not: 680 * 1. Reset P-State force on all pipes first 681 * 2. For each main pipe, force P-State disallow (P-State allow moderated by DMUB) 682 */ 683 void dcn32_subvp_update_force_pstate(struct dc *dc, struct dc_state *context) 684 { 685 int i; 686 int num_subvp = 0; 687 /* Unforce p-state for each pipe 688 */ 689 for (i = 0; i < dc->res_pool->pipe_count; i++) { 690 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; 691 struct hubp *hubp = pipe->plane_res.hubp; 692 693 if (hubp && hubp->funcs->hubp_update_force_pstate_disallow) 694 hubp->funcs->hubp_update_force_pstate_disallow(hubp, false); 695 if (pipe->stream && pipe->stream->mall_stream_config.type == SUBVP_MAIN) 696 num_subvp++; 697 } 698 699 if (num_subvp == 0) 700 return; 701 702 /* Loop through each pipe -- for each subvp main pipe force p-state allow equal to false. 703 */ 704 for (i = 0; i < dc->res_pool->pipe_count; i++) { 705 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; 706 707 if (pipe->stream && pipe->plane_state && (pipe->stream->mall_stream_config.type == SUBVP_MAIN)) { 708 struct hubp *hubp = pipe->plane_res.hubp; 709 710 if (hubp && hubp->funcs->hubp_update_force_pstate_disallow) 711 hubp->funcs->hubp_update_force_pstate_disallow(hubp, true); 712 } 713 } 714 } 715 716 /* Update MALL_SEL register based on if pipe / plane 717 * is a phantom pipe, main pipe, and if using MALL 718 * for SS. 719 */ 720 void dcn32_update_mall_sel(struct dc *dc, struct dc_state *context) 721 { 722 int i; 723 unsigned int num_ways = dcn32_calculate_cab_allocation(dc, context); 724 bool cache_cursor = false; 725 726 for (i = 0; i < dc->res_pool->pipe_count; i++) { 727 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; 728 struct hubp *hubp = pipe->plane_res.hubp; 729 730 if (pipe->stream && pipe->plane_state && hubp && hubp->funcs->hubp_update_mall_sel) { 731 int cursor_size = hubp->curs_attr.pitch * hubp->curs_attr.height; 732 733 switch (hubp->curs_attr.color_format) { 734 case CURSOR_MODE_MONO: 735 cursor_size /= 2; 736 break; 737 case CURSOR_MODE_COLOR_1BIT_AND: 738 case CURSOR_MODE_COLOR_PRE_MULTIPLIED_ALPHA: 739 case CURSOR_MODE_COLOR_UN_PRE_MULTIPLIED_ALPHA: 740 cursor_size *= 4; 741 break; 742 743 case CURSOR_MODE_COLOR_64BIT_FP_PRE_MULTIPLIED: 744 case CURSOR_MODE_COLOR_64BIT_FP_UN_PRE_MULTIPLIED: 745 default: 746 cursor_size *= 8; 747 break; 748 } 749 750 if (cursor_size > 16384) 751 cache_cursor = true; 752 753 if (pipe->stream->mall_stream_config.type == SUBVP_PHANTOM) { 754 hubp->funcs->hubp_update_mall_sel(hubp, 1, false); 755 } else { 756 // MALL not supported with Stereo3D 757 hubp->funcs->hubp_update_mall_sel(hubp, 758 num_ways <= dc->caps.cache_num_ways && 759 pipe->stream->link->psr_settings.psr_version == DC_PSR_VERSION_UNSUPPORTED && 760 pipe->plane_state->address.type != PLN_ADDR_TYPE_GRPH_STEREO && 761 !pipe->plane_state->address.tmz_surface ? 2 : 0, 762 cache_cursor); 763 } 764 } 765 } 766 } 767 768 /* Program the sub-viewport pipe configuration after the main / phantom pipes 769 * have been programmed in hardware. 770 * 1. Update force P-State for all the main pipes (disallow P-state) 771 * 2. Update MALL_SEL register 772 * 3. Program FORCE_ONE_ROW_FOR_FRAME for main subvp pipes 773 */ 774 void dcn32_program_mall_pipe_config(struct dc *dc, struct dc_state *context) 775 { 776 int i; 777 struct dce_hwseq *hws = dc->hwseq; 778 779 // Don't force p-state disallow -- can't block dummy p-state 780 781 // Update MALL_SEL register for each pipe 782 if (hws && hws->funcs.update_mall_sel) 783 hws->funcs.update_mall_sel(dc, context); 784 785 //update subvp force pstate 786 if (hws && hws->funcs.subvp_update_force_pstate) 787 dc->hwseq->funcs.subvp_update_force_pstate(dc, context); 788 789 // Program FORCE_ONE_ROW_FOR_FRAME and CURSOR_REQ_MODE for main subvp pipes 790 for (i = 0; i < dc->res_pool->pipe_count; i++) { 791 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; 792 struct hubp *hubp = pipe->plane_res.hubp; 793 794 if (pipe->stream && hubp && hubp->funcs->hubp_prepare_subvp_buffering) { 795 /* TODO - remove setting CURSOR_REQ_MODE to 0 for legacy cases 796 * - need to investigate single pipe MPO + SubVP case to 797 * see if CURSOR_REQ_MODE will be back to 1 for SubVP 798 * when it should be 0 for MPO 799 */ 800 if (pipe->stream->mall_stream_config.type == SUBVP_MAIN) { 801 hubp->funcs->hubp_prepare_subvp_buffering(hubp, true); 802 } 803 } 804 } 805 } 806 807 void dcn32_init_hw(struct dc *dc) 808 { 809 struct abm **abms = dc->res_pool->multiple_abms; 810 struct dce_hwseq *hws = dc->hwseq; 811 struct dc_bios *dcb = dc->ctx->dc_bios; 812 struct resource_pool *res_pool = dc->res_pool; 813 int i; 814 int edp_num; 815 uint32_t backlight = MAX_BACKLIGHT_LEVEL; 816 817 if (dc->clk_mgr && dc->clk_mgr->funcs->init_clocks) 818 dc->clk_mgr->funcs->init_clocks(dc->clk_mgr); 819 820 // Initialize the dccg 821 if (res_pool->dccg->funcs->dccg_init) 822 res_pool->dccg->funcs->dccg_init(res_pool->dccg); 823 824 if (!dcb->funcs->is_accelerated_mode(dcb)) { 825 hws->funcs.bios_golden_init(dc); 826 hws->funcs.disable_vga(dc->hwseq); 827 } 828 829 // Set default OPTC memory power states 830 if (dc->debug.enable_mem_low_power.bits.optc) { 831 // Shutdown when unassigned and light sleep in VBLANK 832 REG_SET_2(ODM_MEM_PWR_CTRL3, 0, ODM_MEM_UNASSIGNED_PWR_MODE, 3, ODM_MEM_VBLANK_PWR_MODE, 1); 833 } 834 835 if (dc->debug.enable_mem_low_power.bits.vga) { 836 // Power down VGA memory 837 REG_UPDATE(MMHUBBUB_MEM_PWR_CNTL, VGA_MEM_PWR_FORCE, 1); 838 } 839 840 if (dc->ctx->dc_bios->fw_info_valid) { 841 res_pool->ref_clocks.xtalin_clock_inKhz = 842 dc->ctx->dc_bios->fw_info.pll_info.crystal_frequency; 843 844 if (res_pool->dccg && res_pool->hubbub) { 845 (res_pool->dccg->funcs->get_dccg_ref_freq)(res_pool->dccg, 846 dc->ctx->dc_bios->fw_info.pll_info.crystal_frequency, 847 &res_pool->ref_clocks.dccg_ref_clock_inKhz); 848 849 (res_pool->hubbub->funcs->get_dchub_ref_freq)(res_pool->hubbub, 850 res_pool->ref_clocks.dccg_ref_clock_inKhz, 851 &res_pool->ref_clocks.dchub_ref_clock_inKhz); 852 } else { 853 // Not all ASICs have DCCG sw component 854 res_pool->ref_clocks.dccg_ref_clock_inKhz = 855 res_pool->ref_clocks.xtalin_clock_inKhz; 856 res_pool->ref_clocks.dchub_ref_clock_inKhz = 857 res_pool->ref_clocks.xtalin_clock_inKhz; 858 } 859 } else 860 ASSERT_CRITICAL(false); 861 862 for (i = 0; i < dc->link_count; i++) { 863 /* Power up AND update implementation according to the 864 * required signal (which may be different from the 865 * default signal on connector). 866 */ 867 struct dc_link *link = dc->links[i]; 868 869 link->link_enc->funcs->hw_init(link->link_enc); 870 871 /* Check for enabled DIG to identify enabled display */ 872 if (link->link_enc->funcs->is_dig_enabled && 873 link->link_enc->funcs->is_dig_enabled(link->link_enc)) { 874 link->link_status.link_active = true; 875 link->phy_state.symclk_state = SYMCLK_ON_TX_ON; 876 if (link->link_enc->funcs->fec_is_active && 877 link->link_enc->funcs->fec_is_active(link->link_enc)) 878 link->fec_state = dc_link_fec_enabled; 879 } 880 } 881 882 /* Power gate DSCs */ 883 for (i = 0; i < res_pool->res_cap->num_dsc; i++) 884 if (hws->funcs.dsc_pg_control != NULL) 885 hws->funcs.dsc_pg_control(hws, res_pool->dscs[i]->inst, false); 886 887 /* we want to turn off all dp displays before doing detection */ 888 dc_link_blank_all_dp_displays(dc); 889 890 /* If taking control over from VBIOS, we may want to optimize our first 891 * mode set, so we need to skip powering down pipes until we know which 892 * pipes we want to use. 893 * Otherwise, if taking control is not possible, we need to power 894 * everything down. 895 */ 896 if (dcb->funcs->is_accelerated_mode(dcb) || !dc->config.seamless_boot_edp_requested) { 897 hws->funcs.init_pipes(dc, dc->current_state); 898 if (dc->res_pool->hubbub->funcs->allow_self_refresh_control) 899 dc->res_pool->hubbub->funcs->allow_self_refresh_control(dc->res_pool->hubbub, 900 !dc->res_pool->hubbub->ctx->dc->debug.disable_stutter); 901 } 902 903 /* In headless boot cases, DIG may be turned 904 * on which causes HW/SW discrepancies. 905 * To avoid this, power down hardware on boot 906 * if DIG is turned on and seamless boot not enabled 907 */ 908 if (!dc->config.seamless_boot_edp_requested) { 909 struct dc_link *edp_links[MAX_NUM_EDP]; 910 struct dc_link *edp_link; 911 912 get_edp_links(dc, edp_links, &edp_num); 913 if (edp_num) { 914 for (i = 0; i < edp_num; i++) { 915 edp_link = edp_links[i]; 916 if (edp_link->link_enc->funcs->is_dig_enabled && 917 edp_link->link_enc->funcs->is_dig_enabled(edp_link->link_enc) && 918 dc->hwss.edp_backlight_control && 919 dc->hwss.power_down && 920 dc->hwss.edp_power_control) { 921 dc->hwss.edp_backlight_control(edp_link, false); 922 dc->hwss.power_down(dc); 923 dc->hwss.edp_power_control(edp_link, false); 924 } 925 } 926 } else { 927 for (i = 0; i < dc->link_count; i++) { 928 struct dc_link *link = dc->links[i]; 929 930 if (link->link_enc->funcs->is_dig_enabled && 931 link->link_enc->funcs->is_dig_enabled(link->link_enc) && 932 dc->hwss.power_down) { 933 dc->hwss.power_down(dc); 934 break; 935 } 936 937 } 938 } 939 } 940 941 for (i = 0; i < res_pool->audio_count; i++) { 942 struct audio *audio = res_pool->audios[i]; 943 944 audio->funcs->hw_init(audio); 945 } 946 947 for (i = 0; i < dc->link_count; i++) { 948 struct dc_link *link = dc->links[i]; 949 950 if (link->panel_cntl) 951 backlight = link->panel_cntl->funcs->hw_init(link->panel_cntl); 952 } 953 954 for (i = 0; i < dc->res_pool->pipe_count; i++) { 955 if (abms[i] != NULL && abms[i]->funcs != NULL) 956 abms[i]->funcs->abm_init(abms[i], backlight); 957 } 958 959 /* power AFMT HDMI memory TODO: may move to dis/en output save power*/ 960 REG_WRITE(DIO_MEM_PWR_CTRL, 0); 961 962 if (!dc->debug.disable_clock_gate) { 963 /* enable all DCN clock gating */ 964 REG_WRITE(DCCG_GATE_DISABLE_CNTL, 0); 965 966 REG_WRITE(DCCG_GATE_DISABLE_CNTL2, 0); 967 968 REG_UPDATE(DCFCLK_CNTL, DCFCLK_GATE_DIS, 0); 969 } 970 if (hws->funcs.enable_power_gating_plane) 971 hws->funcs.enable_power_gating_plane(dc->hwseq, true); 972 973 if (!dcb->funcs->is_accelerated_mode(dcb) && dc->res_pool->hubbub->funcs->init_watermarks) 974 dc->res_pool->hubbub->funcs->init_watermarks(dc->res_pool->hubbub); 975 976 if (dc->clk_mgr->funcs->notify_wm_ranges) 977 dc->clk_mgr->funcs->notify_wm_ranges(dc->clk_mgr); 978 979 if (dc->clk_mgr->funcs->set_hard_max_memclk) 980 dc->clk_mgr->funcs->set_hard_max_memclk(dc->clk_mgr); 981 982 if (dc->res_pool->hubbub->funcs->force_pstate_change_control) 983 dc->res_pool->hubbub->funcs->force_pstate_change_control( 984 dc->res_pool->hubbub, false, false); 985 986 if (dc->res_pool->hubbub->funcs->init_crb) 987 dc->res_pool->hubbub->funcs->init_crb(dc->res_pool->hubbub); 988 989 if (dc->res_pool->hubbub->funcs->set_request_limit && dc->config.sdpif_request_limit_words_per_umc > 0) 990 dc->res_pool->hubbub->funcs->set_request_limit(dc->res_pool->hubbub, dc->ctx->dc_bios->vram_info.num_chans, dc->config.sdpif_request_limit_words_per_umc); 991 992 // Get DMCUB capabilities 993 if (dc->ctx->dmub_srv) { 994 dc_dmub_srv_query_caps_cmd(dc->ctx->dmub_srv->dmub); 995 dc->caps.dmub_caps.psr = dc->ctx->dmub_srv->dmub->feature_caps.psr; 996 } 997 } 998 999 static int calc_mpc_flow_ctrl_cnt(const struct dc_stream_state *stream, 1000 int opp_cnt) 1001 { 1002 bool hblank_halved = optc2_is_two_pixels_per_containter(&stream->timing); 1003 int flow_ctrl_cnt; 1004 1005 if (opp_cnt >= 2) 1006 hblank_halved = true; 1007 1008 flow_ctrl_cnt = stream->timing.h_total - stream->timing.h_addressable - 1009 stream->timing.h_border_left - 1010 stream->timing.h_border_right; 1011 1012 if (hblank_halved) 1013 flow_ctrl_cnt /= 2; 1014 1015 /* ODM combine 4:1 case */ 1016 if (opp_cnt == 4) 1017 flow_ctrl_cnt /= 2; 1018 1019 return flow_ctrl_cnt; 1020 } 1021 1022 static void update_dsc_on_stream(struct pipe_ctx *pipe_ctx, bool enable) 1023 { 1024 struct display_stream_compressor *dsc = pipe_ctx->stream_res.dsc; 1025 struct dc_stream_state *stream = pipe_ctx->stream; 1026 struct pipe_ctx *odm_pipe; 1027 int opp_cnt = 1; 1028 1029 ASSERT(dsc); 1030 for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) 1031 opp_cnt++; 1032 1033 if (enable) { 1034 struct dsc_config dsc_cfg; 1035 struct dsc_optc_config dsc_optc_cfg; 1036 enum optc_dsc_mode optc_dsc_mode; 1037 1038 /* Enable DSC hw block */ 1039 dsc_cfg.pic_width = (stream->timing.h_addressable + stream->timing.h_border_left + stream->timing.h_border_right) / opp_cnt; 1040 dsc_cfg.pic_height = stream->timing.v_addressable + stream->timing.v_border_top + stream->timing.v_border_bottom; 1041 dsc_cfg.pixel_encoding = stream->timing.pixel_encoding; 1042 dsc_cfg.color_depth = stream->timing.display_color_depth; 1043 dsc_cfg.is_odm = pipe_ctx->next_odm_pipe ? true : false; 1044 dsc_cfg.dc_dsc_cfg = stream->timing.dsc_cfg; 1045 ASSERT(dsc_cfg.dc_dsc_cfg.num_slices_h % opp_cnt == 0); 1046 dsc_cfg.dc_dsc_cfg.num_slices_h /= opp_cnt; 1047 1048 dsc->funcs->dsc_set_config(dsc, &dsc_cfg, &dsc_optc_cfg); 1049 dsc->funcs->dsc_enable(dsc, pipe_ctx->stream_res.opp->inst); 1050 for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) { 1051 struct display_stream_compressor *odm_dsc = odm_pipe->stream_res.dsc; 1052 1053 ASSERT(odm_dsc); 1054 odm_dsc->funcs->dsc_set_config(odm_dsc, &dsc_cfg, &dsc_optc_cfg); 1055 odm_dsc->funcs->dsc_enable(odm_dsc, odm_pipe->stream_res.opp->inst); 1056 } 1057 dsc_cfg.dc_dsc_cfg.num_slices_h *= opp_cnt; 1058 dsc_cfg.pic_width *= opp_cnt; 1059 1060 optc_dsc_mode = dsc_optc_cfg.is_pixel_format_444 ? OPTC_DSC_ENABLED_444 : OPTC_DSC_ENABLED_NATIVE_SUBSAMPLED; 1061 1062 /* Enable DSC in OPTC */ 1063 DC_LOG_DSC("Setting optc DSC config for tg instance %d:", pipe_ctx->stream_res.tg->inst); 1064 pipe_ctx->stream_res.tg->funcs->set_dsc_config(pipe_ctx->stream_res.tg, 1065 optc_dsc_mode, 1066 dsc_optc_cfg.bytes_per_pixel, 1067 dsc_optc_cfg.slice_width); 1068 } else { 1069 /* disable DSC in OPTC */ 1070 pipe_ctx->stream_res.tg->funcs->set_dsc_config( 1071 pipe_ctx->stream_res.tg, 1072 OPTC_DSC_DISABLED, 0, 0); 1073 1074 /* disable DSC block */ 1075 dsc->funcs->dsc_disable(pipe_ctx->stream_res.dsc); 1076 for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) { 1077 ASSERT(odm_pipe->stream_res.dsc); 1078 odm_pipe->stream_res.dsc->funcs->dsc_disable(odm_pipe->stream_res.dsc); 1079 } 1080 } 1081 } 1082 1083 /* 1084 * Given any pipe_ctx, return the total ODM combine factor, and optionally return 1085 * the OPPids which are used 1086 * */ 1087 static unsigned int get_odm_config(struct pipe_ctx *pipe_ctx, unsigned int *opp_instances) 1088 { 1089 unsigned int opp_count = 1; 1090 struct pipe_ctx *odm_pipe; 1091 1092 /* First get to the top pipe */ 1093 for (odm_pipe = pipe_ctx; odm_pipe->prev_odm_pipe; odm_pipe = odm_pipe->prev_odm_pipe) 1094 ; 1095 1096 /* First pipe is always used */ 1097 if (opp_instances) 1098 opp_instances[0] = odm_pipe->stream_res.opp->inst; 1099 1100 /* Find and count odm pipes, if any */ 1101 for (odm_pipe = odm_pipe->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) { 1102 if (opp_instances) 1103 opp_instances[opp_count] = odm_pipe->stream_res.opp->inst; 1104 opp_count++; 1105 } 1106 1107 return opp_count; 1108 } 1109 1110 void dcn32_update_odm(struct dc *dc, struct dc_state *context, struct pipe_ctx *pipe_ctx) 1111 { 1112 struct pipe_ctx *odm_pipe; 1113 int opp_cnt = 0; 1114 int opp_inst[MAX_PIPES] = {0}; 1115 bool rate_control_2x_pclk = (pipe_ctx->stream->timing.flags.INTERLACE || optc2_is_two_pixels_per_containter(&pipe_ctx->stream->timing)); 1116 struct mpc_dwb_flow_control flow_control; 1117 struct mpc *mpc = dc->res_pool->mpc; 1118 int i; 1119 1120 opp_cnt = get_odm_config(pipe_ctx, opp_inst); 1121 1122 if (opp_cnt > 1) 1123 pipe_ctx->stream_res.tg->funcs->set_odm_combine( 1124 pipe_ctx->stream_res.tg, 1125 opp_inst, opp_cnt, 1126 &pipe_ctx->stream->timing); 1127 else 1128 pipe_ctx->stream_res.tg->funcs->set_odm_bypass( 1129 pipe_ctx->stream_res.tg, &pipe_ctx->stream->timing); 1130 1131 rate_control_2x_pclk = rate_control_2x_pclk || opp_cnt > 1; 1132 flow_control.flow_ctrl_mode = 0; 1133 flow_control.flow_ctrl_cnt0 = 0x80; 1134 flow_control.flow_ctrl_cnt1 = calc_mpc_flow_ctrl_cnt(pipe_ctx->stream, opp_cnt); 1135 if (mpc->funcs->set_out_rate_control) { 1136 for (i = 0; i < opp_cnt; ++i) { 1137 mpc->funcs->set_out_rate_control( 1138 mpc, opp_inst[i], 1139 true, 1140 rate_control_2x_pclk, 1141 &flow_control); 1142 } 1143 } 1144 1145 for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) { 1146 odm_pipe->stream_res.opp->funcs->opp_pipe_clock_control( 1147 odm_pipe->stream_res.opp, 1148 true); 1149 } 1150 1151 if (pipe_ctx->stream_res.dsc) { 1152 struct pipe_ctx *current_pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[pipe_ctx->pipe_idx]; 1153 1154 update_dsc_on_stream(pipe_ctx, pipe_ctx->stream->timing.flags.DSC); 1155 1156 /* Check if no longer using pipe for ODM, then need to disconnect DSC for that pipe */ 1157 if (!pipe_ctx->next_odm_pipe && current_pipe_ctx->next_odm_pipe && 1158 current_pipe_ctx->next_odm_pipe->stream_res.dsc) { 1159 struct display_stream_compressor *dsc = current_pipe_ctx->next_odm_pipe->stream_res.dsc; 1160 /* disconnect DSC block from stream */ 1161 dsc->funcs->dsc_disconnect(dsc); 1162 } 1163 } 1164 } 1165 1166 unsigned int dcn32_calculate_dccg_k1_k2_values(struct pipe_ctx *pipe_ctx, unsigned int *k1_div, unsigned int *k2_div) 1167 { 1168 struct dc_stream_state *stream = pipe_ctx->stream; 1169 unsigned int odm_combine_factor = 0; 1170 bool two_pix_per_container = false; 1171 1172 // For phantom pipes, use the same programming as the main pipes 1173 if (pipe_ctx->stream->mall_stream_config.type == SUBVP_PHANTOM) { 1174 stream = pipe_ctx->stream->mall_stream_config.paired_stream; 1175 } 1176 two_pix_per_container = optc2_is_two_pixels_per_containter(&stream->timing); 1177 odm_combine_factor = get_odm_config(pipe_ctx, NULL); 1178 1179 if (is_dp_128b_132b_signal(pipe_ctx)) { 1180 *k1_div = PIXEL_RATE_DIV_BY_1; 1181 *k2_div = PIXEL_RATE_DIV_BY_1; 1182 } else if (dc_is_hdmi_tmds_signal(pipe_ctx->stream->signal) || dc_is_dvi_signal(pipe_ctx->stream->signal)) { 1183 *k1_div = PIXEL_RATE_DIV_BY_1; 1184 if (stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR420) 1185 *k2_div = PIXEL_RATE_DIV_BY_2; 1186 else 1187 *k2_div = PIXEL_RATE_DIV_BY_4; 1188 } else if (dc_is_dp_signal(pipe_ctx->stream->signal) || dc_is_virtual_signal(pipe_ctx->stream->signal)) { 1189 if (two_pix_per_container) { 1190 *k1_div = PIXEL_RATE_DIV_BY_1; 1191 *k2_div = PIXEL_RATE_DIV_BY_2; 1192 } else { 1193 *k1_div = PIXEL_RATE_DIV_BY_1; 1194 *k2_div = PIXEL_RATE_DIV_BY_4; 1195 if ((odm_combine_factor == 2) || dcn32_is_dp_dig_pixel_rate_div_policy(pipe_ctx)) 1196 *k2_div = PIXEL_RATE_DIV_BY_2; 1197 } 1198 } 1199 1200 if ((*k1_div == PIXEL_RATE_DIV_NA) && (*k2_div == PIXEL_RATE_DIV_NA)) 1201 ASSERT(false); 1202 1203 return odm_combine_factor; 1204 } 1205 1206 void dcn32_set_pixels_per_cycle(struct pipe_ctx *pipe_ctx) 1207 { 1208 uint32_t pix_per_cycle = 1; 1209 uint32_t odm_combine_factor = 1; 1210 1211 if (!pipe_ctx || !pipe_ctx->stream || !pipe_ctx->stream_res.stream_enc) 1212 return; 1213 1214 odm_combine_factor = get_odm_config(pipe_ctx, NULL); 1215 if (optc2_is_two_pixels_per_containter(&pipe_ctx->stream->timing) || odm_combine_factor > 1 1216 || dcn32_is_dp_dig_pixel_rate_div_policy(pipe_ctx)) 1217 pix_per_cycle = 2; 1218 1219 if (pipe_ctx->stream_res.stream_enc->funcs->set_input_mode) 1220 pipe_ctx->stream_res.stream_enc->funcs->set_input_mode(pipe_ctx->stream_res.stream_enc, 1221 pix_per_cycle); 1222 } 1223 1224 void dcn32_unblank_stream(struct pipe_ctx *pipe_ctx, 1225 struct dc_link_settings *link_settings) 1226 { 1227 struct encoder_unblank_param params = {0}; 1228 struct dc_stream_state *stream = pipe_ctx->stream; 1229 struct dc_link *link = stream->link; 1230 struct dce_hwseq *hws = link->dc->hwseq; 1231 struct pipe_ctx *odm_pipe; 1232 uint32_t pix_per_cycle = 1; 1233 1234 params.opp_cnt = 1; 1235 for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) 1236 params.opp_cnt++; 1237 1238 /* only 3 items below are used by unblank */ 1239 params.timing = pipe_ctx->stream->timing; 1240 1241 params.link_settings.link_rate = link_settings->link_rate; 1242 1243 if (is_dp_128b_132b_signal(pipe_ctx)) { 1244 /* TODO - DP2.0 HW: Set ODM mode in dp hpo encoder here */ 1245 pipe_ctx->stream_res.hpo_dp_stream_enc->funcs->dp_unblank( 1246 pipe_ctx->stream_res.hpo_dp_stream_enc, 1247 pipe_ctx->stream_res.tg->inst); 1248 } else if (dc_is_dp_signal(pipe_ctx->stream->signal)) { 1249 if (optc2_is_two_pixels_per_containter(&stream->timing) || params.opp_cnt > 1 1250 || dcn32_is_dp_dig_pixel_rate_div_policy(pipe_ctx)) { 1251 params.timing.pix_clk_100hz /= 2; 1252 pix_per_cycle = 2; 1253 } 1254 pipe_ctx->stream_res.stream_enc->funcs->dp_set_odm_combine( 1255 pipe_ctx->stream_res.stream_enc, pix_per_cycle > 1); 1256 pipe_ctx->stream_res.stream_enc->funcs->dp_unblank(link, pipe_ctx->stream_res.stream_enc, ¶ms); 1257 } 1258 1259 if (link->local_sink && link->local_sink->sink_signal == SIGNAL_TYPE_EDP) 1260 hws->funcs.edp_backlight_control(link, true); 1261 } 1262 1263 bool dcn32_is_dp_dig_pixel_rate_div_policy(struct pipe_ctx *pipe_ctx) 1264 { 1265 struct dc *dc = pipe_ctx->stream->ctx->dc; 1266 1267 if (!is_h_timing_divisible_by_2(pipe_ctx->stream)) 1268 return false; 1269 1270 if (dc_is_dp_signal(pipe_ctx->stream->signal) && !is_dp_128b_132b_signal(pipe_ctx) && 1271 dc->debug.enable_dp_dig_pixel_rate_div_policy) 1272 return true; 1273 return false; 1274 } 1275 1276 static void apply_symclk_on_tx_off_wa(struct dc_link *link) 1277 { 1278 /* There are use cases where SYMCLK is referenced by OTG. For instance 1279 * for TMDS signal, OTG relies SYMCLK even if TX video output is off. 1280 * However current link interface will power off PHY when disabling link 1281 * output. This will turn off SYMCLK generated by PHY. The workaround is 1282 * to identify such case where SYMCLK is still in use by OTG when we 1283 * power off PHY. When this is detected, we will temporarily power PHY 1284 * back on and move PHY's SYMCLK state to SYMCLK_ON_TX_OFF by calling 1285 * program_pix_clk interface. When OTG is disabled, we will then power 1286 * off PHY by calling disable link output again. 1287 * 1288 * In future dcn generations, we plan to rework transmitter control 1289 * interface so that we could have an option to set SYMCLK ON TX OFF 1290 * state in one step without this workaround 1291 */ 1292 1293 struct dc *dc = link->ctx->dc; 1294 struct pipe_ctx *pipe_ctx = NULL; 1295 uint8_t i; 1296 1297 if (link->phy_state.symclk_ref_cnts.otg > 0) { 1298 for (i = 0; i < MAX_PIPES; i++) { 1299 pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[i]; 1300 if (pipe_ctx->stream && pipe_ctx->stream->link == link && pipe_ctx->top_pipe == NULL) { 1301 pipe_ctx->clock_source->funcs->program_pix_clk( 1302 pipe_ctx->clock_source, 1303 &pipe_ctx->stream_res.pix_clk_params, 1304 dp_get_link_encoding_format(&pipe_ctx->link_config.dp_link_settings), 1305 &pipe_ctx->pll_settings); 1306 link->phy_state.symclk_state = SYMCLK_ON_TX_OFF; 1307 break; 1308 } 1309 } 1310 } 1311 } 1312 1313 void dcn32_disable_link_output(struct dc_link *link, 1314 const struct link_resource *link_res, 1315 enum signal_type signal) 1316 { 1317 struct dc *dc = link->ctx->dc; 1318 const struct link_hwss *link_hwss = get_link_hwss(link, link_res); 1319 struct dmcu *dmcu = dc->res_pool->dmcu; 1320 1321 if (signal == SIGNAL_TYPE_EDP && 1322 link->dc->hwss.edp_backlight_control) 1323 link->dc->hwss.edp_backlight_control(link, false); 1324 else if (dmcu != NULL && dmcu->funcs->lock_phy) 1325 dmcu->funcs->lock_phy(dmcu); 1326 1327 link_hwss->disable_link_output(link, link_res, signal); 1328 link->phy_state.symclk_state = SYMCLK_OFF_TX_OFF; 1329 1330 if (signal == SIGNAL_TYPE_EDP && 1331 link->dc->hwss.edp_backlight_control) 1332 link->dc->hwss.edp_power_control(link, false); 1333 else if (dmcu != NULL && dmcu->funcs->lock_phy) 1334 dmcu->funcs->unlock_phy(dmcu); 1335 1336 dp_source_sequence_trace(link, DPCD_SOURCE_SEQ_AFTER_DISABLE_LINK_PHY); 1337 1338 apply_symclk_on_tx_off_wa(link); 1339 } 1340 1341 /* For SubVP the main pipe can have a viewport position change 1342 * without a full update. In this case we must also update the 1343 * viewport positions for the phantom pipe accordingly. 1344 */ 1345 void dcn32_update_phantom_vp_position(struct dc *dc, 1346 struct dc_state *context, 1347 struct pipe_ctx *phantom_pipe) 1348 { 1349 uint32_t i; 1350 struct dc_plane_state *phantom_plane = phantom_pipe->plane_state; 1351 1352 for (i = 0; i < dc->res_pool->pipe_count; i++) { 1353 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; 1354 1355 if (pipe->stream && pipe->stream->mall_stream_config.type == SUBVP_MAIN && 1356 pipe->stream->mall_stream_config.paired_stream == phantom_pipe->stream) { 1357 if (pipe->plane_state && pipe->plane_state->update_flags.bits.position_change) { 1358 1359 phantom_plane->src_rect.x = pipe->plane_state->src_rect.x; 1360 phantom_plane->src_rect.y = pipe->plane_state->src_rect.y; 1361 phantom_plane->clip_rect.x = pipe->plane_state->clip_rect.x; 1362 phantom_plane->dst_rect.x = pipe->plane_state->dst_rect.x; 1363 phantom_plane->dst_rect.y = pipe->plane_state->dst_rect.y; 1364 1365 phantom_pipe->plane_state->update_flags.bits.position_change = 1; 1366 resource_build_scaling_params(phantom_pipe); 1367 return; 1368 } 1369 } 1370 } 1371 } 1372 1373 /* Treat the phantom pipe as if it needs to be fully enabled. 1374 * If the pipe was previously in use but not phantom, it would 1375 * have been disabled earlier in the sequence so we need to run 1376 * the full enable sequence. 1377 */ 1378 void dcn32_apply_update_flags_for_phantom(struct pipe_ctx *phantom_pipe) 1379 { 1380 phantom_pipe->update_flags.raw = 0; 1381 if (phantom_pipe->stream && phantom_pipe->stream->mall_stream_config.type == SUBVP_PHANTOM) { 1382 if (phantom_pipe->stream && phantom_pipe->plane_state) { 1383 phantom_pipe->update_flags.bits.enable = 1; 1384 phantom_pipe->update_flags.bits.mpcc = 1; 1385 phantom_pipe->update_flags.bits.dppclk = 1; 1386 phantom_pipe->update_flags.bits.hubp_interdependent = 1; 1387 phantom_pipe->update_flags.bits.hubp_rq_dlg_ttu = 1; 1388 phantom_pipe->update_flags.bits.gamut_remap = 1; 1389 phantom_pipe->update_flags.bits.scaler = 1; 1390 phantom_pipe->update_flags.bits.viewport = 1; 1391 phantom_pipe->update_flags.bits.det_size = 1; 1392 if (!phantom_pipe->top_pipe && !phantom_pipe->prev_odm_pipe) { 1393 phantom_pipe->update_flags.bits.odm = 1; 1394 phantom_pipe->update_flags.bits.global_sync = 1; 1395 } 1396 } 1397 } 1398 } 1399 1400 bool dcn32_dsc_pg_status( 1401 struct dce_hwseq *hws, 1402 unsigned int dsc_inst) 1403 { 1404 uint32_t pwr_status = 0; 1405 1406 switch (dsc_inst) { 1407 case 0: /* DSC0 */ 1408 REG_GET(DOMAIN16_PG_STATUS, 1409 DOMAIN_PGFSM_PWR_STATUS, &pwr_status); 1410 break; 1411 case 1: /* DSC1 */ 1412 1413 REG_GET(DOMAIN17_PG_STATUS, 1414 DOMAIN_PGFSM_PWR_STATUS, &pwr_status); 1415 break; 1416 case 2: /* DSC2 */ 1417 REG_GET(DOMAIN18_PG_STATUS, 1418 DOMAIN_PGFSM_PWR_STATUS, &pwr_status); 1419 break; 1420 case 3: /* DSC3 */ 1421 REG_GET(DOMAIN19_PG_STATUS, 1422 DOMAIN_PGFSM_PWR_STATUS, &pwr_status); 1423 break; 1424 default: 1425 BREAK_TO_DEBUGGER(); 1426 break; 1427 } 1428 1429 return pwr_status == 0; 1430 } 1431 1432 void dcn32_update_dsc_pg(struct dc *dc, 1433 struct dc_state *context, 1434 bool safe_to_disable) 1435 { 1436 struct dce_hwseq *hws = dc->hwseq; 1437 int i; 1438 1439 for (i = 0; i < dc->res_pool->res_cap->num_dsc; i++) { 1440 struct display_stream_compressor *dsc = dc->res_pool->dscs[i]; 1441 bool is_dsc_ungated = hws->funcs.dsc_pg_status(hws, dsc->inst); 1442 1443 if (context->res_ctx.is_dsc_acquired[i]) { 1444 if (!is_dsc_ungated) { 1445 hws->funcs.dsc_pg_control(hws, dsc->inst, true); 1446 } 1447 } else if (safe_to_disable) { 1448 if (is_dsc_ungated) { 1449 hws->funcs.dsc_pg_control(hws, dsc->inst, false); 1450 } 1451 } 1452 } 1453 } 1454 1455 void dcn32_enable_phantom_streams(struct dc *dc, struct dc_state *context) 1456 { 1457 unsigned int i; 1458 1459 for (i = 0; i < dc->res_pool->pipe_count; i++) { 1460 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; 1461 struct pipe_ctx *old_pipe = &dc->current_state->res_ctx.pipe_ctx[i]; 1462 1463 /* If an active, non-phantom pipe is being transitioned into a phantom 1464 * pipe, wait for the double buffer update to complete first before we do 1465 * ANY phantom pipe programming. 1466 */ 1467 if (pipe->stream && pipe->stream->mall_stream_config.type == SUBVP_PHANTOM && 1468 old_pipe->stream && old_pipe->stream->mall_stream_config.type != SUBVP_PHANTOM) { 1469 old_pipe->stream_res.tg->funcs->wait_for_state( 1470 old_pipe->stream_res.tg, 1471 CRTC_STATE_VBLANK); 1472 old_pipe->stream_res.tg->funcs->wait_for_state( 1473 old_pipe->stream_res.tg, 1474 CRTC_STATE_VACTIVE); 1475 } 1476 } 1477 for (i = 0; i < dc->res_pool->pipe_count; i++) { 1478 struct pipe_ctx *new_pipe = &context->res_ctx.pipe_ctx[i]; 1479 1480 if (new_pipe->stream && new_pipe->stream->mall_stream_config.type == SUBVP_PHANTOM) { 1481 // If old context or new context has phantom pipes, apply 1482 // the phantom timings now. We can't change the phantom 1483 // pipe configuration safely without driver acquiring 1484 // the DMCUB lock first. 1485 dc->hwss.apply_ctx_to_hw(dc, context); 1486 break; 1487 } 1488 } 1489 } 1490