1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 27 #include "dm_services.h" 28 #include "dm_helpers.h" 29 #include "core_types.h" 30 #include "resource.h" 31 #include "dccg.h" 32 #include "dce/dce_hwseq.h" 33 #include "dcn30/dcn30_cm_common.h" 34 #include "reg_helper.h" 35 #include "abm.h" 36 #include "hubp.h" 37 #include "dchubbub.h" 38 #include "timing_generator.h" 39 #include "opp.h" 40 #include "ipp.h" 41 #include "mpc.h" 42 #include "mcif_wb.h" 43 #include "dc_dmub_srv.h" 44 #include "link_hwss.h" 45 #include "dpcd_defs.h" 46 #include "dcn32_hwseq.h" 47 #include "clk_mgr.h" 48 #include "dsc.h" 49 #include "dcn20/dcn20_optc.h" 50 #include "dmub_subvp_state.h" 51 #include "dce/dmub_hw_lock_mgr.h" 52 #include "dcn32_resource.h" 53 #include "link.h" 54 #include "dmub/inc/dmub_subvp_state.h" 55 56 #define DC_LOGGER_INIT(logger) 57 58 #define CTX \ 59 hws->ctx 60 #define REG(reg)\ 61 hws->regs->reg 62 #define DC_LOGGER \ 63 dc->ctx->logger 64 65 66 #undef FN 67 #define FN(reg_name, field_name) \ 68 hws->shifts->field_name, hws->masks->field_name 69 70 void dcn32_dsc_pg_control( 71 struct dce_hwseq *hws, 72 unsigned int dsc_inst, 73 bool power_on) 74 { 75 uint32_t power_gate = power_on ? 0 : 1; 76 uint32_t pwr_status = power_on ? 0 : 2; 77 uint32_t org_ip_request_cntl = 0; 78 79 if (hws->ctx->dc->debug.disable_dsc_power_gate) 80 return; 81 82 REG_GET(DC_IP_REQUEST_CNTL, IP_REQUEST_EN, &org_ip_request_cntl); 83 if (org_ip_request_cntl == 0) 84 REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 1); 85 86 switch (dsc_inst) { 87 case 0: /* DSC0 */ 88 REG_UPDATE(DOMAIN16_PG_CONFIG, 89 DOMAIN_POWER_GATE, power_gate); 90 91 REG_WAIT(DOMAIN16_PG_STATUS, 92 DOMAIN_PGFSM_PWR_STATUS, pwr_status, 93 1, 1000); 94 break; 95 case 1: /* DSC1 */ 96 REG_UPDATE(DOMAIN17_PG_CONFIG, 97 DOMAIN_POWER_GATE, power_gate); 98 99 REG_WAIT(DOMAIN17_PG_STATUS, 100 DOMAIN_PGFSM_PWR_STATUS, pwr_status, 101 1, 1000); 102 break; 103 case 2: /* DSC2 */ 104 REG_UPDATE(DOMAIN18_PG_CONFIG, 105 DOMAIN_POWER_GATE, power_gate); 106 107 REG_WAIT(DOMAIN18_PG_STATUS, 108 DOMAIN_PGFSM_PWR_STATUS, pwr_status, 109 1, 1000); 110 break; 111 case 3: /* DSC3 */ 112 REG_UPDATE(DOMAIN19_PG_CONFIG, 113 DOMAIN_POWER_GATE, power_gate); 114 115 REG_WAIT(DOMAIN19_PG_STATUS, 116 DOMAIN_PGFSM_PWR_STATUS, pwr_status, 117 1, 1000); 118 break; 119 default: 120 BREAK_TO_DEBUGGER(); 121 break; 122 } 123 124 if (org_ip_request_cntl == 0) 125 REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 0); 126 } 127 128 129 void dcn32_enable_power_gating_plane( 130 struct dce_hwseq *hws, 131 bool enable) 132 { 133 bool force_on = true; /* disable power gating */ 134 uint32_t org_ip_request_cntl = 0; 135 136 if (enable) 137 force_on = false; 138 139 REG_GET(DC_IP_REQUEST_CNTL, IP_REQUEST_EN, &org_ip_request_cntl); 140 if (org_ip_request_cntl == 0) 141 REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 1); 142 143 /* DCHUBP0/1/2/3 */ 144 REG_UPDATE(DOMAIN0_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on); 145 REG_UPDATE(DOMAIN1_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on); 146 REG_UPDATE(DOMAIN2_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on); 147 REG_UPDATE(DOMAIN3_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on); 148 149 /* DCS0/1/2/3 */ 150 REG_UPDATE(DOMAIN16_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on); 151 REG_UPDATE(DOMAIN17_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on); 152 REG_UPDATE(DOMAIN18_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on); 153 REG_UPDATE(DOMAIN19_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on); 154 155 if (org_ip_request_cntl == 0) 156 REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 0); 157 } 158 159 void dcn32_hubp_pg_control(struct dce_hwseq *hws, unsigned int hubp_inst, bool power_on) 160 { 161 uint32_t power_gate = power_on ? 0 : 1; 162 uint32_t pwr_status = power_on ? 0 : 2; 163 164 if (hws->ctx->dc->debug.disable_hubp_power_gate) 165 return; 166 167 if (REG(DOMAIN0_PG_CONFIG) == 0) 168 return; 169 170 switch (hubp_inst) { 171 case 0: 172 REG_SET(DOMAIN0_PG_CONFIG, 0, DOMAIN_POWER_GATE, power_gate); 173 REG_WAIT(DOMAIN0_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, pwr_status, 1, 1000); 174 break; 175 case 1: 176 REG_SET(DOMAIN1_PG_CONFIG, 0, DOMAIN_POWER_GATE, power_gate); 177 REG_WAIT(DOMAIN1_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, pwr_status, 1, 1000); 178 break; 179 case 2: 180 REG_SET(DOMAIN2_PG_CONFIG, 0, DOMAIN_POWER_GATE, power_gate); 181 REG_WAIT(DOMAIN2_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, pwr_status, 1, 1000); 182 break; 183 case 3: 184 REG_SET(DOMAIN3_PG_CONFIG, 0, DOMAIN_POWER_GATE, power_gate); 185 REG_WAIT(DOMAIN3_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, pwr_status, 1, 1000); 186 break; 187 default: 188 BREAK_TO_DEBUGGER(); 189 break; 190 } 191 } 192 193 static bool dcn32_check_no_memory_request_for_cab(struct dc *dc) 194 { 195 int i; 196 197 /* First, check no-memory-request case */ 198 for (i = 0; i < dc->current_state->stream_count; i++) { 199 if ((dc->current_state->stream_status[i].plane_count) && 200 (dc->current_state->streams[i]->link->psr_settings.psr_version == DC_PSR_VERSION_UNSUPPORTED)) 201 /* Fail eligibility on a visible stream */ 202 break; 203 } 204 205 if (i == dc->current_state->stream_count) 206 return true; 207 208 return false; 209 } 210 211 212 /* This function loops through every surface that needs to be cached in CAB for SS, 213 * and calculates the total number of ways required to store all surfaces (primary, 214 * meta, cursor). 215 */ 216 static uint32_t dcn32_calculate_cab_allocation(struct dc *dc, struct dc_state *ctx) 217 { 218 int i; 219 uint8_t num_ways = 0; 220 uint32_t mall_ss_size_bytes = 0; 221 222 mall_ss_size_bytes = ctx->bw_ctx.bw.dcn.mall_ss_size_bytes; 223 // TODO add additional logic for PSR active stream exclusion optimization 224 // mall_ss_psr_active_size_bytes = ctx->bw_ctx.bw.dcn.mall_ss_psr_active_size_bytes; 225 226 // Include cursor size for CAB allocation 227 for (i = 0; i < dc->res_pool->pipe_count; i++) { 228 struct pipe_ctx *pipe = &ctx->res_ctx.pipe_ctx[i]; 229 230 if (!pipe->stream || !pipe->plane_state) 231 continue; 232 233 mall_ss_size_bytes += dcn32_helper_calculate_mall_bytes_for_cursor(dc, pipe, false); 234 } 235 236 // Convert number of cache lines required to number of ways 237 if (dc->debug.force_mall_ss_num_ways > 0) { 238 num_ways = dc->debug.force_mall_ss_num_ways; 239 } else { 240 num_ways = dcn32_helper_mall_bytes_to_ways(dc, mall_ss_size_bytes); 241 } 242 243 return num_ways; 244 } 245 246 bool dcn32_apply_idle_power_optimizations(struct dc *dc, bool enable) 247 { 248 union dmub_rb_cmd cmd; 249 uint8_t ways, i; 250 int j; 251 bool mall_ss_unsupported = false; 252 struct dc_plane_state *plane = NULL; 253 254 if (!dc->ctx->dmub_srv) 255 return false; 256 257 for (i = 0; i < dc->current_state->stream_count; i++) { 258 /* MALL SS messaging is not supported with PSR at this time */ 259 if (dc->current_state->streams[i] != NULL && 260 dc->current_state->streams[i]->link->psr_settings.psr_version != DC_PSR_VERSION_UNSUPPORTED) 261 return false; 262 } 263 264 if (enable) { 265 if (dc->current_state) { 266 267 /* 1. Check no memory request case for CAB. 268 * If no memory request case, send CAB_ACTION NO_DF_REQ DMUB message 269 */ 270 if (dcn32_check_no_memory_request_for_cab(dc)) { 271 /* Enable no-memory-requests case */ 272 memset(&cmd, 0, sizeof(cmd)); 273 cmd.cab.header.type = DMUB_CMD__CAB_FOR_SS; 274 cmd.cab.header.sub_type = DMUB_CMD__CAB_NO_DCN_REQ; 275 cmd.cab.header.payload_bytes = sizeof(cmd.cab) - sizeof(cmd.cab.header); 276 277 dc_dmub_srv_cmd_queue(dc->ctx->dmub_srv, &cmd); 278 dc_dmub_srv_cmd_execute(dc->ctx->dmub_srv); 279 280 return true; 281 } 282 283 /* 2. Check if all surfaces can fit in CAB. 284 * If surfaces can fit into CAB, send CAB_ACTION_ALLOW DMUB message 285 * and configure HUBP's to fetch from MALL 286 */ 287 ways = dcn32_calculate_cab_allocation(dc, dc->current_state); 288 289 /* MALL not supported with Stereo3D or TMZ surface. If any plane is using stereo, 290 * or TMZ surface, don't try to enter MALL. 291 */ 292 for (i = 0; i < dc->current_state->stream_count; i++) { 293 for (j = 0; j < dc->current_state->stream_status[i].plane_count; j++) { 294 plane = dc->current_state->stream_status[i].plane_states[j]; 295 296 if (plane->address.type == PLN_ADDR_TYPE_GRPH_STEREO || 297 plane->address.tmz_surface) { 298 mall_ss_unsupported = true; 299 break; 300 } 301 } 302 if (mall_ss_unsupported) 303 break; 304 } 305 if (ways <= dc->caps.cache_num_ways && !mall_ss_unsupported) { 306 memset(&cmd, 0, sizeof(cmd)); 307 cmd.cab.header.type = DMUB_CMD__CAB_FOR_SS; 308 cmd.cab.header.sub_type = DMUB_CMD__CAB_DCN_SS_FIT_IN_CAB; 309 cmd.cab.header.payload_bytes = sizeof(cmd.cab) - sizeof(cmd.cab.header); 310 cmd.cab.cab_alloc_ways = ways; 311 312 dc_dmub_srv_cmd_queue(dc->ctx->dmub_srv, &cmd); 313 dc_dmub_srv_cmd_execute(dc->ctx->dmub_srv); 314 315 return true; 316 } 317 318 } 319 return false; 320 } 321 322 /* Disable CAB */ 323 memset(&cmd, 0, sizeof(cmd)); 324 cmd.cab.header.type = DMUB_CMD__CAB_FOR_SS; 325 cmd.cab.header.sub_type = DMUB_CMD__CAB_NO_IDLE_OPTIMIZATION; 326 cmd.cab.header.payload_bytes = 327 sizeof(cmd.cab) - sizeof(cmd.cab.header); 328 329 dc_dmub_srv_cmd_queue(dc->ctx->dmub_srv, &cmd); 330 dc_dmub_srv_cmd_execute(dc->ctx->dmub_srv); 331 dc_dmub_srv_wait_idle(dc->ctx->dmub_srv); 332 333 return true; 334 } 335 336 /* Send DMCUB message with SubVP pipe info 337 * - For each pipe in context, populate payload with required SubVP information 338 * if the pipe is using SubVP for MCLK switch 339 * - This function must be called while the DMUB HW lock is acquired by driver 340 */ 341 void dcn32_commit_subvp_config(struct dc *dc, struct dc_state *context) 342 { 343 int i; 344 bool enable_subvp = false; 345 346 if (!dc->ctx || !dc->ctx->dmub_srv) 347 return; 348 349 for (i = 0; i < dc->res_pool->pipe_count; i++) { 350 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; 351 352 if (pipe_ctx->stream && pipe_ctx->stream->mall_stream_config.paired_stream && 353 pipe_ctx->stream->mall_stream_config.type == SUBVP_MAIN) { 354 // There is at least 1 SubVP pipe, so enable SubVP 355 enable_subvp = true; 356 break; 357 } 358 } 359 dc_dmub_setup_subvp_dmub_command(dc, context, enable_subvp); 360 } 361 362 /* Sub-Viewport DMUB lock needs to be acquired by driver whenever SubVP is active and: 363 * 1. Any full update for any SubVP main pipe 364 * 2. Any immediate flip for any SubVP pipe 365 * 3. Any flip for DRR pipe 366 * 4. If SubVP was previously in use (i.e. in old context) 367 */ 368 void dcn32_subvp_pipe_control_lock(struct dc *dc, 369 struct dc_state *context, 370 bool lock, 371 bool should_lock_all_pipes, 372 struct pipe_ctx *top_pipe_to_program, 373 bool subvp_prev_use) 374 { 375 unsigned int i = 0; 376 bool subvp_immediate_flip = false; 377 bool subvp_in_use = false; 378 struct pipe_ctx *pipe; 379 380 for (i = 0; i < dc->res_pool->pipe_count; i++) { 381 pipe = &context->res_ctx.pipe_ctx[i]; 382 383 if (pipe->stream && pipe->plane_state && pipe->stream->mall_stream_config.type == SUBVP_MAIN) { 384 subvp_in_use = true; 385 break; 386 } 387 } 388 389 if (top_pipe_to_program && top_pipe_to_program->stream && top_pipe_to_program->plane_state) { 390 if (top_pipe_to_program->stream->mall_stream_config.type == SUBVP_MAIN && 391 top_pipe_to_program->plane_state->flip_immediate) 392 subvp_immediate_flip = true; 393 } 394 395 // Don't need to lock for DRR VSYNC flips -- FW will wait for DRR pending update cleared. 396 if ((subvp_in_use && (should_lock_all_pipes || subvp_immediate_flip)) || (!subvp_in_use && subvp_prev_use)) { 397 union dmub_inbox0_cmd_lock_hw hw_lock_cmd = { 0 }; 398 399 if (!lock) { 400 for (i = 0; i < dc->res_pool->pipe_count; i++) { 401 pipe = &context->res_ctx.pipe_ctx[i]; 402 if (pipe->stream && pipe->plane_state && pipe->stream->mall_stream_config.type == SUBVP_MAIN && 403 should_lock_all_pipes) 404 pipe->stream_res.tg->funcs->wait_for_state(pipe->stream_res.tg, CRTC_STATE_VBLANK); 405 } 406 } 407 408 hw_lock_cmd.bits.command_code = DMUB_INBOX0_CMD__HW_LOCK; 409 hw_lock_cmd.bits.hw_lock_client = HW_LOCK_CLIENT_DRIVER; 410 hw_lock_cmd.bits.lock = lock; 411 hw_lock_cmd.bits.should_release = !lock; 412 dmub_hw_lock_mgr_inbox0_cmd(dc->ctx->dmub_srv, hw_lock_cmd); 413 } 414 } 415 416 417 bool dcn32_set_mpc_shaper_3dlut( 418 struct pipe_ctx *pipe_ctx, const struct dc_stream_state *stream) 419 { 420 struct dpp *dpp_base = pipe_ctx->plane_res.dpp; 421 int mpcc_id = pipe_ctx->plane_res.hubp->inst; 422 struct mpc *mpc = pipe_ctx->stream_res.opp->ctx->dc->res_pool->mpc; 423 bool result = false; 424 425 const struct pwl_params *shaper_lut = NULL; 426 //get the shaper lut params 427 if (stream->func_shaper) { 428 if (stream->func_shaper->type == TF_TYPE_HWPWL) 429 shaper_lut = &stream->func_shaper->pwl; 430 else if (stream->func_shaper->type == TF_TYPE_DISTRIBUTED_POINTS) { 431 cm_helper_translate_curve_to_hw_format( 432 stream->func_shaper, 433 &dpp_base->shaper_params, true); 434 shaper_lut = &dpp_base->shaper_params; 435 } 436 } 437 438 if (stream->lut3d_func && 439 stream->lut3d_func->state.bits.initialized == 1) { 440 441 result = mpc->funcs->program_3dlut(mpc, 442 &stream->lut3d_func->lut_3d, 443 mpcc_id); 444 445 result = mpc->funcs->program_shaper(mpc, 446 shaper_lut, 447 mpcc_id); 448 } 449 450 return result; 451 } 452 453 bool dcn32_set_mcm_luts( 454 struct pipe_ctx *pipe_ctx, const struct dc_plane_state *plane_state) 455 { 456 struct dpp *dpp_base = pipe_ctx->plane_res.dpp; 457 int mpcc_id = pipe_ctx->plane_res.hubp->inst; 458 struct mpc *mpc = pipe_ctx->stream_res.opp->ctx->dc->res_pool->mpc; 459 bool result = true; 460 struct pwl_params *lut_params = NULL; 461 462 // 1D LUT 463 if (plane_state->blend_tf) { 464 if (plane_state->blend_tf->type == TF_TYPE_HWPWL) 465 lut_params = &plane_state->blend_tf->pwl; 466 else if (plane_state->blend_tf->type == TF_TYPE_DISTRIBUTED_POINTS) { 467 cm_helper_translate_curve_to_hw_format( 468 plane_state->blend_tf, 469 &dpp_base->regamma_params, false); 470 lut_params = &dpp_base->regamma_params; 471 } 472 } 473 result = mpc->funcs->program_1dlut(mpc, lut_params, mpcc_id); 474 475 // Shaper 476 if (plane_state->in_shaper_func) { 477 if (plane_state->in_shaper_func->type == TF_TYPE_HWPWL) 478 lut_params = &plane_state->in_shaper_func->pwl; 479 else if (plane_state->in_shaper_func->type == TF_TYPE_DISTRIBUTED_POINTS) { 480 // TODO: dpp_base replace 481 ASSERT(false); 482 cm_helper_translate_curve_to_hw_format( 483 plane_state->in_shaper_func, 484 &dpp_base->shaper_params, true); 485 lut_params = &dpp_base->shaper_params; 486 } 487 } 488 489 result = mpc->funcs->program_shaper(mpc, lut_params, mpcc_id); 490 491 // 3D 492 if (plane_state->lut3d_func && plane_state->lut3d_func->state.bits.initialized == 1) 493 result = mpc->funcs->program_3dlut(mpc, &plane_state->lut3d_func->lut_3d, mpcc_id); 494 else 495 result = mpc->funcs->program_3dlut(mpc, NULL, mpcc_id); 496 497 return result; 498 } 499 500 bool dcn32_set_input_transfer_func(struct dc *dc, 501 struct pipe_ctx *pipe_ctx, 502 const struct dc_plane_state *plane_state) 503 { 504 struct dce_hwseq *hws = dc->hwseq; 505 struct mpc *mpc = dc->res_pool->mpc; 506 struct dpp *dpp_base = pipe_ctx->plane_res.dpp; 507 508 enum dc_transfer_func_predefined tf; 509 bool result = true; 510 struct pwl_params *params = NULL; 511 512 if (mpc == NULL || plane_state == NULL) 513 return false; 514 515 tf = TRANSFER_FUNCTION_UNITY; 516 517 if (plane_state->in_transfer_func && 518 plane_state->in_transfer_func->type == TF_TYPE_PREDEFINED) 519 tf = plane_state->in_transfer_func->tf; 520 521 dpp_base->funcs->dpp_set_pre_degam(dpp_base, tf); 522 523 if (plane_state->in_transfer_func) { 524 if (plane_state->in_transfer_func->type == TF_TYPE_HWPWL) 525 params = &plane_state->in_transfer_func->pwl; 526 else if (plane_state->in_transfer_func->type == TF_TYPE_DISTRIBUTED_POINTS && 527 cm3_helper_translate_curve_to_hw_format(plane_state->in_transfer_func, 528 &dpp_base->degamma_params, false)) 529 params = &dpp_base->degamma_params; 530 } 531 532 dpp_base->funcs->dpp_program_gamcor_lut(dpp_base, params); 533 534 if (pipe_ctx->stream_res.opp && 535 pipe_ctx->stream_res.opp->ctx && 536 hws->funcs.set_mcm_luts) 537 result = hws->funcs.set_mcm_luts(pipe_ctx, plane_state); 538 539 return result; 540 } 541 542 bool dcn32_set_output_transfer_func(struct dc *dc, 543 struct pipe_ctx *pipe_ctx, 544 const struct dc_stream_state *stream) 545 { 546 int mpcc_id = pipe_ctx->plane_res.hubp->inst; 547 struct mpc *mpc = pipe_ctx->stream_res.opp->ctx->dc->res_pool->mpc; 548 struct pwl_params *params = NULL; 549 bool ret = false; 550 551 /* program OGAM or 3DLUT only for the top pipe*/ 552 if (pipe_ctx->top_pipe == NULL) { 553 /*program shaper and 3dlut in MPC*/ 554 ret = dcn32_set_mpc_shaper_3dlut(pipe_ctx, stream); 555 if (ret == false && mpc->funcs->set_output_gamma && stream->out_transfer_func) { 556 if (stream->out_transfer_func->type == TF_TYPE_HWPWL) 557 params = &stream->out_transfer_func->pwl; 558 else if (pipe_ctx->stream->out_transfer_func->type == 559 TF_TYPE_DISTRIBUTED_POINTS && 560 cm3_helper_translate_curve_to_hw_format( 561 stream->out_transfer_func, 562 &mpc->blender_params, false)) 563 params = &mpc->blender_params; 564 /* there are no ROM LUTs in OUTGAM */ 565 if (stream->out_transfer_func->type == TF_TYPE_PREDEFINED) 566 BREAK_TO_DEBUGGER(); 567 } 568 } 569 570 mpc->funcs->set_output_gamma(mpc, mpcc_id, params); 571 return ret; 572 } 573 574 /* Program P-State force value according to if pipe is using SubVP / FPO or not: 575 * 1. Reset P-State force on all pipes first 576 * 2. For each main pipe, force P-State disallow (P-State allow moderated by DMUB) 577 */ 578 void dcn32_update_force_pstate(struct dc *dc, struct dc_state *context) 579 { 580 int i; 581 582 /* Unforce p-state for each pipe if it is not FPO or SubVP. 583 * For FPO and SubVP, if it's already forced disallow, leave 584 * it as disallow. 585 */ 586 for (i = 0; i < dc->res_pool->pipe_count; i++) { 587 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; 588 struct hubp *hubp = pipe->plane_res.hubp; 589 590 if (!pipe->stream || (pipe->stream && !(pipe->stream->mall_stream_config.type == SUBVP_MAIN || 591 pipe->stream->fpo_in_use))) { 592 if (hubp && hubp->funcs->hubp_update_force_pstate_disallow) 593 hubp->funcs->hubp_update_force_pstate_disallow(hubp, false); 594 } 595 596 /* Today only FPO uses cursor P-State force. Only clear cursor P-State force 597 * if it's not FPO. 598 */ 599 if (!pipe->stream || (pipe->stream && !pipe->stream->fpo_in_use)) { 600 if (hubp && hubp->funcs->hubp_update_force_cursor_pstate_disallow) 601 hubp->funcs->hubp_update_force_cursor_pstate_disallow(hubp, false); 602 } 603 } 604 605 /* Loop through each pipe -- for each subvp main pipe force p-state allow equal to false. 606 */ 607 for (i = 0; i < dc->res_pool->pipe_count; i++) { 608 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; 609 struct hubp *hubp = pipe->plane_res.hubp; 610 611 if (pipe->stream && pipe->plane_state && pipe->stream->mall_stream_config.type == SUBVP_MAIN) { 612 if (hubp && hubp->funcs->hubp_update_force_pstate_disallow) 613 hubp->funcs->hubp_update_force_pstate_disallow(hubp, true); 614 } 615 616 if (pipe->stream && pipe->stream->fpo_in_use) { 617 if (hubp && hubp->funcs->hubp_update_force_pstate_disallow) 618 hubp->funcs->hubp_update_force_pstate_disallow(hubp, true); 619 /* For now only force cursor p-state disallow for FPO 620 * Needs to be added for subvp once FW side gets updated 621 */ 622 if (hubp && hubp->funcs->hubp_update_force_cursor_pstate_disallow) 623 hubp->funcs->hubp_update_force_cursor_pstate_disallow(hubp, true); 624 } 625 } 626 } 627 628 /* Update MALL_SEL register based on if pipe / plane 629 * is a phantom pipe, main pipe, and if using MALL 630 * for SS. 631 */ 632 void dcn32_update_mall_sel(struct dc *dc, struct dc_state *context) 633 { 634 int i; 635 unsigned int num_ways = dcn32_calculate_cab_allocation(dc, context); 636 bool cache_cursor = false; 637 638 for (i = 0; i < dc->res_pool->pipe_count; i++) { 639 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; 640 struct hubp *hubp = pipe->plane_res.hubp; 641 642 if (pipe->stream && pipe->plane_state && hubp && hubp->funcs->hubp_update_mall_sel) { 643 int cursor_size = hubp->curs_attr.pitch * hubp->curs_attr.height; 644 645 switch (hubp->curs_attr.color_format) { 646 case CURSOR_MODE_MONO: 647 cursor_size /= 2; 648 break; 649 case CURSOR_MODE_COLOR_1BIT_AND: 650 case CURSOR_MODE_COLOR_PRE_MULTIPLIED_ALPHA: 651 case CURSOR_MODE_COLOR_UN_PRE_MULTIPLIED_ALPHA: 652 cursor_size *= 4; 653 break; 654 655 case CURSOR_MODE_COLOR_64BIT_FP_PRE_MULTIPLIED: 656 case CURSOR_MODE_COLOR_64BIT_FP_UN_PRE_MULTIPLIED: 657 default: 658 cursor_size *= 8; 659 break; 660 } 661 662 if (cursor_size > 16384) 663 cache_cursor = true; 664 665 if (pipe->stream->mall_stream_config.type == SUBVP_PHANTOM) { 666 hubp->funcs->hubp_update_mall_sel(hubp, 1, false); 667 } else { 668 // MALL not supported with Stereo3D 669 hubp->funcs->hubp_update_mall_sel(hubp, 670 num_ways <= dc->caps.cache_num_ways && 671 pipe->stream->link->psr_settings.psr_version == DC_PSR_VERSION_UNSUPPORTED && 672 pipe->plane_state->address.type != PLN_ADDR_TYPE_GRPH_STEREO && 673 !pipe->plane_state->address.tmz_surface ? 2 : 0, 674 cache_cursor); 675 } 676 } 677 } 678 } 679 680 /* Program the sub-viewport pipe configuration after the main / phantom pipes 681 * have been programmed in hardware. 682 * 1. Update force P-State for all the main pipes (disallow P-state) 683 * 2. Update MALL_SEL register 684 * 3. Program FORCE_ONE_ROW_FOR_FRAME for main subvp pipes 685 */ 686 void dcn32_program_mall_pipe_config(struct dc *dc, struct dc_state *context) 687 { 688 int i; 689 struct dce_hwseq *hws = dc->hwseq; 690 691 // Don't force p-state disallow -- can't block dummy p-state 692 693 // Update MALL_SEL register for each pipe 694 if (hws && hws->funcs.update_mall_sel) 695 hws->funcs.update_mall_sel(dc, context); 696 697 // Program FORCE_ONE_ROW_FOR_FRAME and CURSOR_REQ_MODE for main subvp pipes 698 for (i = 0; i < dc->res_pool->pipe_count; i++) { 699 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; 700 struct hubp *hubp = pipe->plane_res.hubp; 701 702 if (pipe->stream && hubp && hubp->funcs->hubp_prepare_subvp_buffering) { 703 /* TODO - remove setting CURSOR_REQ_MODE to 0 for legacy cases 704 * - need to investigate single pipe MPO + SubVP case to 705 * see if CURSOR_REQ_MODE will be back to 1 for SubVP 706 * when it should be 0 for MPO 707 */ 708 if (pipe->stream->mall_stream_config.type == SUBVP_MAIN) { 709 hubp->funcs->hubp_prepare_subvp_buffering(hubp, true); 710 } 711 } 712 } 713 } 714 715 static void dcn32_initialize_min_clocks(struct dc *dc) 716 { 717 struct dc_clocks *clocks = &dc->current_state->bw_ctx.bw.dcn.clk; 718 719 clocks->dcfclk_deep_sleep_khz = DCN3_2_DCFCLK_DS_INIT_KHZ; 720 clocks->dcfclk_khz = dc->clk_mgr->bw_params->clk_table.entries[0].dcfclk_mhz * 1000; 721 clocks->socclk_khz = dc->clk_mgr->bw_params->clk_table.entries[0].socclk_mhz * 1000; 722 clocks->dramclk_khz = dc->clk_mgr->bw_params->clk_table.entries[0].memclk_mhz * 1000; 723 clocks->dppclk_khz = dc->clk_mgr->bw_params->clk_table.entries[0].dppclk_mhz * 1000; 724 clocks->dispclk_khz = dc->clk_mgr->bw_params->clk_table.entries[0].dispclk_mhz * 1000; 725 clocks->ref_dtbclk_khz = dc->clk_mgr->bw_params->clk_table.entries[0].dtbclk_mhz * 1000; 726 clocks->fclk_p_state_change_support = true; 727 clocks->p_state_change_support = true; 728 729 dc->clk_mgr->funcs->update_clocks( 730 dc->clk_mgr, 731 dc->current_state, 732 true); 733 } 734 735 void dcn32_init_hw(struct dc *dc) 736 { 737 struct abm **abms = dc->res_pool->multiple_abms; 738 struct dce_hwseq *hws = dc->hwseq; 739 struct dc_bios *dcb = dc->ctx->dc_bios; 740 struct resource_pool *res_pool = dc->res_pool; 741 int i; 742 int edp_num; 743 uint32_t backlight = MAX_BACKLIGHT_LEVEL; 744 745 if (dc->clk_mgr && dc->clk_mgr->funcs->init_clocks) 746 dc->clk_mgr->funcs->init_clocks(dc->clk_mgr); 747 748 // Initialize the dccg 749 if (res_pool->dccg->funcs->dccg_init) 750 res_pool->dccg->funcs->dccg_init(res_pool->dccg); 751 752 if (!dcb->funcs->is_accelerated_mode(dcb)) { 753 hws->funcs.bios_golden_init(dc); 754 hws->funcs.disable_vga(dc->hwseq); 755 } 756 757 // Set default OPTC memory power states 758 if (dc->debug.enable_mem_low_power.bits.optc) { 759 // Shutdown when unassigned and light sleep in VBLANK 760 REG_SET_2(ODM_MEM_PWR_CTRL3, 0, ODM_MEM_UNASSIGNED_PWR_MODE, 3, ODM_MEM_VBLANK_PWR_MODE, 1); 761 } 762 763 if (dc->debug.enable_mem_low_power.bits.vga) { 764 // Power down VGA memory 765 REG_UPDATE(MMHUBBUB_MEM_PWR_CNTL, VGA_MEM_PWR_FORCE, 1); 766 } 767 768 if (dc->ctx->dc_bios->fw_info_valid) { 769 res_pool->ref_clocks.xtalin_clock_inKhz = 770 dc->ctx->dc_bios->fw_info.pll_info.crystal_frequency; 771 772 if (res_pool->dccg && res_pool->hubbub) { 773 (res_pool->dccg->funcs->get_dccg_ref_freq)(res_pool->dccg, 774 dc->ctx->dc_bios->fw_info.pll_info.crystal_frequency, 775 &res_pool->ref_clocks.dccg_ref_clock_inKhz); 776 777 (res_pool->hubbub->funcs->get_dchub_ref_freq)(res_pool->hubbub, 778 res_pool->ref_clocks.dccg_ref_clock_inKhz, 779 &res_pool->ref_clocks.dchub_ref_clock_inKhz); 780 } else { 781 // Not all ASICs have DCCG sw component 782 res_pool->ref_clocks.dccg_ref_clock_inKhz = 783 res_pool->ref_clocks.xtalin_clock_inKhz; 784 res_pool->ref_clocks.dchub_ref_clock_inKhz = 785 res_pool->ref_clocks.xtalin_clock_inKhz; 786 } 787 } else 788 ASSERT_CRITICAL(false); 789 790 for (i = 0; i < dc->link_count; i++) { 791 /* Power up AND update implementation according to the 792 * required signal (which may be different from the 793 * default signal on connector). 794 */ 795 struct dc_link *link = dc->links[i]; 796 797 link->link_enc->funcs->hw_init(link->link_enc); 798 799 /* Check for enabled DIG to identify enabled display */ 800 if (link->link_enc->funcs->is_dig_enabled && 801 link->link_enc->funcs->is_dig_enabled(link->link_enc)) { 802 link->link_status.link_active = true; 803 link->phy_state.symclk_state = SYMCLK_ON_TX_ON; 804 if (link->link_enc->funcs->fec_is_active && 805 link->link_enc->funcs->fec_is_active(link->link_enc)) 806 link->fec_state = dc_link_fec_enabled; 807 } 808 } 809 810 /* enable_power_gating_plane before dsc_pg_control because 811 * FORCEON = 1 with hw default value on bootup, resume from s3 812 */ 813 if (hws->funcs.enable_power_gating_plane) 814 hws->funcs.enable_power_gating_plane(dc->hwseq, true); 815 816 /* we want to turn off all dp displays before doing detection */ 817 dc->link_srv->blank_all_dp_displays(dc); 818 819 /* If taking control over from VBIOS, we may want to optimize our first 820 * mode set, so we need to skip powering down pipes until we know which 821 * pipes we want to use. 822 * Otherwise, if taking control is not possible, we need to power 823 * everything down. 824 */ 825 if (dcb->funcs->is_accelerated_mode(dcb) || !dc->config.seamless_boot_edp_requested) { 826 hws->funcs.init_pipes(dc, dc->current_state); 827 if (dc->res_pool->hubbub->funcs->allow_self_refresh_control) 828 dc->res_pool->hubbub->funcs->allow_self_refresh_control(dc->res_pool->hubbub, 829 !dc->res_pool->hubbub->ctx->dc->debug.disable_stutter); 830 831 dcn32_initialize_min_clocks(dc); 832 833 /* On HW init, allow idle optimizations after pipes have been turned off. 834 * 835 * In certain D3 cases (i.e. BOCO / BOMACO) it's possible that hardware state 836 * is reset (i.e. not in idle at the time hw init is called), but software state 837 * still has idle_optimizations = true, so we must disable idle optimizations first 838 * (i.e. set false), then re-enable (set true). 839 */ 840 dc_allow_idle_optimizations(dc, false); 841 dc_allow_idle_optimizations(dc, true); 842 } 843 844 /* In headless boot cases, DIG may be turned 845 * on which causes HW/SW discrepancies. 846 * To avoid this, power down hardware on boot 847 * if DIG is turned on and seamless boot not enabled 848 */ 849 if (!dc->config.seamless_boot_edp_requested) { 850 struct dc_link *edp_links[MAX_NUM_EDP]; 851 struct dc_link *edp_link; 852 853 dc_get_edp_links(dc, edp_links, &edp_num); 854 if (edp_num) { 855 for (i = 0; i < edp_num; i++) { 856 edp_link = edp_links[i]; 857 if (edp_link->link_enc->funcs->is_dig_enabled && 858 edp_link->link_enc->funcs->is_dig_enabled(edp_link->link_enc) && 859 dc->hwss.edp_backlight_control && 860 dc->hwss.power_down && 861 dc->hwss.edp_power_control) { 862 dc->hwss.edp_backlight_control(edp_link, false); 863 dc->hwss.power_down(dc); 864 dc->hwss.edp_power_control(edp_link, false); 865 } 866 } 867 } else { 868 for (i = 0; i < dc->link_count; i++) { 869 struct dc_link *link = dc->links[i]; 870 871 if (link->link_enc->funcs->is_dig_enabled && 872 link->link_enc->funcs->is_dig_enabled(link->link_enc) && 873 dc->hwss.power_down) { 874 dc->hwss.power_down(dc); 875 break; 876 } 877 878 } 879 } 880 } 881 882 for (i = 0; i < res_pool->audio_count; i++) { 883 struct audio *audio = res_pool->audios[i]; 884 885 audio->funcs->hw_init(audio); 886 } 887 888 for (i = 0; i < dc->link_count; i++) { 889 struct dc_link *link = dc->links[i]; 890 891 if (link->panel_cntl) 892 backlight = link->panel_cntl->funcs->hw_init(link->panel_cntl); 893 } 894 895 for (i = 0; i < dc->res_pool->pipe_count; i++) { 896 if (abms[i] != NULL && abms[i]->funcs != NULL) 897 abms[i]->funcs->abm_init(abms[i], backlight); 898 } 899 900 /* power AFMT HDMI memory TODO: may move to dis/en output save power*/ 901 REG_WRITE(DIO_MEM_PWR_CTRL, 0); 902 903 if (!dc->debug.disable_clock_gate) { 904 /* enable all DCN clock gating */ 905 REG_WRITE(DCCG_GATE_DISABLE_CNTL, 0); 906 907 REG_WRITE(DCCG_GATE_DISABLE_CNTL2, 0); 908 909 REG_UPDATE(DCFCLK_CNTL, DCFCLK_GATE_DIS, 0); 910 } 911 912 if (!dcb->funcs->is_accelerated_mode(dcb) && dc->res_pool->hubbub->funcs->init_watermarks) 913 dc->res_pool->hubbub->funcs->init_watermarks(dc->res_pool->hubbub); 914 915 if (dc->clk_mgr->funcs->notify_wm_ranges) 916 dc->clk_mgr->funcs->notify_wm_ranges(dc->clk_mgr); 917 918 if (dc->clk_mgr->funcs->set_hard_max_memclk && !dc->clk_mgr->dc_mode_softmax_enabled) 919 dc->clk_mgr->funcs->set_hard_max_memclk(dc->clk_mgr); 920 921 if (dc->res_pool->hubbub->funcs->force_pstate_change_control) 922 dc->res_pool->hubbub->funcs->force_pstate_change_control( 923 dc->res_pool->hubbub, false, false); 924 925 if (dc->res_pool->hubbub->funcs->init_crb) 926 dc->res_pool->hubbub->funcs->init_crb(dc->res_pool->hubbub); 927 928 if (dc->res_pool->hubbub->funcs->set_request_limit && dc->config.sdpif_request_limit_words_per_umc > 0) 929 dc->res_pool->hubbub->funcs->set_request_limit(dc->res_pool->hubbub, dc->ctx->dc_bios->vram_info.num_chans, dc->config.sdpif_request_limit_words_per_umc); 930 931 // Get DMCUB capabilities 932 if (dc->ctx->dmub_srv) { 933 dc_dmub_srv_query_caps_cmd(dc->ctx->dmub_srv->dmub); 934 dc->caps.dmub_caps.psr = dc->ctx->dmub_srv->dmub->feature_caps.psr; 935 } 936 } 937 938 static int calc_mpc_flow_ctrl_cnt(const struct dc_stream_state *stream, 939 int opp_cnt) 940 { 941 bool hblank_halved = optc2_is_two_pixels_per_containter(&stream->timing); 942 int flow_ctrl_cnt; 943 944 if (opp_cnt >= 2) 945 hblank_halved = true; 946 947 flow_ctrl_cnt = stream->timing.h_total - stream->timing.h_addressable - 948 stream->timing.h_border_left - 949 stream->timing.h_border_right; 950 951 if (hblank_halved) 952 flow_ctrl_cnt /= 2; 953 954 /* ODM combine 4:1 case */ 955 if (opp_cnt == 4) 956 flow_ctrl_cnt /= 2; 957 958 return flow_ctrl_cnt; 959 } 960 961 static void update_dsc_on_stream(struct pipe_ctx *pipe_ctx, bool enable) 962 { 963 struct display_stream_compressor *dsc = pipe_ctx->stream_res.dsc; 964 struct dc_stream_state *stream = pipe_ctx->stream; 965 struct pipe_ctx *odm_pipe; 966 int opp_cnt = 1; 967 968 ASSERT(dsc); 969 for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) 970 opp_cnt++; 971 972 if (enable) { 973 struct dsc_config dsc_cfg; 974 struct dsc_optc_config dsc_optc_cfg; 975 enum optc_dsc_mode optc_dsc_mode; 976 977 /* Enable DSC hw block */ 978 dsc_cfg.pic_width = (stream->timing.h_addressable + stream->timing.h_border_left + stream->timing.h_border_right) / opp_cnt; 979 dsc_cfg.pic_height = stream->timing.v_addressable + stream->timing.v_border_top + stream->timing.v_border_bottom; 980 dsc_cfg.pixel_encoding = stream->timing.pixel_encoding; 981 dsc_cfg.color_depth = stream->timing.display_color_depth; 982 dsc_cfg.is_odm = pipe_ctx->next_odm_pipe ? true : false; 983 dsc_cfg.dc_dsc_cfg = stream->timing.dsc_cfg; 984 ASSERT(dsc_cfg.dc_dsc_cfg.num_slices_h % opp_cnt == 0); 985 dsc_cfg.dc_dsc_cfg.num_slices_h /= opp_cnt; 986 987 dsc->funcs->dsc_set_config(dsc, &dsc_cfg, &dsc_optc_cfg); 988 dsc->funcs->dsc_enable(dsc, pipe_ctx->stream_res.opp->inst); 989 for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) { 990 struct display_stream_compressor *odm_dsc = odm_pipe->stream_res.dsc; 991 992 ASSERT(odm_dsc); 993 odm_dsc->funcs->dsc_set_config(odm_dsc, &dsc_cfg, &dsc_optc_cfg); 994 odm_dsc->funcs->dsc_enable(odm_dsc, odm_pipe->stream_res.opp->inst); 995 } 996 dsc_cfg.dc_dsc_cfg.num_slices_h *= opp_cnt; 997 dsc_cfg.pic_width *= opp_cnt; 998 999 optc_dsc_mode = dsc_optc_cfg.is_pixel_format_444 ? OPTC_DSC_ENABLED_444 : OPTC_DSC_ENABLED_NATIVE_SUBSAMPLED; 1000 1001 /* Enable DSC in OPTC */ 1002 DC_LOG_DSC("Setting optc DSC config for tg instance %d:", pipe_ctx->stream_res.tg->inst); 1003 pipe_ctx->stream_res.tg->funcs->set_dsc_config(pipe_ctx->stream_res.tg, 1004 optc_dsc_mode, 1005 dsc_optc_cfg.bytes_per_pixel, 1006 dsc_optc_cfg.slice_width); 1007 } else { 1008 /* disable DSC in OPTC */ 1009 pipe_ctx->stream_res.tg->funcs->set_dsc_config( 1010 pipe_ctx->stream_res.tg, 1011 OPTC_DSC_DISABLED, 0, 0); 1012 1013 /* disable DSC block */ 1014 dsc->funcs->dsc_disable(pipe_ctx->stream_res.dsc); 1015 for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) { 1016 ASSERT(odm_pipe->stream_res.dsc); 1017 odm_pipe->stream_res.dsc->funcs->dsc_disable(odm_pipe->stream_res.dsc); 1018 } 1019 } 1020 } 1021 1022 /* 1023 * Given any pipe_ctx, return the total ODM combine factor, and optionally return 1024 * the OPPids which are used 1025 * */ 1026 static unsigned int get_odm_config(struct pipe_ctx *pipe_ctx, unsigned int *opp_instances) 1027 { 1028 unsigned int opp_count = 1; 1029 struct pipe_ctx *odm_pipe; 1030 1031 /* First get to the top pipe */ 1032 for (odm_pipe = pipe_ctx; odm_pipe->prev_odm_pipe; odm_pipe = odm_pipe->prev_odm_pipe) 1033 ; 1034 1035 /* First pipe is always used */ 1036 if (opp_instances) 1037 opp_instances[0] = odm_pipe->stream_res.opp->inst; 1038 1039 /* Find and count odm pipes, if any */ 1040 for (odm_pipe = odm_pipe->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) { 1041 if (opp_instances) 1042 opp_instances[opp_count] = odm_pipe->stream_res.opp->inst; 1043 opp_count++; 1044 } 1045 1046 return opp_count; 1047 } 1048 1049 void dcn32_update_odm(struct dc *dc, struct dc_state *context, struct pipe_ctx *pipe_ctx) 1050 { 1051 struct pipe_ctx *odm_pipe; 1052 int opp_cnt = 0; 1053 int opp_inst[MAX_PIPES] = {0}; 1054 bool rate_control_2x_pclk = (pipe_ctx->stream->timing.flags.INTERLACE || optc2_is_two_pixels_per_containter(&pipe_ctx->stream->timing)); 1055 struct mpc_dwb_flow_control flow_control; 1056 struct mpc *mpc = dc->res_pool->mpc; 1057 int i; 1058 1059 opp_cnt = get_odm_config(pipe_ctx, opp_inst); 1060 1061 if (opp_cnt > 1) 1062 pipe_ctx->stream_res.tg->funcs->set_odm_combine( 1063 pipe_ctx->stream_res.tg, 1064 opp_inst, opp_cnt, 1065 &pipe_ctx->stream->timing); 1066 else 1067 pipe_ctx->stream_res.tg->funcs->set_odm_bypass( 1068 pipe_ctx->stream_res.tg, &pipe_ctx->stream->timing); 1069 1070 rate_control_2x_pclk = rate_control_2x_pclk || opp_cnt > 1; 1071 flow_control.flow_ctrl_mode = 0; 1072 flow_control.flow_ctrl_cnt0 = 0x80; 1073 flow_control.flow_ctrl_cnt1 = calc_mpc_flow_ctrl_cnt(pipe_ctx->stream, opp_cnt); 1074 if (mpc->funcs->set_out_rate_control) { 1075 for (i = 0; i < opp_cnt; ++i) { 1076 mpc->funcs->set_out_rate_control( 1077 mpc, opp_inst[i], 1078 true, 1079 rate_control_2x_pclk, 1080 &flow_control); 1081 } 1082 } 1083 1084 for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) { 1085 odm_pipe->stream_res.opp->funcs->opp_pipe_clock_control( 1086 odm_pipe->stream_res.opp, 1087 true); 1088 } 1089 1090 if (pipe_ctx->stream_res.dsc) { 1091 struct pipe_ctx *current_pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[pipe_ctx->pipe_idx]; 1092 1093 update_dsc_on_stream(pipe_ctx, pipe_ctx->stream->timing.flags.DSC); 1094 1095 /* Check if no longer using pipe for ODM, then need to disconnect DSC for that pipe */ 1096 if (!pipe_ctx->next_odm_pipe && current_pipe_ctx->next_odm_pipe && 1097 current_pipe_ctx->next_odm_pipe->stream_res.dsc) { 1098 struct display_stream_compressor *dsc = current_pipe_ctx->next_odm_pipe->stream_res.dsc; 1099 /* disconnect DSC block from stream */ 1100 dsc->funcs->dsc_disconnect(dsc); 1101 } 1102 } 1103 } 1104 1105 unsigned int dcn32_calculate_dccg_k1_k2_values(struct pipe_ctx *pipe_ctx, unsigned int *k1_div, unsigned int *k2_div) 1106 { 1107 struct dc_stream_state *stream = pipe_ctx->stream; 1108 unsigned int odm_combine_factor = 0; 1109 bool two_pix_per_container = false; 1110 1111 // For phantom pipes, use the same programming as the main pipes 1112 if (pipe_ctx->stream->mall_stream_config.type == SUBVP_PHANTOM) { 1113 stream = pipe_ctx->stream->mall_stream_config.paired_stream; 1114 } 1115 two_pix_per_container = optc2_is_two_pixels_per_containter(&stream->timing); 1116 odm_combine_factor = get_odm_config(pipe_ctx, NULL); 1117 1118 if (stream->ctx->dc->link_srv->dp_is_128b_132b_signal(pipe_ctx)) { 1119 *k1_div = PIXEL_RATE_DIV_BY_1; 1120 *k2_div = PIXEL_RATE_DIV_BY_1; 1121 } else if (dc_is_hdmi_tmds_signal(stream->signal) || dc_is_dvi_signal(stream->signal)) { 1122 *k1_div = PIXEL_RATE_DIV_BY_1; 1123 if (stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR420) 1124 *k2_div = PIXEL_RATE_DIV_BY_2; 1125 else 1126 *k2_div = PIXEL_RATE_DIV_BY_4; 1127 } else if (dc_is_dp_signal(stream->signal) || dc_is_virtual_signal(stream->signal)) { 1128 if (two_pix_per_container) { 1129 *k1_div = PIXEL_RATE_DIV_BY_1; 1130 *k2_div = PIXEL_RATE_DIV_BY_2; 1131 } else { 1132 *k1_div = PIXEL_RATE_DIV_BY_1; 1133 *k2_div = PIXEL_RATE_DIV_BY_4; 1134 if ((odm_combine_factor == 2) || dcn32_is_dp_dig_pixel_rate_div_policy(pipe_ctx)) 1135 *k2_div = PIXEL_RATE_DIV_BY_2; 1136 } 1137 } 1138 1139 if ((*k1_div == PIXEL_RATE_DIV_NA) && (*k2_div == PIXEL_RATE_DIV_NA)) 1140 ASSERT(false); 1141 1142 return odm_combine_factor; 1143 } 1144 1145 void dcn32_set_pixels_per_cycle(struct pipe_ctx *pipe_ctx) 1146 { 1147 uint32_t pix_per_cycle = 1; 1148 uint32_t odm_combine_factor = 1; 1149 1150 if (!pipe_ctx || !pipe_ctx->stream || !pipe_ctx->stream_res.stream_enc) 1151 return; 1152 1153 odm_combine_factor = get_odm_config(pipe_ctx, NULL); 1154 if (optc2_is_two_pixels_per_containter(&pipe_ctx->stream->timing) || odm_combine_factor > 1 1155 || dcn32_is_dp_dig_pixel_rate_div_policy(pipe_ctx)) 1156 pix_per_cycle = 2; 1157 1158 if (pipe_ctx->stream_res.stream_enc->funcs->set_input_mode) 1159 pipe_ctx->stream_res.stream_enc->funcs->set_input_mode(pipe_ctx->stream_res.stream_enc, 1160 pix_per_cycle); 1161 } 1162 1163 void dcn32_unblank_stream(struct pipe_ctx *pipe_ctx, 1164 struct dc_link_settings *link_settings) 1165 { 1166 struct encoder_unblank_param params = {0}; 1167 struct dc_stream_state *stream = pipe_ctx->stream; 1168 struct dc_link *link = stream->link; 1169 struct dce_hwseq *hws = link->dc->hwseq; 1170 struct pipe_ctx *odm_pipe; 1171 uint32_t pix_per_cycle = 1; 1172 1173 params.opp_cnt = 1; 1174 for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) 1175 params.opp_cnt++; 1176 1177 /* only 3 items below are used by unblank */ 1178 params.timing = pipe_ctx->stream->timing; 1179 1180 params.link_settings.link_rate = link_settings->link_rate; 1181 1182 if (link->dc->link_srv->dp_is_128b_132b_signal(pipe_ctx)) { 1183 /* TODO - DP2.0 HW: Set ODM mode in dp hpo encoder here */ 1184 pipe_ctx->stream_res.hpo_dp_stream_enc->funcs->dp_unblank( 1185 pipe_ctx->stream_res.hpo_dp_stream_enc, 1186 pipe_ctx->stream_res.tg->inst); 1187 } else if (dc_is_dp_signal(pipe_ctx->stream->signal)) { 1188 if (optc2_is_two_pixels_per_containter(&stream->timing) || params.opp_cnt > 1 1189 || dcn32_is_dp_dig_pixel_rate_div_policy(pipe_ctx)) { 1190 params.timing.pix_clk_100hz /= 2; 1191 pix_per_cycle = 2; 1192 } 1193 pipe_ctx->stream_res.stream_enc->funcs->dp_set_odm_combine( 1194 pipe_ctx->stream_res.stream_enc, pix_per_cycle > 1); 1195 pipe_ctx->stream_res.stream_enc->funcs->dp_unblank(link, pipe_ctx->stream_res.stream_enc, ¶ms); 1196 } 1197 1198 if (link->local_sink && link->local_sink->sink_signal == SIGNAL_TYPE_EDP) 1199 hws->funcs.edp_backlight_control(link, true); 1200 } 1201 1202 bool dcn32_is_dp_dig_pixel_rate_div_policy(struct pipe_ctx *pipe_ctx) 1203 { 1204 struct dc *dc = pipe_ctx->stream->ctx->dc; 1205 1206 if (!is_h_timing_divisible_by_2(pipe_ctx->stream)) 1207 return false; 1208 1209 if (dc_is_dp_signal(pipe_ctx->stream->signal) && !dc->link_srv->dp_is_128b_132b_signal(pipe_ctx) && 1210 dc->debug.enable_dp_dig_pixel_rate_div_policy) 1211 return true; 1212 return false; 1213 } 1214 1215 static void apply_symclk_on_tx_off_wa(struct dc_link *link) 1216 { 1217 /* There are use cases where SYMCLK is referenced by OTG. For instance 1218 * for TMDS signal, OTG relies SYMCLK even if TX video output is off. 1219 * However current link interface will power off PHY when disabling link 1220 * output. This will turn off SYMCLK generated by PHY. The workaround is 1221 * to identify such case where SYMCLK is still in use by OTG when we 1222 * power off PHY. When this is detected, we will temporarily power PHY 1223 * back on and move PHY's SYMCLK state to SYMCLK_ON_TX_OFF by calling 1224 * program_pix_clk interface. When OTG is disabled, we will then power 1225 * off PHY by calling disable link output again. 1226 * 1227 * In future dcn generations, we plan to rework transmitter control 1228 * interface so that we could have an option to set SYMCLK ON TX OFF 1229 * state in one step without this workaround 1230 */ 1231 1232 struct dc *dc = link->ctx->dc; 1233 struct pipe_ctx *pipe_ctx = NULL; 1234 uint8_t i; 1235 1236 if (link->phy_state.symclk_ref_cnts.otg > 0) { 1237 for (i = 0; i < MAX_PIPES; i++) { 1238 pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[i]; 1239 if (pipe_ctx->stream && pipe_ctx->stream->link == link && pipe_ctx->top_pipe == NULL) { 1240 pipe_ctx->clock_source->funcs->program_pix_clk( 1241 pipe_ctx->clock_source, 1242 &pipe_ctx->stream_res.pix_clk_params, 1243 dc->link_srv->dp_get_encoding_format( 1244 &pipe_ctx->link_config.dp_link_settings), 1245 &pipe_ctx->pll_settings); 1246 link->phy_state.symclk_state = SYMCLK_ON_TX_OFF; 1247 break; 1248 } 1249 } 1250 } 1251 } 1252 1253 void dcn32_disable_link_output(struct dc_link *link, 1254 const struct link_resource *link_res, 1255 enum signal_type signal) 1256 { 1257 struct dc *dc = link->ctx->dc; 1258 const struct link_hwss *link_hwss = get_link_hwss(link, link_res); 1259 struct dmcu *dmcu = dc->res_pool->dmcu; 1260 1261 if (signal == SIGNAL_TYPE_EDP && 1262 link->dc->hwss.edp_backlight_control) 1263 link->dc->hwss.edp_backlight_control(link, false); 1264 else if (dmcu != NULL && dmcu->funcs->lock_phy) 1265 dmcu->funcs->lock_phy(dmcu); 1266 1267 link_hwss->disable_link_output(link, link_res, signal); 1268 link->phy_state.symclk_state = SYMCLK_OFF_TX_OFF; 1269 1270 if (signal == SIGNAL_TYPE_EDP && 1271 link->dc->hwss.edp_backlight_control) 1272 link->dc->hwss.edp_power_control(link, false); 1273 else if (dmcu != NULL && dmcu->funcs->lock_phy) 1274 dmcu->funcs->unlock_phy(dmcu); 1275 1276 dc->link_srv->dp_trace_source_sequence(link, DPCD_SOURCE_SEQ_AFTER_DISABLE_LINK_PHY); 1277 1278 apply_symclk_on_tx_off_wa(link); 1279 } 1280 1281 /* For SubVP the main pipe can have a viewport position change 1282 * without a full update. In this case we must also update the 1283 * viewport positions for the phantom pipe accordingly. 1284 */ 1285 void dcn32_update_phantom_vp_position(struct dc *dc, 1286 struct dc_state *context, 1287 struct pipe_ctx *phantom_pipe) 1288 { 1289 uint32_t i; 1290 struct dc_plane_state *phantom_plane = phantom_pipe->plane_state; 1291 1292 for (i = 0; i < dc->res_pool->pipe_count; i++) { 1293 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; 1294 1295 if (pipe->stream && pipe->stream->mall_stream_config.type == SUBVP_MAIN && 1296 pipe->stream->mall_stream_config.paired_stream == phantom_pipe->stream) { 1297 if (pipe->plane_state && pipe->plane_state->update_flags.bits.position_change) { 1298 1299 phantom_plane->src_rect.x = pipe->plane_state->src_rect.x; 1300 phantom_plane->src_rect.y = pipe->plane_state->src_rect.y; 1301 phantom_plane->clip_rect.x = pipe->plane_state->clip_rect.x; 1302 phantom_plane->dst_rect.x = pipe->plane_state->dst_rect.x; 1303 phantom_plane->dst_rect.y = pipe->plane_state->dst_rect.y; 1304 1305 phantom_pipe->plane_state->update_flags.bits.position_change = 1; 1306 resource_build_scaling_params(phantom_pipe); 1307 return; 1308 } 1309 } 1310 } 1311 } 1312 1313 /* Treat the phantom pipe as if it needs to be fully enabled. 1314 * If the pipe was previously in use but not phantom, it would 1315 * have been disabled earlier in the sequence so we need to run 1316 * the full enable sequence. 1317 */ 1318 void dcn32_apply_update_flags_for_phantom(struct pipe_ctx *phantom_pipe) 1319 { 1320 phantom_pipe->update_flags.raw = 0; 1321 if (phantom_pipe->stream && phantom_pipe->stream->mall_stream_config.type == SUBVP_PHANTOM) { 1322 if (phantom_pipe->stream && phantom_pipe->plane_state) { 1323 phantom_pipe->update_flags.bits.enable = 1; 1324 phantom_pipe->update_flags.bits.mpcc = 1; 1325 phantom_pipe->update_flags.bits.dppclk = 1; 1326 phantom_pipe->update_flags.bits.hubp_interdependent = 1; 1327 phantom_pipe->update_flags.bits.hubp_rq_dlg_ttu = 1; 1328 phantom_pipe->update_flags.bits.gamut_remap = 1; 1329 phantom_pipe->update_flags.bits.scaler = 1; 1330 phantom_pipe->update_flags.bits.viewport = 1; 1331 phantom_pipe->update_flags.bits.det_size = 1; 1332 if (!phantom_pipe->top_pipe && !phantom_pipe->prev_odm_pipe) { 1333 phantom_pipe->update_flags.bits.odm = 1; 1334 phantom_pipe->update_flags.bits.global_sync = 1; 1335 } 1336 } 1337 } 1338 } 1339 1340 bool dcn32_dsc_pg_status( 1341 struct dce_hwseq *hws, 1342 unsigned int dsc_inst) 1343 { 1344 uint32_t pwr_status = 0; 1345 1346 switch (dsc_inst) { 1347 case 0: /* DSC0 */ 1348 REG_GET(DOMAIN16_PG_STATUS, 1349 DOMAIN_PGFSM_PWR_STATUS, &pwr_status); 1350 break; 1351 case 1: /* DSC1 */ 1352 1353 REG_GET(DOMAIN17_PG_STATUS, 1354 DOMAIN_PGFSM_PWR_STATUS, &pwr_status); 1355 break; 1356 case 2: /* DSC2 */ 1357 REG_GET(DOMAIN18_PG_STATUS, 1358 DOMAIN_PGFSM_PWR_STATUS, &pwr_status); 1359 break; 1360 case 3: /* DSC3 */ 1361 REG_GET(DOMAIN19_PG_STATUS, 1362 DOMAIN_PGFSM_PWR_STATUS, &pwr_status); 1363 break; 1364 default: 1365 BREAK_TO_DEBUGGER(); 1366 break; 1367 } 1368 1369 return pwr_status == 0; 1370 } 1371 1372 void dcn32_update_dsc_pg(struct dc *dc, 1373 struct dc_state *context, 1374 bool safe_to_disable) 1375 { 1376 struct dce_hwseq *hws = dc->hwseq; 1377 int i; 1378 1379 for (i = 0; i < dc->res_pool->res_cap->num_dsc; i++) { 1380 struct display_stream_compressor *dsc = dc->res_pool->dscs[i]; 1381 bool is_dsc_ungated = hws->funcs.dsc_pg_status(hws, dsc->inst); 1382 1383 if (context->res_ctx.is_dsc_acquired[i]) { 1384 if (!is_dsc_ungated) { 1385 hws->funcs.dsc_pg_control(hws, dsc->inst, true); 1386 } 1387 } else if (safe_to_disable) { 1388 if (is_dsc_ungated) { 1389 hws->funcs.dsc_pg_control(hws, dsc->inst, false); 1390 } 1391 } 1392 } 1393 } 1394 1395 void dcn32_enable_phantom_streams(struct dc *dc, struct dc_state *context) 1396 { 1397 unsigned int i; 1398 1399 for (i = 0; i < dc->res_pool->pipe_count; i++) { 1400 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; 1401 struct pipe_ctx *old_pipe = &dc->current_state->res_ctx.pipe_ctx[i]; 1402 1403 /* If an active, non-phantom pipe is being transitioned into a phantom 1404 * pipe, wait for the double buffer update to complete first before we do 1405 * ANY phantom pipe programming. 1406 */ 1407 if (pipe->stream && pipe->stream->mall_stream_config.type == SUBVP_PHANTOM && 1408 old_pipe->stream && old_pipe->stream->mall_stream_config.type != SUBVP_PHANTOM) { 1409 old_pipe->stream_res.tg->funcs->wait_for_state( 1410 old_pipe->stream_res.tg, 1411 CRTC_STATE_VBLANK); 1412 old_pipe->stream_res.tg->funcs->wait_for_state( 1413 old_pipe->stream_res.tg, 1414 CRTC_STATE_VACTIVE); 1415 } 1416 } 1417 for (i = 0; i < dc->res_pool->pipe_count; i++) { 1418 struct pipe_ctx *new_pipe = &context->res_ctx.pipe_ctx[i]; 1419 1420 if (new_pipe->stream && new_pipe->stream->mall_stream_config.type == SUBVP_PHANTOM) { 1421 // If old context or new context has phantom pipes, apply 1422 // the phantom timings now. We can't change the phantom 1423 // pipe configuration safely without driver acquiring 1424 // the DMCUB lock first. 1425 dc->hwss.apply_ctx_to_hw(dc, context); 1426 break; 1427 } 1428 } 1429 } 1430 1431 /* Blank pixel data during initialization */ 1432 void dcn32_init_blank( 1433 struct dc *dc, 1434 struct timing_generator *tg) 1435 { 1436 struct dce_hwseq *hws = dc->hwseq; 1437 enum dc_color_space color_space; 1438 struct tg_color black_color = {0}; 1439 struct output_pixel_processor *opp = NULL; 1440 struct output_pixel_processor *bottom_opp = NULL; 1441 uint32_t num_opps, opp_id_src0, opp_id_src1; 1442 uint32_t otg_active_width, otg_active_height; 1443 uint32_t i; 1444 1445 /* program opp dpg blank color */ 1446 color_space = COLOR_SPACE_SRGB; 1447 color_space_to_black_color(dc, color_space, &black_color); 1448 1449 /* get the OTG active size */ 1450 tg->funcs->get_otg_active_size(tg, 1451 &otg_active_width, 1452 &otg_active_height); 1453 1454 /* get the OPTC source */ 1455 tg->funcs->get_optc_source(tg, &num_opps, &opp_id_src0, &opp_id_src1); 1456 1457 if (opp_id_src0 >= dc->res_pool->res_cap->num_opp) { 1458 ASSERT(false); 1459 return; 1460 } 1461 1462 for (i = 0; i < dc->res_pool->res_cap->num_opp; i++) { 1463 if (dc->res_pool->opps[i] != NULL && dc->res_pool->opps[i]->inst == opp_id_src0) { 1464 opp = dc->res_pool->opps[i]; 1465 break; 1466 } 1467 } 1468 1469 if (num_opps == 2) { 1470 otg_active_width = otg_active_width / 2; 1471 1472 if (opp_id_src1 >= dc->res_pool->res_cap->num_opp) { 1473 ASSERT(false); 1474 return; 1475 } 1476 for (i = 0; i < dc->res_pool->res_cap->num_opp; i++) { 1477 if (dc->res_pool->opps[i] != NULL && dc->res_pool->opps[i]->inst == opp_id_src1) { 1478 bottom_opp = dc->res_pool->opps[i]; 1479 break; 1480 } 1481 } 1482 } 1483 1484 if (opp && opp->funcs->opp_set_disp_pattern_generator) 1485 opp->funcs->opp_set_disp_pattern_generator( 1486 opp, 1487 CONTROLLER_DP_TEST_PATTERN_SOLID_COLOR, 1488 CONTROLLER_DP_COLOR_SPACE_UDEFINED, 1489 COLOR_DEPTH_UNDEFINED, 1490 &black_color, 1491 otg_active_width, 1492 otg_active_height, 1493 0); 1494 1495 if (num_opps == 2) { 1496 if (bottom_opp && bottom_opp->funcs->opp_set_disp_pattern_generator) { 1497 bottom_opp->funcs->opp_set_disp_pattern_generator( 1498 bottom_opp, 1499 CONTROLLER_DP_TEST_PATTERN_SOLID_COLOR, 1500 CONTROLLER_DP_COLOR_SPACE_UDEFINED, 1501 COLOR_DEPTH_UNDEFINED, 1502 &black_color, 1503 otg_active_width, 1504 otg_active_height, 1505 0); 1506 hws->funcs.wait_for_blank_complete(bottom_opp); 1507 } 1508 } 1509 1510 if (opp) 1511 hws->funcs.wait_for_blank_complete(opp); 1512 } 1513