1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 27 #include "dm_services.h" 28 #include "dm_helpers.h" 29 #include "core_types.h" 30 #include "resource.h" 31 #include "dccg.h" 32 #include "dce/dce_hwseq.h" 33 #include "dcn30/dcn30_cm_common.h" 34 #include "reg_helper.h" 35 #include "abm.h" 36 #include "hubp.h" 37 #include "dchubbub.h" 38 #include "timing_generator.h" 39 #include "opp.h" 40 #include "ipp.h" 41 #include "mpc.h" 42 #include "mcif_wb.h" 43 #include "dc_dmub_srv.h" 44 #include "link_hwss.h" 45 #include "dpcd_defs.h" 46 #include "dcn32_hwseq.h" 47 #include "clk_mgr.h" 48 #include "dsc.h" 49 #include "dcn20/dcn20_optc.h" 50 #include "dmub_subvp_state.h" 51 #include "dce/dmub_hw_lock_mgr.h" 52 #include "dcn32_resource.h" 53 #include "dc_link_dp.h" 54 #include "dmub/inc/dmub_subvp_state.h" 55 56 #define DC_LOGGER_INIT(logger) 57 58 #define CTX \ 59 hws->ctx 60 #define REG(reg)\ 61 hws->regs->reg 62 #define DC_LOGGER \ 63 dc->ctx->logger 64 65 66 #undef FN 67 #define FN(reg_name, field_name) \ 68 hws->shifts->field_name, hws->masks->field_name 69 70 void dcn32_dsc_pg_control( 71 struct dce_hwseq *hws, 72 unsigned int dsc_inst, 73 bool power_on) 74 { 75 uint32_t power_gate = power_on ? 0 : 1; 76 uint32_t pwr_status = power_on ? 0 : 2; 77 uint32_t org_ip_request_cntl = 0; 78 79 if (hws->ctx->dc->debug.disable_dsc_power_gate) 80 return; 81 82 REG_GET(DC_IP_REQUEST_CNTL, IP_REQUEST_EN, &org_ip_request_cntl); 83 if (org_ip_request_cntl == 0) 84 REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 1); 85 86 switch (dsc_inst) { 87 case 0: /* DSC0 */ 88 REG_UPDATE(DOMAIN16_PG_CONFIG, 89 DOMAIN_POWER_GATE, power_gate); 90 91 REG_WAIT(DOMAIN16_PG_STATUS, 92 DOMAIN_PGFSM_PWR_STATUS, pwr_status, 93 1, 1000); 94 break; 95 case 1: /* DSC1 */ 96 REG_UPDATE(DOMAIN17_PG_CONFIG, 97 DOMAIN_POWER_GATE, power_gate); 98 99 REG_WAIT(DOMAIN17_PG_STATUS, 100 DOMAIN_PGFSM_PWR_STATUS, pwr_status, 101 1, 1000); 102 break; 103 case 2: /* DSC2 */ 104 REG_UPDATE(DOMAIN18_PG_CONFIG, 105 DOMAIN_POWER_GATE, power_gate); 106 107 REG_WAIT(DOMAIN18_PG_STATUS, 108 DOMAIN_PGFSM_PWR_STATUS, pwr_status, 109 1, 1000); 110 break; 111 case 3: /* DSC3 */ 112 REG_UPDATE(DOMAIN19_PG_CONFIG, 113 DOMAIN_POWER_GATE, power_gate); 114 115 REG_WAIT(DOMAIN19_PG_STATUS, 116 DOMAIN_PGFSM_PWR_STATUS, pwr_status, 117 1, 1000); 118 break; 119 default: 120 BREAK_TO_DEBUGGER(); 121 break; 122 } 123 124 if (org_ip_request_cntl == 0) 125 REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 0); 126 } 127 128 129 void dcn32_enable_power_gating_plane( 130 struct dce_hwseq *hws, 131 bool enable) 132 { 133 bool force_on = true; /* disable power gating */ 134 135 if (enable) 136 force_on = false; 137 138 /* DCHUBP0/1/2/3 */ 139 REG_UPDATE(DOMAIN0_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on); 140 REG_UPDATE(DOMAIN1_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on); 141 REG_UPDATE(DOMAIN2_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on); 142 REG_UPDATE(DOMAIN3_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on); 143 144 /* DCS0/1/2/3 */ 145 REG_UPDATE(DOMAIN16_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on); 146 REG_UPDATE(DOMAIN17_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on); 147 REG_UPDATE(DOMAIN18_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on); 148 REG_UPDATE(DOMAIN19_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on); 149 } 150 151 void dcn32_hubp_pg_control(struct dce_hwseq *hws, unsigned int hubp_inst, bool power_on) 152 { 153 uint32_t power_gate = power_on ? 0 : 1; 154 uint32_t pwr_status = power_on ? 0 : 2; 155 156 if (hws->ctx->dc->debug.disable_hubp_power_gate) 157 return; 158 159 if (REG(DOMAIN0_PG_CONFIG) == 0) 160 return; 161 162 switch (hubp_inst) { 163 case 0: 164 REG_SET(DOMAIN0_PG_CONFIG, 0, DOMAIN_POWER_GATE, power_gate); 165 REG_WAIT(DOMAIN0_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, pwr_status, 1, 1000); 166 break; 167 case 1: 168 REG_SET(DOMAIN1_PG_CONFIG, 0, DOMAIN_POWER_GATE, power_gate); 169 REG_WAIT(DOMAIN1_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, pwr_status, 1, 1000); 170 break; 171 case 2: 172 REG_SET(DOMAIN2_PG_CONFIG, 0, DOMAIN_POWER_GATE, power_gate); 173 REG_WAIT(DOMAIN2_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, pwr_status, 1, 1000); 174 break; 175 case 3: 176 REG_SET(DOMAIN3_PG_CONFIG, 0, DOMAIN_POWER_GATE, power_gate); 177 REG_WAIT(DOMAIN3_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, pwr_status, 1, 1000); 178 break; 179 default: 180 BREAK_TO_DEBUGGER(); 181 break; 182 } 183 } 184 185 static bool dcn32_check_no_memory_request_for_cab(struct dc *dc) 186 { 187 int i; 188 189 /* First, check no-memory-request case */ 190 for (i = 0; i < dc->current_state->stream_count; i++) { 191 if (dc->current_state->stream_status[i].plane_count) 192 /* Fail eligibility on a visible stream */ 193 break; 194 } 195 196 if (i == dc->current_state->stream_count) 197 return true; 198 199 return false; 200 } 201 202 203 /* This function loops through every surface that needs to be cached in CAB for SS, 204 * and calculates the total number of ways required to store all surfaces (primary, 205 * meta, cursor). 206 */ 207 static uint32_t dcn32_calculate_cab_allocation(struct dc *dc, struct dc_state *ctx) 208 { 209 int i, j; 210 struct dc_stream_state *stream = NULL; 211 struct dc_plane_state *plane = NULL; 212 uint32_t cursor_size = 0; 213 uint32_t total_lines = 0; 214 uint32_t lines_per_way = 0; 215 uint8_t num_ways = 0; 216 uint8_t bytes_per_pixel = 0; 217 uint8_t cursor_bpp = 0; 218 uint16_t mblk_width = 0; 219 uint16_t mblk_height = 0; 220 uint16_t mall_alloc_width_blk_aligned = 0; 221 uint16_t mall_alloc_height_blk_aligned = 0; 222 uint16_t num_mblks = 0; 223 uint32_t bytes_in_mall = 0; 224 uint32_t cache_lines_used = 0; 225 uint32_t cache_lines_per_plane = 0; 226 227 for (i = 0; i < dc->res_pool->pipe_count; i++) { 228 struct pipe_ctx *pipe = &dc->current_state->res_ctx.pipe_ctx[i]; 229 230 if (!pipe->stream || !pipe->plane_state || 231 pipe->stream->link->psr_settings.psr_version != DC_PSR_VERSION_UNSUPPORTED || 232 pipe->stream->mall_stream_config.type == SUBVP_PHANTOM) 233 continue; 234 235 bytes_per_pixel = pipe->plane_state->format >= SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616 ? 8 : 4; 236 mblk_width = DCN3_2_MBLK_WIDTH; 237 mblk_height = bytes_per_pixel == 4 ? DCN3_2_MBLK_HEIGHT_4BPE : DCN3_2_MBLK_HEIGHT_8BPE; 238 239 /* full_vp_width_blk_aligned = FLOOR(vp_x_start + full_vp_width + blk_width - 1, blk_width) - 240 * FLOOR(vp_x_start, blk_width) 241 * 242 * mall_alloc_width_blk_aligned_l/c = full_vp_width_blk_aligned_l/c 243 */ 244 mall_alloc_width_blk_aligned = ((pipe->plane_res.scl_data.viewport.x + 245 pipe->plane_res.scl_data.viewport.width + mblk_width - 1) / mblk_width * mblk_width) - 246 (pipe->plane_res.scl_data.viewport.x / mblk_width * mblk_width); 247 248 /* full_vp_height_blk_aligned = FLOOR(vp_y_start + full_vp_height + blk_height - 1, blk_height) - 249 * FLOOR(vp_y_start, blk_height) 250 * 251 * mall_alloc_height_blk_aligned_l/c = full_vp_height_blk_aligned_l/c 252 */ 253 mall_alloc_height_blk_aligned = ((pipe->plane_res.scl_data.viewport.y + 254 pipe->plane_res.scl_data.viewport.height + mblk_height - 1) / mblk_height * mblk_height) - 255 (pipe->plane_res.scl_data.viewport.y / mblk_height * mblk_height); 256 257 num_mblks = ((mall_alloc_width_blk_aligned + mblk_width - 1) / mblk_width) * 258 ((mall_alloc_height_blk_aligned + mblk_height - 1) / mblk_height); 259 260 /* For DCC: 261 * meta_num_mblk = CEILING(full_mblk_width_ub_l*full_mblk_height_ub_l*Bpe/256/mblk_bytes, 1) 262 */ 263 if (pipe->plane_state->dcc.enable) 264 num_mblks += (mall_alloc_width_blk_aligned * mall_alloc_width_blk_aligned * bytes_per_pixel + 265 (256 * DCN3_2_MALL_MBLK_SIZE_BYTES) - 1) / (256 * DCN3_2_MALL_MBLK_SIZE_BYTES); 266 267 bytes_in_mall = num_mblks * DCN3_2_MALL_MBLK_SIZE_BYTES; 268 269 /* (cache lines used is total bytes / cache_line size. Add +2 for worst case alignment 270 * (MALL is 64-byte aligned) 271 */ 272 cache_lines_per_plane = bytes_in_mall / dc->caps.cache_line_size + 2; 273 cache_lines_used += cache_lines_per_plane; 274 } 275 276 // Include cursor size for CAB allocation 277 for (j = 0; j < dc->res_pool->pipe_count; j++) { 278 struct pipe_ctx *pipe = &ctx->res_ctx.pipe_ctx[j]; 279 struct hubp *hubp = pipe->plane_res.hubp; 280 281 if (pipe->stream && pipe->plane_state && hubp) 282 /* Find the cursor plane and use the exact size instead of 283 using the max for calculation */ 284 285 if (hubp->curs_attr.width > 0) { 286 // Round cursor width to next multiple of 64 287 cursor_size = (((hubp->curs_attr.width + 63) / 64) * 64) * hubp->curs_attr.height; 288 289 switch (pipe->stream->cursor_attributes.color_format) { 290 case CURSOR_MODE_MONO: 291 cursor_size /= 2; 292 cursor_bpp = 4; 293 break; 294 case CURSOR_MODE_COLOR_1BIT_AND: 295 case CURSOR_MODE_COLOR_PRE_MULTIPLIED_ALPHA: 296 case CURSOR_MODE_COLOR_UN_PRE_MULTIPLIED_ALPHA: 297 cursor_size *= 4; 298 cursor_bpp = 4; 299 break; 300 301 case CURSOR_MODE_COLOR_64BIT_FP_PRE_MULTIPLIED: 302 case CURSOR_MODE_COLOR_64BIT_FP_UN_PRE_MULTIPLIED: 303 cursor_size *= 8; 304 cursor_bpp = 8; 305 break; 306 } 307 308 if (pipe->stream->cursor_position.enable && !dc->debug.alloc_extra_way_for_cursor && 309 cursor_size > 16384) { 310 /* cursor_num_mblk = CEILING(num_cursors*cursor_width*cursor_width*cursor_Bpe/mblk_bytes, 1) 311 */ 312 cache_lines_used += (((hubp->curs_attr.width * hubp->curs_attr.height * cursor_bpp + 313 DCN3_2_MALL_MBLK_SIZE_BYTES - 1) / DCN3_2_MALL_MBLK_SIZE_BYTES) * 314 DCN3_2_MALL_MBLK_SIZE_BYTES) / dc->caps.cache_line_size + 2; 315 } 316 break; 317 } 318 } 319 320 // Convert number of cache lines required to number of ways 321 total_lines = dc->caps.max_cab_allocation_bytes / dc->caps.cache_line_size; 322 lines_per_way = total_lines / dc->caps.cache_num_ways; 323 num_ways = cache_lines_used / lines_per_way; 324 325 if (cache_lines_used % lines_per_way > 0) 326 num_ways++; 327 328 for (i = 0; i < ctx->stream_count; i++) { 329 stream = ctx->streams[i]; 330 for (j = 0; j < ctx->stream_status[i].plane_count; j++) { 331 plane = ctx->stream_status[i].plane_states[j]; 332 333 if (stream->cursor_position.enable && plane && 334 dc->debug.alloc_extra_way_for_cursor && 335 cursor_size > 16384) { 336 /* Cursor caching is not supported since it won't be on the same line. 337 * So we need an extra line to accommodate it. With large cursors and a single 4k monitor 338 * this case triggers corruption. If we're at the edge, then dont trigger display refresh 339 * from MALL. We only need to cache cursor if its greater that 64x64 at 4 bpp. 340 */ 341 num_ways++; 342 /* We only expect one cursor plane */ 343 break; 344 } 345 } 346 } 347 if (dc->debug.force_mall_ss_num_ways > 0) { 348 num_ways = dc->debug.force_mall_ss_num_ways; 349 } 350 return num_ways; 351 } 352 353 bool dcn32_apply_idle_power_optimizations(struct dc *dc, bool enable) 354 { 355 union dmub_rb_cmd cmd; 356 uint8_t ways, i; 357 int j; 358 bool mall_ss_unsupported = false; 359 struct dc_plane_state *plane = NULL; 360 361 if (!dc->ctx->dmub_srv) 362 return false; 363 364 if (enable) { 365 if (dc->current_state) { 366 367 /* 1. Check no memory request case for CAB. 368 * If no memory request case, send CAB_ACTION NO_DF_REQ DMUB message 369 */ 370 if (dcn32_check_no_memory_request_for_cab(dc)) { 371 /* Enable no-memory-requests case */ 372 memset(&cmd, 0, sizeof(cmd)); 373 cmd.cab.header.type = DMUB_CMD__CAB_FOR_SS; 374 cmd.cab.header.sub_type = DMUB_CMD__CAB_NO_DCN_REQ; 375 cmd.cab.header.payload_bytes = sizeof(cmd.cab) - sizeof(cmd.cab.header); 376 377 dc_dmub_srv_cmd_queue(dc->ctx->dmub_srv, &cmd); 378 dc_dmub_srv_cmd_execute(dc->ctx->dmub_srv); 379 380 return true; 381 } 382 383 /* 2. Check if all surfaces can fit in CAB. 384 * If surfaces can fit into CAB, send CAB_ACTION_ALLOW DMUB message 385 * and configure HUBP's to fetch from MALL 386 */ 387 ways = dcn32_calculate_cab_allocation(dc, dc->current_state); 388 389 /* MALL not supported with Stereo3D or TMZ surface. If any plane is using stereo, 390 * or TMZ surface, don't try to enter MALL. 391 */ 392 for (i = 0; i < dc->current_state->stream_count; i++) { 393 for (j = 0; j < dc->current_state->stream_status[i].plane_count; j++) { 394 plane = dc->current_state->stream_status[i].plane_states[j]; 395 396 if (plane->address.type == PLN_ADDR_TYPE_GRPH_STEREO || 397 plane->address.tmz_surface) { 398 mall_ss_unsupported = true; 399 break; 400 } 401 } 402 if (mall_ss_unsupported) 403 break; 404 } 405 if (ways <= dc->caps.cache_num_ways && !mall_ss_unsupported) { 406 memset(&cmd, 0, sizeof(cmd)); 407 cmd.cab.header.type = DMUB_CMD__CAB_FOR_SS; 408 cmd.cab.header.sub_type = DMUB_CMD__CAB_DCN_SS_FIT_IN_CAB; 409 cmd.cab.header.payload_bytes = sizeof(cmd.cab) - sizeof(cmd.cab.header); 410 cmd.cab.cab_alloc_ways = ways; 411 412 dc_dmub_srv_cmd_queue(dc->ctx->dmub_srv, &cmd); 413 dc_dmub_srv_cmd_execute(dc->ctx->dmub_srv); 414 415 return true; 416 } 417 418 } 419 return false; 420 } 421 422 /* Disable CAB */ 423 memset(&cmd, 0, sizeof(cmd)); 424 cmd.cab.header.type = DMUB_CMD__CAB_FOR_SS; 425 cmd.cab.header.sub_type = DMUB_CMD__CAB_NO_IDLE_OPTIMIZATION; 426 cmd.cab.header.payload_bytes = 427 sizeof(cmd.cab) - sizeof(cmd.cab.header); 428 429 dc_dmub_srv_cmd_queue(dc->ctx->dmub_srv, &cmd); 430 dc_dmub_srv_cmd_execute(dc->ctx->dmub_srv); 431 dc_dmub_srv_wait_idle(dc->ctx->dmub_srv); 432 433 return true; 434 } 435 436 /* Send DMCUB message with SubVP pipe info 437 * - For each pipe in context, populate payload with required SubVP information 438 * if the pipe is using SubVP for MCLK switch 439 * - This function must be called while the DMUB HW lock is acquired by driver 440 */ 441 void dcn32_commit_subvp_config(struct dc *dc, struct dc_state *context) 442 { 443 int i; 444 bool enable_subvp = false; 445 446 if (!dc->ctx || !dc->ctx->dmub_srv) 447 return; 448 449 for (i = 0; i < dc->res_pool->pipe_count; i++) { 450 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; 451 452 if (pipe_ctx->stream && pipe_ctx->stream->mall_stream_config.paired_stream && 453 pipe_ctx->stream->mall_stream_config.type == SUBVP_MAIN) { 454 // There is at least 1 SubVP pipe, so enable SubVP 455 enable_subvp = true; 456 break; 457 } 458 } 459 dc_dmub_setup_subvp_dmub_command(dc, context, enable_subvp); 460 } 461 462 /* Sub-Viewport DMUB lock needs to be acquired by driver whenever SubVP is active and: 463 * 1. Any full update for any SubVP main pipe 464 * 2. Any immediate flip for any SubVP pipe 465 * 3. Any flip for DRR pipe 466 * 4. If SubVP was previously in use (i.e. in old context) 467 */ 468 void dcn32_subvp_pipe_control_lock(struct dc *dc, 469 struct dc_state *context, 470 bool lock, 471 bool should_lock_all_pipes, 472 struct pipe_ctx *top_pipe_to_program, 473 bool subvp_prev_use) 474 { 475 unsigned int i = 0; 476 bool subvp_immediate_flip = false; 477 bool subvp_in_use = false; 478 struct pipe_ctx *pipe; 479 480 for (i = 0; i < dc->res_pool->pipe_count; i++) { 481 pipe = &context->res_ctx.pipe_ctx[i]; 482 483 if (pipe->stream && pipe->plane_state && pipe->stream->mall_stream_config.type == SUBVP_MAIN) { 484 subvp_in_use = true; 485 break; 486 } 487 } 488 489 if (top_pipe_to_program && top_pipe_to_program->stream && top_pipe_to_program->plane_state) { 490 if (top_pipe_to_program->stream->mall_stream_config.type == SUBVP_MAIN && 491 top_pipe_to_program->plane_state->flip_immediate) 492 subvp_immediate_flip = true; 493 } 494 495 // Don't need to lock for DRR VSYNC flips -- FW will wait for DRR pending update cleared. 496 if ((subvp_in_use && (should_lock_all_pipes || subvp_immediate_flip)) || (!subvp_in_use && subvp_prev_use)) { 497 union dmub_inbox0_cmd_lock_hw hw_lock_cmd = { 0 }; 498 499 if (!lock) { 500 for (i = 0; i < dc->res_pool->pipe_count; i++) { 501 pipe = &context->res_ctx.pipe_ctx[i]; 502 if (pipe->stream && pipe->plane_state && pipe->stream->mall_stream_config.type == SUBVP_MAIN && 503 should_lock_all_pipes) 504 pipe->stream_res.tg->funcs->wait_for_state(pipe->stream_res.tg, CRTC_STATE_VBLANK); 505 } 506 } 507 508 hw_lock_cmd.bits.command_code = DMUB_INBOX0_CMD__HW_LOCK; 509 hw_lock_cmd.bits.hw_lock_client = HW_LOCK_CLIENT_DRIVER; 510 hw_lock_cmd.bits.lock = lock; 511 hw_lock_cmd.bits.should_release = !lock; 512 dmub_hw_lock_mgr_inbox0_cmd(dc->ctx->dmub_srv, hw_lock_cmd); 513 } 514 } 515 516 517 static bool dcn32_set_mpc_shaper_3dlut( 518 struct pipe_ctx *pipe_ctx, const struct dc_stream_state *stream) 519 { 520 struct dpp *dpp_base = pipe_ctx->plane_res.dpp; 521 int mpcc_id = pipe_ctx->plane_res.hubp->inst; 522 struct mpc *mpc = pipe_ctx->stream_res.opp->ctx->dc->res_pool->mpc; 523 bool result = false; 524 525 const struct pwl_params *shaper_lut = NULL; 526 //get the shaper lut params 527 if (stream->func_shaper) { 528 if (stream->func_shaper->type == TF_TYPE_HWPWL) 529 shaper_lut = &stream->func_shaper->pwl; 530 else if (stream->func_shaper->type == TF_TYPE_DISTRIBUTED_POINTS) { 531 cm_helper_translate_curve_to_hw_format( 532 stream->func_shaper, 533 &dpp_base->shaper_params, true); 534 shaper_lut = &dpp_base->shaper_params; 535 } 536 } 537 538 if (stream->lut3d_func && 539 stream->lut3d_func->state.bits.initialized == 1) { 540 541 result = mpc->funcs->program_3dlut(mpc, 542 &stream->lut3d_func->lut_3d, 543 mpcc_id); 544 545 result = mpc->funcs->program_shaper(mpc, 546 shaper_lut, 547 mpcc_id); 548 } 549 550 return result; 551 } 552 553 bool dcn32_set_mcm_luts( 554 struct pipe_ctx *pipe_ctx, const struct dc_plane_state *plane_state) 555 { 556 struct dpp *dpp_base = pipe_ctx->plane_res.dpp; 557 int mpcc_id = pipe_ctx->plane_res.hubp->inst; 558 struct mpc *mpc = pipe_ctx->stream_res.opp->ctx->dc->res_pool->mpc; 559 bool result = true; 560 struct pwl_params *lut_params = NULL; 561 562 // 1D LUT 563 if (plane_state->blend_tf) { 564 if (plane_state->blend_tf->type == TF_TYPE_HWPWL) 565 lut_params = &plane_state->blend_tf->pwl; 566 else if (plane_state->blend_tf->type == TF_TYPE_DISTRIBUTED_POINTS) { 567 cm_helper_translate_curve_to_hw_format( 568 plane_state->blend_tf, 569 &dpp_base->regamma_params, false); 570 lut_params = &dpp_base->regamma_params; 571 } 572 } 573 result = mpc->funcs->program_1dlut(mpc, lut_params, mpcc_id); 574 575 // Shaper 576 if (plane_state->in_shaper_func) { 577 if (plane_state->in_shaper_func->type == TF_TYPE_HWPWL) 578 lut_params = &plane_state->in_shaper_func->pwl; 579 else if (plane_state->in_shaper_func->type == TF_TYPE_DISTRIBUTED_POINTS) { 580 // TODO: dpp_base replace 581 ASSERT(false); 582 cm_helper_translate_curve_to_hw_format( 583 plane_state->in_shaper_func, 584 &dpp_base->shaper_params, true); 585 lut_params = &dpp_base->shaper_params; 586 } 587 } 588 589 result = mpc->funcs->program_shaper(mpc, lut_params, mpcc_id); 590 591 // 3D 592 if (plane_state->lut3d_func && plane_state->lut3d_func->state.bits.initialized == 1) 593 result = mpc->funcs->program_3dlut(mpc, &plane_state->lut3d_func->lut_3d, mpcc_id); 594 else 595 result = mpc->funcs->program_3dlut(mpc, NULL, mpcc_id); 596 597 return result; 598 } 599 600 bool dcn32_set_input_transfer_func(struct dc *dc, 601 struct pipe_ctx *pipe_ctx, 602 const struct dc_plane_state *plane_state) 603 { 604 struct dce_hwseq *hws = dc->hwseq; 605 struct mpc *mpc = dc->res_pool->mpc; 606 struct dpp *dpp_base = pipe_ctx->plane_res.dpp; 607 608 enum dc_transfer_func_predefined tf; 609 bool result = true; 610 struct pwl_params *params = NULL; 611 612 if (mpc == NULL || plane_state == NULL) 613 return false; 614 615 tf = TRANSFER_FUNCTION_UNITY; 616 617 if (plane_state->in_transfer_func && 618 plane_state->in_transfer_func->type == TF_TYPE_PREDEFINED) 619 tf = plane_state->in_transfer_func->tf; 620 621 dpp_base->funcs->dpp_set_pre_degam(dpp_base, tf); 622 623 if (plane_state->in_transfer_func) { 624 if (plane_state->in_transfer_func->type == TF_TYPE_HWPWL) 625 params = &plane_state->in_transfer_func->pwl; 626 else if (plane_state->in_transfer_func->type == TF_TYPE_DISTRIBUTED_POINTS && 627 cm3_helper_translate_curve_to_hw_format(plane_state->in_transfer_func, 628 &dpp_base->degamma_params, false)) 629 params = &dpp_base->degamma_params; 630 } 631 632 dpp_base->funcs->dpp_program_gamcor_lut(dpp_base, params); 633 634 if (pipe_ctx->stream_res.opp && 635 pipe_ctx->stream_res.opp->ctx && 636 hws->funcs.set_mcm_luts) 637 result = hws->funcs.set_mcm_luts(pipe_ctx, plane_state); 638 639 return result; 640 } 641 642 bool dcn32_set_output_transfer_func(struct dc *dc, 643 struct pipe_ctx *pipe_ctx, 644 const struct dc_stream_state *stream) 645 { 646 int mpcc_id = pipe_ctx->plane_res.hubp->inst; 647 struct mpc *mpc = pipe_ctx->stream_res.opp->ctx->dc->res_pool->mpc; 648 struct pwl_params *params = NULL; 649 bool ret = false; 650 651 /* program OGAM or 3DLUT only for the top pipe*/ 652 if (pipe_ctx->top_pipe == NULL) { 653 /*program shaper and 3dlut in MPC*/ 654 ret = dcn32_set_mpc_shaper_3dlut(pipe_ctx, stream); 655 if (ret == false && mpc->funcs->set_output_gamma && stream->out_transfer_func) { 656 if (stream->out_transfer_func->type == TF_TYPE_HWPWL) 657 params = &stream->out_transfer_func->pwl; 658 else if (pipe_ctx->stream->out_transfer_func->type == 659 TF_TYPE_DISTRIBUTED_POINTS && 660 cm3_helper_translate_curve_to_hw_format( 661 stream->out_transfer_func, 662 &mpc->blender_params, false)) 663 params = &mpc->blender_params; 664 /* there are no ROM LUTs in OUTGAM */ 665 if (stream->out_transfer_func->type == TF_TYPE_PREDEFINED) 666 BREAK_TO_DEBUGGER(); 667 } 668 } 669 670 mpc->funcs->set_output_gamma(mpc, mpcc_id, params); 671 return ret; 672 } 673 674 /* Program P-State force value according to if pipe is using SubVP or not: 675 * 1. Reset P-State force on all pipes first 676 * 2. For each main pipe, force P-State disallow (P-State allow moderated by DMUB) 677 */ 678 void dcn32_subvp_update_force_pstate(struct dc *dc, struct dc_state *context) 679 { 680 int i; 681 int num_subvp = 0; 682 /* Unforce p-state for each pipe 683 */ 684 for (i = 0; i < dc->res_pool->pipe_count; i++) { 685 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; 686 struct hubp *hubp = pipe->plane_res.hubp; 687 688 if (hubp && hubp->funcs->hubp_update_force_pstate_disallow) 689 hubp->funcs->hubp_update_force_pstate_disallow(hubp, false); 690 if (pipe->stream && pipe->stream->mall_stream_config.type == SUBVP_MAIN) 691 num_subvp++; 692 } 693 694 if (num_subvp == 0) 695 return; 696 697 /* Loop through each pipe -- for each subvp main pipe force p-state allow equal to false. 698 */ 699 for (i = 0; i < dc->res_pool->pipe_count; i++) { 700 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; 701 702 // For SubVP + DRR, also force disallow on the DRR pipe 703 // (We will force allow in the DMUB sequence -- some DRR timings by default won't allow P-State so we have 704 // to force once the vblank is stretched). 705 if (pipe->stream && pipe->plane_state && (pipe->stream->mall_stream_config.type == SUBVP_MAIN || 706 (pipe->stream->mall_stream_config.type == SUBVP_NONE && pipe->stream->ignore_msa_timing_param))) { 707 struct hubp *hubp = pipe->plane_res.hubp; 708 709 if (hubp && hubp->funcs->hubp_update_force_pstate_disallow) 710 hubp->funcs->hubp_update_force_pstate_disallow(hubp, true); 711 } 712 } 713 } 714 715 /* Update MALL_SEL register based on if pipe / plane 716 * is a phantom pipe, main pipe, and if using MALL 717 * for SS. 718 */ 719 void dcn32_update_mall_sel(struct dc *dc, struct dc_state *context) 720 { 721 int i; 722 unsigned int num_ways = dcn32_calculate_cab_allocation(dc, context); 723 bool cache_cursor = false; 724 725 for (i = 0; i < dc->res_pool->pipe_count; i++) { 726 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; 727 struct hubp *hubp = pipe->plane_res.hubp; 728 729 if (pipe->stream && pipe->plane_state && hubp && hubp->funcs->hubp_update_mall_sel) { 730 //Round cursor width up to next multiple of 64 731 int cursor_width = ((hubp->curs_attr.width + 63) / 64) * 64; 732 int cursor_height = hubp->curs_attr.height; 733 int cursor_size = cursor_width * cursor_height; 734 735 switch (hubp->curs_attr.color_format) { 736 case CURSOR_MODE_MONO: 737 cursor_size /= 2; 738 break; 739 case CURSOR_MODE_COLOR_1BIT_AND: 740 case CURSOR_MODE_COLOR_PRE_MULTIPLIED_ALPHA: 741 case CURSOR_MODE_COLOR_UN_PRE_MULTIPLIED_ALPHA: 742 cursor_size *= 4; 743 break; 744 745 case CURSOR_MODE_COLOR_64BIT_FP_PRE_MULTIPLIED: 746 case CURSOR_MODE_COLOR_64BIT_FP_UN_PRE_MULTIPLIED: 747 default: 748 cursor_size *= 8; 749 break; 750 } 751 752 if (cursor_size > 16384) 753 cache_cursor = true; 754 755 if (pipe->stream->mall_stream_config.type == SUBVP_PHANTOM) { 756 hubp->funcs->hubp_update_mall_sel(hubp, 1, false); 757 } else { 758 // MALL not supported with Stereo3D 759 hubp->funcs->hubp_update_mall_sel(hubp, 760 num_ways <= dc->caps.cache_num_ways && 761 pipe->stream->link->psr_settings.psr_version == DC_PSR_VERSION_UNSUPPORTED && 762 pipe->plane_state->address.type != PLN_ADDR_TYPE_GRPH_STEREO && 763 !pipe->plane_state->address.tmz_surface ? 2 : 0, 764 cache_cursor); 765 } 766 } 767 } 768 } 769 770 /* Program the sub-viewport pipe configuration after the main / phantom pipes 771 * have been programmed in hardware. 772 * 1. Update force P-State for all the main pipes (disallow P-state) 773 * 2. Update MALL_SEL register 774 * 3. Program FORCE_ONE_ROW_FOR_FRAME for main subvp pipes 775 */ 776 void dcn32_program_mall_pipe_config(struct dc *dc, struct dc_state *context) 777 { 778 int i; 779 struct dce_hwseq *hws = dc->hwseq; 780 781 // Don't force p-state disallow -- can't block dummy p-state 782 783 // Update MALL_SEL register for each pipe 784 if (hws && hws->funcs.update_mall_sel) 785 hws->funcs.update_mall_sel(dc, context); 786 787 // Program FORCE_ONE_ROW_FOR_FRAME and CURSOR_REQ_MODE for main subvp pipes 788 for (i = 0; i < dc->res_pool->pipe_count; i++) { 789 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; 790 struct hubp *hubp = pipe->plane_res.hubp; 791 792 if (pipe->stream && hubp && hubp->funcs->hubp_prepare_subvp_buffering) { 793 /* TODO - remove setting CURSOR_REQ_MODE to 0 for legacy cases 794 * - need to investigate single pipe MPO + SubVP case to 795 * see if CURSOR_REQ_MODE will be back to 1 for SubVP 796 * when it should be 0 for MPO 797 */ 798 if (pipe->stream->mall_stream_config.type == SUBVP_MAIN) { 799 hubp->funcs->hubp_prepare_subvp_buffering(hubp, true); 800 } 801 } 802 } 803 } 804 805 void dcn32_init_hw(struct dc *dc) 806 { 807 struct abm **abms = dc->res_pool->multiple_abms; 808 struct dce_hwseq *hws = dc->hwseq; 809 struct dc_bios *dcb = dc->ctx->dc_bios; 810 struct resource_pool *res_pool = dc->res_pool; 811 int i; 812 int edp_num; 813 uint32_t backlight = MAX_BACKLIGHT_LEVEL; 814 815 if (dc->clk_mgr && dc->clk_mgr->funcs->init_clocks) 816 dc->clk_mgr->funcs->init_clocks(dc->clk_mgr); 817 818 // Initialize the dccg 819 if (res_pool->dccg->funcs->dccg_init) 820 res_pool->dccg->funcs->dccg_init(res_pool->dccg); 821 822 if (!dcb->funcs->is_accelerated_mode(dcb)) { 823 hws->funcs.bios_golden_init(dc); 824 hws->funcs.disable_vga(dc->hwseq); 825 } 826 827 // Set default OPTC memory power states 828 if (dc->debug.enable_mem_low_power.bits.optc) { 829 // Shutdown when unassigned and light sleep in VBLANK 830 REG_SET_2(ODM_MEM_PWR_CTRL3, 0, ODM_MEM_UNASSIGNED_PWR_MODE, 3, ODM_MEM_VBLANK_PWR_MODE, 1); 831 } 832 833 if (dc->debug.enable_mem_low_power.bits.vga) { 834 // Power down VGA memory 835 REG_UPDATE(MMHUBBUB_MEM_PWR_CNTL, VGA_MEM_PWR_FORCE, 1); 836 } 837 838 if (dc->ctx->dc_bios->fw_info_valid) { 839 res_pool->ref_clocks.xtalin_clock_inKhz = 840 dc->ctx->dc_bios->fw_info.pll_info.crystal_frequency; 841 842 if (res_pool->dccg && res_pool->hubbub) { 843 (res_pool->dccg->funcs->get_dccg_ref_freq)(res_pool->dccg, 844 dc->ctx->dc_bios->fw_info.pll_info.crystal_frequency, 845 &res_pool->ref_clocks.dccg_ref_clock_inKhz); 846 847 (res_pool->hubbub->funcs->get_dchub_ref_freq)(res_pool->hubbub, 848 res_pool->ref_clocks.dccg_ref_clock_inKhz, 849 &res_pool->ref_clocks.dchub_ref_clock_inKhz); 850 } else { 851 // Not all ASICs have DCCG sw component 852 res_pool->ref_clocks.dccg_ref_clock_inKhz = 853 res_pool->ref_clocks.xtalin_clock_inKhz; 854 res_pool->ref_clocks.dchub_ref_clock_inKhz = 855 res_pool->ref_clocks.xtalin_clock_inKhz; 856 } 857 } else 858 ASSERT_CRITICAL(false); 859 860 for (i = 0; i < dc->link_count; i++) { 861 /* Power up AND update implementation according to the 862 * required signal (which may be different from the 863 * default signal on connector). 864 */ 865 struct dc_link *link = dc->links[i]; 866 867 link->link_enc->funcs->hw_init(link->link_enc); 868 869 /* Check for enabled DIG to identify enabled display */ 870 if (link->link_enc->funcs->is_dig_enabled && 871 link->link_enc->funcs->is_dig_enabled(link->link_enc)) { 872 link->link_status.link_active = true; 873 link->phy_state.symclk_state = SYMCLK_ON_TX_ON; 874 if (link->link_enc->funcs->fec_is_active && 875 link->link_enc->funcs->fec_is_active(link->link_enc)) 876 link->fec_state = dc_link_fec_enabled; 877 } 878 } 879 880 /* Power gate DSCs */ 881 for (i = 0; i < res_pool->res_cap->num_dsc; i++) 882 if (hws->funcs.dsc_pg_control != NULL) 883 hws->funcs.dsc_pg_control(hws, res_pool->dscs[i]->inst, false); 884 885 /* we want to turn off all dp displays before doing detection */ 886 dc_link_blank_all_dp_displays(dc); 887 888 /* If taking control over from VBIOS, we may want to optimize our first 889 * mode set, so we need to skip powering down pipes until we know which 890 * pipes we want to use. 891 * Otherwise, if taking control is not possible, we need to power 892 * everything down. 893 */ 894 if (dcb->funcs->is_accelerated_mode(dcb) || !dc->config.seamless_boot_edp_requested) { 895 hws->funcs.init_pipes(dc, dc->current_state); 896 if (dc->res_pool->hubbub->funcs->allow_self_refresh_control) 897 dc->res_pool->hubbub->funcs->allow_self_refresh_control(dc->res_pool->hubbub, 898 !dc->res_pool->hubbub->ctx->dc->debug.disable_stutter); 899 } 900 901 /* In headless boot cases, DIG may be turned 902 * on which causes HW/SW discrepancies. 903 * To avoid this, power down hardware on boot 904 * if DIG is turned on and seamless boot not enabled 905 */ 906 if (!dc->config.seamless_boot_edp_requested) { 907 struct dc_link *edp_links[MAX_NUM_EDP]; 908 struct dc_link *edp_link; 909 910 get_edp_links(dc, edp_links, &edp_num); 911 if (edp_num) { 912 for (i = 0; i < edp_num; i++) { 913 edp_link = edp_links[i]; 914 if (edp_link->link_enc->funcs->is_dig_enabled && 915 edp_link->link_enc->funcs->is_dig_enabled(edp_link->link_enc) && 916 dc->hwss.edp_backlight_control && 917 dc->hwss.power_down && 918 dc->hwss.edp_power_control) { 919 dc->hwss.edp_backlight_control(edp_link, false); 920 dc->hwss.power_down(dc); 921 dc->hwss.edp_power_control(edp_link, false); 922 } 923 } 924 } else { 925 for (i = 0; i < dc->link_count; i++) { 926 struct dc_link *link = dc->links[i]; 927 928 if (link->link_enc->funcs->is_dig_enabled && 929 link->link_enc->funcs->is_dig_enabled(link->link_enc) && 930 dc->hwss.power_down) { 931 dc->hwss.power_down(dc); 932 break; 933 } 934 935 } 936 } 937 } 938 939 for (i = 0; i < res_pool->audio_count; i++) { 940 struct audio *audio = res_pool->audios[i]; 941 942 audio->funcs->hw_init(audio); 943 } 944 945 for (i = 0; i < dc->link_count; i++) { 946 struct dc_link *link = dc->links[i]; 947 948 if (link->panel_cntl) 949 backlight = link->panel_cntl->funcs->hw_init(link->panel_cntl); 950 } 951 952 for (i = 0; i < dc->res_pool->pipe_count; i++) { 953 if (abms[i] != NULL && abms[i]->funcs != NULL) 954 abms[i]->funcs->abm_init(abms[i], backlight); 955 } 956 957 /* power AFMT HDMI memory TODO: may move to dis/en output save power*/ 958 REG_WRITE(DIO_MEM_PWR_CTRL, 0); 959 960 if (!dc->debug.disable_clock_gate) { 961 /* enable all DCN clock gating */ 962 REG_WRITE(DCCG_GATE_DISABLE_CNTL, 0); 963 964 REG_WRITE(DCCG_GATE_DISABLE_CNTL2, 0); 965 966 REG_UPDATE(DCFCLK_CNTL, DCFCLK_GATE_DIS, 0); 967 } 968 if (hws->funcs.enable_power_gating_plane) 969 hws->funcs.enable_power_gating_plane(dc->hwseq, true); 970 971 if (!dcb->funcs->is_accelerated_mode(dcb) && dc->res_pool->hubbub->funcs->init_watermarks) 972 dc->res_pool->hubbub->funcs->init_watermarks(dc->res_pool->hubbub); 973 974 if (dc->clk_mgr->funcs->notify_wm_ranges) 975 dc->clk_mgr->funcs->notify_wm_ranges(dc->clk_mgr); 976 977 if (dc->clk_mgr->funcs->set_hard_max_memclk) 978 dc->clk_mgr->funcs->set_hard_max_memclk(dc->clk_mgr); 979 980 if (dc->res_pool->hubbub->funcs->force_pstate_change_control) 981 dc->res_pool->hubbub->funcs->force_pstate_change_control( 982 dc->res_pool->hubbub, false, false); 983 984 if (dc->res_pool->hubbub->funcs->init_crb) 985 dc->res_pool->hubbub->funcs->init_crb(dc->res_pool->hubbub); 986 987 // Get DMCUB capabilities 988 if (dc->ctx->dmub_srv) { 989 dc_dmub_srv_query_caps_cmd(dc->ctx->dmub_srv->dmub); 990 dc->caps.dmub_caps.psr = dc->ctx->dmub_srv->dmub->feature_caps.psr; 991 } 992 993 /* Enable support for ODM and windowed MPO if policy flag is set */ 994 if (dc->debug.enable_single_display_2to1_odm_policy) 995 dc->config.enable_windowed_mpo_odm = true; 996 } 997 998 static int calc_mpc_flow_ctrl_cnt(const struct dc_stream_state *stream, 999 int opp_cnt) 1000 { 1001 bool hblank_halved = optc2_is_two_pixels_per_containter(&stream->timing); 1002 int flow_ctrl_cnt; 1003 1004 if (opp_cnt >= 2) 1005 hblank_halved = true; 1006 1007 flow_ctrl_cnt = stream->timing.h_total - stream->timing.h_addressable - 1008 stream->timing.h_border_left - 1009 stream->timing.h_border_right; 1010 1011 if (hblank_halved) 1012 flow_ctrl_cnt /= 2; 1013 1014 /* ODM combine 4:1 case */ 1015 if (opp_cnt == 4) 1016 flow_ctrl_cnt /= 2; 1017 1018 return flow_ctrl_cnt; 1019 } 1020 1021 static void update_dsc_on_stream(struct pipe_ctx *pipe_ctx, bool enable) 1022 { 1023 struct display_stream_compressor *dsc = pipe_ctx->stream_res.dsc; 1024 struct dc_stream_state *stream = pipe_ctx->stream; 1025 struct pipe_ctx *odm_pipe; 1026 int opp_cnt = 1; 1027 1028 ASSERT(dsc); 1029 for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) 1030 opp_cnt++; 1031 1032 if (enable) { 1033 struct dsc_config dsc_cfg; 1034 struct dsc_optc_config dsc_optc_cfg; 1035 enum optc_dsc_mode optc_dsc_mode; 1036 1037 /* Enable DSC hw block */ 1038 dsc_cfg.pic_width = (stream->timing.h_addressable + stream->timing.h_border_left + stream->timing.h_border_right) / opp_cnt; 1039 dsc_cfg.pic_height = stream->timing.v_addressable + stream->timing.v_border_top + stream->timing.v_border_bottom; 1040 dsc_cfg.pixel_encoding = stream->timing.pixel_encoding; 1041 dsc_cfg.color_depth = stream->timing.display_color_depth; 1042 dsc_cfg.is_odm = pipe_ctx->next_odm_pipe ? true : false; 1043 dsc_cfg.dc_dsc_cfg = stream->timing.dsc_cfg; 1044 ASSERT(dsc_cfg.dc_dsc_cfg.num_slices_h % opp_cnt == 0); 1045 dsc_cfg.dc_dsc_cfg.num_slices_h /= opp_cnt; 1046 1047 dsc->funcs->dsc_set_config(dsc, &dsc_cfg, &dsc_optc_cfg); 1048 dsc->funcs->dsc_enable(dsc, pipe_ctx->stream_res.opp->inst); 1049 for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) { 1050 struct display_stream_compressor *odm_dsc = odm_pipe->stream_res.dsc; 1051 1052 ASSERT(odm_dsc); 1053 odm_dsc->funcs->dsc_set_config(odm_dsc, &dsc_cfg, &dsc_optc_cfg); 1054 odm_dsc->funcs->dsc_enable(odm_dsc, odm_pipe->stream_res.opp->inst); 1055 } 1056 dsc_cfg.dc_dsc_cfg.num_slices_h *= opp_cnt; 1057 dsc_cfg.pic_width *= opp_cnt; 1058 1059 optc_dsc_mode = dsc_optc_cfg.is_pixel_format_444 ? OPTC_DSC_ENABLED_444 : OPTC_DSC_ENABLED_NATIVE_SUBSAMPLED; 1060 1061 /* Enable DSC in OPTC */ 1062 DC_LOG_DSC("Setting optc DSC config for tg instance %d:", pipe_ctx->stream_res.tg->inst); 1063 pipe_ctx->stream_res.tg->funcs->set_dsc_config(pipe_ctx->stream_res.tg, 1064 optc_dsc_mode, 1065 dsc_optc_cfg.bytes_per_pixel, 1066 dsc_optc_cfg.slice_width); 1067 } else { 1068 /* disable DSC in OPTC */ 1069 pipe_ctx->stream_res.tg->funcs->set_dsc_config( 1070 pipe_ctx->stream_res.tg, 1071 OPTC_DSC_DISABLED, 0, 0); 1072 1073 /* disable DSC block */ 1074 dsc->funcs->dsc_disable(pipe_ctx->stream_res.dsc); 1075 for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) { 1076 ASSERT(odm_pipe->stream_res.dsc); 1077 odm_pipe->stream_res.dsc->funcs->dsc_disable(odm_pipe->stream_res.dsc); 1078 } 1079 } 1080 } 1081 1082 /* 1083 * Given any pipe_ctx, return the total ODM combine factor, and optionally return 1084 * the OPPids which are used 1085 * */ 1086 static unsigned int get_odm_config(struct pipe_ctx *pipe_ctx, unsigned int *opp_instances) 1087 { 1088 unsigned int opp_count = 1; 1089 struct pipe_ctx *odm_pipe; 1090 1091 /* First get to the top pipe */ 1092 for (odm_pipe = pipe_ctx; odm_pipe->prev_odm_pipe; odm_pipe = odm_pipe->prev_odm_pipe) 1093 ; 1094 1095 /* First pipe is always used */ 1096 if (opp_instances) 1097 opp_instances[0] = odm_pipe->stream_res.opp->inst; 1098 1099 /* Find and count odm pipes, if any */ 1100 for (odm_pipe = odm_pipe->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) { 1101 if (opp_instances) 1102 opp_instances[opp_count] = odm_pipe->stream_res.opp->inst; 1103 opp_count++; 1104 } 1105 1106 return opp_count; 1107 } 1108 1109 void dcn32_update_odm(struct dc *dc, struct dc_state *context, struct pipe_ctx *pipe_ctx) 1110 { 1111 struct pipe_ctx *odm_pipe; 1112 int opp_cnt = 0; 1113 int opp_inst[MAX_PIPES] = {0}; 1114 bool rate_control_2x_pclk = (pipe_ctx->stream->timing.flags.INTERLACE || optc2_is_two_pixels_per_containter(&pipe_ctx->stream->timing)); 1115 struct mpc_dwb_flow_control flow_control; 1116 struct mpc *mpc = dc->res_pool->mpc; 1117 int i; 1118 1119 opp_cnt = get_odm_config(pipe_ctx, opp_inst); 1120 1121 if (opp_cnt > 1) 1122 pipe_ctx->stream_res.tg->funcs->set_odm_combine( 1123 pipe_ctx->stream_res.tg, 1124 opp_inst, opp_cnt, 1125 &pipe_ctx->stream->timing); 1126 else 1127 pipe_ctx->stream_res.tg->funcs->set_odm_bypass( 1128 pipe_ctx->stream_res.tg, &pipe_ctx->stream->timing); 1129 1130 rate_control_2x_pclk = rate_control_2x_pclk || opp_cnt > 1; 1131 flow_control.flow_ctrl_mode = 0; 1132 flow_control.flow_ctrl_cnt0 = 0x80; 1133 flow_control.flow_ctrl_cnt1 = calc_mpc_flow_ctrl_cnt(pipe_ctx->stream, opp_cnt); 1134 if (mpc->funcs->set_out_rate_control) { 1135 for (i = 0; i < opp_cnt; ++i) { 1136 mpc->funcs->set_out_rate_control( 1137 mpc, opp_inst[i], 1138 true, 1139 rate_control_2x_pclk, 1140 &flow_control); 1141 } 1142 } 1143 1144 for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) { 1145 odm_pipe->stream_res.opp->funcs->opp_pipe_clock_control( 1146 odm_pipe->stream_res.opp, 1147 true); 1148 } 1149 1150 if (pipe_ctx->stream_res.dsc) { 1151 struct pipe_ctx *current_pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[pipe_ctx->pipe_idx]; 1152 1153 update_dsc_on_stream(pipe_ctx, pipe_ctx->stream->timing.flags.DSC); 1154 1155 /* Check if no longer using pipe for ODM, then need to disconnect DSC for that pipe */ 1156 if (!pipe_ctx->next_odm_pipe && current_pipe_ctx->next_odm_pipe && 1157 current_pipe_ctx->next_odm_pipe->stream_res.dsc) { 1158 struct display_stream_compressor *dsc = current_pipe_ctx->next_odm_pipe->stream_res.dsc; 1159 /* disconnect DSC block from stream */ 1160 dsc->funcs->dsc_disconnect(dsc); 1161 } 1162 } 1163 } 1164 1165 unsigned int dcn32_calculate_dccg_k1_k2_values(struct pipe_ctx *pipe_ctx, unsigned int *k1_div, unsigned int *k2_div) 1166 { 1167 struct dc_stream_state *stream = pipe_ctx->stream; 1168 unsigned int odm_combine_factor = 0; 1169 bool two_pix_per_container = false; 1170 1171 // For phantom pipes, use the same programming as the main pipes 1172 if (pipe_ctx->stream->mall_stream_config.type == SUBVP_PHANTOM) { 1173 stream = pipe_ctx->stream->mall_stream_config.paired_stream; 1174 } 1175 two_pix_per_container = optc2_is_two_pixels_per_containter(&stream->timing); 1176 odm_combine_factor = get_odm_config(pipe_ctx, NULL); 1177 1178 if (pipe_ctx->stream->signal == SIGNAL_TYPE_VIRTUAL) 1179 return odm_combine_factor; 1180 1181 if (is_dp_128b_132b_signal(pipe_ctx)) { 1182 *k2_div = PIXEL_RATE_DIV_BY_1; 1183 } else if (dc_is_hdmi_tmds_signal(pipe_ctx->stream->signal) || dc_is_dvi_signal(pipe_ctx->stream->signal)) { 1184 *k1_div = PIXEL_RATE_DIV_BY_1; 1185 if (stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR420) 1186 *k2_div = PIXEL_RATE_DIV_BY_2; 1187 else 1188 *k2_div = PIXEL_RATE_DIV_BY_4; 1189 } else if (dc_is_dp_signal(pipe_ctx->stream->signal)) { 1190 if (two_pix_per_container) { 1191 *k1_div = PIXEL_RATE_DIV_BY_1; 1192 *k2_div = PIXEL_RATE_DIV_BY_2; 1193 } else { 1194 *k1_div = PIXEL_RATE_DIV_BY_1; 1195 *k2_div = PIXEL_RATE_DIV_BY_4; 1196 if ((odm_combine_factor == 2) || dcn32_is_dp_dig_pixel_rate_div_policy(pipe_ctx)) 1197 *k2_div = PIXEL_RATE_DIV_BY_2; 1198 } 1199 } 1200 1201 if ((*k1_div == PIXEL_RATE_DIV_NA) && (*k2_div == PIXEL_RATE_DIV_NA)) 1202 ASSERT(false); 1203 1204 return odm_combine_factor; 1205 } 1206 1207 void dcn32_set_pixels_per_cycle(struct pipe_ctx *pipe_ctx) 1208 { 1209 uint32_t pix_per_cycle = 1; 1210 uint32_t odm_combine_factor = 1; 1211 1212 if (!pipe_ctx || !pipe_ctx->stream || !pipe_ctx->stream_res.stream_enc) 1213 return; 1214 1215 odm_combine_factor = get_odm_config(pipe_ctx, NULL); 1216 if (optc2_is_two_pixels_per_containter(&pipe_ctx->stream->timing) || odm_combine_factor > 1 1217 || dcn32_is_dp_dig_pixel_rate_div_policy(pipe_ctx)) 1218 pix_per_cycle = 2; 1219 1220 if (pipe_ctx->stream_res.stream_enc->funcs->set_input_mode) 1221 pipe_ctx->stream_res.stream_enc->funcs->set_input_mode(pipe_ctx->stream_res.stream_enc, 1222 pix_per_cycle); 1223 } 1224 1225 void dcn32_unblank_stream(struct pipe_ctx *pipe_ctx, 1226 struct dc_link_settings *link_settings) 1227 { 1228 struct encoder_unblank_param params = {0}; 1229 struct dc_stream_state *stream = pipe_ctx->stream; 1230 struct dc_link *link = stream->link; 1231 struct dce_hwseq *hws = link->dc->hwseq; 1232 struct pipe_ctx *odm_pipe; 1233 uint32_t pix_per_cycle = 1; 1234 1235 params.opp_cnt = 1; 1236 for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) 1237 params.opp_cnt++; 1238 1239 /* only 3 items below are used by unblank */ 1240 params.timing = pipe_ctx->stream->timing; 1241 1242 params.link_settings.link_rate = link_settings->link_rate; 1243 1244 if (is_dp_128b_132b_signal(pipe_ctx)) { 1245 /* TODO - DP2.0 HW: Set ODM mode in dp hpo encoder here */ 1246 pipe_ctx->stream_res.hpo_dp_stream_enc->funcs->dp_unblank( 1247 pipe_ctx->stream_res.hpo_dp_stream_enc, 1248 pipe_ctx->stream_res.tg->inst); 1249 } else if (dc_is_dp_signal(pipe_ctx->stream->signal)) { 1250 if (optc2_is_two_pixels_per_containter(&stream->timing) || params.opp_cnt > 1 1251 || dcn32_is_dp_dig_pixel_rate_div_policy(pipe_ctx)) { 1252 params.timing.pix_clk_100hz /= 2; 1253 pix_per_cycle = 2; 1254 } 1255 pipe_ctx->stream_res.stream_enc->funcs->dp_set_odm_combine( 1256 pipe_ctx->stream_res.stream_enc, pix_per_cycle > 1); 1257 pipe_ctx->stream_res.stream_enc->funcs->dp_unblank(link, pipe_ctx->stream_res.stream_enc, ¶ms); 1258 } 1259 1260 if (link->local_sink && link->local_sink->sink_signal == SIGNAL_TYPE_EDP) 1261 hws->funcs.edp_backlight_control(link, true); 1262 } 1263 1264 bool dcn32_is_dp_dig_pixel_rate_div_policy(struct pipe_ctx *pipe_ctx) 1265 { 1266 struct dc *dc = pipe_ctx->stream->ctx->dc; 1267 1268 if (!is_h_timing_divisible_by_2(pipe_ctx->stream)) 1269 return false; 1270 1271 if (dc_is_dp_signal(pipe_ctx->stream->signal) && !is_dp_128b_132b_signal(pipe_ctx) && 1272 dc->debug.enable_dp_dig_pixel_rate_div_policy) 1273 return true; 1274 return false; 1275 } 1276 1277 static void apply_symclk_on_tx_off_wa(struct dc_link *link) 1278 { 1279 /* There are use cases where SYMCLK is referenced by OTG. For instance 1280 * for TMDS signal, OTG relies SYMCLK even if TX video output is off. 1281 * However current link interface will power off PHY when disabling link 1282 * output. This will turn off SYMCLK generated by PHY. The workaround is 1283 * to identify such case where SYMCLK is still in use by OTG when we 1284 * power off PHY. When this is detected, we will temporarily power PHY 1285 * back on and move PHY's SYMCLK state to SYMCLK_ON_TX_OFF by calling 1286 * program_pix_clk interface. When OTG is disabled, we will then power 1287 * off PHY by calling disable link output again. 1288 * 1289 * In future dcn generations, we plan to rework transmitter control 1290 * interface so that we could have an option to set SYMCLK ON TX OFF 1291 * state in one step without this workaround 1292 */ 1293 1294 struct dc *dc = link->ctx->dc; 1295 struct pipe_ctx *pipe_ctx = NULL; 1296 uint8_t i; 1297 1298 if (link->phy_state.symclk_ref_cnts.otg > 0) { 1299 for (i = 0; i < MAX_PIPES; i++) { 1300 pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[i]; 1301 if (pipe_ctx->stream && pipe_ctx->stream->link == link && pipe_ctx->top_pipe == NULL) { 1302 pipe_ctx->clock_source->funcs->program_pix_clk( 1303 pipe_ctx->clock_source, 1304 &pipe_ctx->stream_res.pix_clk_params, 1305 dp_get_link_encoding_format(&pipe_ctx->link_config.dp_link_settings), 1306 &pipe_ctx->pll_settings); 1307 link->phy_state.symclk_state = SYMCLK_ON_TX_OFF; 1308 break; 1309 } 1310 } 1311 } 1312 } 1313 1314 void dcn32_disable_link_output(struct dc_link *link, 1315 const struct link_resource *link_res, 1316 enum signal_type signal) 1317 { 1318 struct dc *dc = link->ctx->dc; 1319 const struct link_hwss *link_hwss = get_link_hwss(link, link_res); 1320 struct dmcu *dmcu = dc->res_pool->dmcu; 1321 1322 if (signal == SIGNAL_TYPE_EDP && 1323 link->dc->hwss.edp_backlight_control) 1324 link->dc->hwss.edp_backlight_control(link, false); 1325 else if (dmcu != NULL && dmcu->funcs->lock_phy) 1326 dmcu->funcs->lock_phy(dmcu); 1327 1328 link_hwss->disable_link_output(link, link_res, signal); 1329 link->phy_state.symclk_state = SYMCLK_OFF_TX_OFF; 1330 1331 if (signal == SIGNAL_TYPE_EDP && 1332 link->dc->hwss.edp_backlight_control) 1333 link->dc->hwss.edp_power_control(link, false); 1334 else if (dmcu != NULL && dmcu->funcs->lock_phy) 1335 dmcu->funcs->unlock_phy(dmcu); 1336 1337 dp_source_sequence_trace(link, DPCD_SOURCE_SEQ_AFTER_DISABLE_LINK_PHY); 1338 1339 apply_symclk_on_tx_off_wa(link); 1340 } 1341 1342 /* For SubVP the main pipe can have a viewport position change 1343 * without a full update. In this case we must also update the 1344 * viewport positions for the phantom pipe accordingly. 1345 */ 1346 void dcn32_update_phantom_vp_position(struct dc *dc, 1347 struct dc_state *context, 1348 struct pipe_ctx *phantom_pipe) 1349 { 1350 uint32_t i; 1351 struct dc_plane_state *phantom_plane = phantom_pipe->plane_state; 1352 1353 for (i = 0; i < dc->res_pool->pipe_count; i++) { 1354 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; 1355 1356 if (pipe->stream && pipe->stream->mall_stream_config.type == SUBVP_MAIN && 1357 pipe->stream->mall_stream_config.paired_stream == phantom_pipe->stream) { 1358 if (pipe->plane_state && pipe->plane_state->update_flags.bits.position_change) { 1359 1360 phantom_plane->src_rect.x = pipe->plane_state->src_rect.x; 1361 phantom_plane->src_rect.y = pipe->plane_state->src_rect.y; 1362 phantom_plane->clip_rect.x = pipe->plane_state->clip_rect.x; 1363 phantom_plane->dst_rect.x = pipe->plane_state->dst_rect.x; 1364 phantom_plane->dst_rect.y = pipe->plane_state->dst_rect.y; 1365 1366 phantom_pipe->plane_state->update_flags.bits.position_change = 1; 1367 resource_build_scaling_params(phantom_pipe); 1368 return; 1369 } 1370 } 1371 } 1372 } 1373 1374 bool dcn32_dsc_pg_status( 1375 struct dce_hwseq *hws, 1376 unsigned int dsc_inst) 1377 { 1378 uint32_t pwr_status = 0; 1379 1380 switch (dsc_inst) { 1381 case 0: /* DSC0 */ 1382 REG_GET(DOMAIN16_PG_STATUS, 1383 DOMAIN_PGFSM_PWR_STATUS, &pwr_status); 1384 break; 1385 case 1: /* DSC1 */ 1386 1387 REG_GET(DOMAIN17_PG_STATUS, 1388 DOMAIN_PGFSM_PWR_STATUS, &pwr_status); 1389 break; 1390 case 2: /* DSC2 */ 1391 REG_GET(DOMAIN18_PG_STATUS, 1392 DOMAIN_PGFSM_PWR_STATUS, &pwr_status); 1393 break; 1394 case 3: /* DSC3 */ 1395 REG_GET(DOMAIN19_PG_STATUS, 1396 DOMAIN_PGFSM_PWR_STATUS, &pwr_status); 1397 break; 1398 default: 1399 BREAK_TO_DEBUGGER(); 1400 break; 1401 } 1402 1403 return pwr_status == 0; 1404 } 1405 1406 void dcn32_update_dsc_pg(struct dc *dc, 1407 struct dc_state *context, 1408 bool safe_to_disable) 1409 { 1410 struct dce_hwseq *hws = dc->hwseq; 1411 int i; 1412 1413 for (i = 0; i < dc->res_pool->res_cap->num_dsc; i++) { 1414 struct display_stream_compressor *dsc = dc->res_pool->dscs[i]; 1415 bool is_dsc_ungated = hws->funcs.dsc_pg_status(hws, dsc->inst); 1416 1417 if (context->res_ctx.is_dsc_acquired[i]) { 1418 if (!is_dsc_ungated) { 1419 hws->funcs.dsc_pg_control(hws, dsc->inst, true); 1420 } 1421 } else if (safe_to_disable) { 1422 if (is_dsc_ungated) { 1423 hws->funcs.dsc_pg_control(hws, dsc->inst, false); 1424 } 1425 } 1426 } 1427 } 1428