1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 27 #include "dm_services.h" 28 #include "dm_helpers.h" 29 #include "core_types.h" 30 #include "resource.h" 31 #include "dccg.h" 32 #include "dce/dce_hwseq.h" 33 #include "dcn30/dcn30_cm_common.h" 34 #include "reg_helper.h" 35 #include "abm.h" 36 #include "hubp.h" 37 #include "dchubbub.h" 38 #include "timing_generator.h" 39 #include "opp.h" 40 #include "ipp.h" 41 #include "mpc.h" 42 #include "mcif_wb.h" 43 #include "dc_dmub_srv.h" 44 #include "link_hwss.h" 45 #include "dpcd_defs.h" 46 #include "dcn32_hwseq.h" 47 #include "clk_mgr.h" 48 #include "dsc.h" 49 #include "dcn20/dcn20_optc.h" 50 #include "dmub_subvp_state.h" 51 #include "dce/dmub_hw_lock_mgr.h" 52 #include "dc_link_dp.h" 53 #include "dmub/inc/dmub_subvp_state.h" 54 55 #define DC_LOGGER_INIT(logger) 56 57 #define CTX \ 58 hws->ctx 59 #define REG(reg)\ 60 hws->regs->reg 61 #define DC_LOGGER \ 62 dc->ctx->logger 63 64 65 #undef FN 66 #define FN(reg_name, field_name) \ 67 hws->shifts->field_name, hws->masks->field_name 68 69 void dcn32_dsc_pg_control( 70 struct dce_hwseq *hws, 71 unsigned int dsc_inst, 72 bool power_on) 73 { 74 uint32_t power_gate = power_on ? 0 : 1; 75 uint32_t pwr_status = power_on ? 0 : 2; 76 uint32_t org_ip_request_cntl = 0; 77 78 if (hws->ctx->dc->debug.disable_dsc_power_gate) 79 return; 80 81 REG_GET(DC_IP_REQUEST_CNTL, IP_REQUEST_EN, &org_ip_request_cntl); 82 if (org_ip_request_cntl == 0) 83 REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 1); 84 85 switch (dsc_inst) { 86 case 0: /* DSC0 */ 87 REG_UPDATE(DOMAIN16_PG_CONFIG, 88 DOMAIN_POWER_GATE, power_gate); 89 90 REG_WAIT(DOMAIN16_PG_STATUS, 91 DOMAIN_PGFSM_PWR_STATUS, pwr_status, 92 1, 1000); 93 break; 94 case 1: /* DSC1 */ 95 REG_UPDATE(DOMAIN17_PG_CONFIG, 96 DOMAIN_POWER_GATE, power_gate); 97 98 REG_WAIT(DOMAIN17_PG_STATUS, 99 DOMAIN_PGFSM_PWR_STATUS, pwr_status, 100 1, 1000); 101 break; 102 case 2: /* DSC2 */ 103 REG_UPDATE(DOMAIN18_PG_CONFIG, 104 DOMAIN_POWER_GATE, power_gate); 105 106 REG_WAIT(DOMAIN18_PG_STATUS, 107 DOMAIN_PGFSM_PWR_STATUS, pwr_status, 108 1, 1000); 109 break; 110 case 3: /* DSC3 */ 111 REG_UPDATE(DOMAIN19_PG_CONFIG, 112 DOMAIN_POWER_GATE, power_gate); 113 114 REG_WAIT(DOMAIN19_PG_STATUS, 115 DOMAIN_PGFSM_PWR_STATUS, pwr_status, 116 1, 1000); 117 break; 118 default: 119 BREAK_TO_DEBUGGER(); 120 break; 121 } 122 123 if (org_ip_request_cntl == 0) 124 REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 0); 125 } 126 127 128 void dcn32_enable_power_gating_plane( 129 struct dce_hwseq *hws, 130 bool enable) 131 { 132 bool force_on = true; /* disable power gating */ 133 134 if (enable) 135 force_on = false; 136 137 /* DCHUBP0/1/2/3 */ 138 REG_UPDATE(DOMAIN0_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on); 139 REG_UPDATE(DOMAIN1_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on); 140 REG_UPDATE(DOMAIN2_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on); 141 REG_UPDATE(DOMAIN3_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on); 142 143 /* DCS0/1/2/3 */ 144 REG_UPDATE(DOMAIN16_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on); 145 REG_UPDATE(DOMAIN17_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on); 146 REG_UPDATE(DOMAIN18_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on); 147 REG_UPDATE(DOMAIN19_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on); 148 } 149 150 void dcn32_hubp_pg_control(struct dce_hwseq *hws, unsigned int hubp_inst, bool power_on) 151 { 152 uint32_t power_gate = power_on ? 0 : 1; 153 uint32_t pwr_status = power_on ? 0 : 2; 154 155 if (hws->ctx->dc->debug.disable_hubp_power_gate) 156 return; 157 158 if (REG(DOMAIN0_PG_CONFIG) == 0) 159 return; 160 161 switch (hubp_inst) { 162 case 0: 163 REG_SET(DOMAIN0_PG_CONFIG, 0, DOMAIN_POWER_GATE, power_gate); 164 REG_WAIT(DOMAIN0_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, pwr_status, 1, 1000); 165 break; 166 case 1: 167 REG_SET(DOMAIN1_PG_CONFIG, 0, DOMAIN_POWER_GATE, power_gate); 168 REG_WAIT(DOMAIN1_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, pwr_status, 1, 1000); 169 break; 170 case 2: 171 REG_SET(DOMAIN2_PG_CONFIG, 0, DOMAIN_POWER_GATE, power_gate); 172 REG_WAIT(DOMAIN2_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, pwr_status, 1, 1000); 173 break; 174 case 3: 175 REG_SET(DOMAIN3_PG_CONFIG, 0, DOMAIN_POWER_GATE, power_gate); 176 REG_WAIT(DOMAIN3_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, pwr_status, 1, 1000); 177 break; 178 default: 179 BREAK_TO_DEBUGGER(); 180 break; 181 } 182 } 183 184 static bool dcn32_check_no_memory_request_for_cab(struct dc *dc) 185 { 186 int i; 187 188 /* First, check no-memory-request case */ 189 for (i = 0; i < dc->current_state->stream_count; i++) { 190 if (dc->current_state->stream_status[i].plane_count) 191 /* Fail eligibility on a visible stream */ 192 break; 193 } 194 195 if (i == dc->current_state->stream_count) 196 return true; 197 198 return false; 199 } 200 201 /* This function takes in the start address and surface size to be cached in CAB 202 * and calculates the total number of cache lines required to store the surface. 203 * The number of cache lines used for each surface is calculated independently of 204 * one another. For example, if there is a primary surface(1), meta surface(2), and 205 * cursor(3), this function should be called 3 times to calculate the number of cache 206 * lines used for each of those surfaces. 207 */ 208 static uint32_t dcn32_cache_lines_for_surface(struct dc *dc, uint32_t surface_size, uint64_t start_address) 209 { 210 uint32_t lines_used = 1; 211 uint32_t num_cached_bytes = 0; 212 uint32_t remaining_size = 0; 213 uint32_t cache_line_size = dc->caps.cache_line_size; 214 uint32_t remainder = 0; 215 216 /* 1. Calculate surface size minus the number of bytes stored 217 * in the first cache line (all bytes in first cache line might 218 * not be fully used). 219 */ 220 div_u64_rem(start_address, cache_line_size, &remainder); 221 num_cached_bytes = cache_line_size - remainder; 222 remaining_size = surface_size - num_cached_bytes; 223 224 /* 2. Calculate number of cache lines that will be fully used with 225 * the remaining number of bytes to be stored. 226 */ 227 lines_used += (remaining_size / cache_line_size); 228 229 /* 3. Check if we need an extra line due to the remaining size not being 230 * a multiple of CACHE_LINE_SIZE. 231 */ 232 if (remaining_size % cache_line_size > 0) 233 lines_used++; 234 235 return lines_used; 236 } 237 238 /* This function loops through every surface that needs to be cached in CAB for SS, 239 * and calculates the total number of ways required to store all surfaces (primary, 240 * meta, cursor). 241 */ 242 static uint32_t dcn32_calculate_cab_allocation(struct dc *dc, struct dc_state *ctx) 243 { 244 uint8_t i, j; 245 struct dc_stream_state *stream = NULL; 246 struct dc_plane_state *plane = NULL; 247 uint32_t surface_size = 0; 248 uint32_t cursor_size = 0; 249 uint32_t cache_lines_used = 0; 250 uint32_t total_lines = 0; 251 uint32_t lines_per_way = 0; 252 uint32_t num_ways = 0; 253 254 for (i = 0; i < ctx->stream_count; i++) { 255 stream = ctx->streams[i]; 256 257 // Don't include PSR surface in the total surface size for CAB allocation 258 if (stream->link->psr_settings.psr_version != DC_PSR_VERSION_UNSUPPORTED) 259 continue; 260 261 if (ctx->stream_status[i].plane_count == 0) 262 continue; 263 264 // For each stream, loop through each plane to calculate the number of cache 265 // lines required to store the surface in CAB 266 for (j = 0; j < ctx->stream_status[i].plane_count; j++) { 267 plane = ctx->stream_status[i].plane_states[j]; 268 269 // Calculate total surface size 270 surface_size = plane->plane_size.surface_pitch * 271 plane->plane_size.surface_size.height * 272 (plane->format >= SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616 ? 8 : 4); 273 274 // Convert surface size + starting address to number of cache lines required 275 // (alignment accounted for) 276 cache_lines_used += dcn32_cache_lines_for_surface(dc, surface_size, 277 plane->address.grph.addr.quad_part); 278 279 if (plane->address.grph.meta_addr.quad_part) { 280 // Meta surface 281 cache_lines_used += dcn32_cache_lines_for_surface(dc, surface_size, 282 plane->address.grph.meta_addr.quad_part); 283 } 284 } 285 286 // Include cursor size for CAB allocation 287 if (stream->cursor_position.enable && plane->address.grph.cursor_cache_addr.quad_part) { 288 cursor_size = dc->caps.max_cursor_size * dc->caps.max_cursor_size; 289 switch (stream->cursor_attributes.color_format) { 290 case CURSOR_MODE_MONO: 291 cursor_size /= 2; 292 break; 293 case CURSOR_MODE_COLOR_1BIT_AND: 294 case CURSOR_MODE_COLOR_PRE_MULTIPLIED_ALPHA: 295 case CURSOR_MODE_COLOR_UN_PRE_MULTIPLIED_ALPHA: 296 cursor_size *= 4; 297 break; 298 299 case CURSOR_MODE_COLOR_64BIT_FP_PRE_MULTIPLIED: 300 case CURSOR_MODE_COLOR_64BIT_FP_UN_PRE_MULTIPLIED: 301 cursor_size *= 8; 302 break; 303 } 304 cache_lines_used += dcn32_cache_lines_for_surface(dc, surface_size, 305 plane->address.grph.cursor_cache_addr.quad_part); 306 } 307 } 308 309 // Convert number of cache lines required to number of ways 310 total_lines = dc->caps.max_cab_allocation_bytes / dc->caps.cache_line_size; 311 lines_per_way = total_lines / dc->caps.cache_num_ways; 312 num_ways = cache_lines_used / lines_per_way; 313 314 if (cache_lines_used % lines_per_way > 0) 315 num_ways++; 316 317 return num_ways; 318 } 319 320 bool dcn32_apply_idle_power_optimizations(struct dc *dc, bool enable) 321 { 322 union dmub_rb_cmd cmd; 323 uint8_t ways; 324 325 if (!dc->ctx->dmub_srv) 326 return false; 327 328 if (enable) { 329 if (dc->current_state) { 330 331 /* 1. Check no memory request case for CAB. 332 * If no memory request case, send CAB_ACTION NO_DF_REQ DMUB message 333 */ 334 if (dcn32_check_no_memory_request_for_cab(dc)) { 335 /* Enable no-memory-requests case */ 336 memset(&cmd, 0, sizeof(cmd)); 337 cmd.cab.header.type = DMUB_CMD__CAB_FOR_SS; 338 cmd.cab.header.sub_type = DMUB_CMD__CAB_NO_DCN_REQ; 339 cmd.cab.header.payload_bytes = sizeof(cmd.cab) - sizeof(cmd.cab.header); 340 341 dc_dmub_srv_cmd_queue(dc->ctx->dmub_srv, &cmd); 342 dc_dmub_srv_cmd_execute(dc->ctx->dmub_srv); 343 344 return true; 345 } 346 347 /* 2. Check if all surfaces can fit in CAB. 348 * If surfaces can fit into CAB, send CAB_ACTION_ALLOW DMUB message 349 * and configure HUBP's to fetch from MALL 350 */ 351 ways = dcn32_calculate_cab_allocation(dc, dc->current_state); 352 if (ways <= dc->caps.cache_num_ways) { 353 memset(&cmd, 0, sizeof(cmd)); 354 cmd.cab.header.type = DMUB_CMD__CAB_FOR_SS; 355 cmd.cab.header.sub_type = DMUB_CMD__CAB_DCN_SS_FIT_IN_CAB; 356 cmd.cab.header.payload_bytes = sizeof(cmd.cab) - sizeof(cmd.cab.header); 357 cmd.cab.cab_alloc_ways = ways; 358 359 dc_dmub_srv_cmd_queue(dc->ctx->dmub_srv, &cmd); 360 dc_dmub_srv_cmd_execute(dc->ctx->dmub_srv); 361 362 return true; 363 } 364 365 } 366 return false; 367 } 368 369 /* Disable CAB */ 370 memset(&cmd, 0, sizeof(cmd)); 371 cmd.cab.header.type = DMUB_CMD__CAB_FOR_SS; 372 cmd.cab.header.sub_type = DMUB_CMD__CAB_NO_IDLE_OPTIMIZATION; 373 cmd.cab.header.payload_bytes = 374 sizeof(cmd.cab) - sizeof(cmd.cab.header); 375 376 dc_dmub_srv_cmd_queue(dc->ctx->dmub_srv, &cmd); 377 dc_dmub_srv_cmd_execute(dc->ctx->dmub_srv); 378 dc_dmub_srv_wait_idle(dc->ctx->dmub_srv); 379 380 return true; 381 } 382 383 /* Send DMCUB message with SubVP pipe info 384 * - For each pipe in context, populate payload with required SubVP information 385 * if the pipe is using SubVP for MCLK switch 386 * - This function must be called while the DMUB HW lock is acquired by driver 387 */ 388 void dcn32_commit_subvp_config(struct dc *dc, struct dc_state *context) 389 { 390 /* 391 int i; 392 bool enable_subvp = false; 393 394 if (!dc->ctx || !dc->ctx->dmub_srv) 395 return; 396 397 for (i = 0; i < dc->res_pool->pipe_count; i++) { 398 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; 399 400 if (pipe_ctx->stream && pipe_ctx->stream->mall_stream_config.paired_stream && 401 pipe_ctx->stream->mall_stream_config.type == SUBVP_MAIN) { 402 // There is at least 1 SubVP pipe, so enable SubVP 403 enable_subvp = true; 404 break; 405 } 406 } 407 dc_dmub_setup_subvp_dmub_command(dc, context, enable_subvp); 408 */ 409 } 410 411 /* Sub-Viewport DMUB lock needs to be acquired by driver whenever SubVP is active and: 412 * 1. Any full update for any SubVP main pipe 413 * 2. Any immediate flip for any SubVP pipe 414 * 3. Any flip for DRR pipe 415 * 4. If SubVP was previously in use (i.e. in old context) 416 */ 417 void dcn32_subvp_pipe_control_lock(struct dc *dc, 418 struct dc_state *context, 419 bool lock, 420 bool should_lock_all_pipes, 421 struct pipe_ctx *top_pipe_to_program, 422 bool subvp_prev_use) 423 { 424 unsigned int i = 0; 425 bool subvp_immediate_flip = false; 426 bool subvp_in_use = false; 427 bool drr_pipe = false; 428 struct pipe_ctx *pipe; 429 430 for (i = 0; i < dc->res_pool->pipe_count; i++) { 431 pipe = &context->res_ctx.pipe_ctx[i]; 432 433 if (pipe->stream && pipe->plane_state && pipe->stream->mall_stream_config.type == SUBVP_MAIN) { 434 subvp_in_use = true; 435 break; 436 } 437 } 438 439 if (top_pipe_to_program && top_pipe_to_program->stream && top_pipe_to_program->plane_state) { 440 if (top_pipe_to_program->stream->mall_stream_config.type == SUBVP_MAIN && 441 top_pipe_to_program->plane_state->flip_immediate) 442 subvp_immediate_flip = true; 443 else if (top_pipe_to_program->stream->mall_stream_config.type == SUBVP_NONE && 444 top_pipe_to_program->stream->ignore_msa_timing_param) 445 drr_pipe = true; 446 } 447 448 if ((subvp_in_use && (should_lock_all_pipes || subvp_immediate_flip || drr_pipe)) || (!subvp_in_use && subvp_prev_use)) { 449 union dmub_inbox0_cmd_lock_hw hw_lock_cmd = { 0 }; 450 451 if (!lock) { 452 for (i = 0; i < dc->res_pool->pipe_count; i++) { 453 pipe = &context->res_ctx.pipe_ctx[i]; 454 if (pipe->stream && pipe->plane_state && pipe->stream->mall_stream_config.type == SUBVP_MAIN && 455 should_lock_all_pipes) 456 pipe->stream_res.tg->funcs->wait_for_state(pipe->stream_res.tg, CRTC_STATE_VBLANK); 457 } 458 } 459 460 hw_lock_cmd.bits.command_code = DMUB_INBOX0_CMD__HW_LOCK; 461 hw_lock_cmd.bits.hw_lock_client = HW_LOCK_CLIENT_DRIVER; 462 hw_lock_cmd.bits.lock = lock; 463 hw_lock_cmd.bits.should_release = !lock; 464 dmub_hw_lock_mgr_inbox0_cmd(dc->ctx->dmub_srv, hw_lock_cmd); 465 } 466 } 467 468 469 static bool dcn32_set_mpc_shaper_3dlut( 470 struct pipe_ctx *pipe_ctx, const struct dc_stream_state *stream) 471 { 472 struct dpp *dpp_base = pipe_ctx->plane_res.dpp; 473 int mpcc_id = pipe_ctx->plane_res.hubp->inst; 474 struct mpc *mpc = pipe_ctx->stream_res.opp->ctx->dc->res_pool->mpc; 475 bool result = false; 476 477 const struct pwl_params *shaper_lut = NULL; 478 //get the shaper lut params 479 if (stream->func_shaper) { 480 if (stream->func_shaper->type == TF_TYPE_HWPWL) 481 shaper_lut = &stream->func_shaper->pwl; 482 else if (stream->func_shaper->type == TF_TYPE_DISTRIBUTED_POINTS) { 483 cm_helper_translate_curve_to_hw_format( 484 stream->func_shaper, 485 &dpp_base->shaper_params, true); 486 shaper_lut = &dpp_base->shaper_params; 487 } 488 } 489 490 if (stream->lut3d_func && 491 stream->lut3d_func->state.bits.initialized == 1) { 492 493 result = mpc->funcs->program_3dlut(mpc, 494 &stream->lut3d_func->lut_3d, 495 mpcc_id); 496 497 result = mpc->funcs->program_shaper(mpc, 498 shaper_lut, 499 mpcc_id); 500 } 501 502 return result; 503 } 504 505 bool dcn32_set_mcm_luts( 506 struct pipe_ctx *pipe_ctx, const struct dc_plane_state *plane_state) 507 { 508 struct dpp *dpp_base = pipe_ctx->plane_res.dpp; 509 int mpcc_id = pipe_ctx->plane_res.hubp->inst; 510 struct mpc *mpc = pipe_ctx->stream_res.opp->ctx->dc->res_pool->mpc; 511 bool result = true; 512 struct pwl_params *lut_params = NULL; 513 514 // 1D LUT 515 if (plane_state->blend_tf) { 516 if (plane_state->blend_tf->type == TF_TYPE_HWPWL) 517 lut_params = &plane_state->blend_tf->pwl; 518 else if (plane_state->blend_tf->type == TF_TYPE_DISTRIBUTED_POINTS) { 519 cm_helper_translate_curve_to_hw_format( 520 plane_state->blend_tf, 521 &dpp_base->regamma_params, false); 522 lut_params = &dpp_base->regamma_params; 523 } 524 } 525 result = mpc->funcs->program_1dlut(mpc, lut_params, mpcc_id); 526 527 // Shaper 528 if (plane_state->in_shaper_func) { 529 if (plane_state->in_shaper_func->type == TF_TYPE_HWPWL) 530 lut_params = &plane_state->in_shaper_func->pwl; 531 else if (plane_state->in_shaper_func->type == TF_TYPE_DISTRIBUTED_POINTS) { 532 // TODO: dpp_base replace 533 ASSERT(false); 534 cm_helper_translate_curve_to_hw_format( 535 plane_state->in_shaper_func, 536 &dpp_base->shaper_params, true); 537 lut_params = &dpp_base->shaper_params; 538 } 539 } 540 541 result = mpc->funcs->program_shaper(mpc, lut_params, mpcc_id); 542 543 // 3D 544 if (plane_state->lut3d_func && plane_state->lut3d_func->state.bits.initialized == 1) 545 result = mpc->funcs->program_3dlut(mpc, &plane_state->lut3d_func->lut_3d, mpcc_id); 546 else 547 result = mpc->funcs->program_3dlut(mpc, NULL, mpcc_id); 548 549 return result; 550 } 551 552 bool dcn32_set_input_transfer_func(struct dc *dc, 553 struct pipe_ctx *pipe_ctx, 554 const struct dc_plane_state *plane_state) 555 { 556 struct dce_hwseq *hws = dc->hwseq; 557 struct mpc *mpc = dc->res_pool->mpc; 558 struct dpp *dpp_base = pipe_ctx->plane_res.dpp; 559 560 enum dc_transfer_func_predefined tf; 561 bool result = true; 562 struct pwl_params *params = NULL; 563 564 if (mpc == NULL || plane_state == NULL) 565 return false; 566 567 tf = TRANSFER_FUNCTION_UNITY; 568 569 if (plane_state->in_transfer_func && 570 plane_state->in_transfer_func->type == TF_TYPE_PREDEFINED) 571 tf = plane_state->in_transfer_func->tf; 572 573 dpp_base->funcs->dpp_set_pre_degam(dpp_base, tf); 574 575 if (plane_state->in_transfer_func) { 576 if (plane_state->in_transfer_func->type == TF_TYPE_HWPWL) 577 params = &plane_state->in_transfer_func->pwl; 578 else if (plane_state->in_transfer_func->type == TF_TYPE_DISTRIBUTED_POINTS && 579 cm3_helper_translate_curve_to_hw_format(plane_state->in_transfer_func, 580 &dpp_base->degamma_params, false)) 581 params = &dpp_base->degamma_params; 582 } 583 584 result = dpp_base->funcs->dpp_program_gamcor_lut(dpp_base, params); 585 586 if (result && 587 pipe_ctx->stream_res.opp && 588 pipe_ctx->stream_res.opp->ctx && 589 hws->funcs.set_mcm_luts) 590 result = hws->funcs.set_mcm_luts(pipe_ctx, plane_state); 591 592 return result; 593 } 594 595 bool dcn32_set_output_transfer_func(struct dc *dc, 596 struct pipe_ctx *pipe_ctx, 597 const struct dc_stream_state *stream) 598 { 599 int mpcc_id = pipe_ctx->plane_res.hubp->inst; 600 struct mpc *mpc = pipe_ctx->stream_res.opp->ctx->dc->res_pool->mpc; 601 struct pwl_params *params = NULL; 602 bool ret = false; 603 604 /* program OGAM or 3DLUT only for the top pipe*/ 605 if (pipe_ctx->top_pipe == NULL) { 606 /*program shaper and 3dlut in MPC*/ 607 ret = dcn32_set_mpc_shaper_3dlut(pipe_ctx, stream); 608 if (ret == false && mpc->funcs->set_output_gamma && stream->out_transfer_func) { 609 if (stream->out_transfer_func->type == TF_TYPE_HWPWL) 610 params = &stream->out_transfer_func->pwl; 611 else if (pipe_ctx->stream->out_transfer_func->type == 612 TF_TYPE_DISTRIBUTED_POINTS && 613 cm3_helper_translate_curve_to_hw_format( 614 stream->out_transfer_func, 615 &mpc->blender_params, false)) 616 params = &mpc->blender_params; 617 /* there are no ROM LUTs in OUTGAM */ 618 if (stream->out_transfer_func->type == TF_TYPE_PREDEFINED) 619 BREAK_TO_DEBUGGER(); 620 } 621 } 622 623 mpc->funcs->set_output_gamma(mpc, mpcc_id, params); 624 return ret; 625 } 626 627 /* Program P-State force value according to if pipe is using SubVP or not: 628 * 1. Reset P-State force on all pipes first 629 * 2. For each main pipe, force P-State disallow (P-State allow moderated by DMUB) 630 */ 631 void dcn32_subvp_update_force_pstate(struct dc *dc, struct dc_state *context) 632 { 633 int i; 634 int num_subvp = 0; 635 /* Unforce p-state for each pipe 636 */ 637 for (i = 0; i < dc->res_pool->pipe_count; i++) { 638 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; 639 struct hubp *hubp = pipe->plane_res.hubp; 640 641 if (hubp && hubp->funcs->hubp_update_force_pstate_disallow) 642 hubp->funcs->hubp_update_force_pstate_disallow(hubp, false); 643 if (pipe->stream && pipe->stream->mall_stream_config.type == SUBVP_MAIN) 644 num_subvp++; 645 } 646 647 if (num_subvp == 0) 648 return; 649 650 /* Loop through each pipe -- for each subvp main pipe force p-state allow equal to false. 651 */ 652 for (i = 0; i < dc->res_pool->pipe_count; i++) { 653 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; 654 655 // For SubVP + DRR, also force disallow on the DRR pipe 656 // (We will force allow in the DMUB sequence -- some DRR timings by default won't allow P-State so we have 657 // to force once the vblank is stretched). 658 if (pipe->stream && pipe->plane_state && (pipe->stream->mall_stream_config.type == SUBVP_MAIN || 659 (pipe->stream->mall_stream_config.type == SUBVP_NONE && pipe->stream->ignore_msa_timing_param))) { 660 struct hubp *hubp = pipe->plane_res.hubp; 661 662 if (hubp && hubp->funcs->hubp_update_force_pstate_disallow) 663 hubp->funcs->hubp_update_force_pstate_disallow(hubp, true); 664 } 665 } 666 } 667 668 /* Update MALL_SEL register based on if pipe / plane 669 * is a phantom pipe, main pipe, and if using MALL 670 * for SS. 671 */ 672 void dcn32_update_mall_sel(struct dc *dc, struct dc_state *context) 673 { 674 int i; 675 unsigned int num_ways = dcn32_calculate_cab_allocation(dc, context); 676 677 for (i = 0; i < dc->res_pool->pipe_count; i++) { 678 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; 679 struct hubp *hubp = pipe->plane_res.hubp; 680 681 if (pipe->stream && pipe->plane_state && hubp && hubp->funcs->hubp_update_mall_sel) { 682 if (pipe->stream->mall_stream_config.type == SUBVP_PHANTOM) { 683 hubp->funcs->hubp_update_mall_sel(hubp, 1); 684 } else { 685 hubp->funcs->hubp_update_mall_sel(hubp, 686 num_ways <= dc->caps.cache_num_ways && 687 pipe->stream->link->psr_settings.psr_version == DC_PSR_VERSION_UNSUPPORTED ? 2 : 0); 688 } 689 } 690 } 691 } 692 693 /* Program the sub-viewport pipe configuration after the main / phantom pipes 694 * have been programmed in hardware. 695 * 1. Update force P-State for all the main pipes (disallow P-state) 696 * 2. Update MALL_SEL register 697 * 3. Program FORCE_ONE_ROW_FOR_FRAME for main subvp pipes 698 */ 699 void dcn32_program_mall_pipe_config(struct dc *dc, struct dc_state *context) 700 { 701 int i; 702 struct dce_hwseq *hws = dc->hwseq; 703 704 // Don't force p-state disallow -- can't block dummy p-state 705 706 // Update MALL_SEL register for each pipe 707 if (hws && hws->funcs.update_mall_sel) 708 hws->funcs.update_mall_sel(dc, context); 709 710 // Program FORCE_ONE_ROW_FOR_FRAME and CURSOR_REQ_MODE for main subvp pipes 711 for (i = 0; i < dc->res_pool->pipe_count; i++) { 712 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; 713 struct hubp *hubp = pipe->plane_res.hubp; 714 715 if (pipe->stream && hubp && hubp->funcs->hubp_prepare_subvp_buffering) { 716 /* TODO - remove setting CURSOR_REQ_MODE to 0 for legacy cases 717 * - need to investigate single pipe MPO + SubVP case to 718 * see if CURSOR_REQ_MODE will be back to 1 for SubVP 719 * when it should be 0 for MPO 720 */ 721 if (pipe->stream->mall_stream_config.type == SUBVP_MAIN) { 722 hubp->funcs->hubp_prepare_subvp_buffering(hubp, true); 723 } 724 } 725 } 726 } 727 728 void dcn32_init_hw(struct dc *dc) 729 { 730 struct abm **abms = dc->res_pool->multiple_abms; 731 struct dce_hwseq *hws = dc->hwseq; 732 struct dc_bios *dcb = dc->ctx->dc_bios; 733 struct resource_pool *res_pool = dc->res_pool; 734 int i; 735 int edp_num; 736 uint32_t backlight = MAX_BACKLIGHT_LEVEL; 737 738 if (dc->clk_mgr && dc->clk_mgr->funcs->init_clocks) 739 dc->clk_mgr->funcs->init_clocks(dc->clk_mgr); 740 741 // Initialize the dccg 742 if (res_pool->dccg->funcs->dccg_init) 743 res_pool->dccg->funcs->dccg_init(res_pool->dccg); 744 745 if (!dcb->funcs->is_accelerated_mode(dcb)) { 746 hws->funcs.bios_golden_init(dc); 747 hws->funcs.disable_vga(dc->hwseq); 748 } 749 750 // Set default OPTC memory power states 751 if (dc->debug.enable_mem_low_power.bits.optc) { 752 // Shutdown when unassigned and light sleep in VBLANK 753 REG_SET_2(ODM_MEM_PWR_CTRL3, 0, ODM_MEM_UNASSIGNED_PWR_MODE, 3, ODM_MEM_VBLANK_PWR_MODE, 1); 754 } 755 756 if (dc->debug.enable_mem_low_power.bits.vga) { 757 // Power down VGA memory 758 REG_UPDATE(MMHUBBUB_MEM_PWR_CNTL, VGA_MEM_PWR_FORCE, 1); 759 } 760 761 if (dc->ctx->dc_bios->fw_info_valid) { 762 res_pool->ref_clocks.xtalin_clock_inKhz = 763 dc->ctx->dc_bios->fw_info.pll_info.crystal_frequency; 764 765 if (res_pool->dccg && res_pool->hubbub) { 766 (res_pool->dccg->funcs->get_dccg_ref_freq)(res_pool->dccg, 767 dc->ctx->dc_bios->fw_info.pll_info.crystal_frequency, 768 &res_pool->ref_clocks.dccg_ref_clock_inKhz); 769 770 (res_pool->hubbub->funcs->get_dchub_ref_freq)(res_pool->hubbub, 771 res_pool->ref_clocks.dccg_ref_clock_inKhz, 772 &res_pool->ref_clocks.dchub_ref_clock_inKhz); 773 } else { 774 // Not all ASICs have DCCG sw component 775 res_pool->ref_clocks.dccg_ref_clock_inKhz = 776 res_pool->ref_clocks.xtalin_clock_inKhz; 777 res_pool->ref_clocks.dchub_ref_clock_inKhz = 778 res_pool->ref_clocks.xtalin_clock_inKhz; 779 } 780 } else 781 ASSERT_CRITICAL(false); 782 783 for (i = 0; i < dc->link_count; i++) { 784 /* Power up AND update implementation according to the 785 * required signal (which may be different from the 786 * default signal on connector). 787 */ 788 struct dc_link *link = dc->links[i]; 789 790 link->link_enc->funcs->hw_init(link->link_enc); 791 792 /* Check for enabled DIG to identify enabled display */ 793 if (link->link_enc->funcs->is_dig_enabled && 794 link->link_enc->funcs->is_dig_enabled(link->link_enc)) { 795 link->link_status.link_active = true; 796 if (link->link_enc->funcs->fec_is_active && 797 link->link_enc->funcs->fec_is_active(link->link_enc)) 798 link->fec_state = dc_link_fec_enabled; 799 } 800 } 801 802 /* Power gate DSCs */ 803 for (i = 0; i < res_pool->res_cap->num_dsc; i++) 804 if (hws->funcs.dsc_pg_control != NULL) 805 hws->funcs.dsc_pg_control(hws, res_pool->dscs[i]->inst, false); 806 807 /* we want to turn off all dp displays before doing detection */ 808 dc_link_blank_all_dp_displays(dc); 809 810 /* If taking control over from VBIOS, we may want to optimize our first 811 * mode set, so we need to skip powering down pipes until we know which 812 * pipes we want to use. 813 * Otherwise, if taking control is not possible, we need to power 814 * everything down. 815 */ 816 if (dcb->funcs->is_accelerated_mode(dcb) || !dc->config.seamless_boot_edp_requested) { 817 hws->funcs.init_pipes(dc, dc->current_state); 818 if (dc->res_pool->hubbub->funcs->allow_self_refresh_control) 819 dc->res_pool->hubbub->funcs->allow_self_refresh_control(dc->res_pool->hubbub, 820 !dc->res_pool->hubbub->ctx->dc->debug.disable_stutter); 821 } 822 823 /* In headless boot cases, DIG may be turned 824 * on which causes HW/SW discrepancies. 825 * To avoid this, power down hardware on boot 826 * if DIG is turned on and seamless boot not enabled 827 */ 828 if (!dc->config.seamless_boot_edp_requested) { 829 struct dc_link *edp_links[MAX_NUM_EDP]; 830 struct dc_link *edp_link; 831 832 get_edp_links(dc, edp_links, &edp_num); 833 if (edp_num) { 834 for (i = 0; i < edp_num; i++) { 835 edp_link = edp_links[i]; 836 if (edp_link->link_enc->funcs->is_dig_enabled && 837 edp_link->link_enc->funcs->is_dig_enabled(edp_link->link_enc) && 838 dc->hwss.edp_backlight_control && 839 dc->hwss.power_down && 840 dc->hwss.edp_power_control) { 841 dc->hwss.edp_backlight_control(edp_link, false); 842 dc->hwss.power_down(dc); 843 dc->hwss.edp_power_control(edp_link, false); 844 } 845 } 846 } else { 847 for (i = 0; i < dc->link_count; i++) { 848 struct dc_link *link = dc->links[i]; 849 850 if (link->link_enc->funcs->is_dig_enabled && 851 link->link_enc->funcs->is_dig_enabled(link->link_enc) && 852 dc->hwss.power_down) { 853 dc->hwss.power_down(dc); 854 break; 855 } 856 857 } 858 } 859 } 860 861 for (i = 0; i < res_pool->audio_count; i++) { 862 struct audio *audio = res_pool->audios[i]; 863 864 audio->funcs->hw_init(audio); 865 } 866 867 for (i = 0; i < dc->link_count; i++) { 868 struct dc_link *link = dc->links[i]; 869 870 if (link->panel_cntl) 871 backlight = link->panel_cntl->funcs->hw_init(link->panel_cntl); 872 } 873 874 for (i = 0; i < dc->res_pool->pipe_count; i++) { 875 if (abms[i] != NULL && abms[i]->funcs != NULL) 876 abms[i]->funcs->abm_init(abms[i], backlight); 877 } 878 879 /* power AFMT HDMI memory TODO: may move to dis/en output save power*/ 880 REG_WRITE(DIO_MEM_PWR_CTRL, 0); 881 882 if (!dc->debug.disable_clock_gate) { 883 /* enable all DCN clock gating */ 884 REG_WRITE(DCCG_GATE_DISABLE_CNTL, 0); 885 886 REG_WRITE(DCCG_GATE_DISABLE_CNTL2, 0); 887 888 REG_UPDATE(DCFCLK_CNTL, DCFCLK_GATE_DIS, 0); 889 } 890 if (hws->funcs.enable_power_gating_plane) 891 hws->funcs.enable_power_gating_plane(dc->hwseq, true); 892 893 if (!dcb->funcs->is_accelerated_mode(dcb) && dc->res_pool->hubbub->funcs->init_watermarks) 894 dc->res_pool->hubbub->funcs->init_watermarks(dc->res_pool->hubbub); 895 896 if (dc->clk_mgr->funcs->notify_wm_ranges) 897 dc->clk_mgr->funcs->notify_wm_ranges(dc->clk_mgr); 898 899 if (dc->clk_mgr->funcs->set_hard_max_memclk) 900 dc->clk_mgr->funcs->set_hard_max_memclk(dc->clk_mgr); 901 902 if (dc->res_pool->hubbub->funcs->force_pstate_change_control) 903 dc->res_pool->hubbub->funcs->force_pstate_change_control( 904 dc->res_pool->hubbub, false, false); 905 906 if (dc->res_pool->hubbub->funcs->init_crb) 907 dc->res_pool->hubbub->funcs->init_crb(dc->res_pool->hubbub); 908 909 // Get DMCUB capabilities 910 if (dc->ctx->dmub_srv) { 911 dc_dmub_srv_query_caps_cmd(dc->ctx->dmub_srv->dmub); 912 dc->caps.dmub_caps.psr = dc->ctx->dmub_srv->dmub->feature_caps.psr; 913 } 914 } 915 916 static int calc_mpc_flow_ctrl_cnt(const struct dc_stream_state *stream, 917 int opp_cnt) 918 { 919 bool hblank_halved = optc2_is_two_pixels_per_containter(&stream->timing); 920 int flow_ctrl_cnt; 921 922 if (opp_cnt >= 2) 923 hblank_halved = true; 924 925 flow_ctrl_cnt = stream->timing.h_total - stream->timing.h_addressable - 926 stream->timing.h_border_left - 927 stream->timing.h_border_right; 928 929 if (hblank_halved) 930 flow_ctrl_cnt /= 2; 931 932 /* ODM combine 4:1 case */ 933 if (opp_cnt == 4) 934 flow_ctrl_cnt /= 2; 935 936 return flow_ctrl_cnt; 937 } 938 939 static void update_dsc_on_stream(struct pipe_ctx *pipe_ctx, bool enable) 940 { 941 struct display_stream_compressor *dsc = pipe_ctx->stream_res.dsc; 942 struct dc_stream_state *stream = pipe_ctx->stream; 943 struct pipe_ctx *odm_pipe; 944 int opp_cnt = 1; 945 946 ASSERT(dsc); 947 for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) 948 opp_cnt++; 949 950 if (enable) { 951 struct dsc_config dsc_cfg; 952 struct dsc_optc_config dsc_optc_cfg; 953 enum optc_dsc_mode optc_dsc_mode; 954 955 /* Enable DSC hw block */ 956 dsc_cfg.pic_width = (stream->timing.h_addressable + stream->timing.h_border_left + stream->timing.h_border_right) / opp_cnt; 957 dsc_cfg.pic_height = stream->timing.v_addressable + stream->timing.v_border_top + stream->timing.v_border_bottom; 958 dsc_cfg.pixel_encoding = stream->timing.pixel_encoding; 959 dsc_cfg.color_depth = stream->timing.display_color_depth; 960 dsc_cfg.is_odm = pipe_ctx->next_odm_pipe ? true : false; 961 dsc_cfg.dc_dsc_cfg = stream->timing.dsc_cfg; 962 ASSERT(dsc_cfg.dc_dsc_cfg.num_slices_h % opp_cnt == 0); 963 dsc_cfg.dc_dsc_cfg.num_slices_h /= opp_cnt; 964 965 dsc->funcs->dsc_set_config(dsc, &dsc_cfg, &dsc_optc_cfg); 966 dsc->funcs->dsc_enable(dsc, pipe_ctx->stream_res.opp->inst); 967 for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) { 968 struct display_stream_compressor *odm_dsc = odm_pipe->stream_res.dsc; 969 970 ASSERT(odm_dsc); 971 odm_dsc->funcs->dsc_set_config(odm_dsc, &dsc_cfg, &dsc_optc_cfg); 972 odm_dsc->funcs->dsc_enable(odm_dsc, odm_pipe->stream_res.opp->inst); 973 } 974 dsc_cfg.dc_dsc_cfg.num_slices_h *= opp_cnt; 975 dsc_cfg.pic_width *= opp_cnt; 976 977 optc_dsc_mode = dsc_optc_cfg.is_pixel_format_444 ? OPTC_DSC_ENABLED_444 : OPTC_DSC_ENABLED_NATIVE_SUBSAMPLED; 978 979 /* Enable DSC in OPTC */ 980 DC_LOG_DSC("Setting optc DSC config for tg instance %d:", pipe_ctx->stream_res.tg->inst); 981 pipe_ctx->stream_res.tg->funcs->set_dsc_config(pipe_ctx->stream_res.tg, 982 optc_dsc_mode, 983 dsc_optc_cfg.bytes_per_pixel, 984 dsc_optc_cfg.slice_width); 985 } else { 986 /* disable DSC in OPTC */ 987 pipe_ctx->stream_res.tg->funcs->set_dsc_config( 988 pipe_ctx->stream_res.tg, 989 OPTC_DSC_DISABLED, 0, 0); 990 991 /* disable DSC block */ 992 dsc->funcs->dsc_disable(pipe_ctx->stream_res.dsc); 993 for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) { 994 ASSERT(odm_pipe->stream_res.dsc); 995 odm_pipe->stream_res.dsc->funcs->dsc_disable(odm_pipe->stream_res.dsc); 996 } 997 } 998 } 999 1000 /* 1001 * Given any pipe_ctx, return the total ODM combine factor, and optionally return 1002 * the OPPids which are used 1003 * */ 1004 static unsigned int get_odm_config(struct pipe_ctx *pipe_ctx, unsigned int *opp_instances) 1005 { 1006 unsigned int opp_count = 1; 1007 struct pipe_ctx *odm_pipe; 1008 1009 /* First get to the top pipe */ 1010 for (odm_pipe = pipe_ctx; odm_pipe->prev_odm_pipe; odm_pipe = odm_pipe->prev_odm_pipe) 1011 ; 1012 1013 /* First pipe is always used */ 1014 if (opp_instances) 1015 opp_instances[0] = odm_pipe->stream_res.opp->inst; 1016 1017 /* Find and count odm pipes, if any */ 1018 for (odm_pipe = odm_pipe->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) { 1019 if (opp_instances) 1020 opp_instances[opp_count] = odm_pipe->stream_res.opp->inst; 1021 opp_count++; 1022 } 1023 1024 return opp_count; 1025 } 1026 1027 void dcn32_update_odm(struct dc *dc, struct dc_state *context, struct pipe_ctx *pipe_ctx) 1028 { 1029 struct pipe_ctx *odm_pipe; 1030 int opp_cnt = 0; 1031 int opp_inst[MAX_PIPES] = {0}; 1032 bool rate_control_2x_pclk = (pipe_ctx->stream->timing.flags.INTERLACE || optc2_is_two_pixels_per_containter(&pipe_ctx->stream->timing)); 1033 struct mpc_dwb_flow_control flow_control; 1034 struct mpc *mpc = dc->res_pool->mpc; 1035 int i; 1036 1037 opp_cnt = get_odm_config(pipe_ctx, opp_inst); 1038 1039 if (opp_cnt > 1) 1040 pipe_ctx->stream_res.tg->funcs->set_odm_combine( 1041 pipe_ctx->stream_res.tg, 1042 opp_inst, opp_cnt, 1043 &pipe_ctx->stream->timing); 1044 else 1045 pipe_ctx->stream_res.tg->funcs->set_odm_bypass( 1046 pipe_ctx->stream_res.tg, &pipe_ctx->stream->timing); 1047 1048 rate_control_2x_pclk = rate_control_2x_pclk || opp_cnt > 1; 1049 flow_control.flow_ctrl_mode = 0; 1050 flow_control.flow_ctrl_cnt0 = 0x80; 1051 flow_control.flow_ctrl_cnt1 = calc_mpc_flow_ctrl_cnt(pipe_ctx->stream, opp_cnt); 1052 if (mpc->funcs->set_out_rate_control) { 1053 for (i = 0; i < opp_cnt; ++i) { 1054 mpc->funcs->set_out_rate_control( 1055 mpc, opp_inst[i], 1056 true, 1057 rate_control_2x_pclk, 1058 &flow_control); 1059 } 1060 } 1061 1062 for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) { 1063 odm_pipe->stream_res.opp->funcs->opp_pipe_clock_control( 1064 odm_pipe->stream_res.opp, 1065 true); 1066 } 1067 1068 // Don't program pixel clock after link is already enabled 1069 /* if (false == pipe_ctx->clock_source->funcs->program_pix_clk( 1070 pipe_ctx->clock_source, 1071 &pipe_ctx->stream_res.pix_clk_params, 1072 &pipe_ctx->pll_settings)) { 1073 BREAK_TO_DEBUGGER(); 1074 }*/ 1075 1076 if (pipe_ctx->stream_res.dsc) 1077 update_dsc_on_stream(pipe_ctx, pipe_ctx->stream->timing.flags.DSC); 1078 } 1079 1080 unsigned int dcn32_calculate_dccg_k1_k2_values(struct pipe_ctx *pipe_ctx, unsigned int *k1_div, unsigned int *k2_div) 1081 { 1082 struct dc_stream_state *stream = pipe_ctx->stream; 1083 unsigned int odm_combine_factor = 0; 1084 struct dc *dc = pipe_ctx->stream->ctx->dc; 1085 bool two_pix_per_container = optc2_is_two_pixels_per_containter(&stream->timing); 1086 1087 odm_combine_factor = get_odm_config(pipe_ctx, NULL); 1088 1089 if (is_dp_128b_132b_signal(pipe_ctx)) { 1090 *k2_div = PIXEL_RATE_DIV_BY_1; 1091 } else if (dc_is_hdmi_tmds_signal(pipe_ctx->stream->signal) || dc_is_dvi_signal(pipe_ctx->stream->signal)) { 1092 *k1_div = PIXEL_RATE_DIV_BY_1; 1093 if (stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR420) 1094 *k2_div = PIXEL_RATE_DIV_BY_2; 1095 else 1096 *k2_div = PIXEL_RATE_DIV_BY_4; 1097 } else if (dc_is_dp_signal(pipe_ctx->stream->signal)) { 1098 if (two_pix_per_container) { 1099 *k1_div = PIXEL_RATE_DIV_BY_1; 1100 *k2_div = PIXEL_RATE_DIV_BY_2; 1101 } else { 1102 *k1_div = PIXEL_RATE_DIV_BY_1; 1103 *k2_div = PIXEL_RATE_DIV_BY_4; 1104 if ((odm_combine_factor == 2) || dc->debug.enable_dp_dig_pixel_rate_div_policy) 1105 *k2_div = PIXEL_RATE_DIV_BY_2; 1106 } 1107 } 1108 1109 if ((*k1_div == PIXEL_RATE_DIV_NA) && (*k2_div == PIXEL_RATE_DIV_NA)) 1110 ASSERT(false); 1111 1112 return odm_combine_factor; 1113 } 1114 1115 void dcn32_set_pixels_per_cycle(struct pipe_ctx *pipe_ctx) 1116 { 1117 uint32_t pix_per_cycle = 1; 1118 uint32_t odm_combine_factor = 1; 1119 1120 if (!pipe_ctx || !pipe_ctx->stream || !pipe_ctx->stream_res.stream_enc) 1121 return; 1122 1123 odm_combine_factor = get_odm_config(pipe_ctx, NULL); 1124 if (optc2_is_two_pixels_per_containter(&pipe_ctx->stream->timing) || odm_combine_factor > 1 1125 || dcn32_is_dp_dig_pixel_rate_div_policy(pipe_ctx)) 1126 pix_per_cycle = 2; 1127 1128 if (pipe_ctx->stream_res.stream_enc->funcs->set_input_mode) 1129 pipe_ctx->stream_res.stream_enc->funcs->set_input_mode(pipe_ctx->stream_res.stream_enc, 1130 pix_per_cycle); 1131 } 1132 1133 void dcn32_unblank_stream(struct pipe_ctx *pipe_ctx, 1134 struct dc_link_settings *link_settings) 1135 { 1136 struct encoder_unblank_param params = {0}; 1137 struct dc_stream_state *stream = pipe_ctx->stream; 1138 struct dc_link *link = stream->link; 1139 struct dce_hwseq *hws = link->dc->hwseq; 1140 struct pipe_ctx *odm_pipe; 1141 struct dc *dc = pipe_ctx->stream->ctx->dc; 1142 uint32_t pix_per_cycle = 1; 1143 1144 params.opp_cnt = 1; 1145 for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) 1146 params.opp_cnt++; 1147 1148 /* only 3 items below are used by unblank */ 1149 params.timing = pipe_ctx->stream->timing; 1150 1151 params.link_settings.link_rate = link_settings->link_rate; 1152 1153 if (is_dp_128b_132b_signal(pipe_ctx)) { 1154 /* TODO - DP2.0 HW: Set ODM mode in dp hpo encoder here */ 1155 pipe_ctx->stream_res.hpo_dp_stream_enc->funcs->dp_unblank( 1156 pipe_ctx->stream_res.hpo_dp_stream_enc, 1157 pipe_ctx->stream_res.tg->inst); 1158 } else if (dc_is_dp_signal(pipe_ctx->stream->signal)) { 1159 if (optc2_is_two_pixels_per_containter(&stream->timing) || params.opp_cnt > 1 1160 || dc->debug.enable_dp_dig_pixel_rate_div_policy) { 1161 params.timing.pix_clk_100hz /= 2; 1162 pix_per_cycle = 2; 1163 } 1164 pipe_ctx->stream_res.stream_enc->funcs->dp_set_odm_combine( 1165 pipe_ctx->stream_res.stream_enc, pix_per_cycle > 1); 1166 pipe_ctx->stream_res.stream_enc->funcs->dp_unblank(link, pipe_ctx->stream_res.stream_enc, ¶ms); 1167 } 1168 1169 if (link->local_sink && link->local_sink->sink_signal == SIGNAL_TYPE_EDP) 1170 hws->funcs.edp_backlight_control(link, true); 1171 } 1172 1173 bool dcn32_is_dp_dig_pixel_rate_div_policy(struct pipe_ctx *pipe_ctx) 1174 { 1175 struct dc *dc = pipe_ctx->stream->ctx->dc; 1176 1177 if (dc_is_dp_signal(pipe_ctx->stream->signal) && !is_dp_128b_132b_signal(pipe_ctx) && 1178 dc->debug.enable_dp_dig_pixel_rate_div_policy) 1179 return true; 1180 return false; 1181 } 1182