1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 27 #include "dm_services.h" 28 #include "dm_helpers.h" 29 #include "core_types.h" 30 #include "resource.h" 31 #include "dccg.h" 32 #include "dce/dce_hwseq.h" 33 #include "dcn30/dcn30_cm_common.h" 34 #include "reg_helper.h" 35 #include "abm.h" 36 #include "hubp.h" 37 #include "dchubbub.h" 38 #include "timing_generator.h" 39 #include "opp.h" 40 #include "ipp.h" 41 #include "mpc.h" 42 #include "mcif_wb.h" 43 #include "dc_dmub_srv.h" 44 #include "link_hwss.h" 45 #include "dpcd_defs.h" 46 #include "dcn32_hwseq.h" 47 #include "clk_mgr.h" 48 #include "dsc.h" 49 #include "dcn20/dcn20_optc.h" 50 #include "dmub_subvp_state.h" 51 #include "dce/dmub_hw_lock_mgr.h" 52 #include "dcn32_resource.h" 53 #include "link.h" 54 #include "dmub/inc/dmub_subvp_state.h" 55 56 #define DC_LOGGER_INIT(logger) 57 58 #define CTX \ 59 hws->ctx 60 #define REG(reg)\ 61 hws->regs->reg 62 #define DC_LOGGER \ 63 dc->ctx->logger 64 65 66 #undef FN 67 #define FN(reg_name, field_name) \ 68 hws->shifts->field_name, hws->masks->field_name 69 70 void dcn32_dsc_pg_control( 71 struct dce_hwseq *hws, 72 unsigned int dsc_inst, 73 bool power_on) 74 { 75 uint32_t power_gate = power_on ? 0 : 1; 76 uint32_t pwr_status = power_on ? 0 : 2; 77 uint32_t org_ip_request_cntl = 0; 78 79 if (hws->ctx->dc->debug.disable_dsc_power_gate) 80 return; 81 82 REG_GET(DC_IP_REQUEST_CNTL, IP_REQUEST_EN, &org_ip_request_cntl); 83 if (org_ip_request_cntl == 0) 84 REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 1); 85 86 switch (dsc_inst) { 87 case 0: /* DSC0 */ 88 REG_UPDATE(DOMAIN16_PG_CONFIG, 89 DOMAIN_POWER_GATE, power_gate); 90 91 REG_WAIT(DOMAIN16_PG_STATUS, 92 DOMAIN_PGFSM_PWR_STATUS, pwr_status, 93 1, 1000); 94 break; 95 case 1: /* DSC1 */ 96 REG_UPDATE(DOMAIN17_PG_CONFIG, 97 DOMAIN_POWER_GATE, power_gate); 98 99 REG_WAIT(DOMAIN17_PG_STATUS, 100 DOMAIN_PGFSM_PWR_STATUS, pwr_status, 101 1, 1000); 102 break; 103 case 2: /* DSC2 */ 104 REG_UPDATE(DOMAIN18_PG_CONFIG, 105 DOMAIN_POWER_GATE, power_gate); 106 107 REG_WAIT(DOMAIN18_PG_STATUS, 108 DOMAIN_PGFSM_PWR_STATUS, pwr_status, 109 1, 1000); 110 break; 111 case 3: /* DSC3 */ 112 REG_UPDATE(DOMAIN19_PG_CONFIG, 113 DOMAIN_POWER_GATE, power_gate); 114 115 REG_WAIT(DOMAIN19_PG_STATUS, 116 DOMAIN_PGFSM_PWR_STATUS, pwr_status, 117 1, 1000); 118 break; 119 default: 120 BREAK_TO_DEBUGGER(); 121 break; 122 } 123 124 if (org_ip_request_cntl == 0) 125 REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 0); 126 } 127 128 129 void dcn32_enable_power_gating_plane( 130 struct dce_hwseq *hws, 131 bool enable) 132 { 133 bool force_on = true; /* disable power gating */ 134 uint32_t org_ip_request_cntl = 0; 135 136 if (enable) 137 force_on = false; 138 139 REG_GET(DC_IP_REQUEST_CNTL, IP_REQUEST_EN, &org_ip_request_cntl); 140 if (org_ip_request_cntl == 0) 141 REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 1); 142 143 /* DCHUBP0/1/2/3 */ 144 REG_UPDATE(DOMAIN0_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on); 145 REG_UPDATE(DOMAIN1_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on); 146 REG_UPDATE(DOMAIN2_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on); 147 REG_UPDATE(DOMAIN3_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on); 148 149 /* DCS0/1/2/3 */ 150 REG_UPDATE(DOMAIN16_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on); 151 REG_UPDATE(DOMAIN17_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on); 152 REG_UPDATE(DOMAIN18_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on); 153 REG_UPDATE(DOMAIN19_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on); 154 155 if (org_ip_request_cntl == 0) 156 REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 0); 157 } 158 159 void dcn32_hubp_pg_control(struct dce_hwseq *hws, unsigned int hubp_inst, bool power_on) 160 { 161 uint32_t power_gate = power_on ? 0 : 1; 162 uint32_t pwr_status = power_on ? 0 : 2; 163 164 if (hws->ctx->dc->debug.disable_hubp_power_gate) 165 return; 166 167 if (REG(DOMAIN0_PG_CONFIG) == 0) 168 return; 169 170 switch (hubp_inst) { 171 case 0: 172 REG_SET(DOMAIN0_PG_CONFIG, 0, DOMAIN_POWER_GATE, power_gate); 173 REG_WAIT(DOMAIN0_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, pwr_status, 1, 1000); 174 break; 175 case 1: 176 REG_SET(DOMAIN1_PG_CONFIG, 0, DOMAIN_POWER_GATE, power_gate); 177 REG_WAIT(DOMAIN1_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, pwr_status, 1, 1000); 178 break; 179 case 2: 180 REG_SET(DOMAIN2_PG_CONFIG, 0, DOMAIN_POWER_GATE, power_gate); 181 REG_WAIT(DOMAIN2_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, pwr_status, 1, 1000); 182 break; 183 case 3: 184 REG_SET(DOMAIN3_PG_CONFIG, 0, DOMAIN_POWER_GATE, power_gate); 185 REG_WAIT(DOMAIN3_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, pwr_status, 1, 1000); 186 break; 187 default: 188 BREAK_TO_DEBUGGER(); 189 break; 190 } 191 } 192 193 static bool dcn32_check_no_memory_request_for_cab(struct dc *dc) 194 { 195 int i; 196 197 /* First, check no-memory-request case */ 198 for (i = 0; i < dc->current_state->stream_count; i++) { 199 if ((dc->current_state->stream_status[i].plane_count) && 200 (dc->current_state->streams[i]->link->psr_settings.psr_version == DC_PSR_VERSION_UNSUPPORTED)) 201 /* Fail eligibility on a visible stream */ 202 break; 203 } 204 205 if (i == dc->current_state->stream_count) 206 return true; 207 208 return false; 209 } 210 211 212 /* This function loops through every surface that needs to be cached in CAB for SS, 213 * and calculates the total number of ways required to store all surfaces (primary, 214 * meta, cursor). 215 */ 216 static uint32_t dcn32_calculate_cab_allocation(struct dc *dc, struct dc_state *ctx) 217 { 218 int i; 219 uint8_t num_ways = 0; 220 uint32_t mall_ss_size_bytes = 0; 221 222 mall_ss_size_bytes = ctx->bw_ctx.bw.dcn.mall_ss_size_bytes; 223 // TODO add additional logic for PSR active stream exclusion optimization 224 // mall_ss_psr_active_size_bytes = ctx->bw_ctx.bw.dcn.mall_ss_psr_active_size_bytes; 225 226 // Include cursor size for CAB allocation 227 for (i = 0; i < dc->res_pool->pipe_count; i++) { 228 struct pipe_ctx *pipe = &ctx->res_ctx.pipe_ctx[i]; 229 230 if (!pipe->stream || !pipe->plane_state) 231 continue; 232 233 mall_ss_size_bytes += dcn32_helper_calculate_mall_bytes_for_cursor(dc, pipe, false); 234 } 235 236 // Convert number of cache lines required to number of ways 237 if (dc->debug.force_mall_ss_num_ways > 0) { 238 num_ways = dc->debug.force_mall_ss_num_ways; 239 } else { 240 num_ways = dcn32_helper_mall_bytes_to_ways(dc, mall_ss_size_bytes); 241 } 242 243 return num_ways; 244 } 245 246 bool dcn32_apply_idle_power_optimizations(struct dc *dc, bool enable) 247 { 248 union dmub_rb_cmd cmd; 249 uint8_t ways, i; 250 int j; 251 bool mall_ss_unsupported = false; 252 struct dc_plane_state *plane = NULL; 253 254 if (!dc->ctx->dmub_srv) 255 return false; 256 257 for (i = 0; i < dc->current_state->stream_count; i++) { 258 /* MALL SS messaging is not supported with PSR at this time */ 259 if (dc->current_state->streams[i] != NULL && 260 dc->current_state->streams[i]->link->psr_settings.psr_version != DC_PSR_VERSION_UNSUPPORTED) 261 return false; 262 } 263 264 if (enable) { 265 if (dc->current_state) { 266 267 /* 1. Check no memory request case for CAB. 268 * If no memory request case, send CAB_ACTION NO_DF_REQ DMUB message 269 */ 270 if (dcn32_check_no_memory_request_for_cab(dc)) { 271 /* Enable no-memory-requests case */ 272 memset(&cmd, 0, sizeof(cmd)); 273 cmd.cab.header.type = DMUB_CMD__CAB_FOR_SS; 274 cmd.cab.header.sub_type = DMUB_CMD__CAB_NO_DCN_REQ; 275 cmd.cab.header.payload_bytes = sizeof(cmd.cab) - sizeof(cmd.cab.header); 276 277 dc_dmub_srv_cmd_queue(dc->ctx->dmub_srv, &cmd); 278 dc_dmub_srv_cmd_execute(dc->ctx->dmub_srv); 279 280 return true; 281 } 282 283 /* 2. Check if all surfaces can fit in CAB. 284 * If surfaces can fit into CAB, send CAB_ACTION_ALLOW DMUB message 285 * and configure HUBP's to fetch from MALL 286 */ 287 ways = dcn32_calculate_cab_allocation(dc, dc->current_state); 288 289 /* MALL not supported with Stereo3D or TMZ surface. If any plane is using stereo, 290 * or TMZ surface, don't try to enter MALL. 291 */ 292 for (i = 0; i < dc->current_state->stream_count; i++) { 293 for (j = 0; j < dc->current_state->stream_status[i].plane_count; j++) { 294 plane = dc->current_state->stream_status[i].plane_states[j]; 295 296 if (plane->address.type == PLN_ADDR_TYPE_GRPH_STEREO || 297 plane->address.tmz_surface) { 298 mall_ss_unsupported = true; 299 break; 300 } 301 } 302 if (mall_ss_unsupported) 303 break; 304 } 305 if (ways <= dc->caps.cache_num_ways && !mall_ss_unsupported) { 306 memset(&cmd, 0, sizeof(cmd)); 307 cmd.cab.header.type = DMUB_CMD__CAB_FOR_SS; 308 cmd.cab.header.sub_type = DMUB_CMD__CAB_DCN_SS_FIT_IN_CAB; 309 cmd.cab.header.payload_bytes = sizeof(cmd.cab) - sizeof(cmd.cab.header); 310 cmd.cab.cab_alloc_ways = ways; 311 312 dc_dmub_srv_cmd_queue(dc->ctx->dmub_srv, &cmd); 313 dc_dmub_srv_cmd_execute(dc->ctx->dmub_srv); 314 315 return true; 316 } 317 318 } 319 return false; 320 } 321 322 /* Disable CAB */ 323 memset(&cmd, 0, sizeof(cmd)); 324 cmd.cab.header.type = DMUB_CMD__CAB_FOR_SS; 325 cmd.cab.header.sub_type = DMUB_CMD__CAB_NO_IDLE_OPTIMIZATION; 326 cmd.cab.header.payload_bytes = 327 sizeof(cmd.cab) - sizeof(cmd.cab.header); 328 329 dc_dmub_srv_cmd_queue(dc->ctx->dmub_srv, &cmd); 330 dc_dmub_srv_cmd_execute(dc->ctx->dmub_srv); 331 dc_dmub_srv_wait_idle(dc->ctx->dmub_srv); 332 333 return true; 334 } 335 336 /* Send DMCUB message with SubVP pipe info 337 * - For each pipe in context, populate payload with required SubVP information 338 * if the pipe is using SubVP for MCLK switch 339 * - This function must be called while the DMUB HW lock is acquired by driver 340 */ 341 void dcn32_commit_subvp_config(struct dc *dc, struct dc_state *context) 342 { 343 int i; 344 bool enable_subvp = false; 345 346 if (!dc->ctx || !dc->ctx->dmub_srv) 347 return; 348 349 for (i = 0; i < dc->res_pool->pipe_count; i++) { 350 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; 351 352 if (pipe_ctx->stream && pipe_ctx->stream->mall_stream_config.paired_stream && 353 pipe_ctx->stream->mall_stream_config.type == SUBVP_MAIN) { 354 // There is at least 1 SubVP pipe, so enable SubVP 355 enable_subvp = true; 356 break; 357 } 358 } 359 dc_dmub_setup_subvp_dmub_command(dc, context, enable_subvp); 360 } 361 362 /* Sub-Viewport DMUB lock needs to be acquired by driver whenever SubVP is active and: 363 * 1. Any full update for any SubVP main pipe 364 * 2. Any immediate flip for any SubVP pipe 365 * 3. Any flip for DRR pipe 366 * 4. If SubVP was previously in use (i.e. in old context) 367 */ 368 void dcn32_subvp_pipe_control_lock(struct dc *dc, 369 struct dc_state *context, 370 bool lock, 371 bool should_lock_all_pipes, 372 struct pipe_ctx *top_pipe_to_program, 373 bool subvp_prev_use) 374 { 375 unsigned int i = 0; 376 bool subvp_immediate_flip = false; 377 bool subvp_in_use = false; 378 struct pipe_ctx *pipe; 379 380 for (i = 0; i < dc->res_pool->pipe_count; i++) { 381 pipe = &context->res_ctx.pipe_ctx[i]; 382 383 if (pipe->stream && pipe->plane_state && pipe->stream->mall_stream_config.type == SUBVP_MAIN) { 384 subvp_in_use = true; 385 break; 386 } 387 } 388 389 if (top_pipe_to_program && top_pipe_to_program->stream && top_pipe_to_program->plane_state) { 390 if (top_pipe_to_program->stream->mall_stream_config.type == SUBVP_MAIN && 391 top_pipe_to_program->plane_state->flip_immediate) 392 subvp_immediate_flip = true; 393 } 394 395 // Don't need to lock for DRR VSYNC flips -- FW will wait for DRR pending update cleared. 396 if ((subvp_in_use && (should_lock_all_pipes || subvp_immediate_flip)) || (!subvp_in_use && subvp_prev_use)) { 397 union dmub_inbox0_cmd_lock_hw hw_lock_cmd = { 0 }; 398 399 if (!lock) { 400 for (i = 0; i < dc->res_pool->pipe_count; i++) { 401 pipe = &context->res_ctx.pipe_ctx[i]; 402 if (pipe->stream && pipe->plane_state && pipe->stream->mall_stream_config.type == SUBVP_MAIN && 403 should_lock_all_pipes) 404 pipe->stream_res.tg->funcs->wait_for_state(pipe->stream_res.tg, CRTC_STATE_VBLANK); 405 } 406 } 407 408 hw_lock_cmd.bits.command_code = DMUB_INBOX0_CMD__HW_LOCK; 409 hw_lock_cmd.bits.hw_lock_client = HW_LOCK_CLIENT_DRIVER; 410 hw_lock_cmd.bits.lock = lock; 411 hw_lock_cmd.bits.should_release = !lock; 412 dmub_hw_lock_mgr_inbox0_cmd(dc->ctx->dmub_srv, hw_lock_cmd); 413 } 414 } 415 416 417 bool dcn32_set_mpc_shaper_3dlut( 418 struct pipe_ctx *pipe_ctx, const struct dc_stream_state *stream) 419 { 420 struct dpp *dpp_base = pipe_ctx->plane_res.dpp; 421 int mpcc_id = pipe_ctx->plane_res.hubp->inst; 422 struct mpc *mpc = pipe_ctx->stream_res.opp->ctx->dc->res_pool->mpc; 423 bool result = false; 424 425 const struct pwl_params *shaper_lut = NULL; 426 //get the shaper lut params 427 if (stream->func_shaper) { 428 if (stream->func_shaper->type == TF_TYPE_HWPWL) 429 shaper_lut = &stream->func_shaper->pwl; 430 else if (stream->func_shaper->type == TF_TYPE_DISTRIBUTED_POINTS) { 431 cm_helper_translate_curve_to_hw_format( 432 stream->func_shaper, 433 &dpp_base->shaper_params, true); 434 shaper_lut = &dpp_base->shaper_params; 435 } 436 } 437 438 if (stream->lut3d_func && 439 stream->lut3d_func->state.bits.initialized == 1) { 440 441 result = mpc->funcs->program_3dlut(mpc, 442 &stream->lut3d_func->lut_3d, 443 mpcc_id); 444 445 result = mpc->funcs->program_shaper(mpc, 446 shaper_lut, 447 mpcc_id); 448 } 449 450 return result; 451 } 452 453 bool dcn32_set_mcm_luts( 454 struct pipe_ctx *pipe_ctx, const struct dc_plane_state *plane_state) 455 { 456 struct dpp *dpp_base = pipe_ctx->plane_res.dpp; 457 int mpcc_id = pipe_ctx->plane_res.hubp->inst; 458 struct mpc *mpc = pipe_ctx->stream_res.opp->ctx->dc->res_pool->mpc; 459 bool result = true; 460 struct pwl_params *lut_params = NULL; 461 462 // 1D LUT 463 if (plane_state->blend_tf) { 464 if (plane_state->blend_tf->type == TF_TYPE_HWPWL) 465 lut_params = &plane_state->blend_tf->pwl; 466 else if (plane_state->blend_tf->type == TF_TYPE_DISTRIBUTED_POINTS) { 467 cm_helper_translate_curve_to_hw_format( 468 plane_state->blend_tf, 469 &dpp_base->regamma_params, false); 470 lut_params = &dpp_base->regamma_params; 471 } 472 } 473 result = mpc->funcs->program_1dlut(mpc, lut_params, mpcc_id); 474 475 // Shaper 476 if (plane_state->in_shaper_func) { 477 if (plane_state->in_shaper_func->type == TF_TYPE_HWPWL) 478 lut_params = &plane_state->in_shaper_func->pwl; 479 else if (plane_state->in_shaper_func->type == TF_TYPE_DISTRIBUTED_POINTS) { 480 // TODO: dpp_base replace 481 ASSERT(false); 482 cm_helper_translate_curve_to_hw_format( 483 plane_state->in_shaper_func, 484 &dpp_base->shaper_params, true); 485 lut_params = &dpp_base->shaper_params; 486 } 487 } 488 489 result = mpc->funcs->program_shaper(mpc, lut_params, mpcc_id); 490 491 // 3D 492 if (plane_state->lut3d_func && plane_state->lut3d_func->state.bits.initialized == 1) 493 result = mpc->funcs->program_3dlut(mpc, &plane_state->lut3d_func->lut_3d, mpcc_id); 494 else 495 result = mpc->funcs->program_3dlut(mpc, NULL, mpcc_id); 496 497 return result; 498 } 499 500 bool dcn32_set_input_transfer_func(struct dc *dc, 501 struct pipe_ctx *pipe_ctx, 502 const struct dc_plane_state *plane_state) 503 { 504 struct dce_hwseq *hws = dc->hwseq; 505 struct mpc *mpc = dc->res_pool->mpc; 506 struct dpp *dpp_base = pipe_ctx->plane_res.dpp; 507 508 enum dc_transfer_func_predefined tf; 509 bool result = true; 510 struct pwl_params *params = NULL; 511 512 if (mpc == NULL || plane_state == NULL) 513 return false; 514 515 tf = TRANSFER_FUNCTION_UNITY; 516 517 if (plane_state->in_transfer_func && 518 plane_state->in_transfer_func->type == TF_TYPE_PREDEFINED) 519 tf = plane_state->in_transfer_func->tf; 520 521 dpp_base->funcs->dpp_set_pre_degam(dpp_base, tf); 522 523 if (plane_state->in_transfer_func) { 524 if (plane_state->in_transfer_func->type == TF_TYPE_HWPWL) 525 params = &plane_state->in_transfer_func->pwl; 526 else if (plane_state->in_transfer_func->type == TF_TYPE_DISTRIBUTED_POINTS && 527 cm3_helper_translate_curve_to_hw_format(plane_state->in_transfer_func, 528 &dpp_base->degamma_params, false)) 529 params = &dpp_base->degamma_params; 530 } 531 532 dpp_base->funcs->dpp_program_gamcor_lut(dpp_base, params); 533 534 if (pipe_ctx->stream_res.opp && 535 pipe_ctx->stream_res.opp->ctx && 536 hws->funcs.set_mcm_luts) 537 result = hws->funcs.set_mcm_luts(pipe_ctx, plane_state); 538 539 return result; 540 } 541 542 bool dcn32_set_output_transfer_func(struct dc *dc, 543 struct pipe_ctx *pipe_ctx, 544 const struct dc_stream_state *stream) 545 { 546 int mpcc_id = pipe_ctx->plane_res.hubp->inst; 547 struct mpc *mpc = pipe_ctx->stream_res.opp->ctx->dc->res_pool->mpc; 548 struct pwl_params *params = NULL; 549 bool ret = false; 550 551 /* program OGAM or 3DLUT only for the top pipe*/ 552 if (pipe_ctx->top_pipe == NULL) { 553 /*program shaper and 3dlut in MPC*/ 554 ret = dcn32_set_mpc_shaper_3dlut(pipe_ctx, stream); 555 if (ret == false && mpc->funcs->set_output_gamma && stream->out_transfer_func) { 556 if (stream->out_transfer_func->type == TF_TYPE_HWPWL) 557 params = &stream->out_transfer_func->pwl; 558 else if (pipe_ctx->stream->out_transfer_func->type == 559 TF_TYPE_DISTRIBUTED_POINTS && 560 cm3_helper_translate_curve_to_hw_format( 561 stream->out_transfer_func, 562 &mpc->blender_params, false)) 563 params = &mpc->blender_params; 564 /* there are no ROM LUTs in OUTGAM */ 565 if (stream->out_transfer_func->type == TF_TYPE_PREDEFINED) 566 BREAK_TO_DEBUGGER(); 567 } 568 } 569 570 mpc->funcs->set_output_gamma(mpc, mpcc_id, params); 571 return ret; 572 } 573 574 /* Program P-State force value according to if pipe is using SubVP / FPO or not: 575 * 1. Reset P-State force on all pipes first 576 * 2. For each main pipe, force P-State disallow (P-State allow moderated by DMUB) 577 */ 578 void dcn32_update_force_pstate(struct dc *dc, struct dc_state *context) 579 { 580 int i; 581 582 /* Unforce p-state for each pipe if it is not FPO or SubVP. 583 * For FPO and SubVP, if it's already forced disallow, leave 584 * it as disallow. 585 */ 586 for (i = 0; i < dc->res_pool->pipe_count; i++) { 587 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; 588 struct hubp *hubp = pipe->plane_res.hubp; 589 590 if (!pipe->stream || (pipe->stream && !(pipe->stream->mall_stream_config.type == SUBVP_MAIN || 591 pipe->stream->fpo_in_use))) { 592 if (hubp && hubp->funcs->hubp_update_force_pstate_disallow) 593 hubp->funcs->hubp_update_force_pstate_disallow(hubp, false); 594 } 595 596 /* Today only FPO uses cursor P-State force. Only clear cursor P-State force 597 * if it's not FPO. 598 */ 599 if (!pipe->stream || (pipe->stream && !pipe->stream->fpo_in_use)) { 600 if (hubp && hubp->funcs->hubp_update_force_cursor_pstate_disallow) 601 hubp->funcs->hubp_update_force_cursor_pstate_disallow(hubp, false); 602 } 603 } 604 605 /* Loop through each pipe -- for each subvp main pipe force p-state allow equal to false. 606 */ 607 for (i = 0; i < dc->res_pool->pipe_count; i++) { 608 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; 609 struct hubp *hubp = pipe->plane_res.hubp; 610 611 if (pipe->stream && pipe->plane_state && pipe->stream->mall_stream_config.type == SUBVP_MAIN) { 612 if (hubp && hubp->funcs->hubp_update_force_pstate_disallow) 613 hubp->funcs->hubp_update_force_pstate_disallow(hubp, true); 614 } 615 616 if (pipe->stream && pipe->stream->fpo_in_use) { 617 if (hubp && hubp->funcs->hubp_update_force_pstate_disallow) 618 hubp->funcs->hubp_update_force_pstate_disallow(hubp, true); 619 /* For now only force cursor p-state disallow for FPO 620 * Needs to be added for subvp once FW side gets updated 621 */ 622 if (hubp && hubp->funcs->hubp_update_force_cursor_pstate_disallow) 623 hubp->funcs->hubp_update_force_cursor_pstate_disallow(hubp, true); 624 } 625 } 626 } 627 628 /* Update MALL_SEL register based on if pipe / plane 629 * is a phantom pipe, main pipe, and if using MALL 630 * for SS. 631 */ 632 void dcn32_update_mall_sel(struct dc *dc, struct dc_state *context) 633 { 634 int i; 635 unsigned int num_ways = dcn32_calculate_cab_allocation(dc, context); 636 bool cache_cursor = false; 637 638 for (i = 0; i < dc->res_pool->pipe_count; i++) { 639 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; 640 struct hubp *hubp = pipe->plane_res.hubp; 641 642 if (pipe->stream && pipe->plane_state && hubp && hubp->funcs->hubp_update_mall_sel) { 643 int cursor_size = hubp->curs_attr.pitch * hubp->curs_attr.height; 644 645 switch (hubp->curs_attr.color_format) { 646 case CURSOR_MODE_MONO: 647 cursor_size /= 2; 648 break; 649 case CURSOR_MODE_COLOR_1BIT_AND: 650 case CURSOR_MODE_COLOR_PRE_MULTIPLIED_ALPHA: 651 case CURSOR_MODE_COLOR_UN_PRE_MULTIPLIED_ALPHA: 652 cursor_size *= 4; 653 break; 654 655 case CURSOR_MODE_COLOR_64BIT_FP_PRE_MULTIPLIED: 656 case CURSOR_MODE_COLOR_64BIT_FP_UN_PRE_MULTIPLIED: 657 default: 658 cursor_size *= 8; 659 break; 660 } 661 662 if (cursor_size > 16384) 663 cache_cursor = true; 664 665 if (pipe->stream->mall_stream_config.type == SUBVP_PHANTOM) { 666 hubp->funcs->hubp_update_mall_sel(hubp, 1, false); 667 } else { 668 // MALL not supported with Stereo3D 669 hubp->funcs->hubp_update_mall_sel(hubp, 670 num_ways <= dc->caps.cache_num_ways && 671 pipe->stream->link->psr_settings.psr_version == DC_PSR_VERSION_UNSUPPORTED && 672 pipe->plane_state->address.type != PLN_ADDR_TYPE_GRPH_STEREO && 673 !pipe->plane_state->address.tmz_surface ? 2 : 0, 674 cache_cursor); 675 } 676 } 677 } 678 } 679 680 /* Program the sub-viewport pipe configuration after the main / phantom pipes 681 * have been programmed in hardware. 682 * 1. Update force P-State for all the main pipes (disallow P-state) 683 * 2. Update MALL_SEL register 684 * 3. Program FORCE_ONE_ROW_FOR_FRAME for main subvp pipes 685 */ 686 void dcn32_program_mall_pipe_config(struct dc *dc, struct dc_state *context) 687 { 688 int i; 689 struct dce_hwseq *hws = dc->hwseq; 690 691 // Don't force p-state disallow -- can't block dummy p-state 692 693 // Update MALL_SEL register for each pipe 694 if (hws && hws->funcs.update_mall_sel) 695 hws->funcs.update_mall_sel(dc, context); 696 697 // Program FORCE_ONE_ROW_FOR_FRAME and CURSOR_REQ_MODE for main subvp pipes 698 for (i = 0; i < dc->res_pool->pipe_count; i++) { 699 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; 700 struct hubp *hubp = pipe->plane_res.hubp; 701 702 if (pipe->stream && hubp && hubp->funcs->hubp_prepare_subvp_buffering) { 703 /* TODO - remove setting CURSOR_REQ_MODE to 0 for legacy cases 704 * - need to investigate single pipe MPO + SubVP case to 705 * see if CURSOR_REQ_MODE will be back to 1 for SubVP 706 * when it should be 0 for MPO 707 */ 708 if (pipe->stream->mall_stream_config.type == SUBVP_MAIN) { 709 hubp->funcs->hubp_prepare_subvp_buffering(hubp, true); 710 } 711 } 712 } 713 } 714 715 static void dcn32_initialize_min_clocks(struct dc *dc) 716 { 717 struct dc_clocks *clocks = &dc->current_state->bw_ctx.bw.dcn.clk; 718 719 clocks->dcfclk_deep_sleep_khz = DCN3_2_DCFCLK_DS_INIT_KHZ; 720 clocks->dcfclk_khz = dc->clk_mgr->bw_params->clk_table.entries[0].dcfclk_mhz * 1000; 721 clocks->socclk_khz = dc->clk_mgr->bw_params->clk_table.entries[0].socclk_mhz * 1000; 722 clocks->dramclk_khz = dc->clk_mgr->bw_params->clk_table.entries[0].memclk_mhz * 1000; 723 clocks->dppclk_khz = dc->clk_mgr->bw_params->clk_table.entries[0].dppclk_mhz * 1000; 724 if (dc->debug.disable_boot_optimizations) { 725 clocks->dispclk_khz = dc->clk_mgr->bw_params->clk_table.entries[0].dispclk_mhz * 1000; 726 } else { 727 /* Even though DPG_EN = 1 for the connected display, it still requires the 728 * correct timing so we cannot set DISPCLK to min freq or it could cause 729 * audio corruption. Read current DISPCLK from DENTIST and request the same 730 * freq to ensure that the timing is valid and unchanged. 731 */ 732 clocks->dispclk_khz = dc->clk_mgr->funcs->get_dispclk_from_dentist(dc->clk_mgr); 733 clocks->ref_dtbclk_khz = dc->clk_mgr->bw_params->clk_table.entries[0].dtbclk_mhz * 1000; 734 clocks->fclk_p_state_change_support = true; 735 clocks->p_state_change_support = true; 736 } 737 738 dc->clk_mgr->funcs->update_clocks( 739 dc->clk_mgr, 740 dc->current_state, 741 true); 742 } 743 744 void dcn32_init_hw(struct dc *dc) 745 { 746 struct abm **abms = dc->res_pool->multiple_abms; 747 struct dce_hwseq *hws = dc->hwseq; 748 struct dc_bios *dcb = dc->ctx->dc_bios; 749 struct resource_pool *res_pool = dc->res_pool; 750 int i; 751 int edp_num; 752 uint32_t backlight = MAX_BACKLIGHT_LEVEL; 753 754 if (dc->clk_mgr && dc->clk_mgr->funcs->init_clocks) 755 dc->clk_mgr->funcs->init_clocks(dc->clk_mgr); 756 757 // Initialize the dccg 758 if (res_pool->dccg->funcs->dccg_init) 759 res_pool->dccg->funcs->dccg_init(res_pool->dccg); 760 761 if (!dcb->funcs->is_accelerated_mode(dcb)) { 762 hws->funcs.bios_golden_init(dc); 763 hws->funcs.disable_vga(dc->hwseq); 764 } 765 766 // Set default OPTC memory power states 767 if (dc->debug.enable_mem_low_power.bits.optc) { 768 // Shutdown when unassigned and light sleep in VBLANK 769 REG_SET_2(ODM_MEM_PWR_CTRL3, 0, ODM_MEM_UNASSIGNED_PWR_MODE, 3, ODM_MEM_VBLANK_PWR_MODE, 1); 770 } 771 772 if (dc->debug.enable_mem_low_power.bits.vga) { 773 // Power down VGA memory 774 REG_UPDATE(MMHUBBUB_MEM_PWR_CNTL, VGA_MEM_PWR_FORCE, 1); 775 } 776 777 if (dc->ctx->dc_bios->fw_info_valid) { 778 res_pool->ref_clocks.xtalin_clock_inKhz = 779 dc->ctx->dc_bios->fw_info.pll_info.crystal_frequency; 780 781 if (res_pool->dccg && res_pool->hubbub) { 782 (res_pool->dccg->funcs->get_dccg_ref_freq)(res_pool->dccg, 783 dc->ctx->dc_bios->fw_info.pll_info.crystal_frequency, 784 &res_pool->ref_clocks.dccg_ref_clock_inKhz); 785 786 (res_pool->hubbub->funcs->get_dchub_ref_freq)(res_pool->hubbub, 787 res_pool->ref_clocks.dccg_ref_clock_inKhz, 788 &res_pool->ref_clocks.dchub_ref_clock_inKhz); 789 } else { 790 // Not all ASICs have DCCG sw component 791 res_pool->ref_clocks.dccg_ref_clock_inKhz = 792 res_pool->ref_clocks.xtalin_clock_inKhz; 793 res_pool->ref_clocks.dchub_ref_clock_inKhz = 794 res_pool->ref_clocks.xtalin_clock_inKhz; 795 } 796 } else 797 ASSERT_CRITICAL(false); 798 799 for (i = 0; i < dc->link_count; i++) { 800 /* Power up AND update implementation according to the 801 * required signal (which may be different from the 802 * default signal on connector). 803 */ 804 struct dc_link *link = dc->links[i]; 805 806 link->link_enc->funcs->hw_init(link->link_enc); 807 808 /* Check for enabled DIG to identify enabled display */ 809 if (link->link_enc->funcs->is_dig_enabled && 810 link->link_enc->funcs->is_dig_enabled(link->link_enc)) { 811 link->link_status.link_active = true; 812 link->phy_state.symclk_state = SYMCLK_ON_TX_ON; 813 if (link->link_enc->funcs->fec_is_active && 814 link->link_enc->funcs->fec_is_active(link->link_enc)) 815 link->fec_state = dc_link_fec_enabled; 816 } 817 } 818 819 /* enable_power_gating_plane before dsc_pg_control because 820 * FORCEON = 1 with hw default value on bootup, resume from s3 821 */ 822 if (hws->funcs.enable_power_gating_plane) 823 hws->funcs.enable_power_gating_plane(dc->hwseq, true); 824 825 /* we want to turn off all dp displays before doing detection */ 826 dc->link_srv->blank_all_dp_displays(dc); 827 828 /* If taking control over from VBIOS, we may want to optimize our first 829 * mode set, so we need to skip powering down pipes until we know which 830 * pipes we want to use. 831 * Otherwise, if taking control is not possible, we need to power 832 * everything down. 833 */ 834 if (dcb->funcs->is_accelerated_mode(dcb) || !dc->config.seamless_boot_edp_requested) { 835 /* Disable boot optimizations means power down everything including PHY, DIG, 836 * and OTG (i.e. the boot is not optimized because we do a full power down). 837 */ 838 if (dc->hwss.enable_accelerated_mode && dc->debug.disable_boot_optimizations) 839 dc->hwss.enable_accelerated_mode(dc, dc->current_state); 840 else 841 hws->funcs.init_pipes(dc, dc->current_state); 842 843 if (dc->res_pool->hubbub->funcs->allow_self_refresh_control) 844 dc->res_pool->hubbub->funcs->allow_self_refresh_control(dc->res_pool->hubbub, 845 !dc->res_pool->hubbub->ctx->dc->debug.disable_stutter); 846 847 dcn32_initialize_min_clocks(dc); 848 849 /* On HW init, allow idle optimizations after pipes have been turned off. 850 * 851 * In certain D3 cases (i.e. BOCO / BOMACO) it's possible that hardware state 852 * is reset (i.e. not in idle at the time hw init is called), but software state 853 * still has idle_optimizations = true, so we must disable idle optimizations first 854 * (i.e. set false), then re-enable (set true). 855 */ 856 dc_allow_idle_optimizations(dc, false); 857 dc_allow_idle_optimizations(dc, true); 858 } 859 860 /* In headless boot cases, DIG may be turned 861 * on which causes HW/SW discrepancies. 862 * To avoid this, power down hardware on boot 863 * if DIG is turned on and seamless boot not enabled 864 */ 865 if (!dc->config.seamless_boot_edp_requested) { 866 struct dc_link *edp_links[MAX_NUM_EDP]; 867 struct dc_link *edp_link; 868 869 dc_get_edp_links(dc, edp_links, &edp_num); 870 if (edp_num) { 871 for (i = 0; i < edp_num; i++) { 872 edp_link = edp_links[i]; 873 if (edp_link->link_enc->funcs->is_dig_enabled && 874 edp_link->link_enc->funcs->is_dig_enabled(edp_link->link_enc) && 875 dc->hwss.edp_backlight_control && 876 dc->hwss.power_down && 877 dc->hwss.edp_power_control) { 878 dc->hwss.edp_backlight_control(edp_link, false); 879 dc->hwss.power_down(dc); 880 dc->hwss.edp_power_control(edp_link, false); 881 } 882 } 883 } else { 884 for (i = 0; i < dc->link_count; i++) { 885 struct dc_link *link = dc->links[i]; 886 887 if (link->link_enc->funcs->is_dig_enabled && 888 link->link_enc->funcs->is_dig_enabled(link->link_enc) && 889 dc->hwss.power_down) { 890 dc->hwss.power_down(dc); 891 break; 892 } 893 894 } 895 } 896 } 897 898 for (i = 0; i < res_pool->audio_count; i++) { 899 struct audio *audio = res_pool->audios[i]; 900 901 audio->funcs->hw_init(audio); 902 } 903 904 for (i = 0; i < dc->link_count; i++) { 905 struct dc_link *link = dc->links[i]; 906 907 if (link->panel_cntl) 908 backlight = link->panel_cntl->funcs->hw_init(link->panel_cntl); 909 } 910 911 for (i = 0; i < dc->res_pool->pipe_count; i++) { 912 if (abms[i] != NULL && abms[i]->funcs != NULL) 913 abms[i]->funcs->abm_init(abms[i], backlight); 914 } 915 916 /* power AFMT HDMI memory TODO: may move to dis/en output save power*/ 917 REG_WRITE(DIO_MEM_PWR_CTRL, 0); 918 919 if (!dc->debug.disable_clock_gate) { 920 /* enable all DCN clock gating */ 921 REG_WRITE(DCCG_GATE_DISABLE_CNTL, 0); 922 923 REG_WRITE(DCCG_GATE_DISABLE_CNTL2, 0); 924 925 REG_UPDATE(DCFCLK_CNTL, DCFCLK_GATE_DIS, 0); 926 } 927 928 if (!dcb->funcs->is_accelerated_mode(dcb) && dc->res_pool->hubbub->funcs->init_watermarks) 929 dc->res_pool->hubbub->funcs->init_watermarks(dc->res_pool->hubbub); 930 931 if (dc->clk_mgr->funcs->notify_wm_ranges) 932 dc->clk_mgr->funcs->notify_wm_ranges(dc->clk_mgr); 933 934 if (dc->clk_mgr->funcs->set_hard_max_memclk && !dc->clk_mgr->dc_mode_softmax_enabled) 935 dc->clk_mgr->funcs->set_hard_max_memclk(dc->clk_mgr); 936 937 if (dc->res_pool->hubbub->funcs->force_pstate_change_control) 938 dc->res_pool->hubbub->funcs->force_pstate_change_control( 939 dc->res_pool->hubbub, false, false); 940 941 if (dc->res_pool->hubbub->funcs->init_crb) 942 dc->res_pool->hubbub->funcs->init_crb(dc->res_pool->hubbub); 943 944 if (dc->res_pool->hubbub->funcs->set_request_limit && dc->config.sdpif_request_limit_words_per_umc > 0) 945 dc->res_pool->hubbub->funcs->set_request_limit(dc->res_pool->hubbub, dc->ctx->dc_bios->vram_info.num_chans, dc->config.sdpif_request_limit_words_per_umc); 946 947 // Get DMCUB capabilities 948 if (dc->ctx->dmub_srv) { 949 dc_dmub_srv_query_caps_cmd(dc->ctx->dmub_srv->dmub); 950 dc->caps.dmub_caps.psr = dc->ctx->dmub_srv->dmub->feature_caps.psr; 951 dc->caps.dmub_caps.mclk_sw = dc->ctx->dmub_srv->dmub->feature_caps.fw_assisted_mclk_switch; 952 } 953 } 954 955 static int calc_mpc_flow_ctrl_cnt(const struct dc_stream_state *stream, 956 int opp_cnt) 957 { 958 bool hblank_halved = optc2_is_two_pixels_per_containter(&stream->timing); 959 int flow_ctrl_cnt; 960 961 if (opp_cnt >= 2) 962 hblank_halved = true; 963 964 flow_ctrl_cnt = stream->timing.h_total - stream->timing.h_addressable - 965 stream->timing.h_border_left - 966 stream->timing.h_border_right; 967 968 if (hblank_halved) 969 flow_ctrl_cnt /= 2; 970 971 /* ODM combine 4:1 case */ 972 if (opp_cnt == 4) 973 flow_ctrl_cnt /= 2; 974 975 return flow_ctrl_cnt; 976 } 977 978 static void update_dsc_on_stream(struct pipe_ctx *pipe_ctx, bool enable) 979 { 980 struct display_stream_compressor *dsc = pipe_ctx->stream_res.dsc; 981 struct dc_stream_state *stream = pipe_ctx->stream; 982 struct pipe_ctx *odm_pipe; 983 int opp_cnt = 1; 984 985 ASSERT(dsc); 986 for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) 987 opp_cnt++; 988 989 if (enable) { 990 struct dsc_config dsc_cfg; 991 struct dsc_optc_config dsc_optc_cfg; 992 enum optc_dsc_mode optc_dsc_mode; 993 994 /* Enable DSC hw block */ 995 dsc_cfg.pic_width = (stream->timing.h_addressable + stream->timing.h_border_left + stream->timing.h_border_right) / opp_cnt; 996 dsc_cfg.pic_height = stream->timing.v_addressable + stream->timing.v_border_top + stream->timing.v_border_bottom; 997 dsc_cfg.pixel_encoding = stream->timing.pixel_encoding; 998 dsc_cfg.color_depth = stream->timing.display_color_depth; 999 dsc_cfg.is_odm = pipe_ctx->next_odm_pipe ? true : false; 1000 dsc_cfg.dc_dsc_cfg = stream->timing.dsc_cfg; 1001 ASSERT(dsc_cfg.dc_dsc_cfg.num_slices_h % opp_cnt == 0); 1002 dsc_cfg.dc_dsc_cfg.num_slices_h /= opp_cnt; 1003 1004 dsc->funcs->dsc_set_config(dsc, &dsc_cfg, &dsc_optc_cfg); 1005 dsc->funcs->dsc_enable(dsc, pipe_ctx->stream_res.opp->inst); 1006 for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) { 1007 struct display_stream_compressor *odm_dsc = odm_pipe->stream_res.dsc; 1008 1009 ASSERT(odm_dsc); 1010 odm_dsc->funcs->dsc_set_config(odm_dsc, &dsc_cfg, &dsc_optc_cfg); 1011 odm_dsc->funcs->dsc_enable(odm_dsc, odm_pipe->stream_res.opp->inst); 1012 } 1013 dsc_cfg.dc_dsc_cfg.num_slices_h *= opp_cnt; 1014 dsc_cfg.pic_width *= opp_cnt; 1015 1016 optc_dsc_mode = dsc_optc_cfg.is_pixel_format_444 ? OPTC_DSC_ENABLED_444 : OPTC_DSC_ENABLED_NATIVE_SUBSAMPLED; 1017 1018 /* Enable DSC in OPTC */ 1019 DC_LOG_DSC("Setting optc DSC config for tg instance %d:", pipe_ctx->stream_res.tg->inst); 1020 pipe_ctx->stream_res.tg->funcs->set_dsc_config(pipe_ctx->stream_res.tg, 1021 optc_dsc_mode, 1022 dsc_optc_cfg.bytes_per_pixel, 1023 dsc_optc_cfg.slice_width); 1024 } else { 1025 /* disable DSC in OPTC */ 1026 pipe_ctx->stream_res.tg->funcs->set_dsc_config( 1027 pipe_ctx->stream_res.tg, 1028 OPTC_DSC_DISABLED, 0, 0); 1029 1030 /* disable DSC block */ 1031 dsc->funcs->dsc_disable(pipe_ctx->stream_res.dsc); 1032 for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) { 1033 ASSERT(odm_pipe->stream_res.dsc); 1034 odm_pipe->stream_res.dsc->funcs->dsc_disable(odm_pipe->stream_res.dsc); 1035 } 1036 } 1037 } 1038 1039 /* 1040 * Given any pipe_ctx, return the total ODM combine factor, and optionally return 1041 * the OPPids which are used 1042 * */ 1043 static unsigned int get_odm_config(struct pipe_ctx *pipe_ctx, unsigned int *opp_instances) 1044 { 1045 unsigned int opp_count = 1; 1046 struct pipe_ctx *odm_pipe; 1047 1048 /* First get to the top pipe */ 1049 for (odm_pipe = pipe_ctx; odm_pipe->prev_odm_pipe; odm_pipe = odm_pipe->prev_odm_pipe) 1050 ; 1051 1052 /* First pipe is always used */ 1053 if (opp_instances) 1054 opp_instances[0] = odm_pipe->stream_res.opp->inst; 1055 1056 /* Find and count odm pipes, if any */ 1057 for (odm_pipe = odm_pipe->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) { 1058 if (opp_instances) 1059 opp_instances[opp_count] = odm_pipe->stream_res.opp->inst; 1060 opp_count++; 1061 } 1062 1063 return opp_count; 1064 } 1065 1066 void dcn32_update_odm(struct dc *dc, struct dc_state *context, struct pipe_ctx *pipe_ctx) 1067 { 1068 struct pipe_ctx *odm_pipe; 1069 int opp_cnt = 0; 1070 int opp_inst[MAX_PIPES] = {0}; 1071 bool rate_control_2x_pclk = (pipe_ctx->stream->timing.flags.INTERLACE || optc2_is_two_pixels_per_containter(&pipe_ctx->stream->timing)); 1072 struct mpc_dwb_flow_control flow_control; 1073 struct mpc *mpc = dc->res_pool->mpc; 1074 int i; 1075 1076 opp_cnt = get_odm_config(pipe_ctx, opp_inst); 1077 1078 if (opp_cnt > 1) 1079 pipe_ctx->stream_res.tg->funcs->set_odm_combine( 1080 pipe_ctx->stream_res.tg, 1081 opp_inst, opp_cnt, 1082 &pipe_ctx->stream->timing); 1083 else 1084 pipe_ctx->stream_res.tg->funcs->set_odm_bypass( 1085 pipe_ctx->stream_res.tg, &pipe_ctx->stream->timing); 1086 1087 rate_control_2x_pclk = rate_control_2x_pclk || opp_cnt > 1; 1088 flow_control.flow_ctrl_mode = 0; 1089 flow_control.flow_ctrl_cnt0 = 0x80; 1090 flow_control.flow_ctrl_cnt1 = calc_mpc_flow_ctrl_cnt(pipe_ctx->stream, opp_cnt); 1091 if (mpc->funcs->set_out_rate_control) { 1092 for (i = 0; i < opp_cnt; ++i) { 1093 mpc->funcs->set_out_rate_control( 1094 mpc, opp_inst[i], 1095 true, 1096 rate_control_2x_pclk, 1097 &flow_control); 1098 } 1099 } 1100 1101 for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) { 1102 odm_pipe->stream_res.opp->funcs->opp_pipe_clock_control( 1103 odm_pipe->stream_res.opp, 1104 true); 1105 } 1106 1107 if (pipe_ctx->stream_res.dsc) { 1108 struct pipe_ctx *current_pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[pipe_ctx->pipe_idx]; 1109 1110 update_dsc_on_stream(pipe_ctx, pipe_ctx->stream->timing.flags.DSC); 1111 1112 /* Check if no longer using pipe for ODM, then need to disconnect DSC for that pipe */ 1113 if (!pipe_ctx->next_odm_pipe && current_pipe_ctx->next_odm_pipe && 1114 current_pipe_ctx->next_odm_pipe->stream_res.dsc) { 1115 struct display_stream_compressor *dsc = current_pipe_ctx->next_odm_pipe->stream_res.dsc; 1116 /* disconnect DSC block from stream */ 1117 dsc->funcs->dsc_disconnect(dsc); 1118 } 1119 } 1120 } 1121 1122 unsigned int dcn32_calculate_dccg_k1_k2_values(struct pipe_ctx *pipe_ctx, unsigned int *k1_div, unsigned int *k2_div) 1123 { 1124 struct dc_stream_state *stream = pipe_ctx->stream; 1125 unsigned int odm_combine_factor = 0; 1126 bool two_pix_per_container = false; 1127 1128 // For phantom pipes, use the same programming as the main pipes 1129 if (pipe_ctx->stream->mall_stream_config.type == SUBVP_PHANTOM) { 1130 stream = pipe_ctx->stream->mall_stream_config.paired_stream; 1131 } 1132 two_pix_per_container = optc2_is_two_pixels_per_containter(&stream->timing); 1133 odm_combine_factor = get_odm_config(pipe_ctx, NULL); 1134 1135 if (stream->ctx->dc->link_srv->dp_is_128b_132b_signal(pipe_ctx)) { 1136 *k1_div = PIXEL_RATE_DIV_BY_1; 1137 *k2_div = PIXEL_RATE_DIV_BY_1; 1138 } else if (dc_is_hdmi_tmds_signal(stream->signal) || dc_is_dvi_signal(stream->signal)) { 1139 *k1_div = PIXEL_RATE_DIV_BY_1; 1140 if (stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR420) 1141 *k2_div = PIXEL_RATE_DIV_BY_2; 1142 else 1143 *k2_div = PIXEL_RATE_DIV_BY_4; 1144 } else if (dc_is_dp_signal(stream->signal) || dc_is_virtual_signal(stream->signal)) { 1145 if (two_pix_per_container) { 1146 *k1_div = PIXEL_RATE_DIV_BY_1; 1147 *k2_div = PIXEL_RATE_DIV_BY_2; 1148 } else { 1149 *k1_div = PIXEL_RATE_DIV_BY_1; 1150 *k2_div = PIXEL_RATE_DIV_BY_4; 1151 if ((odm_combine_factor == 2) || dcn32_is_dp_dig_pixel_rate_div_policy(pipe_ctx)) 1152 *k2_div = PIXEL_RATE_DIV_BY_2; 1153 } 1154 } 1155 1156 if ((*k1_div == PIXEL_RATE_DIV_NA) && (*k2_div == PIXEL_RATE_DIV_NA)) 1157 ASSERT(false); 1158 1159 return odm_combine_factor; 1160 } 1161 1162 void dcn32_set_pixels_per_cycle(struct pipe_ctx *pipe_ctx) 1163 { 1164 uint32_t pix_per_cycle = 1; 1165 uint32_t odm_combine_factor = 1; 1166 1167 if (!pipe_ctx || !pipe_ctx->stream || !pipe_ctx->stream_res.stream_enc) 1168 return; 1169 1170 odm_combine_factor = get_odm_config(pipe_ctx, NULL); 1171 if (optc2_is_two_pixels_per_containter(&pipe_ctx->stream->timing) || odm_combine_factor > 1 1172 || dcn32_is_dp_dig_pixel_rate_div_policy(pipe_ctx)) 1173 pix_per_cycle = 2; 1174 1175 if (pipe_ctx->stream_res.stream_enc->funcs->set_input_mode) 1176 pipe_ctx->stream_res.stream_enc->funcs->set_input_mode(pipe_ctx->stream_res.stream_enc, 1177 pix_per_cycle); 1178 } 1179 1180 void dcn32_unblank_stream(struct pipe_ctx *pipe_ctx, 1181 struct dc_link_settings *link_settings) 1182 { 1183 struct encoder_unblank_param params = {0}; 1184 struct dc_stream_state *stream = pipe_ctx->stream; 1185 struct dc_link *link = stream->link; 1186 struct dce_hwseq *hws = link->dc->hwseq; 1187 struct pipe_ctx *odm_pipe; 1188 uint32_t pix_per_cycle = 1; 1189 1190 params.opp_cnt = 1; 1191 for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) 1192 params.opp_cnt++; 1193 1194 /* only 3 items below are used by unblank */ 1195 params.timing = pipe_ctx->stream->timing; 1196 1197 params.link_settings.link_rate = link_settings->link_rate; 1198 1199 if (link->dc->link_srv->dp_is_128b_132b_signal(pipe_ctx)) { 1200 /* TODO - DP2.0 HW: Set ODM mode in dp hpo encoder here */ 1201 pipe_ctx->stream_res.hpo_dp_stream_enc->funcs->dp_unblank( 1202 pipe_ctx->stream_res.hpo_dp_stream_enc, 1203 pipe_ctx->stream_res.tg->inst); 1204 } else if (dc_is_dp_signal(pipe_ctx->stream->signal)) { 1205 if (optc2_is_two_pixels_per_containter(&stream->timing) || params.opp_cnt > 1 1206 || dcn32_is_dp_dig_pixel_rate_div_policy(pipe_ctx)) { 1207 params.timing.pix_clk_100hz /= 2; 1208 pix_per_cycle = 2; 1209 } 1210 pipe_ctx->stream_res.stream_enc->funcs->dp_set_odm_combine( 1211 pipe_ctx->stream_res.stream_enc, pix_per_cycle > 1); 1212 pipe_ctx->stream_res.stream_enc->funcs->dp_unblank(link, pipe_ctx->stream_res.stream_enc, ¶ms); 1213 } 1214 1215 if (link->local_sink && link->local_sink->sink_signal == SIGNAL_TYPE_EDP) 1216 hws->funcs.edp_backlight_control(link, true); 1217 } 1218 1219 bool dcn32_is_dp_dig_pixel_rate_div_policy(struct pipe_ctx *pipe_ctx) 1220 { 1221 struct dc *dc = pipe_ctx->stream->ctx->dc; 1222 1223 if (!is_h_timing_divisible_by_2(pipe_ctx->stream)) 1224 return false; 1225 1226 if (dc_is_dp_signal(pipe_ctx->stream->signal) && !dc->link_srv->dp_is_128b_132b_signal(pipe_ctx) && 1227 dc->debug.enable_dp_dig_pixel_rate_div_policy) 1228 return true; 1229 return false; 1230 } 1231 1232 static void apply_symclk_on_tx_off_wa(struct dc_link *link) 1233 { 1234 /* There are use cases where SYMCLK is referenced by OTG. For instance 1235 * for TMDS signal, OTG relies SYMCLK even if TX video output is off. 1236 * However current link interface will power off PHY when disabling link 1237 * output. This will turn off SYMCLK generated by PHY. The workaround is 1238 * to identify such case where SYMCLK is still in use by OTG when we 1239 * power off PHY. When this is detected, we will temporarily power PHY 1240 * back on and move PHY's SYMCLK state to SYMCLK_ON_TX_OFF by calling 1241 * program_pix_clk interface. When OTG is disabled, we will then power 1242 * off PHY by calling disable link output again. 1243 * 1244 * In future dcn generations, we plan to rework transmitter control 1245 * interface so that we could have an option to set SYMCLK ON TX OFF 1246 * state in one step without this workaround 1247 */ 1248 1249 struct dc *dc = link->ctx->dc; 1250 struct pipe_ctx *pipe_ctx = NULL; 1251 uint8_t i; 1252 1253 if (link->phy_state.symclk_ref_cnts.otg > 0) { 1254 for (i = 0; i < MAX_PIPES; i++) { 1255 pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[i]; 1256 if (pipe_ctx->stream && pipe_ctx->stream->link == link && pipe_ctx->top_pipe == NULL) { 1257 pipe_ctx->clock_source->funcs->program_pix_clk( 1258 pipe_ctx->clock_source, 1259 &pipe_ctx->stream_res.pix_clk_params, 1260 dc->link_srv->dp_get_encoding_format( 1261 &pipe_ctx->link_config.dp_link_settings), 1262 &pipe_ctx->pll_settings); 1263 link->phy_state.symclk_state = SYMCLK_ON_TX_OFF; 1264 break; 1265 } 1266 } 1267 } 1268 } 1269 1270 void dcn32_disable_link_output(struct dc_link *link, 1271 const struct link_resource *link_res, 1272 enum signal_type signal) 1273 { 1274 struct dc *dc = link->ctx->dc; 1275 const struct link_hwss *link_hwss = get_link_hwss(link, link_res); 1276 struct dmcu *dmcu = dc->res_pool->dmcu; 1277 1278 if (signal == SIGNAL_TYPE_EDP && 1279 link->dc->hwss.edp_backlight_control) 1280 link->dc->hwss.edp_backlight_control(link, false); 1281 else if (dmcu != NULL && dmcu->funcs->lock_phy) 1282 dmcu->funcs->lock_phy(dmcu); 1283 1284 link_hwss->disable_link_output(link, link_res, signal); 1285 link->phy_state.symclk_state = SYMCLK_OFF_TX_OFF; 1286 1287 if (signal == SIGNAL_TYPE_EDP && 1288 link->dc->hwss.edp_backlight_control) 1289 link->dc->hwss.edp_power_control(link, false); 1290 else if (dmcu != NULL && dmcu->funcs->lock_phy) 1291 dmcu->funcs->unlock_phy(dmcu); 1292 1293 dc->link_srv->dp_trace_source_sequence(link, DPCD_SOURCE_SEQ_AFTER_DISABLE_LINK_PHY); 1294 1295 apply_symclk_on_tx_off_wa(link); 1296 } 1297 1298 /* For SubVP the main pipe can have a viewport position change 1299 * without a full update. In this case we must also update the 1300 * viewport positions for the phantom pipe accordingly. 1301 */ 1302 void dcn32_update_phantom_vp_position(struct dc *dc, 1303 struct dc_state *context, 1304 struct pipe_ctx *phantom_pipe) 1305 { 1306 uint32_t i; 1307 struct dc_plane_state *phantom_plane = phantom_pipe->plane_state; 1308 1309 for (i = 0; i < dc->res_pool->pipe_count; i++) { 1310 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; 1311 1312 if (pipe->stream && pipe->stream->mall_stream_config.type == SUBVP_MAIN && 1313 pipe->stream->mall_stream_config.paired_stream == phantom_pipe->stream) { 1314 if (pipe->plane_state && pipe->plane_state->update_flags.bits.position_change) { 1315 1316 phantom_plane->src_rect.x = pipe->plane_state->src_rect.x; 1317 phantom_plane->src_rect.y = pipe->plane_state->src_rect.y; 1318 phantom_plane->clip_rect.x = pipe->plane_state->clip_rect.x; 1319 phantom_plane->dst_rect.x = pipe->plane_state->dst_rect.x; 1320 phantom_plane->dst_rect.y = pipe->plane_state->dst_rect.y; 1321 1322 phantom_pipe->plane_state->update_flags.bits.position_change = 1; 1323 resource_build_scaling_params(phantom_pipe); 1324 return; 1325 } 1326 } 1327 } 1328 } 1329 1330 /* Treat the phantom pipe as if it needs to be fully enabled. 1331 * If the pipe was previously in use but not phantom, it would 1332 * have been disabled earlier in the sequence so we need to run 1333 * the full enable sequence. 1334 */ 1335 void dcn32_apply_update_flags_for_phantom(struct pipe_ctx *phantom_pipe) 1336 { 1337 phantom_pipe->update_flags.raw = 0; 1338 if (phantom_pipe->stream && phantom_pipe->stream->mall_stream_config.type == SUBVP_PHANTOM) { 1339 if (phantom_pipe->stream && phantom_pipe->plane_state) { 1340 phantom_pipe->update_flags.bits.enable = 1; 1341 phantom_pipe->update_flags.bits.mpcc = 1; 1342 phantom_pipe->update_flags.bits.dppclk = 1; 1343 phantom_pipe->update_flags.bits.hubp_interdependent = 1; 1344 phantom_pipe->update_flags.bits.hubp_rq_dlg_ttu = 1; 1345 phantom_pipe->update_flags.bits.gamut_remap = 1; 1346 phantom_pipe->update_flags.bits.scaler = 1; 1347 phantom_pipe->update_flags.bits.viewport = 1; 1348 phantom_pipe->update_flags.bits.det_size = 1; 1349 if (!phantom_pipe->top_pipe && !phantom_pipe->prev_odm_pipe) { 1350 phantom_pipe->update_flags.bits.odm = 1; 1351 phantom_pipe->update_flags.bits.global_sync = 1; 1352 } 1353 } 1354 } 1355 } 1356 1357 bool dcn32_dsc_pg_status( 1358 struct dce_hwseq *hws, 1359 unsigned int dsc_inst) 1360 { 1361 uint32_t pwr_status = 0; 1362 1363 switch (dsc_inst) { 1364 case 0: /* DSC0 */ 1365 REG_GET(DOMAIN16_PG_STATUS, 1366 DOMAIN_PGFSM_PWR_STATUS, &pwr_status); 1367 break; 1368 case 1: /* DSC1 */ 1369 1370 REG_GET(DOMAIN17_PG_STATUS, 1371 DOMAIN_PGFSM_PWR_STATUS, &pwr_status); 1372 break; 1373 case 2: /* DSC2 */ 1374 REG_GET(DOMAIN18_PG_STATUS, 1375 DOMAIN_PGFSM_PWR_STATUS, &pwr_status); 1376 break; 1377 case 3: /* DSC3 */ 1378 REG_GET(DOMAIN19_PG_STATUS, 1379 DOMAIN_PGFSM_PWR_STATUS, &pwr_status); 1380 break; 1381 default: 1382 BREAK_TO_DEBUGGER(); 1383 break; 1384 } 1385 1386 return pwr_status == 0; 1387 } 1388 1389 void dcn32_update_dsc_pg(struct dc *dc, 1390 struct dc_state *context, 1391 bool safe_to_disable) 1392 { 1393 struct dce_hwseq *hws = dc->hwseq; 1394 int i; 1395 1396 for (i = 0; i < dc->res_pool->res_cap->num_dsc; i++) { 1397 struct display_stream_compressor *dsc = dc->res_pool->dscs[i]; 1398 bool is_dsc_ungated = hws->funcs.dsc_pg_status(hws, dsc->inst); 1399 1400 if (context->res_ctx.is_dsc_acquired[i]) { 1401 if (!is_dsc_ungated) { 1402 hws->funcs.dsc_pg_control(hws, dsc->inst, true); 1403 } 1404 } else if (safe_to_disable) { 1405 if (is_dsc_ungated) { 1406 hws->funcs.dsc_pg_control(hws, dsc->inst, false); 1407 } 1408 } 1409 } 1410 } 1411 1412 void dcn32_enable_phantom_streams(struct dc *dc, struct dc_state *context) 1413 { 1414 unsigned int i; 1415 1416 for (i = 0; i < dc->res_pool->pipe_count; i++) { 1417 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; 1418 struct pipe_ctx *old_pipe = &dc->current_state->res_ctx.pipe_ctx[i]; 1419 1420 /* If an active, non-phantom pipe is being transitioned into a phantom 1421 * pipe, wait for the double buffer update to complete first before we do 1422 * ANY phantom pipe programming. 1423 */ 1424 if (pipe->stream && pipe->stream->mall_stream_config.type == SUBVP_PHANTOM && 1425 old_pipe->stream && old_pipe->stream->mall_stream_config.type != SUBVP_PHANTOM) { 1426 old_pipe->stream_res.tg->funcs->wait_for_state( 1427 old_pipe->stream_res.tg, 1428 CRTC_STATE_VBLANK); 1429 old_pipe->stream_res.tg->funcs->wait_for_state( 1430 old_pipe->stream_res.tg, 1431 CRTC_STATE_VACTIVE); 1432 } 1433 } 1434 for (i = 0; i < dc->res_pool->pipe_count; i++) { 1435 struct pipe_ctx *new_pipe = &context->res_ctx.pipe_ctx[i]; 1436 1437 if (new_pipe->stream && new_pipe->stream->mall_stream_config.type == SUBVP_PHANTOM) { 1438 // If old context or new context has phantom pipes, apply 1439 // the phantom timings now. We can't change the phantom 1440 // pipe configuration safely without driver acquiring 1441 // the DMCUB lock first. 1442 dc->hwss.apply_ctx_to_hw(dc, context); 1443 break; 1444 } 1445 } 1446 } 1447 1448 /* Blank pixel data during initialization */ 1449 void dcn32_init_blank( 1450 struct dc *dc, 1451 struct timing_generator *tg) 1452 { 1453 struct dce_hwseq *hws = dc->hwseq; 1454 enum dc_color_space color_space; 1455 struct tg_color black_color = {0}; 1456 struct output_pixel_processor *opp = NULL; 1457 struct output_pixel_processor *bottom_opp = NULL; 1458 uint32_t num_opps, opp_id_src0, opp_id_src1; 1459 uint32_t otg_active_width, otg_active_height; 1460 uint32_t i; 1461 1462 /* program opp dpg blank color */ 1463 color_space = COLOR_SPACE_SRGB; 1464 color_space_to_black_color(dc, color_space, &black_color); 1465 1466 /* get the OTG active size */ 1467 tg->funcs->get_otg_active_size(tg, 1468 &otg_active_width, 1469 &otg_active_height); 1470 1471 /* get the OPTC source */ 1472 tg->funcs->get_optc_source(tg, &num_opps, &opp_id_src0, &opp_id_src1); 1473 1474 if (opp_id_src0 >= dc->res_pool->res_cap->num_opp) { 1475 ASSERT(false); 1476 return; 1477 } 1478 1479 for (i = 0; i < dc->res_pool->res_cap->num_opp; i++) { 1480 if (dc->res_pool->opps[i] != NULL && dc->res_pool->opps[i]->inst == opp_id_src0) { 1481 opp = dc->res_pool->opps[i]; 1482 break; 1483 } 1484 } 1485 1486 if (num_opps == 2) { 1487 otg_active_width = otg_active_width / 2; 1488 1489 if (opp_id_src1 >= dc->res_pool->res_cap->num_opp) { 1490 ASSERT(false); 1491 return; 1492 } 1493 for (i = 0; i < dc->res_pool->res_cap->num_opp; i++) { 1494 if (dc->res_pool->opps[i] != NULL && dc->res_pool->opps[i]->inst == opp_id_src1) { 1495 bottom_opp = dc->res_pool->opps[i]; 1496 break; 1497 } 1498 } 1499 } 1500 1501 if (opp && opp->funcs->opp_set_disp_pattern_generator) 1502 opp->funcs->opp_set_disp_pattern_generator( 1503 opp, 1504 CONTROLLER_DP_TEST_PATTERN_SOLID_COLOR, 1505 CONTROLLER_DP_COLOR_SPACE_UDEFINED, 1506 COLOR_DEPTH_UNDEFINED, 1507 &black_color, 1508 otg_active_width, 1509 otg_active_height, 1510 0); 1511 1512 if (num_opps == 2) { 1513 if (bottom_opp && bottom_opp->funcs->opp_set_disp_pattern_generator) { 1514 bottom_opp->funcs->opp_set_disp_pattern_generator( 1515 bottom_opp, 1516 CONTROLLER_DP_TEST_PATTERN_SOLID_COLOR, 1517 CONTROLLER_DP_COLOR_SPACE_UDEFINED, 1518 COLOR_DEPTH_UNDEFINED, 1519 &black_color, 1520 otg_active_width, 1521 otg_active_height, 1522 0); 1523 hws->funcs.wait_for_blank_complete(bottom_opp); 1524 } 1525 } 1526 1527 if (opp) 1528 hws->funcs.wait_for_blank_complete(opp); 1529 } 1530