1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 27 #include "dm_services.h" 28 #include "dm_helpers.h" 29 #include "core_types.h" 30 #include "resource.h" 31 #include "dccg.h" 32 #include "dce/dce_hwseq.h" 33 #include "dcn30/dcn30_cm_common.h" 34 #include "reg_helper.h" 35 #include "abm.h" 36 #include "hubp.h" 37 #include "dchubbub.h" 38 #include "timing_generator.h" 39 #include "opp.h" 40 #include "ipp.h" 41 #include "mpc.h" 42 #include "mcif_wb.h" 43 #include "dc_dmub_srv.h" 44 #include "link_hwss.h" 45 #include "dpcd_defs.h" 46 #include "dcn32_hwseq.h" 47 #include "clk_mgr.h" 48 #include "dsc.h" 49 #include "dcn20/dcn20_optc.h" 50 #include "dc_link_dp.h" 51 52 #define DC_LOGGER_INIT(logger) 53 54 #define CTX \ 55 hws->ctx 56 #define REG(reg)\ 57 hws->regs->reg 58 #define DC_LOGGER \ 59 dc->ctx->logger 60 61 62 #undef FN 63 #define FN(reg_name, field_name) \ 64 hws->shifts->field_name, hws->masks->field_name 65 66 void dcn32_dsc_pg_control( 67 struct dce_hwseq *hws, 68 unsigned int dsc_inst, 69 bool power_on) 70 { 71 uint32_t power_gate = power_on ? 0 : 1; 72 uint32_t pwr_status = power_on ? 0 : 2; 73 uint32_t org_ip_request_cntl = 0; 74 75 if (hws->ctx->dc->debug.disable_dsc_power_gate) 76 return; 77 78 REG_GET(DC_IP_REQUEST_CNTL, IP_REQUEST_EN, &org_ip_request_cntl); 79 if (org_ip_request_cntl == 0) 80 REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 1); 81 82 switch (dsc_inst) { 83 case 0: /* DSC0 */ 84 REG_UPDATE(DOMAIN16_PG_CONFIG, 85 DOMAIN_POWER_GATE, power_gate); 86 87 REG_WAIT(DOMAIN16_PG_STATUS, 88 DOMAIN_PGFSM_PWR_STATUS, pwr_status, 89 1, 1000); 90 break; 91 case 1: /* DSC1 */ 92 REG_UPDATE(DOMAIN17_PG_CONFIG, 93 DOMAIN_POWER_GATE, power_gate); 94 95 REG_WAIT(DOMAIN17_PG_STATUS, 96 DOMAIN_PGFSM_PWR_STATUS, pwr_status, 97 1, 1000); 98 break; 99 case 2: /* DSC2 */ 100 REG_UPDATE(DOMAIN18_PG_CONFIG, 101 DOMAIN_POWER_GATE, power_gate); 102 103 REG_WAIT(DOMAIN18_PG_STATUS, 104 DOMAIN_PGFSM_PWR_STATUS, pwr_status, 105 1, 1000); 106 break; 107 case 3: /* DSC3 */ 108 REG_UPDATE(DOMAIN19_PG_CONFIG, 109 DOMAIN_POWER_GATE, power_gate); 110 111 REG_WAIT(DOMAIN19_PG_STATUS, 112 DOMAIN_PGFSM_PWR_STATUS, pwr_status, 113 1, 1000); 114 break; 115 default: 116 BREAK_TO_DEBUGGER(); 117 break; 118 } 119 120 if (org_ip_request_cntl == 0) 121 REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 0); 122 } 123 124 125 void dcn32_enable_power_gating_plane( 126 struct dce_hwseq *hws, 127 bool enable) 128 { 129 bool force_on = true; /* disable power gating */ 130 131 if (enable) 132 force_on = false; 133 134 /* DCHUBP0/1/2/3 */ 135 REG_UPDATE(DOMAIN0_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on); 136 REG_UPDATE(DOMAIN1_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on); 137 REG_UPDATE(DOMAIN2_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on); 138 REG_UPDATE(DOMAIN3_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on); 139 140 /* DCS0/1/2/3 */ 141 REG_UPDATE(DOMAIN16_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on); 142 REG_UPDATE(DOMAIN17_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on); 143 REG_UPDATE(DOMAIN18_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on); 144 REG_UPDATE(DOMAIN19_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on); 145 } 146 147 void dcn32_hubp_pg_control(struct dce_hwseq *hws, unsigned int hubp_inst, bool power_on) 148 { 149 uint32_t power_gate = power_on ? 0 : 1; 150 uint32_t pwr_status = power_on ? 0 : 2; 151 152 if (hws->ctx->dc->debug.disable_hubp_power_gate) 153 return; 154 155 if (REG(DOMAIN0_PG_CONFIG) == 0) 156 return; 157 158 switch (hubp_inst) { 159 case 0: 160 REG_SET(DOMAIN0_PG_CONFIG, 0, DOMAIN_POWER_GATE, power_gate); 161 REG_WAIT(DOMAIN0_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, pwr_status, 1, 1000); 162 break; 163 case 1: 164 REG_SET(DOMAIN1_PG_CONFIG, 0, DOMAIN_POWER_GATE, power_gate); 165 REG_WAIT(DOMAIN1_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, pwr_status, 1, 1000); 166 break; 167 case 2: 168 REG_SET(DOMAIN2_PG_CONFIG, 0, DOMAIN_POWER_GATE, power_gate); 169 REG_WAIT(DOMAIN2_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, pwr_status, 1, 1000); 170 break; 171 case 3: 172 REG_SET(DOMAIN3_PG_CONFIG, 0, DOMAIN_POWER_GATE, power_gate); 173 REG_WAIT(DOMAIN3_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, pwr_status, 1, 1000); 174 break; 175 default: 176 BREAK_TO_DEBUGGER(); 177 break; 178 } 179 } 180 181 static bool dcn32_check_no_memory_request_for_cab(struct dc *dc) 182 { 183 int i; 184 185 /* First, check no-memory-request case */ 186 for (i = 0; i < dc->current_state->stream_count; i++) { 187 if (dc->current_state->stream_status[i].plane_count) 188 /* Fail eligibility on a visible stream */ 189 break; 190 } 191 192 if (i == dc->current_state->stream_count) 193 return true; 194 195 return false; 196 } 197 198 /* This function takes in the start address and surface size to be cached in CAB 199 * and calculates the total number of cache lines required to store the surface. 200 * The number of cache lines used for each surface is calculated independently of 201 * one another. For example, if there is a primary surface(1), meta surface(2), and 202 * cursor(3), this function should be called 3 times to calculate the number of cache 203 * lines used for each of those surfaces. 204 */ 205 static uint32_t dcn32_cache_lines_for_surface(struct dc *dc, uint32_t surface_size, uint64_t start_address) 206 { 207 uint32_t lines_used = 1; 208 uint32_t num_cached_bytes = 0; 209 uint32_t remaining_size = 0; 210 uint32_t cache_line_size = dc->caps.cache_line_size; 211 212 /* 1. Calculate surface size minus the number of bytes stored 213 * in the first cache line (all bytes in first cache line might 214 * not be fully used). 215 */ 216 num_cached_bytes = cache_line_size - (start_address % cache_line_size); 217 remaining_size = surface_size - num_cached_bytes; 218 219 /* 2. Calculate number of cache lines that will be fully used with 220 * the remaining number of bytes to be stored. 221 */ 222 lines_used += (remaining_size / cache_line_size); 223 224 /* 3. Check if we need an extra line due to the remaining size not being 225 * a multiple of CACHE_LINE_SIZE. 226 */ 227 if (remaining_size % cache_line_size > 0) 228 lines_used++; 229 230 return lines_used; 231 } 232 233 /* This function loops through every surface that needs to be cached in CAB for SS, 234 * and calculates the total number of ways required to store all surfaces (primary, 235 * meta, cursor). 236 */ 237 static uint32_t dcn32_calculate_cab_allocation(struct dc *dc, struct dc_state *ctx) 238 { 239 uint8_t i, j; 240 struct dc_stream_state *stream = NULL; 241 struct dc_plane_state *plane = NULL; 242 uint32_t surface_size = 0; 243 uint32_t cursor_size = 0; 244 uint32_t cache_lines_used = 0; 245 uint32_t total_lines = 0; 246 uint32_t lines_per_way = 0; 247 uint32_t num_ways = 0; 248 249 for (i = 0; i < ctx->stream_count; i++) { 250 stream = ctx->streams[i]; 251 252 // Don't include PSR surface in the total surface size for CAB allocation 253 if (stream->link->psr_settings.psr_version != DC_PSR_VERSION_UNSUPPORTED) 254 continue; 255 256 if (ctx->stream_status[i].plane_count == 0) 257 continue; 258 259 // For each stream, loop through each plane to calculate the number of cache 260 // lines required to store the surface in CAB 261 for (j = 0; j < ctx->stream_status[i].plane_count; j++) { 262 plane = ctx->stream_status[i].plane_states[j]; 263 264 // Calculate total surface size 265 surface_size = plane->plane_size.surface_pitch * 266 plane->plane_size.surface_size.height * 267 (plane->format >= SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616 ? 8 : 4); 268 269 // Convert surface size + starting address to number of cache lines required 270 // (alignment accounted for) 271 cache_lines_used += dcn32_cache_lines_for_surface(dc, surface_size, 272 plane->address.grph.addr.quad_part); 273 274 if (plane->address.grph.meta_addr.quad_part) { 275 // Meta surface 276 cache_lines_used += dcn32_cache_lines_for_surface(dc, surface_size, 277 plane->address.grph.meta_addr.quad_part); 278 } 279 } 280 281 // Include cursor size for CAB allocation 282 if (stream->cursor_position.enable && plane->address.grph.cursor_cache_addr.quad_part) { 283 cursor_size = dc->caps.max_cursor_size * dc->caps.max_cursor_size; 284 switch (stream->cursor_attributes.color_format) { 285 case CURSOR_MODE_MONO: 286 cursor_size /= 2; 287 break; 288 case CURSOR_MODE_COLOR_1BIT_AND: 289 case CURSOR_MODE_COLOR_PRE_MULTIPLIED_ALPHA: 290 case CURSOR_MODE_COLOR_UN_PRE_MULTIPLIED_ALPHA: 291 cursor_size *= 4; 292 break; 293 294 case CURSOR_MODE_COLOR_64BIT_FP_PRE_MULTIPLIED: 295 case CURSOR_MODE_COLOR_64BIT_FP_UN_PRE_MULTIPLIED: 296 cursor_size *= 8; 297 break; 298 } 299 cache_lines_used += dcn32_cache_lines_for_surface(dc, surface_size, 300 plane->address.grph.cursor_cache_addr.quad_part); 301 } 302 } 303 304 // Convert number of cache lines required to number of ways 305 total_lines = dc->caps.max_cab_allocation_bytes / dc->caps.cache_line_size; 306 lines_per_way = total_lines / dc->caps.cache_num_ways; 307 num_ways = cache_lines_used / lines_per_way; 308 309 if (cache_lines_used % lines_per_way > 0) 310 num_ways++; 311 312 return num_ways; 313 } 314 315 bool dcn32_apply_idle_power_optimizations(struct dc *dc, bool enable) 316 { 317 union dmub_rb_cmd cmd; 318 uint8_t ways; 319 320 if (!dc->ctx->dmub_srv) 321 return false; 322 323 if (enable) { 324 if (dc->current_state) { 325 326 /* 1. Check no memory request case for CAB. 327 * If no memory request case, send CAB_ACTION NO_DF_REQ DMUB message 328 */ 329 if (dcn32_check_no_memory_request_for_cab(dc)) { 330 /* Enable no-memory-requests case */ 331 memset(&cmd, 0, sizeof(cmd)); 332 cmd.cab.header.type = DMUB_CMD__CAB_FOR_SS; 333 cmd.cab.header.sub_type = DMUB_CMD__CAB_NO_DCN_REQ; 334 cmd.cab.header.payload_bytes = sizeof(cmd.cab) - sizeof(cmd.cab.header); 335 336 dc_dmub_srv_cmd_queue(dc->ctx->dmub_srv, &cmd); 337 dc_dmub_srv_cmd_execute(dc->ctx->dmub_srv); 338 339 return true; 340 } 341 342 /* 2. Check if all surfaces can fit in CAB. 343 * If surfaces can fit into CAB, send CAB_ACTION_ALLOW DMUB message 344 * and configure HUBP's to fetch from MALL 345 */ 346 ways = dcn32_calculate_cab_allocation(dc, dc->current_state); 347 if (ways <= dc->caps.cache_num_ways) { 348 memset(&cmd, 0, sizeof(cmd)); 349 cmd.cab.header.type = DMUB_CMD__CAB_FOR_SS; 350 cmd.cab.header.sub_type = DMUB_CMD__CAB_DCN_SS_FIT_IN_CAB; 351 cmd.cab.header.payload_bytes = sizeof(cmd.cab) - sizeof(cmd.cab.header); 352 cmd.cab.cab_alloc_ways = ways; 353 354 dc_dmub_srv_cmd_queue(dc->ctx->dmub_srv, &cmd); 355 dc_dmub_srv_cmd_execute(dc->ctx->dmub_srv); 356 357 return true; 358 } 359 360 } 361 return false; 362 } 363 364 /* Disable CAB */ 365 memset(&cmd, 0, sizeof(cmd)); 366 cmd.cab.header.type = DMUB_CMD__CAB_FOR_SS; 367 cmd.cab.header.sub_type = DMUB_CMD__CAB_NO_IDLE_OPTIMIZATION; 368 cmd.cab.header.payload_bytes = 369 sizeof(cmd.cab) - sizeof(cmd.cab.header); 370 371 dc_dmub_srv_cmd_queue(dc->ctx->dmub_srv, &cmd); 372 dc_dmub_srv_cmd_execute(dc->ctx->dmub_srv); 373 dc_dmub_srv_wait_idle(dc->ctx->dmub_srv); 374 375 return false; 376 } 377 378 /* Send DMCUB message with SubVP pipe info 379 * - For each pipe in context, populate payload with required SubVP information 380 * if the pipe is using SubVP for MCLK switch 381 * - This function must be called while the DMUB HW lock is acquired by driver 382 */ 383 void dcn32_commit_subvp_config(struct dc *dc, struct dc_state *context) 384 { 385 /* 386 int i; 387 bool enable_subvp = false; 388 389 if (!dc->ctx || !dc->ctx->dmub_srv) 390 return; 391 392 for (i = 0; i < dc->res_pool->pipe_count; i++) { 393 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; 394 395 if (pipe_ctx->stream && pipe_ctx->stream->mall_stream_config.paired_stream && 396 pipe_ctx->stream->mall_stream_config.type == SUBVP_MAIN) { 397 // There is at least 1 SubVP pipe, so enable SubVP 398 enable_subvp = true; 399 break; 400 } 401 } 402 dc_dmub_setup_subvp_dmub_command(dc, context, enable_subvp); 403 */ 404 } 405 406 static bool dcn32_set_mpc_shaper_3dlut( 407 struct pipe_ctx *pipe_ctx, const struct dc_stream_state *stream) 408 { 409 struct dpp *dpp_base = pipe_ctx->plane_res.dpp; 410 int mpcc_id = pipe_ctx->plane_res.hubp->inst; 411 struct mpc *mpc = pipe_ctx->stream_res.opp->ctx->dc->res_pool->mpc; 412 bool result = false; 413 414 const struct pwl_params *shaper_lut = NULL; 415 //get the shaper lut params 416 if (stream->func_shaper) { 417 if (stream->func_shaper->type == TF_TYPE_HWPWL) 418 shaper_lut = &stream->func_shaper->pwl; 419 else if (stream->func_shaper->type == TF_TYPE_DISTRIBUTED_POINTS) { 420 cm_helper_translate_curve_to_hw_format( 421 stream->func_shaper, 422 &dpp_base->shaper_params, true); 423 shaper_lut = &dpp_base->shaper_params; 424 } 425 } 426 427 if (stream->lut3d_func && 428 stream->lut3d_func->state.bits.initialized == 1) { 429 430 result = mpc->funcs->program_3dlut(mpc, 431 &stream->lut3d_func->lut_3d, 432 mpcc_id); 433 434 result = mpc->funcs->program_shaper(mpc, 435 shaper_lut, 436 mpcc_id); 437 } 438 439 return result; 440 } 441 bool dcn32_set_output_transfer_func(struct dc *dc, 442 struct pipe_ctx *pipe_ctx, 443 const struct dc_stream_state *stream) 444 { 445 int mpcc_id = pipe_ctx->plane_res.hubp->inst; 446 struct mpc *mpc = pipe_ctx->stream_res.opp->ctx->dc->res_pool->mpc; 447 struct pwl_params *params = NULL; 448 bool ret = false; 449 450 /* program OGAM or 3DLUT only for the top pipe*/ 451 if (pipe_ctx->top_pipe == NULL) { 452 /*program shaper and 3dlut in MPC*/ 453 ret = dcn32_set_mpc_shaper_3dlut(pipe_ctx, stream); 454 if (ret == false && mpc->funcs->set_output_gamma && stream->out_transfer_func) { 455 if (stream->out_transfer_func->type == TF_TYPE_HWPWL) 456 params = &stream->out_transfer_func->pwl; 457 else if (pipe_ctx->stream->out_transfer_func->type == 458 TF_TYPE_DISTRIBUTED_POINTS && 459 cm3_helper_translate_curve_to_hw_format( 460 stream->out_transfer_func, 461 &mpc->blender_params, false)) 462 params = &mpc->blender_params; 463 /* there are no ROM LUTs in OUTGAM */ 464 if (stream->out_transfer_func->type == TF_TYPE_PREDEFINED) 465 BREAK_TO_DEBUGGER(); 466 } 467 } 468 469 mpc->funcs->set_output_gamma(mpc, mpcc_id, params); 470 return ret; 471 } 472 473 /* Program P-State force value according to if pipe is using SubVP or not: 474 * 1. Reset P-State force on all pipes first 475 * 2. For each main pipe, force P-State disallow (P-State allow moderated by DMUB) 476 */ 477 void dcn32_subvp_update_force_pstate(struct dc *dc, struct dc_state *context) 478 { 479 int i; 480 int num_subvp = 0; 481 /* Unforce p-state for each pipe 482 */ 483 for (i = 0; i < dc->res_pool->pipe_count; i++) { 484 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; 485 struct hubp *hubp = pipe->plane_res.hubp; 486 487 if (hubp && hubp->funcs->hubp_update_force_pstate_disallow) 488 hubp->funcs->hubp_update_force_pstate_disallow(hubp, false); 489 if (pipe->stream && pipe->stream->mall_stream_config.type == SUBVP_MAIN) 490 num_subvp++; 491 } 492 493 if (num_subvp == 0) 494 return; 495 496 /* Loop through each pipe -- for each subvp main pipe force p-state allow equal to false. 497 */ 498 for (i = 0; i < dc->res_pool->pipe_count; i++) { 499 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; 500 501 if (pipe->stream && pipe->plane_state && pipe->stream->mall_stream_config.type == SUBVP_MAIN) { 502 struct hubp *hubp = pipe->plane_res.hubp; 503 504 if (hubp && hubp->funcs->hubp_update_force_pstate_disallow) 505 hubp->funcs->hubp_update_force_pstate_disallow(hubp, true); 506 } 507 } 508 } 509 510 /* Update MALL_SEL register based on if pipe / plane 511 * is a phantom pipe, main pipe, and if using MALL 512 * for SS. 513 */ 514 void dcn32_update_mall_sel(struct dc *dc, struct dc_state *context) 515 { 516 int i; 517 unsigned int num_ways = dcn32_calculate_cab_allocation(dc, context); 518 519 for (i = 0; i < dc->res_pool->pipe_count; i++) { 520 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; 521 struct hubp *hubp = pipe->plane_res.hubp; 522 523 if (pipe->stream && pipe->plane_state && hubp && hubp->funcs->hubp_update_mall_sel) { 524 if (pipe->stream->mall_stream_config.type == SUBVP_PHANTOM) { 525 hubp->funcs->hubp_update_mall_sel(hubp, 1); 526 } else { 527 hubp->funcs->hubp_update_mall_sel(hubp, 528 num_ways <= dc->caps.cache_num_ways && 529 pipe->stream->link->psr_settings.psr_version == DC_PSR_VERSION_UNSUPPORTED ? 2 : 0); 530 } 531 } 532 } 533 } 534 535 /* Program the sub-viewport pipe configuration after the main / phantom pipes 536 * have been programmed in hardware. 537 * 1. Update force P-State for all the main pipes (disallow P-state) 538 * 2. Update MALL_SEL register 539 * 3. Program FORCE_ONE_ROW_FOR_FRAME for main subvp pipes 540 */ 541 void dcn32_program_mall_pipe_config(struct dc *dc, struct dc_state *context) 542 { 543 int i; 544 struct dce_hwseq *hws = dc->hwseq; 545 // Update force P-state for each pipe accordingly 546 if (hws && hws->funcs.subvp_update_force_pstate) 547 hws->funcs.subvp_update_force_pstate(dc, context); 548 549 // Update MALL_SEL register for each pipe 550 if (hws && hws->funcs.update_mall_sel) 551 hws->funcs.update_mall_sel(dc, context); 552 553 // Program FORCE_ONE_ROW_FOR_FRAME and CURSOR_REQ_MODE for main subvp pipes 554 for (i = 0; i < dc->res_pool->pipe_count; i++) { 555 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; 556 struct hubp *hubp = pipe->plane_res.hubp; 557 558 if (pipe->stream && hubp && hubp->funcs->hubp_prepare_subvp_buffering) { 559 /* TODO - remove setting CURSOR_REQ_MODE to 0 for legacy cases 560 * - need to investigate single pipe MPO + SubVP case to 561 * see if CURSOR_REQ_MODE will be back to 1 for SubVP 562 * when it should be 0 for MPO 563 */ 564 if (pipe->stream->mall_stream_config.type == SUBVP_MAIN) { 565 hubp->funcs->hubp_prepare_subvp_buffering(hubp, true); 566 } 567 } 568 } 569 } 570 571 void dcn32_init_hw(struct dc *dc) 572 { 573 struct abm **abms = dc->res_pool->multiple_abms; 574 struct dce_hwseq *hws = dc->hwseq; 575 struct dc_bios *dcb = dc->ctx->dc_bios; 576 struct resource_pool *res_pool = dc->res_pool; 577 int i; 578 int edp_num; 579 uint32_t backlight = MAX_BACKLIGHT_LEVEL; 580 581 dc->debug.disable_idle_power_optimizations = true; 582 if (dc->clk_mgr && dc->clk_mgr->funcs->init_clocks) 583 dc->clk_mgr->funcs->init_clocks(dc->clk_mgr); 584 585 // Initialize the dccg 586 if (res_pool->dccg->funcs->dccg_init) 587 res_pool->dccg->funcs->dccg_init(res_pool->dccg); 588 589 if (!dcb->funcs->is_accelerated_mode(dcb)) { 590 hws->funcs.bios_golden_init(dc); 591 hws->funcs.disable_vga(dc->hwseq); 592 } 593 594 // Set default OPTC memory power states 595 if (dc->debug.enable_mem_low_power.bits.optc) { 596 // Shutdown when unassigned and light sleep in VBLANK 597 REG_SET_2(ODM_MEM_PWR_CTRL3, 0, ODM_MEM_UNASSIGNED_PWR_MODE, 3, ODM_MEM_VBLANK_PWR_MODE, 1); 598 } 599 600 if (dc->debug.enable_mem_low_power.bits.vga) { 601 // Power down VGA memory 602 REG_UPDATE(MMHUBBUB_MEM_PWR_CNTL, VGA_MEM_PWR_FORCE, 1); 603 } 604 605 if (dc->ctx->dc_bios->fw_info_valid) { 606 res_pool->ref_clocks.xtalin_clock_inKhz = 607 dc->ctx->dc_bios->fw_info.pll_info.crystal_frequency; 608 609 if (res_pool->dccg && res_pool->hubbub) { 610 (res_pool->dccg->funcs->get_dccg_ref_freq)(res_pool->dccg, 611 dc->ctx->dc_bios->fw_info.pll_info.crystal_frequency, 612 &res_pool->ref_clocks.dccg_ref_clock_inKhz); 613 614 (res_pool->hubbub->funcs->get_dchub_ref_freq)(res_pool->hubbub, 615 res_pool->ref_clocks.dccg_ref_clock_inKhz, 616 &res_pool->ref_clocks.dchub_ref_clock_inKhz); 617 } else { 618 // Not all ASICs have DCCG sw component 619 res_pool->ref_clocks.dccg_ref_clock_inKhz = 620 res_pool->ref_clocks.xtalin_clock_inKhz; 621 res_pool->ref_clocks.dchub_ref_clock_inKhz = 622 res_pool->ref_clocks.xtalin_clock_inKhz; 623 } 624 } else 625 ASSERT_CRITICAL(false); 626 627 for (i = 0; i < dc->link_count; i++) { 628 /* Power up AND update implementation according to the 629 * required signal (which may be different from the 630 * default signal on connector). 631 */ 632 struct dc_link *link = dc->links[i]; 633 634 link->link_enc->funcs->hw_init(link->link_enc); 635 636 /* Check for enabled DIG to identify enabled display */ 637 if (link->link_enc->funcs->is_dig_enabled && 638 link->link_enc->funcs->is_dig_enabled(link->link_enc)) { 639 link->link_status.link_active = true; 640 if (link->link_enc->funcs->fec_is_active && 641 link->link_enc->funcs->fec_is_active(link->link_enc)) 642 link->fec_state = dc_link_fec_enabled; 643 } 644 } 645 646 /* Power gate DSCs */ 647 for (i = 0; i < res_pool->res_cap->num_dsc; i++) 648 if (hws->funcs.dsc_pg_control != NULL) 649 hws->funcs.dsc_pg_control(hws, res_pool->dscs[i]->inst, false); 650 651 /* we want to turn off all dp displays before doing detection */ 652 dc_link_blank_all_dp_displays(dc); 653 654 /* If taking control over from VBIOS, we may want to optimize our first 655 * mode set, so we need to skip powering down pipes until we know which 656 * pipes we want to use. 657 * Otherwise, if taking control is not possible, we need to power 658 * everything down. 659 */ 660 if (dcb->funcs->is_accelerated_mode(dcb) || !dc->config.seamless_boot_edp_requested) { 661 hws->funcs.init_pipes(dc, dc->current_state); 662 if (dc->res_pool->hubbub->funcs->allow_self_refresh_control) 663 dc->res_pool->hubbub->funcs->allow_self_refresh_control(dc->res_pool->hubbub, 664 !dc->res_pool->hubbub->ctx->dc->debug.disable_stutter); 665 } 666 667 /* In headless boot cases, DIG may be turned 668 * on which causes HW/SW discrepancies. 669 * To avoid this, power down hardware on boot 670 * if DIG is turned on and seamless boot not enabled 671 */ 672 if (!dc->config.seamless_boot_edp_requested) { 673 struct dc_link *edp_links[MAX_NUM_EDP]; 674 struct dc_link *edp_link; 675 676 get_edp_links(dc, edp_links, &edp_num); 677 if (edp_num) { 678 for (i = 0; i < edp_num; i++) { 679 edp_link = edp_links[i]; 680 if (edp_link->link_enc->funcs->is_dig_enabled && 681 edp_link->link_enc->funcs->is_dig_enabled(edp_link->link_enc) && 682 dc->hwss.edp_backlight_control && 683 dc->hwss.power_down && 684 dc->hwss.edp_power_control) { 685 dc->hwss.edp_backlight_control(edp_link, false); 686 dc->hwss.power_down(dc); 687 dc->hwss.edp_power_control(edp_link, false); 688 } 689 } 690 } else { 691 for (i = 0; i < dc->link_count; i++) { 692 struct dc_link *link = dc->links[i]; 693 694 if (link->link_enc->funcs->is_dig_enabled && 695 link->link_enc->funcs->is_dig_enabled(link->link_enc) && 696 dc->hwss.power_down) { 697 dc->hwss.power_down(dc); 698 break; 699 } 700 701 } 702 } 703 } 704 705 for (i = 0; i < res_pool->audio_count; i++) { 706 struct audio *audio = res_pool->audios[i]; 707 708 audio->funcs->hw_init(audio); 709 } 710 711 for (i = 0; i < dc->link_count; i++) { 712 struct dc_link *link = dc->links[i]; 713 714 if (link->panel_cntl) 715 backlight = link->panel_cntl->funcs->hw_init(link->panel_cntl); 716 } 717 718 for (i = 0; i < dc->res_pool->pipe_count; i++) { 719 if (abms[i] != NULL && abms[i]->funcs != NULL) 720 abms[i]->funcs->abm_init(abms[i], backlight); 721 } 722 723 /* power AFMT HDMI memory TODO: may move to dis/en output save power*/ 724 REG_WRITE(DIO_MEM_PWR_CTRL, 0); 725 726 if (!dc->debug.disable_clock_gate) { 727 /* enable all DCN clock gating */ 728 REG_WRITE(DCCG_GATE_DISABLE_CNTL, 0); 729 730 REG_WRITE(DCCG_GATE_DISABLE_CNTL2, 0); 731 732 REG_UPDATE(DCFCLK_CNTL, DCFCLK_GATE_DIS, 0); 733 } 734 if (hws->funcs.enable_power_gating_plane) 735 hws->funcs.enable_power_gating_plane(dc->hwseq, true); 736 737 if (!dcb->funcs->is_accelerated_mode(dcb) && dc->res_pool->hubbub->funcs->init_watermarks) 738 dc->res_pool->hubbub->funcs->init_watermarks(dc->res_pool->hubbub); 739 740 if (dc->clk_mgr->funcs->notify_wm_ranges) 741 dc->clk_mgr->funcs->notify_wm_ranges(dc->clk_mgr); 742 743 if (dc->clk_mgr->funcs->set_hard_max_memclk) 744 dc->clk_mgr->funcs->set_hard_max_memclk(dc->clk_mgr); 745 746 if (dc->res_pool->hubbub->funcs->force_pstate_change_control) 747 dc->res_pool->hubbub->funcs->force_pstate_change_control( 748 dc->res_pool->hubbub, false, false); 749 750 if (dc->res_pool->hubbub->funcs->init_crb) 751 dc->res_pool->hubbub->funcs->init_crb(dc->res_pool->hubbub); 752 753 // Get DMCUB capabilities 754 if (dc->ctx->dmub_srv) { 755 dc_dmub_srv_query_caps_cmd(dc->ctx->dmub_srv->dmub); 756 dc->caps.dmub_caps.psr = dc->ctx->dmub_srv->dmub->feature_caps.psr; 757 } 758 } 759 760 static int calc_mpc_flow_ctrl_cnt(const struct dc_stream_state *stream, 761 int opp_cnt) 762 { 763 bool hblank_halved = optc2_is_two_pixels_per_containter(&stream->timing); 764 int flow_ctrl_cnt; 765 766 if (opp_cnt >= 2) 767 hblank_halved = true; 768 769 flow_ctrl_cnt = stream->timing.h_total - stream->timing.h_addressable - 770 stream->timing.h_border_left - 771 stream->timing.h_border_right; 772 773 if (hblank_halved) 774 flow_ctrl_cnt /= 2; 775 776 /* ODM combine 4:1 case */ 777 if (opp_cnt == 4) 778 flow_ctrl_cnt /= 2; 779 780 return flow_ctrl_cnt; 781 } 782 783 static void update_dsc_on_stream(struct pipe_ctx *pipe_ctx, bool enable) 784 { 785 struct display_stream_compressor *dsc = pipe_ctx->stream_res.dsc; 786 struct dc_stream_state *stream = pipe_ctx->stream; 787 struct pipe_ctx *odm_pipe; 788 int opp_cnt = 1; 789 790 ASSERT(dsc); 791 for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) 792 opp_cnt++; 793 794 if (enable) { 795 struct dsc_config dsc_cfg; 796 struct dsc_optc_config dsc_optc_cfg; 797 enum optc_dsc_mode optc_dsc_mode; 798 799 /* Enable DSC hw block */ 800 dsc_cfg.pic_width = (stream->timing.h_addressable + stream->timing.h_border_left + stream->timing.h_border_right) / opp_cnt; 801 dsc_cfg.pic_height = stream->timing.v_addressable + stream->timing.v_border_top + stream->timing.v_border_bottom; 802 dsc_cfg.pixel_encoding = stream->timing.pixel_encoding; 803 dsc_cfg.color_depth = stream->timing.display_color_depth; 804 dsc_cfg.is_odm = pipe_ctx->next_odm_pipe ? true : false; 805 dsc_cfg.dc_dsc_cfg = stream->timing.dsc_cfg; 806 ASSERT(dsc_cfg.dc_dsc_cfg.num_slices_h % opp_cnt == 0); 807 dsc_cfg.dc_dsc_cfg.num_slices_h /= opp_cnt; 808 809 dsc->funcs->dsc_set_config(dsc, &dsc_cfg, &dsc_optc_cfg); 810 dsc->funcs->dsc_enable(dsc, pipe_ctx->stream_res.opp->inst); 811 for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) { 812 struct display_stream_compressor *odm_dsc = odm_pipe->stream_res.dsc; 813 814 ASSERT(odm_dsc); 815 odm_dsc->funcs->dsc_set_config(odm_dsc, &dsc_cfg, &dsc_optc_cfg); 816 odm_dsc->funcs->dsc_enable(odm_dsc, odm_pipe->stream_res.opp->inst); 817 } 818 dsc_cfg.dc_dsc_cfg.num_slices_h *= opp_cnt; 819 dsc_cfg.pic_width *= opp_cnt; 820 821 optc_dsc_mode = dsc_optc_cfg.is_pixel_format_444 ? OPTC_DSC_ENABLED_444 : OPTC_DSC_ENABLED_NATIVE_SUBSAMPLED; 822 823 /* Enable DSC in OPTC */ 824 DC_LOG_DSC("Setting optc DSC config for tg instance %d:", pipe_ctx->stream_res.tg->inst); 825 pipe_ctx->stream_res.tg->funcs->set_dsc_config(pipe_ctx->stream_res.tg, 826 optc_dsc_mode, 827 dsc_optc_cfg.bytes_per_pixel, 828 dsc_optc_cfg.slice_width); 829 } else { 830 /* disable DSC in OPTC */ 831 pipe_ctx->stream_res.tg->funcs->set_dsc_config( 832 pipe_ctx->stream_res.tg, 833 OPTC_DSC_DISABLED, 0, 0); 834 835 /* disable DSC block */ 836 dsc->funcs->dsc_disable(pipe_ctx->stream_res.dsc); 837 for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) { 838 ASSERT(odm_pipe->stream_res.dsc); 839 odm_pipe->stream_res.dsc->funcs->dsc_disable(odm_pipe->stream_res.dsc); 840 } 841 } 842 } 843 844 /* 845 * Given any pipe_ctx, return the total ODM combine factor, and optionally return 846 * the OPPids which are used 847 * */ 848 static unsigned int get_odm_config(struct pipe_ctx *pipe_ctx, unsigned int *opp_instances) 849 { 850 unsigned int opp_count = 1; 851 struct pipe_ctx *odm_pipe; 852 853 /* First get to the top pipe */ 854 for (odm_pipe = pipe_ctx; odm_pipe->prev_odm_pipe; odm_pipe = odm_pipe->prev_odm_pipe) 855 ; 856 857 /* First pipe is always used */ 858 if (opp_instances) 859 opp_instances[0] = odm_pipe->stream_res.opp->inst; 860 861 /* Find and count odm pipes, if any */ 862 for (odm_pipe = odm_pipe->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) { 863 if (opp_instances) 864 opp_instances[opp_count] = odm_pipe->stream_res.opp->inst; 865 opp_count++; 866 } 867 868 return opp_count; 869 } 870 871 void dcn32_update_odm(struct dc *dc, struct dc_state *context, struct pipe_ctx *pipe_ctx) 872 { 873 struct pipe_ctx *odm_pipe; 874 int opp_cnt = 0; 875 int opp_inst[MAX_PIPES] = {0}; 876 bool rate_control_2x_pclk = (pipe_ctx->stream->timing.flags.INTERLACE || optc2_is_two_pixels_per_containter(&pipe_ctx->stream->timing)); 877 struct mpc_dwb_flow_control flow_control; 878 struct mpc *mpc = dc->res_pool->mpc; 879 int i; 880 881 opp_cnt = get_odm_config(pipe_ctx, opp_inst); 882 883 if (opp_cnt > 1) 884 pipe_ctx->stream_res.tg->funcs->set_odm_combine( 885 pipe_ctx->stream_res.tg, 886 opp_inst, opp_cnt, 887 &pipe_ctx->stream->timing); 888 else 889 pipe_ctx->stream_res.tg->funcs->set_odm_bypass( 890 pipe_ctx->stream_res.tg, &pipe_ctx->stream->timing); 891 892 rate_control_2x_pclk = rate_control_2x_pclk || opp_cnt > 1; 893 flow_control.flow_ctrl_mode = 0; 894 flow_control.flow_ctrl_cnt0 = 0x80; 895 flow_control.flow_ctrl_cnt1 = calc_mpc_flow_ctrl_cnt(pipe_ctx->stream, opp_cnt); 896 if (mpc->funcs->set_out_rate_control) { 897 for (i = 0; i < opp_cnt; ++i) { 898 mpc->funcs->set_out_rate_control( 899 mpc, opp_inst[i], 900 true, 901 rate_control_2x_pclk, 902 &flow_control); 903 } 904 } 905 906 for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) { 907 odm_pipe->stream_res.opp->funcs->opp_pipe_clock_control( 908 odm_pipe->stream_res.opp, 909 true); 910 } 911 912 // Don't program pixel clock after link is already enabled 913 /* if (false == pipe_ctx->clock_source->funcs->program_pix_clk( 914 pipe_ctx->clock_source, 915 &pipe_ctx->stream_res.pix_clk_params, 916 &pipe_ctx->pll_settings)) { 917 BREAK_TO_DEBUGGER(); 918 }*/ 919 920 if (pipe_ctx->stream_res.dsc) 921 update_dsc_on_stream(pipe_ctx, pipe_ctx->stream->timing.flags.DSC); 922 } 923 924 unsigned int dcn32_calculate_dccg_k1_k2_values(struct pipe_ctx *pipe_ctx, unsigned int *k1_div, unsigned int *k2_div) 925 { 926 struct dc_stream_state *stream = pipe_ctx->stream; 927 unsigned int odm_combine_factor = 0; 928 929 odm_combine_factor = get_odm_config(pipe_ctx, NULL); 930 931 if (is_dp_128b_132b_signal(pipe_ctx)) { 932 *k2_div = PIXEL_RATE_DIV_BY_1; 933 } else if (dc_is_hdmi_tmds_signal(pipe_ctx->stream->signal) || dc_is_dvi_signal(pipe_ctx->stream->signal)) { 934 *k1_div = PIXEL_RATE_DIV_BY_1; 935 if (stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR420) 936 *k2_div = PIXEL_RATE_DIV_BY_2; 937 else 938 *k2_div = PIXEL_RATE_DIV_BY_4; 939 } else if (dc_is_dp_signal(pipe_ctx->stream->signal)) { 940 if (stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR420) { 941 *k1_div = PIXEL_RATE_DIV_BY_1; 942 *k2_div = PIXEL_RATE_DIV_BY_2; 943 } else if (stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR422) { 944 *k1_div = PIXEL_RATE_DIV_BY_2; 945 *k2_div = PIXEL_RATE_DIV_BY_2; 946 } else { 947 if (odm_combine_factor == 1) 948 *k2_div = PIXEL_RATE_DIV_BY_4; 949 else if (odm_combine_factor == 2) 950 *k2_div = PIXEL_RATE_DIV_BY_2; 951 } 952 } 953 954 if ((*k1_div == PIXEL_RATE_DIV_NA) && (*k2_div == PIXEL_RATE_DIV_NA)) 955 ASSERT(false); 956 957 return odm_combine_factor; 958 } 959