1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 27 #include "dm_services.h" 28 #include "dm_helpers.h" 29 #include "core_types.h" 30 #include "resource.h" 31 #include "dccg.h" 32 #include "dce/dce_hwseq.h" 33 #include "dcn30/dcn30_cm_common.h" 34 #include "reg_helper.h" 35 #include "abm.h" 36 #include "hubp.h" 37 #include "dchubbub.h" 38 #include "timing_generator.h" 39 #include "opp.h" 40 #include "ipp.h" 41 #include "mpc.h" 42 #include "mcif_wb.h" 43 #include "dc_dmub_srv.h" 44 #include "link_hwss.h" 45 #include "dpcd_defs.h" 46 #include "dcn32_hwseq.h" 47 #include "clk_mgr.h" 48 #include "dsc.h" 49 #include "dcn20/dcn20_optc.h" 50 #include "dmub_subvp_state.h" 51 #include "dce/dmub_hw_lock_mgr.h" 52 #include "dcn32_resource.h" 53 #include "dc_link_dp.h" 54 #include "dmub/inc/dmub_subvp_state.h" 55 56 #define DC_LOGGER_INIT(logger) 57 58 #define CTX \ 59 hws->ctx 60 #define REG(reg)\ 61 hws->regs->reg 62 #define DC_LOGGER \ 63 dc->ctx->logger 64 65 66 #undef FN 67 #define FN(reg_name, field_name) \ 68 hws->shifts->field_name, hws->masks->field_name 69 70 void dcn32_dsc_pg_control( 71 struct dce_hwseq *hws, 72 unsigned int dsc_inst, 73 bool power_on) 74 { 75 uint32_t power_gate = power_on ? 0 : 1; 76 uint32_t pwr_status = power_on ? 0 : 2; 77 uint32_t org_ip_request_cntl = 0; 78 79 if (hws->ctx->dc->debug.disable_dsc_power_gate) 80 return; 81 82 REG_GET(DC_IP_REQUEST_CNTL, IP_REQUEST_EN, &org_ip_request_cntl); 83 if (org_ip_request_cntl == 0) 84 REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 1); 85 86 switch (dsc_inst) { 87 case 0: /* DSC0 */ 88 REG_UPDATE(DOMAIN16_PG_CONFIG, 89 DOMAIN_POWER_GATE, power_gate); 90 91 REG_WAIT(DOMAIN16_PG_STATUS, 92 DOMAIN_PGFSM_PWR_STATUS, pwr_status, 93 1, 1000); 94 break; 95 case 1: /* DSC1 */ 96 REG_UPDATE(DOMAIN17_PG_CONFIG, 97 DOMAIN_POWER_GATE, power_gate); 98 99 REG_WAIT(DOMAIN17_PG_STATUS, 100 DOMAIN_PGFSM_PWR_STATUS, pwr_status, 101 1, 1000); 102 break; 103 case 2: /* DSC2 */ 104 REG_UPDATE(DOMAIN18_PG_CONFIG, 105 DOMAIN_POWER_GATE, power_gate); 106 107 REG_WAIT(DOMAIN18_PG_STATUS, 108 DOMAIN_PGFSM_PWR_STATUS, pwr_status, 109 1, 1000); 110 break; 111 case 3: /* DSC3 */ 112 REG_UPDATE(DOMAIN19_PG_CONFIG, 113 DOMAIN_POWER_GATE, power_gate); 114 115 REG_WAIT(DOMAIN19_PG_STATUS, 116 DOMAIN_PGFSM_PWR_STATUS, pwr_status, 117 1, 1000); 118 break; 119 default: 120 BREAK_TO_DEBUGGER(); 121 break; 122 } 123 124 if (org_ip_request_cntl == 0) 125 REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 0); 126 } 127 128 129 void dcn32_enable_power_gating_plane( 130 struct dce_hwseq *hws, 131 bool enable) 132 { 133 bool force_on = true; /* disable power gating */ 134 135 if (enable) 136 force_on = false; 137 138 /* DCHUBP0/1/2/3 */ 139 REG_UPDATE(DOMAIN0_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on); 140 REG_UPDATE(DOMAIN1_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on); 141 REG_UPDATE(DOMAIN2_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on); 142 REG_UPDATE(DOMAIN3_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on); 143 144 /* DCS0/1/2/3 */ 145 REG_UPDATE(DOMAIN16_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on); 146 REG_UPDATE(DOMAIN17_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on); 147 REG_UPDATE(DOMAIN18_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on); 148 REG_UPDATE(DOMAIN19_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on); 149 } 150 151 void dcn32_hubp_pg_control(struct dce_hwseq *hws, unsigned int hubp_inst, bool power_on) 152 { 153 uint32_t power_gate = power_on ? 0 : 1; 154 uint32_t pwr_status = power_on ? 0 : 2; 155 156 if (hws->ctx->dc->debug.disable_hubp_power_gate) 157 return; 158 159 if (REG(DOMAIN0_PG_CONFIG) == 0) 160 return; 161 162 switch (hubp_inst) { 163 case 0: 164 REG_SET(DOMAIN0_PG_CONFIG, 0, DOMAIN_POWER_GATE, power_gate); 165 REG_WAIT(DOMAIN0_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, pwr_status, 1, 1000); 166 break; 167 case 1: 168 REG_SET(DOMAIN1_PG_CONFIG, 0, DOMAIN_POWER_GATE, power_gate); 169 REG_WAIT(DOMAIN1_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, pwr_status, 1, 1000); 170 break; 171 case 2: 172 REG_SET(DOMAIN2_PG_CONFIG, 0, DOMAIN_POWER_GATE, power_gate); 173 REG_WAIT(DOMAIN2_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, pwr_status, 1, 1000); 174 break; 175 case 3: 176 REG_SET(DOMAIN3_PG_CONFIG, 0, DOMAIN_POWER_GATE, power_gate); 177 REG_WAIT(DOMAIN3_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, pwr_status, 1, 1000); 178 break; 179 default: 180 BREAK_TO_DEBUGGER(); 181 break; 182 } 183 } 184 185 static bool dcn32_check_no_memory_request_for_cab(struct dc *dc) 186 { 187 int i; 188 189 /* First, check no-memory-request case */ 190 for (i = 0; i < dc->current_state->stream_count; i++) { 191 if (dc->current_state->stream_status[i].plane_count) 192 /* Fail eligibility on a visible stream */ 193 break; 194 } 195 196 if (i == dc->current_state->stream_count) 197 return true; 198 199 return false; 200 } 201 202 203 /* This function loops through every surface that needs to be cached in CAB for SS, 204 * and calculates the total number of ways required to store all surfaces (primary, 205 * meta, cursor). 206 */ 207 static uint32_t dcn32_calculate_cab_allocation(struct dc *dc, struct dc_state *ctx) 208 { 209 int i, j; 210 struct dc_stream_state *stream = NULL; 211 struct dc_plane_state *plane = NULL; 212 uint32_t cursor_size = 0; 213 uint32_t total_lines = 0; 214 uint32_t lines_per_way = 0; 215 uint8_t num_ways = 0; 216 uint8_t bytes_per_pixel = 0; 217 uint8_t cursor_bpp = 0; 218 uint16_t mblk_width = 0; 219 uint16_t mblk_height = 0; 220 uint16_t mall_alloc_width_blk_aligned = 0; 221 uint16_t mall_alloc_height_blk_aligned = 0; 222 uint16_t num_mblks = 0; 223 uint32_t bytes_in_mall = 0; 224 uint32_t cache_lines_used = 0; 225 uint32_t cache_lines_per_plane = 0; 226 227 for (i = 0; i < dc->res_pool->pipe_count; i++) { 228 struct pipe_ctx *pipe = &dc->current_state->res_ctx.pipe_ctx[i]; 229 230 /* If PSR is supported on an eDP panel that's connected, but that panel is 231 * not in PSR at the time of trying to enter MALL SS, we have to include it 232 * in the static screen CAB calculation 233 */ 234 if (!pipe->stream || !pipe->plane_state || 235 (pipe->stream->link->psr_settings.psr_version != DC_PSR_VERSION_UNSUPPORTED && 236 pipe->stream->link->psr_settings.psr_allow_active) || 237 pipe->stream->mall_stream_config.type == SUBVP_PHANTOM) 238 continue; 239 240 bytes_per_pixel = pipe->plane_state->format >= SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616 ? 8 : 4; 241 mblk_width = DCN3_2_MBLK_WIDTH; 242 mblk_height = bytes_per_pixel == 4 ? DCN3_2_MBLK_HEIGHT_4BPE : DCN3_2_MBLK_HEIGHT_8BPE; 243 244 /* full_vp_width_blk_aligned = FLOOR(vp_x_start + full_vp_width + blk_width - 1, blk_width) - 245 * FLOOR(vp_x_start, blk_width) 246 * 247 * mall_alloc_width_blk_aligned_l/c = full_vp_width_blk_aligned_l/c 248 */ 249 mall_alloc_width_blk_aligned = ((pipe->plane_res.scl_data.viewport.x + 250 pipe->plane_res.scl_data.viewport.width + mblk_width - 1) / mblk_width * mblk_width) - 251 (pipe->plane_res.scl_data.viewport.x / mblk_width * mblk_width); 252 253 /* full_vp_height_blk_aligned = FLOOR(vp_y_start + full_vp_height + blk_height - 1, blk_height) - 254 * FLOOR(vp_y_start, blk_height) 255 * 256 * mall_alloc_height_blk_aligned_l/c = full_vp_height_blk_aligned_l/c 257 */ 258 mall_alloc_height_blk_aligned = ((pipe->plane_res.scl_data.viewport.y + 259 pipe->plane_res.scl_data.viewport.height + mblk_height - 1) / mblk_height * mblk_height) - 260 (pipe->plane_res.scl_data.viewport.y / mblk_height * mblk_height); 261 262 num_mblks = ((mall_alloc_width_blk_aligned + mblk_width - 1) / mblk_width) * 263 ((mall_alloc_height_blk_aligned + mblk_height - 1) / mblk_height); 264 265 /*For DCC: 266 * meta_num_mblk = CEILING(meta_pitch*full_vp_height*Bpe/256/mblk_bytes, 1) 267 */ 268 if (pipe->plane_state->dcc.enable) 269 num_mblks += (pipe->plane_state->dcc.meta_pitch * pipe->plane_res.scl_data.viewport.height * bytes_per_pixel + 270 (256 * DCN3_2_MALL_MBLK_SIZE_BYTES) - 1) / (256 * DCN3_2_MALL_MBLK_SIZE_BYTES); 271 272 bytes_in_mall = num_mblks * DCN3_2_MALL_MBLK_SIZE_BYTES; 273 274 /* (cache lines used is total bytes / cache_line size. Add +2 for worst case alignment 275 * (MALL is 64-byte aligned) 276 */ 277 cache_lines_per_plane = bytes_in_mall / dc->caps.cache_line_size + 2; 278 cache_lines_used += cache_lines_per_plane; 279 } 280 281 // Include cursor size for CAB allocation 282 for (j = 0; j < dc->res_pool->pipe_count; j++) { 283 struct pipe_ctx *pipe = &ctx->res_ctx.pipe_ctx[j]; 284 struct hubp *hubp = pipe->plane_res.hubp; 285 286 if (pipe->stream && pipe->plane_state && hubp) 287 /* Find the cursor plane and use the exact size instead of 288 using the max for calculation */ 289 290 if (hubp->curs_attr.width > 0) { 291 cursor_size = hubp->curs_attr.pitch * hubp->curs_attr.height; 292 293 switch (pipe->stream->cursor_attributes.color_format) { 294 case CURSOR_MODE_MONO: 295 cursor_size /= 2; 296 cursor_bpp = 4; 297 break; 298 case CURSOR_MODE_COLOR_1BIT_AND: 299 case CURSOR_MODE_COLOR_PRE_MULTIPLIED_ALPHA: 300 case CURSOR_MODE_COLOR_UN_PRE_MULTIPLIED_ALPHA: 301 cursor_size *= 4; 302 cursor_bpp = 4; 303 break; 304 305 case CURSOR_MODE_COLOR_64BIT_FP_PRE_MULTIPLIED: 306 case CURSOR_MODE_COLOR_64BIT_FP_UN_PRE_MULTIPLIED: 307 cursor_size *= 8; 308 cursor_bpp = 8; 309 break; 310 } 311 312 if (pipe->stream->cursor_position.enable && !dc->debug.alloc_extra_way_for_cursor && 313 cursor_size > 16384) { 314 /* cursor_num_mblk = CEILING(num_cursors*cursor_width*cursor_width*cursor_Bpe/mblk_bytes, 1) 315 */ 316 cache_lines_used += (((cursor_size + DCN3_2_MALL_MBLK_SIZE_BYTES - 1) / 317 DCN3_2_MALL_MBLK_SIZE_BYTES) * DCN3_2_MALL_MBLK_SIZE_BYTES) / 318 dc->caps.cache_line_size + 2; 319 break; 320 } 321 } 322 } 323 324 // Convert number of cache lines required to number of ways 325 total_lines = dc->caps.max_cab_allocation_bytes / dc->caps.cache_line_size; 326 lines_per_way = total_lines / dc->caps.cache_num_ways; 327 num_ways = cache_lines_used / lines_per_way; 328 329 if (cache_lines_used % lines_per_way > 0) 330 num_ways++; 331 332 for (i = 0; i < ctx->stream_count; i++) { 333 stream = ctx->streams[i]; 334 for (j = 0; j < ctx->stream_status[i].plane_count; j++) { 335 plane = ctx->stream_status[i].plane_states[j]; 336 337 if (stream->cursor_position.enable && plane && 338 dc->debug.alloc_extra_way_for_cursor && 339 cursor_size > 16384) { 340 /* Cursor caching is not supported since it won't be on the same line. 341 * So we need an extra line to accommodate it. With large cursors and a single 4k monitor 342 * this case triggers corruption. If we're at the edge, then dont trigger display refresh 343 * from MALL. We only need to cache cursor if its greater that 64x64 at 4 bpp. 344 */ 345 num_ways++; 346 /* We only expect one cursor plane */ 347 break; 348 } 349 } 350 } 351 if (dc->debug.force_mall_ss_num_ways > 0) { 352 num_ways = dc->debug.force_mall_ss_num_ways; 353 } 354 return num_ways; 355 } 356 357 bool dcn32_apply_idle_power_optimizations(struct dc *dc, bool enable) 358 { 359 union dmub_rb_cmd cmd; 360 uint8_t ways, i; 361 int j; 362 bool mall_ss_unsupported = false; 363 struct dc_plane_state *plane = NULL; 364 365 if (!dc->ctx->dmub_srv) 366 return false; 367 368 if (enable) { 369 if (dc->current_state) { 370 371 /* 1. Check no memory request case for CAB. 372 * If no memory request case, send CAB_ACTION NO_DF_REQ DMUB message 373 */ 374 if (dcn32_check_no_memory_request_for_cab(dc)) { 375 /* Enable no-memory-requests case */ 376 memset(&cmd, 0, sizeof(cmd)); 377 cmd.cab.header.type = DMUB_CMD__CAB_FOR_SS; 378 cmd.cab.header.sub_type = DMUB_CMD__CAB_NO_DCN_REQ; 379 cmd.cab.header.payload_bytes = sizeof(cmd.cab) - sizeof(cmd.cab.header); 380 381 dc_dmub_srv_cmd_queue(dc->ctx->dmub_srv, &cmd); 382 dc_dmub_srv_cmd_execute(dc->ctx->dmub_srv); 383 384 return true; 385 } 386 387 /* 2. Check if all surfaces can fit in CAB. 388 * If surfaces can fit into CAB, send CAB_ACTION_ALLOW DMUB message 389 * and configure HUBP's to fetch from MALL 390 */ 391 ways = dcn32_calculate_cab_allocation(dc, dc->current_state); 392 393 /* MALL not supported with Stereo3D or TMZ surface. If any plane is using stereo, 394 * or TMZ surface, don't try to enter MALL. 395 */ 396 for (i = 0; i < dc->current_state->stream_count; i++) { 397 for (j = 0; j < dc->current_state->stream_status[i].plane_count; j++) { 398 plane = dc->current_state->stream_status[i].plane_states[j]; 399 400 if (plane->address.type == PLN_ADDR_TYPE_GRPH_STEREO || 401 plane->address.tmz_surface) { 402 mall_ss_unsupported = true; 403 break; 404 } 405 } 406 if (mall_ss_unsupported) 407 break; 408 } 409 if (ways <= dc->caps.cache_num_ways && !mall_ss_unsupported) { 410 memset(&cmd, 0, sizeof(cmd)); 411 cmd.cab.header.type = DMUB_CMD__CAB_FOR_SS; 412 cmd.cab.header.sub_type = DMUB_CMD__CAB_DCN_SS_FIT_IN_CAB; 413 cmd.cab.header.payload_bytes = sizeof(cmd.cab) - sizeof(cmd.cab.header); 414 cmd.cab.cab_alloc_ways = ways; 415 416 dc_dmub_srv_cmd_queue(dc->ctx->dmub_srv, &cmd); 417 dc_dmub_srv_cmd_execute(dc->ctx->dmub_srv); 418 419 return true; 420 } 421 422 } 423 return false; 424 } 425 426 /* Disable CAB */ 427 memset(&cmd, 0, sizeof(cmd)); 428 cmd.cab.header.type = DMUB_CMD__CAB_FOR_SS; 429 cmd.cab.header.sub_type = DMUB_CMD__CAB_NO_IDLE_OPTIMIZATION; 430 cmd.cab.header.payload_bytes = 431 sizeof(cmd.cab) - sizeof(cmd.cab.header); 432 433 dc_dmub_srv_cmd_queue(dc->ctx->dmub_srv, &cmd); 434 dc_dmub_srv_cmd_execute(dc->ctx->dmub_srv); 435 dc_dmub_srv_wait_idle(dc->ctx->dmub_srv); 436 437 return true; 438 } 439 440 /* Send DMCUB message with SubVP pipe info 441 * - For each pipe in context, populate payload with required SubVP information 442 * if the pipe is using SubVP for MCLK switch 443 * - This function must be called while the DMUB HW lock is acquired by driver 444 */ 445 void dcn32_commit_subvp_config(struct dc *dc, struct dc_state *context) 446 { 447 int i; 448 bool enable_subvp = false; 449 450 if (!dc->ctx || !dc->ctx->dmub_srv) 451 return; 452 453 for (i = 0; i < dc->res_pool->pipe_count; i++) { 454 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; 455 456 if (pipe_ctx->stream && pipe_ctx->stream->mall_stream_config.paired_stream && 457 pipe_ctx->stream->mall_stream_config.type == SUBVP_MAIN) { 458 // There is at least 1 SubVP pipe, so enable SubVP 459 enable_subvp = true; 460 break; 461 } 462 } 463 dc_dmub_setup_subvp_dmub_command(dc, context, enable_subvp); 464 } 465 466 /* Sub-Viewport DMUB lock needs to be acquired by driver whenever SubVP is active and: 467 * 1. Any full update for any SubVP main pipe 468 * 2. Any immediate flip for any SubVP pipe 469 * 3. Any flip for DRR pipe 470 * 4. If SubVP was previously in use (i.e. in old context) 471 */ 472 void dcn32_subvp_pipe_control_lock(struct dc *dc, 473 struct dc_state *context, 474 bool lock, 475 bool should_lock_all_pipes, 476 struct pipe_ctx *top_pipe_to_program, 477 bool subvp_prev_use) 478 { 479 unsigned int i = 0; 480 bool subvp_immediate_flip = false; 481 bool subvp_in_use = false; 482 struct pipe_ctx *pipe; 483 484 for (i = 0; i < dc->res_pool->pipe_count; i++) { 485 pipe = &context->res_ctx.pipe_ctx[i]; 486 487 if (pipe->stream && pipe->plane_state && pipe->stream->mall_stream_config.type == SUBVP_MAIN) { 488 subvp_in_use = true; 489 break; 490 } 491 } 492 493 if (top_pipe_to_program && top_pipe_to_program->stream && top_pipe_to_program->plane_state) { 494 if (top_pipe_to_program->stream->mall_stream_config.type == SUBVP_MAIN && 495 top_pipe_to_program->plane_state->flip_immediate) 496 subvp_immediate_flip = true; 497 } 498 499 // Don't need to lock for DRR VSYNC flips -- FW will wait for DRR pending update cleared. 500 if ((subvp_in_use && (should_lock_all_pipes || subvp_immediate_flip)) || (!subvp_in_use && subvp_prev_use)) { 501 union dmub_inbox0_cmd_lock_hw hw_lock_cmd = { 0 }; 502 503 if (!lock) { 504 for (i = 0; i < dc->res_pool->pipe_count; i++) { 505 pipe = &context->res_ctx.pipe_ctx[i]; 506 if (pipe->stream && pipe->plane_state && pipe->stream->mall_stream_config.type == SUBVP_MAIN && 507 should_lock_all_pipes) 508 pipe->stream_res.tg->funcs->wait_for_state(pipe->stream_res.tg, CRTC_STATE_VBLANK); 509 } 510 } 511 512 hw_lock_cmd.bits.command_code = DMUB_INBOX0_CMD__HW_LOCK; 513 hw_lock_cmd.bits.hw_lock_client = HW_LOCK_CLIENT_DRIVER; 514 hw_lock_cmd.bits.lock = lock; 515 hw_lock_cmd.bits.should_release = !lock; 516 dmub_hw_lock_mgr_inbox0_cmd(dc->ctx->dmub_srv, hw_lock_cmd); 517 } 518 } 519 520 521 static bool dcn32_set_mpc_shaper_3dlut( 522 struct pipe_ctx *pipe_ctx, const struct dc_stream_state *stream) 523 { 524 struct dpp *dpp_base = pipe_ctx->plane_res.dpp; 525 int mpcc_id = pipe_ctx->plane_res.hubp->inst; 526 struct mpc *mpc = pipe_ctx->stream_res.opp->ctx->dc->res_pool->mpc; 527 bool result = false; 528 529 const struct pwl_params *shaper_lut = NULL; 530 //get the shaper lut params 531 if (stream->func_shaper) { 532 if (stream->func_shaper->type == TF_TYPE_HWPWL) 533 shaper_lut = &stream->func_shaper->pwl; 534 else if (stream->func_shaper->type == TF_TYPE_DISTRIBUTED_POINTS) { 535 cm_helper_translate_curve_to_hw_format( 536 stream->func_shaper, 537 &dpp_base->shaper_params, true); 538 shaper_lut = &dpp_base->shaper_params; 539 } 540 } 541 542 if (stream->lut3d_func && 543 stream->lut3d_func->state.bits.initialized == 1) { 544 545 result = mpc->funcs->program_3dlut(mpc, 546 &stream->lut3d_func->lut_3d, 547 mpcc_id); 548 549 result = mpc->funcs->program_shaper(mpc, 550 shaper_lut, 551 mpcc_id); 552 } 553 554 return result; 555 } 556 557 bool dcn32_set_mcm_luts( 558 struct pipe_ctx *pipe_ctx, const struct dc_plane_state *plane_state) 559 { 560 struct dpp *dpp_base = pipe_ctx->plane_res.dpp; 561 int mpcc_id = pipe_ctx->plane_res.hubp->inst; 562 struct mpc *mpc = pipe_ctx->stream_res.opp->ctx->dc->res_pool->mpc; 563 bool result = true; 564 struct pwl_params *lut_params = NULL; 565 566 // 1D LUT 567 if (plane_state->blend_tf) { 568 if (plane_state->blend_tf->type == TF_TYPE_HWPWL) 569 lut_params = &plane_state->blend_tf->pwl; 570 else if (plane_state->blend_tf->type == TF_TYPE_DISTRIBUTED_POINTS) { 571 cm_helper_translate_curve_to_hw_format( 572 plane_state->blend_tf, 573 &dpp_base->regamma_params, false); 574 lut_params = &dpp_base->regamma_params; 575 } 576 } 577 result = mpc->funcs->program_1dlut(mpc, lut_params, mpcc_id); 578 579 // Shaper 580 if (plane_state->in_shaper_func) { 581 if (plane_state->in_shaper_func->type == TF_TYPE_HWPWL) 582 lut_params = &plane_state->in_shaper_func->pwl; 583 else if (plane_state->in_shaper_func->type == TF_TYPE_DISTRIBUTED_POINTS) { 584 // TODO: dpp_base replace 585 ASSERT(false); 586 cm_helper_translate_curve_to_hw_format( 587 plane_state->in_shaper_func, 588 &dpp_base->shaper_params, true); 589 lut_params = &dpp_base->shaper_params; 590 } 591 } 592 593 result = mpc->funcs->program_shaper(mpc, lut_params, mpcc_id); 594 595 // 3D 596 if (plane_state->lut3d_func && plane_state->lut3d_func->state.bits.initialized == 1) 597 result = mpc->funcs->program_3dlut(mpc, &plane_state->lut3d_func->lut_3d, mpcc_id); 598 else 599 result = mpc->funcs->program_3dlut(mpc, NULL, mpcc_id); 600 601 return result; 602 } 603 604 bool dcn32_set_input_transfer_func(struct dc *dc, 605 struct pipe_ctx *pipe_ctx, 606 const struct dc_plane_state *plane_state) 607 { 608 struct dce_hwseq *hws = dc->hwseq; 609 struct mpc *mpc = dc->res_pool->mpc; 610 struct dpp *dpp_base = pipe_ctx->plane_res.dpp; 611 612 enum dc_transfer_func_predefined tf; 613 bool result = true; 614 struct pwl_params *params = NULL; 615 616 if (mpc == NULL || plane_state == NULL) 617 return false; 618 619 tf = TRANSFER_FUNCTION_UNITY; 620 621 if (plane_state->in_transfer_func && 622 plane_state->in_transfer_func->type == TF_TYPE_PREDEFINED) 623 tf = plane_state->in_transfer_func->tf; 624 625 dpp_base->funcs->dpp_set_pre_degam(dpp_base, tf); 626 627 if (plane_state->in_transfer_func) { 628 if (plane_state->in_transfer_func->type == TF_TYPE_HWPWL) 629 params = &plane_state->in_transfer_func->pwl; 630 else if (plane_state->in_transfer_func->type == TF_TYPE_DISTRIBUTED_POINTS && 631 cm3_helper_translate_curve_to_hw_format(plane_state->in_transfer_func, 632 &dpp_base->degamma_params, false)) 633 params = &dpp_base->degamma_params; 634 } 635 636 dpp_base->funcs->dpp_program_gamcor_lut(dpp_base, params); 637 638 if (pipe_ctx->stream_res.opp && 639 pipe_ctx->stream_res.opp->ctx && 640 hws->funcs.set_mcm_luts) 641 result = hws->funcs.set_mcm_luts(pipe_ctx, plane_state); 642 643 return result; 644 } 645 646 bool dcn32_set_output_transfer_func(struct dc *dc, 647 struct pipe_ctx *pipe_ctx, 648 const struct dc_stream_state *stream) 649 { 650 int mpcc_id = pipe_ctx->plane_res.hubp->inst; 651 struct mpc *mpc = pipe_ctx->stream_res.opp->ctx->dc->res_pool->mpc; 652 struct pwl_params *params = NULL; 653 bool ret = false; 654 655 /* program OGAM or 3DLUT only for the top pipe*/ 656 if (pipe_ctx->top_pipe == NULL) { 657 /*program shaper and 3dlut in MPC*/ 658 ret = dcn32_set_mpc_shaper_3dlut(pipe_ctx, stream); 659 if (ret == false && mpc->funcs->set_output_gamma && stream->out_transfer_func) { 660 if (stream->out_transfer_func->type == TF_TYPE_HWPWL) 661 params = &stream->out_transfer_func->pwl; 662 else if (pipe_ctx->stream->out_transfer_func->type == 663 TF_TYPE_DISTRIBUTED_POINTS && 664 cm3_helper_translate_curve_to_hw_format( 665 stream->out_transfer_func, 666 &mpc->blender_params, false)) 667 params = &mpc->blender_params; 668 /* there are no ROM LUTs in OUTGAM */ 669 if (stream->out_transfer_func->type == TF_TYPE_PREDEFINED) 670 BREAK_TO_DEBUGGER(); 671 } 672 } 673 674 mpc->funcs->set_output_gamma(mpc, mpcc_id, params); 675 return ret; 676 } 677 678 /* Program P-State force value according to if pipe is using SubVP or not: 679 * 1. Reset P-State force on all pipes first 680 * 2. For each main pipe, force P-State disallow (P-State allow moderated by DMUB) 681 */ 682 void dcn32_subvp_update_force_pstate(struct dc *dc, struct dc_state *context) 683 { 684 int i; 685 int num_subvp = 0; 686 /* Unforce p-state for each pipe 687 */ 688 for (i = 0; i < dc->res_pool->pipe_count; i++) { 689 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; 690 struct hubp *hubp = pipe->plane_res.hubp; 691 692 if (hubp && hubp->funcs->hubp_update_force_pstate_disallow) 693 hubp->funcs->hubp_update_force_pstate_disallow(hubp, false); 694 if (pipe->stream && pipe->stream->mall_stream_config.type == SUBVP_MAIN) 695 num_subvp++; 696 } 697 698 if (num_subvp == 0) 699 return; 700 701 /* Loop through each pipe -- for each subvp main pipe force p-state allow equal to false. 702 */ 703 for (i = 0; i < dc->res_pool->pipe_count; i++) { 704 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; 705 706 if (pipe->stream && pipe->plane_state && (pipe->stream->mall_stream_config.type == SUBVP_MAIN)) { 707 struct hubp *hubp = pipe->plane_res.hubp; 708 709 if (hubp && hubp->funcs->hubp_update_force_pstate_disallow) 710 hubp->funcs->hubp_update_force_pstate_disallow(hubp, true); 711 } 712 } 713 } 714 715 /* Update MALL_SEL register based on if pipe / plane 716 * is a phantom pipe, main pipe, and if using MALL 717 * for SS. 718 */ 719 void dcn32_update_mall_sel(struct dc *dc, struct dc_state *context) 720 { 721 int i; 722 unsigned int num_ways = dcn32_calculate_cab_allocation(dc, context); 723 bool cache_cursor = false; 724 725 for (i = 0; i < dc->res_pool->pipe_count; i++) { 726 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; 727 struct hubp *hubp = pipe->plane_res.hubp; 728 729 if (pipe->stream && pipe->plane_state && hubp && hubp->funcs->hubp_update_mall_sel) { 730 int cursor_size = hubp->curs_attr.pitch * hubp->curs_attr.height; 731 732 switch (hubp->curs_attr.color_format) { 733 case CURSOR_MODE_MONO: 734 cursor_size /= 2; 735 break; 736 case CURSOR_MODE_COLOR_1BIT_AND: 737 case CURSOR_MODE_COLOR_PRE_MULTIPLIED_ALPHA: 738 case CURSOR_MODE_COLOR_UN_PRE_MULTIPLIED_ALPHA: 739 cursor_size *= 4; 740 break; 741 742 case CURSOR_MODE_COLOR_64BIT_FP_PRE_MULTIPLIED: 743 case CURSOR_MODE_COLOR_64BIT_FP_UN_PRE_MULTIPLIED: 744 default: 745 cursor_size *= 8; 746 break; 747 } 748 749 if (cursor_size > 16384) 750 cache_cursor = true; 751 752 if (pipe->stream->mall_stream_config.type == SUBVP_PHANTOM) { 753 hubp->funcs->hubp_update_mall_sel(hubp, 1, false); 754 } else { 755 // MALL not supported with Stereo3D 756 hubp->funcs->hubp_update_mall_sel(hubp, 757 num_ways <= dc->caps.cache_num_ways && 758 pipe->stream->link->psr_settings.psr_version == DC_PSR_VERSION_UNSUPPORTED && 759 pipe->plane_state->address.type != PLN_ADDR_TYPE_GRPH_STEREO && 760 !pipe->plane_state->address.tmz_surface ? 2 : 0, 761 cache_cursor); 762 } 763 } 764 } 765 } 766 767 /* Program the sub-viewport pipe configuration after the main / phantom pipes 768 * have been programmed in hardware. 769 * 1. Update force P-State for all the main pipes (disallow P-state) 770 * 2. Update MALL_SEL register 771 * 3. Program FORCE_ONE_ROW_FOR_FRAME for main subvp pipes 772 */ 773 void dcn32_program_mall_pipe_config(struct dc *dc, struct dc_state *context) 774 { 775 int i; 776 struct dce_hwseq *hws = dc->hwseq; 777 778 // Don't force p-state disallow -- can't block dummy p-state 779 780 // Update MALL_SEL register for each pipe 781 if (hws && hws->funcs.update_mall_sel) 782 hws->funcs.update_mall_sel(dc, context); 783 784 //update subvp force pstate 785 if (hws && hws->funcs.subvp_update_force_pstate) 786 dc->hwseq->funcs.subvp_update_force_pstate(dc, context); 787 788 // Program FORCE_ONE_ROW_FOR_FRAME and CURSOR_REQ_MODE for main subvp pipes 789 for (i = 0; i < dc->res_pool->pipe_count; i++) { 790 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; 791 struct hubp *hubp = pipe->plane_res.hubp; 792 793 if (pipe->stream && hubp && hubp->funcs->hubp_prepare_subvp_buffering) { 794 /* TODO - remove setting CURSOR_REQ_MODE to 0 for legacy cases 795 * - need to investigate single pipe MPO + SubVP case to 796 * see if CURSOR_REQ_MODE will be back to 1 for SubVP 797 * when it should be 0 for MPO 798 */ 799 if (pipe->stream->mall_stream_config.type == SUBVP_MAIN) { 800 hubp->funcs->hubp_prepare_subvp_buffering(hubp, true); 801 } 802 } 803 } 804 } 805 806 void dcn32_init_hw(struct dc *dc) 807 { 808 struct abm **abms = dc->res_pool->multiple_abms; 809 struct dce_hwseq *hws = dc->hwseq; 810 struct dc_bios *dcb = dc->ctx->dc_bios; 811 struct resource_pool *res_pool = dc->res_pool; 812 int i; 813 int edp_num; 814 uint32_t backlight = MAX_BACKLIGHT_LEVEL; 815 816 if (dc->clk_mgr && dc->clk_mgr->funcs->init_clocks) 817 dc->clk_mgr->funcs->init_clocks(dc->clk_mgr); 818 819 // Initialize the dccg 820 if (res_pool->dccg->funcs->dccg_init) 821 res_pool->dccg->funcs->dccg_init(res_pool->dccg); 822 823 if (!dcb->funcs->is_accelerated_mode(dcb)) { 824 hws->funcs.bios_golden_init(dc); 825 hws->funcs.disable_vga(dc->hwseq); 826 } 827 828 // Set default OPTC memory power states 829 if (dc->debug.enable_mem_low_power.bits.optc) { 830 // Shutdown when unassigned and light sleep in VBLANK 831 REG_SET_2(ODM_MEM_PWR_CTRL3, 0, ODM_MEM_UNASSIGNED_PWR_MODE, 3, ODM_MEM_VBLANK_PWR_MODE, 1); 832 } 833 834 if (dc->debug.enable_mem_low_power.bits.vga) { 835 // Power down VGA memory 836 REG_UPDATE(MMHUBBUB_MEM_PWR_CNTL, VGA_MEM_PWR_FORCE, 1); 837 } 838 839 if (dc->ctx->dc_bios->fw_info_valid) { 840 res_pool->ref_clocks.xtalin_clock_inKhz = 841 dc->ctx->dc_bios->fw_info.pll_info.crystal_frequency; 842 843 if (res_pool->dccg && res_pool->hubbub) { 844 (res_pool->dccg->funcs->get_dccg_ref_freq)(res_pool->dccg, 845 dc->ctx->dc_bios->fw_info.pll_info.crystal_frequency, 846 &res_pool->ref_clocks.dccg_ref_clock_inKhz); 847 848 (res_pool->hubbub->funcs->get_dchub_ref_freq)(res_pool->hubbub, 849 res_pool->ref_clocks.dccg_ref_clock_inKhz, 850 &res_pool->ref_clocks.dchub_ref_clock_inKhz); 851 } else { 852 // Not all ASICs have DCCG sw component 853 res_pool->ref_clocks.dccg_ref_clock_inKhz = 854 res_pool->ref_clocks.xtalin_clock_inKhz; 855 res_pool->ref_clocks.dchub_ref_clock_inKhz = 856 res_pool->ref_clocks.xtalin_clock_inKhz; 857 } 858 } else 859 ASSERT_CRITICAL(false); 860 861 for (i = 0; i < dc->link_count; i++) { 862 /* Power up AND update implementation according to the 863 * required signal (which may be different from the 864 * default signal on connector). 865 */ 866 struct dc_link *link = dc->links[i]; 867 868 link->link_enc->funcs->hw_init(link->link_enc); 869 870 /* Check for enabled DIG to identify enabled display */ 871 if (link->link_enc->funcs->is_dig_enabled && 872 link->link_enc->funcs->is_dig_enabled(link->link_enc)) { 873 link->link_status.link_active = true; 874 link->phy_state.symclk_state = SYMCLK_ON_TX_ON; 875 if (link->link_enc->funcs->fec_is_active && 876 link->link_enc->funcs->fec_is_active(link->link_enc)) 877 link->fec_state = dc_link_fec_enabled; 878 } 879 } 880 881 /* Power gate DSCs */ 882 for (i = 0; i < res_pool->res_cap->num_dsc; i++) 883 if (hws->funcs.dsc_pg_control != NULL) 884 hws->funcs.dsc_pg_control(hws, res_pool->dscs[i]->inst, false); 885 886 /* we want to turn off all dp displays before doing detection */ 887 dc_link_blank_all_dp_displays(dc); 888 889 /* If taking control over from VBIOS, we may want to optimize our first 890 * mode set, so we need to skip powering down pipes until we know which 891 * pipes we want to use. 892 * Otherwise, if taking control is not possible, we need to power 893 * everything down. 894 */ 895 if (dcb->funcs->is_accelerated_mode(dcb) || !dc->config.seamless_boot_edp_requested) { 896 hws->funcs.init_pipes(dc, dc->current_state); 897 if (dc->res_pool->hubbub->funcs->allow_self_refresh_control) 898 dc->res_pool->hubbub->funcs->allow_self_refresh_control(dc->res_pool->hubbub, 899 !dc->res_pool->hubbub->ctx->dc->debug.disable_stutter); 900 } 901 902 /* In headless boot cases, DIG may be turned 903 * on which causes HW/SW discrepancies. 904 * To avoid this, power down hardware on boot 905 * if DIG is turned on and seamless boot not enabled 906 */ 907 if (!dc->config.seamless_boot_edp_requested) { 908 struct dc_link *edp_links[MAX_NUM_EDP]; 909 struct dc_link *edp_link; 910 911 get_edp_links(dc, edp_links, &edp_num); 912 if (edp_num) { 913 for (i = 0; i < edp_num; i++) { 914 edp_link = edp_links[i]; 915 if (edp_link->link_enc->funcs->is_dig_enabled && 916 edp_link->link_enc->funcs->is_dig_enabled(edp_link->link_enc) && 917 dc->hwss.edp_backlight_control && 918 dc->hwss.power_down && 919 dc->hwss.edp_power_control) { 920 dc->hwss.edp_backlight_control(edp_link, false); 921 dc->hwss.power_down(dc); 922 dc->hwss.edp_power_control(edp_link, false); 923 } 924 } 925 } else { 926 for (i = 0; i < dc->link_count; i++) { 927 struct dc_link *link = dc->links[i]; 928 929 if (link->link_enc->funcs->is_dig_enabled && 930 link->link_enc->funcs->is_dig_enabled(link->link_enc) && 931 dc->hwss.power_down) { 932 dc->hwss.power_down(dc); 933 break; 934 } 935 936 } 937 } 938 } 939 940 for (i = 0; i < res_pool->audio_count; i++) { 941 struct audio *audio = res_pool->audios[i]; 942 943 audio->funcs->hw_init(audio); 944 } 945 946 for (i = 0; i < dc->link_count; i++) { 947 struct dc_link *link = dc->links[i]; 948 949 if (link->panel_cntl) 950 backlight = link->panel_cntl->funcs->hw_init(link->panel_cntl); 951 } 952 953 for (i = 0; i < dc->res_pool->pipe_count; i++) { 954 if (abms[i] != NULL && abms[i]->funcs != NULL) 955 abms[i]->funcs->abm_init(abms[i], backlight); 956 } 957 958 /* power AFMT HDMI memory TODO: may move to dis/en output save power*/ 959 REG_WRITE(DIO_MEM_PWR_CTRL, 0); 960 961 if (!dc->debug.disable_clock_gate) { 962 /* enable all DCN clock gating */ 963 REG_WRITE(DCCG_GATE_DISABLE_CNTL, 0); 964 965 REG_WRITE(DCCG_GATE_DISABLE_CNTL2, 0); 966 967 REG_UPDATE(DCFCLK_CNTL, DCFCLK_GATE_DIS, 0); 968 } 969 if (hws->funcs.enable_power_gating_plane) 970 hws->funcs.enable_power_gating_plane(dc->hwseq, true); 971 972 if (!dcb->funcs->is_accelerated_mode(dcb) && dc->res_pool->hubbub->funcs->init_watermarks) 973 dc->res_pool->hubbub->funcs->init_watermarks(dc->res_pool->hubbub); 974 975 if (dc->clk_mgr->funcs->notify_wm_ranges) 976 dc->clk_mgr->funcs->notify_wm_ranges(dc->clk_mgr); 977 978 if (dc->clk_mgr->funcs->set_hard_max_memclk) 979 dc->clk_mgr->funcs->set_hard_max_memclk(dc->clk_mgr); 980 981 if (dc->res_pool->hubbub->funcs->force_pstate_change_control) 982 dc->res_pool->hubbub->funcs->force_pstate_change_control( 983 dc->res_pool->hubbub, false, false); 984 985 if (dc->res_pool->hubbub->funcs->init_crb) 986 dc->res_pool->hubbub->funcs->init_crb(dc->res_pool->hubbub); 987 988 if (dc->res_pool->hubbub->funcs->set_request_limit && dc->config.sdpif_request_limit_words_per_umc > 0) 989 dc->res_pool->hubbub->funcs->set_request_limit(dc->res_pool->hubbub, dc->ctx->dc_bios->vram_info.num_chans, dc->config.sdpif_request_limit_words_per_umc); 990 991 // Get DMCUB capabilities 992 if (dc->ctx->dmub_srv) { 993 dc_dmub_srv_query_caps_cmd(dc->ctx->dmub_srv->dmub); 994 dc->caps.dmub_caps.psr = dc->ctx->dmub_srv->dmub->feature_caps.psr; 995 } 996 } 997 998 static int calc_mpc_flow_ctrl_cnt(const struct dc_stream_state *stream, 999 int opp_cnt) 1000 { 1001 bool hblank_halved = optc2_is_two_pixels_per_containter(&stream->timing); 1002 int flow_ctrl_cnt; 1003 1004 if (opp_cnt >= 2) 1005 hblank_halved = true; 1006 1007 flow_ctrl_cnt = stream->timing.h_total - stream->timing.h_addressable - 1008 stream->timing.h_border_left - 1009 stream->timing.h_border_right; 1010 1011 if (hblank_halved) 1012 flow_ctrl_cnt /= 2; 1013 1014 /* ODM combine 4:1 case */ 1015 if (opp_cnt == 4) 1016 flow_ctrl_cnt /= 2; 1017 1018 return flow_ctrl_cnt; 1019 } 1020 1021 static void update_dsc_on_stream(struct pipe_ctx *pipe_ctx, bool enable) 1022 { 1023 struct display_stream_compressor *dsc = pipe_ctx->stream_res.dsc; 1024 struct dc_stream_state *stream = pipe_ctx->stream; 1025 struct pipe_ctx *odm_pipe; 1026 int opp_cnt = 1; 1027 1028 ASSERT(dsc); 1029 for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) 1030 opp_cnt++; 1031 1032 if (enable) { 1033 struct dsc_config dsc_cfg; 1034 struct dsc_optc_config dsc_optc_cfg; 1035 enum optc_dsc_mode optc_dsc_mode; 1036 1037 /* Enable DSC hw block */ 1038 dsc_cfg.pic_width = (stream->timing.h_addressable + stream->timing.h_border_left + stream->timing.h_border_right) / opp_cnt; 1039 dsc_cfg.pic_height = stream->timing.v_addressable + stream->timing.v_border_top + stream->timing.v_border_bottom; 1040 dsc_cfg.pixel_encoding = stream->timing.pixel_encoding; 1041 dsc_cfg.color_depth = stream->timing.display_color_depth; 1042 dsc_cfg.is_odm = pipe_ctx->next_odm_pipe ? true : false; 1043 dsc_cfg.dc_dsc_cfg = stream->timing.dsc_cfg; 1044 ASSERT(dsc_cfg.dc_dsc_cfg.num_slices_h % opp_cnt == 0); 1045 dsc_cfg.dc_dsc_cfg.num_slices_h /= opp_cnt; 1046 1047 dsc->funcs->dsc_set_config(dsc, &dsc_cfg, &dsc_optc_cfg); 1048 dsc->funcs->dsc_enable(dsc, pipe_ctx->stream_res.opp->inst); 1049 for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) { 1050 struct display_stream_compressor *odm_dsc = odm_pipe->stream_res.dsc; 1051 1052 ASSERT(odm_dsc); 1053 odm_dsc->funcs->dsc_set_config(odm_dsc, &dsc_cfg, &dsc_optc_cfg); 1054 odm_dsc->funcs->dsc_enable(odm_dsc, odm_pipe->stream_res.opp->inst); 1055 } 1056 dsc_cfg.dc_dsc_cfg.num_slices_h *= opp_cnt; 1057 dsc_cfg.pic_width *= opp_cnt; 1058 1059 optc_dsc_mode = dsc_optc_cfg.is_pixel_format_444 ? OPTC_DSC_ENABLED_444 : OPTC_DSC_ENABLED_NATIVE_SUBSAMPLED; 1060 1061 /* Enable DSC in OPTC */ 1062 DC_LOG_DSC("Setting optc DSC config for tg instance %d:", pipe_ctx->stream_res.tg->inst); 1063 pipe_ctx->stream_res.tg->funcs->set_dsc_config(pipe_ctx->stream_res.tg, 1064 optc_dsc_mode, 1065 dsc_optc_cfg.bytes_per_pixel, 1066 dsc_optc_cfg.slice_width); 1067 } else { 1068 /* disable DSC in OPTC */ 1069 pipe_ctx->stream_res.tg->funcs->set_dsc_config( 1070 pipe_ctx->stream_res.tg, 1071 OPTC_DSC_DISABLED, 0, 0); 1072 1073 /* disable DSC block */ 1074 dsc->funcs->dsc_disable(pipe_ctx->stream_res.dsc); 1075 for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) { 1076 ASSERT(odm_pipe->stream_res.dsc); 1077 odm_pipe->stream_res.dsc->funcs->dsc_disable(odm_pipe->stream_res.dsc); 1078 } 1079 } 1080 } 1081 1082 /* 1083 * Given any pipe_ctx, return the total ODM combine factor, and optionally return 1084 * the OPPids which are used 1085 * */ 1086 static unsigned int get_odm_config(struct pipe_ctx *pipe_ctx, unsigned int *opp_instances) 1087 { 1088 unsigned int opp_count = 1; 1089 struct pipe_ctx *odm_pipe; 1090 1091 /* First get to the top pipe */ 1092 for (odm_pipe = pipe_ctx; odm_pipe->prev_odm_pipe; odm_pipe = odm_pipe->prev_odm_pipe) 1093 ; 1094 1095 /* First pipe is always used */ 1096 if (opp_instances) 1097 opp_instances[0] = odm_pipe->stream_res.opp->inst; 1098 1099 /* Find and count odm pipes, if any */ 1100 for (odm_pipe = odm_pipe->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) { 1101 if (opp_instances) 1102 opp_instances[opp_count] = odm_pipe->stream_res.opp->inst; 1103 opp_count++; 1104 } 1105 1106 return opp_count; 1107 } 1108 1109 void dcn32_update_odm(struct dc *dc, struct dc_state *context, struct pipe_ctx *pipe_ctx) 1110 { 1111 struct pipe_ctx *odm_pipe; 1112 int opp_cnt = 0; 1113 int opp_inst[MAX_PIPES] = {0}; 1114 bool rate_control_2x_pclk = (pipe_ctx->stream->timing.flags.INTERLACE || optc2_is_two_pixels_per_containter(&pipe_ctx->stream->timing)); 1115 struct mpc_dwb_flow_control flow_control; 1116 struct mpc *mpc = dc->res_pool->mpc; 1117 int i; 1118 1119 opp_cnt = get_odm_config(pipe_ctx, opp_inst); 1120 1121 if (opp_cnt > 1) 1122 pipe_ctx->stream_res.tg->funcs->set_odm_combine( 1123 pipe_ctx->stream_res.tg, 1124 opp_inst, opp_cnt, 1125 &pipe_ctx->stream->timing); 1126 else 1127 pipe_ctx->stream_res.tg->funcs->set_odm_bypass( 1128 pipe_ctx->stream_res.tg, &pipe_ctx->stream->timing); 1129 1130 rate_control_2x_pclk = rate_control_2x_pclk || opp_cnt > 1; 1131 flow_control.flow_ctrl_mode = 0; 1132 flow_control.flow_ctrl_cnt0 = 0x80; 1133 flow_control.flow_ctrl_cnt1 = calc_mpc_flow_ctrl_cnt(pipe_ctx->stream, opp_cnt); 1134 if (mpc->funcs->set_out_rate_control) { 1135 for (i = 0; i < opp_cnt; ++i) { 1136 mpc->funcs->set_out_rate_control( 1137 mpc, opp_inst[i], 1138 true, 1139 rate_control_2x_pclk, 1140 &flow_control); 1141 } 1142 } 1143 1144 for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) { 1145 odm_pipe->stream_res.opp->funcs->opp_pipe_clock_control( 1146 odm_pipe->stream_res.opp, 1147 true); 1148 } 1149 1150 if (pipe_ctx->stream_res.dsc) { 1151 struct pipe_ctx *current_pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[pipe_ctx->pipe_idx]; 1152 1153 update_dsc_on_stream(pipe_ctx, pipe_ctx->stream->timing.flags.DSC); 1154 1155 /* Check if no longer using pipe for ODM, then need to disconnect DSC for that pipe */ 1156 if (!pipe_ctx->next_odm_pipe && current_pipe_ctx->next_odm_pipe && 1157 current_pipe_ctx->next_odm_pipe->stream_res.dsc) { 1158 struct display_stream_compressor *dsc = current_pipe_ctx->next_odm_pipe->stream_res.dsc; 1159 /* disconnect DSC block from stream */ 1160 dsc->funcs->dsc_disconnect(dsc); 1161 } 1162 } 1163 } 1164 1165 unsigned int dcn32_calculate_dccg_k1_k2_values(struct pipe_ctx *pipe_ctx, unsigned int *k1_div, unsigned int *k2_div) 1166 { 1167 struct dc_stream_state *stream = pipe_ctx->stream; 1168 unsigned int odm_combine_factor = 0; 1169 bool two_pix_per_container = false; 1170 1171 // For phantom pipes, use the same programming as the main pipes 1172 if (pipe_ctx->stream->mall_stream_config.type == SUBVP_PHANTOM) { 1173 stream = pipe_ctx->stream->mall_stream_config.paired_stream; 1174 } 1175 two_pix_per_container = optc2_is_two_pixels_per_containter(&stream->timing); 1176 odm_combine_factor = get_odm_config(pipe_ctx, NULL); 1177 1178 if (is_dp_128b_132b_signal(pipe_ctx)) { 1179 *k1_div = PIXEL_RATE_DIV_BY_1; 1180 *k2_div = PIXEL_RATE_DIV_BY_1; 1181 } else if (dc_is_hdmi_tmds_signal(pipe_ctx->stream->signal) || dc_is_dvi_signal(pipe_ctx->stream->signal)) { 1182 *k1_div = PIXEL_RATE_DIV_BY_1; 1183 if (stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR420) 1184 *k2_div = PIXEL_RATE_DIV_BY_2; 1185 else 1186 *k2_div = PIXEL_RATE_DIV_BY_4; 1187 } else if (dc_is_dp_signal(pipe_ctx->stream->signal) || dc_is_virtual_signal(pipe_ctx->stream->signal)) { 1188 if (two_pix_per_container) { 1189 *k1_div = PIXEL_RATE_DIV_BY_1; 1190 *k2_div = PIXEL_RATE_DIV_BY_2; 1191 } else { 1192 *k1_div = PIXEL_RATE_DIV_BY_1; 1193 *k2_div = PIXEL_RATE_DIV_BY_4; 1194 if ((odm_combine_factor == 2) || dcn32_is_dp_dig_pixel_rate_div_policy(pipe_ctx)) 1195 *k2_div = PIXEL_RATE_DIV_BY_2; 1196 } 1197 } 1198 1199 if ((*k1_div == PIXEL_RATE_DIV_NA) && (*k2_div == PIXEL_RATE_DIV_NA)) 1200 ASSERT(false); 1201 1202 return odm_combine_factor; 1203 } 1204 1205 void dcn32_set_pixels_per_cycle(struct pipe_ctx *pipe_ctx) 1206 { 1207 uint32_t pix_per_cycle = 1; 1208 uint32_t odm_combine_factor = 1; 1209 1210 if (!pipe_ctx || !pipe_ctx->stream || !pipe_ctx->stream_res.stream_enc) 1211 return; 1212 1213 odm_combine_factor = get_odm_config(pipe_ctx, NULL); 1214 if (optc2_is_two_pixels_per_containter(&pipe_ctx->stream->timing) || odm_combine_factor > 1 1215 || dcn32_is_dp_dig_pixel_rate_div_policy(pipe_ctx)) 1216 pix_per_cycle = 2; 1217 1218 if (pipe_ctx->stream_res.stream_enc->funcs->set_input_mode) 1219 pipe_ctx->stream_res.stream_enc->funcs->set_input_mode(pipe_ctx->stream_res.stream_enc, 1220 pix_per_cycle); 1221 } 1222 1223 void dcn32_unblank_stream(struct pipe_ctx *pipe_ctx, 1224 struct dc_link_settings *link_settings) 1225 { 1226 struct encoder_unblank_param params = {0}; 1227 struct dc_stream_state *stream = pipe_ctx->stream; 1228 struct dc_link *link = stream->link; 1229 struct dce_hwseq *hws = link->dc->hwseq; 1230 struct pipe_ctx *odm_pipe; 1231 uint32_t pix_per_cycle = 1; 1232 1233 params.opp_cnt = 1; 1234 for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) 1235 params.opp_cnt++; 1236 1237 /* only 3 items below are used by unblank */ 1238 params.timing = pipe_ctx->stream->timing; 1239 1240 params.link_settings.link_rate = link_settings->link_rate; 1241 1242 if (is_dp_128b_132b_signal(pipe_ctx)) { 1243 /* TODO - DP2.0 HW: Set ODM mode in dp hpo encoder here */ 1244 pipe_ctx->stream_res.hpo_dp_stream_enc->funcs->dp_unblank( 1245 pipe_ctx->stream_res.hpo_dp_stream_enc, 1246 pipe_ctx->stream_res.tg->inst); 1247 } else if (dc_is_dp_signal(pipe_ctx->stream->signal)) { 1248 if (optc2_is_two_pixels_per_containter(&stream->timing) || params.opp_cnt > 1 1249 || dcn32_is_dp_dig_pixel_rate_div_policy(pipe_ctx)) { 1250 params.timing.pix_clk_100hz /= 2; 1251 pix_per_cycle = 2; 1252 } 1253 pipe_ctx->stream_res.stream_enc->funcs->dp_set_odm_combine( 1254 pipe_ctx->stream_res.stream_enc, pix_per_cycle > 1); 1255 pipe_ctx->stream_res.stream_enc->funcs->dp_unblank(link, pipe_ctx->stream_res.stream_enc, ¶ms); 1256 } 1257 1258 if (link->local_sink && link->local_sink->sink_signal == SIGNAL_TYPE_EDP) 1259 hws->funcs.edp_backlight_control(link, true); 1260 } 1261 1262 bool dcn32_is_dp_dig_pixel_rate_div_policy(struct pipe_ctx *pipe_ctx) 1263 { 1264 struct dc *dc = pipe_ctx->stream->ctx->dc; 1265 1266 if (!is_h_timing_divisible_by_2(pipe_ctx->stream)) 1267 return false; 1268 1269 if (dc_is_dp_signal(pipe_ctx->stream->signal) && !is_dp_128b_132b_signal(pipe_ctx) && 1270 dc->debug.enable_dp_dig_pixel_rate_div_policy) 1271 return true; 1272 return false; 1273 } 1274 1275 static void apply_symclk_on_tx_off_wa(struct dc_link *link) 1276 { 1277 /* There are use cases where SYMCLK is referenced by OTG. For instance 1278 * for TMDS signal, OTG relies SYMCLK even if TX video output is off. 1279 * However current link interface will power off PHY when disabling link 1280 * output. This will turn off SYMCLK generated by PHY. The workaround is 1281 * to identify such case where SYMCLK is still in use by OTG when we 1282 * power off PHY. When this is detected, we will temporarily power PHY 1283 * back on and move PHY's SYMCLK state to SYMCLK_ON_TX_OFF by calling 1284 * program_pix_clk interface. When OTG is disabled, we will then power 1285 * off PHY by calling disable link output again. 1286 * 1287 * In future dcn generations, we plan to rework transmitter control 1288 * interface so that we could have an option to set SYMCLK ON TX OFF 1289 * state in one step without this workaround 1290 */ 1291 1292 struct dc *dc = link->ctx->dc; 1293 struct pipe_ctx *pipe_ctx = NULL; 1294 uint8_t i; 1295 1296 if (link->phy_state.symclk_ref_cnts.otg > 0) { 1297 for (i = 0; i < MAX_PIPES; i++) { 1298 pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[i]; 1299 if (pipe_ctx->stream && pipe_ctx->stream->link == link && pipe_ctx->top_pipe == NULL) { 1300 pipe_ctx->clock_source->funcs->program_pix_clk( 1301 pipe_ctx->clock_source, 1302 &pipe_ctx->stream_res.pix_clk_params, 1303 dp_get_link_encoding_format(&pipe_ctx->link_config.dp_link_settings), 1304 &pipe_ctx->pll_settings); 1305 link->phy_state.symclk_state = SYMCLK_ON_TX_OFF; 1306 break; 1307 } 1308 } 1309 } 1310 } 1311 1312 void dcn32_disable_link_output(struct dc_link *link, 1313 const struct link_resource *link_res, 1314 enum signal_type signal) 1315 { 1316 struct dc *dc = link->ctx->dc; 1317 const struct link_hwss *link_hwss = get_link_hwss(link, link_res); 1318 struct dmcu *dmcu = dc->res_pool->dmcu; 1319 1320 if (signal == SIGNAL_TYPE_EDP && 1321 link->dc->hwss.edp_backlight_control) 1322 link->dc->hwss.edp_backlight_control(link, false); 1323 else if (dmcu != NULL && dmcu->funcs->lock_phy) 1324 dmcu->funcs->lock_phy(dmcu); 1325 1326 link_hwss->disable_link_output(link, link_res, signal); 1327 link->phy_state.symclk_state = SYMCLK_OFF_TX_OFF; 1328 1329 if (signal == SIGNAL_TYPE_EDP && 1330 link->dc->hwss.edp_backlight_control) 1331 link->dc->hwss.edp_power_control(link, false); 1332 else if (dmcu != NULL && dmcu->funcs->lock_phy) 1333 dmcu->funcs->unlock_phy(dmcu); 1334 1335 dp_source_sequence_trace(link, DPCD_SOURCE_SEQ_AFTER_DISABLE_LINK_PHY); 1336 1337 apply_symclk_on_tx_off_wa(link); 1338 } 1339 1340 /* For SubVP the main pipe can have a viewport position change 1341 * without a full update. In this case we must also update the 1342 * viewport positions for the phantom pipe accordingly. 1343 */ 1344 void dcn32_update_phantom_vp_position(struct dc *dc, 1345 struct dc_state *context, 1346 struct pipe_ctx *phantom_pipe) 1347 { 1348 uint32_t i; 1349 struct dc_plane_state *phantom_plane = phantom_pipe->plane_state; 1350 1351 for (i = 0; i < dc->res_pool->pipe_count; i++) { 1352 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; 1353 1354 if (pipe->stream && pipe->stream->mall_stream_config.type == SUBVP_MAIN && 1355 pipe->stream->mall_stream_config.paired_stream == phantom_pipe->stream) { 1356 if (pipe->plane_state && pipe->plane_state->update_flags.bits.position_change) { 1357 1358 phantom_plane->src_rect.x = pipe->plane_state->src_rect.x; 1359 phantom_plane->src_rect.y = pipe->plane_state->src_rect.y; 1360 phantom_plane->clip_rect.x = pipe->plane_state->clip_rect.x; 1361 phantom_plane->dst_rect.x = pipe->plane_state->dst_rect.x; 1362 phantom_plane->dst_rect.y = pipe->plane_state->dst_rect.y; 1363 1364 phantom_pipe->plane_state->update_flags.bits.position_change = 1; 1365 resource_build_scaling_params(phantom_pipe); 1366 return; 1367 } 1368 } 1369 } 1370 } 1371 1372 /* Treat the phantom pipe as if it needs to be fully enabled. 1373 * If the pipe was previously in use but not phantom, it would 1374 * have been disabled earlier in the sequence so we need to run 1375 * the full enable sequence. 1376 */ 1377 void dcn32_apply_update_flags_for_phantom(struct pipe_ctx *phantom_pipe) 1378 { 1379 phantom_pipe->update_flags.raw = 0; 1380 if (phantom_pipe->stream && phantom_pipe->stream->mall_stream_config.type == SUBVP_PHANTOM) { 1381 if (phantom_pipe->stream && phantom_pipe->plane_state) { 1382 phantom_pipe->update_flags.bits.enable = 1; 1383 phantom_pipe->update_flags.bits.mpcc = 1; 1384 phantom_pipe->update_flags.bits.dppclk = 1; 1385 phantom_pipe->update_flags.bits.hubp_interdependent = 1; 1386 phantom_pipe->update_flags.bits.hubp_rq_dlg_ttu = 1; 1387 phantom_pipe->update_flags.bits.gamut_remap = 1; 1388 phantom_pipe->update_flags.bits.scaler = 1; 1389 phantom_pipe->update_flags.bits.viewport = 1; 1390 phantom_pipe->update_flags.bits.det_size = 1; 1391 if (!phantom_pipe->top_pipe && !phantom_pipe->prev_odm_pipe) { 1392 phantom_pipe->update_flags.bits.odm = 1; 1393 phantom_pipe->update_flags.bits.global_sync = 1; 1394 } 1395 } 1396 } 1397 } 1398 1399 bool dcn32_dsc_pg_status( 1400 struct dce_hwseq *hws, 1401 unsigned int dsc_inst) 1402 { 1403 uint32_t pwr_status = 0; 1404 1405 switch (dsc_inst) { 1406 case 0: /* DSC0 */ 1407 REG_GET(DOMAIN16_PG_STATUS, 1408 DOMAIN_PGFSM_PWR_STATUS, &pwr_status); 1409 break; 1410 case 1: /* DSC1 */ 1411 1412 REG_GET(DOMAIN17_PG_STATUS, 1413 DOMAIN_PGFSM_PWR_STATUS, &pwr_status); 1414 break; 1415 case 2: /* DSC2 */ 1416 REG_GET(DOMAIN18_PG_STATUS, 1417 DOMAIN_PGFSM_PWR_STATUS, &pwr_status); 1418 break; 1419 case 3: /* DSC3 */ 1420 REG_GET(DOMAIN19_PG_STATUS, 1421 DOMAIN_PGFSM_PWR_STATUS, &pwr_status); 1422 break; 1423 default: 1424 BREAK_TO_DEBUGGER(); 1425 break; 1426 } 1427 1428 return pwr_status == 0; 1429 } 1430 1431 void dcn32_update_dsc_pg(struct dc *dc, 1432 struct dc_state *context, 1433 bool safe_to_disable) 1434 { 1435 struct dce_hwseq *hws = dc->hwseq; 1436 int i; 1437 1438 for (i = 0; i < dc->res_pool->res_cap->num_dsc; i++) { 1439 struct display_stream_compressor *dsc = dc->res_pool->dscs[i]; 1440 bool is_dsc_ungated = hws->funcs.dsc_pg_status(hws, dsc->inst); 1441 1442 if (context->res_ctx.is_dsc_acquired[i]) { 1443 if (!is_dsc_ungated) { 1444 hws->funcs.dsc_pg_control(hws, dsc->inst, true); 1445 } 1446 } else if (safe_to_disable) { 1447 if (is_dsc_ungated) { 1448 hws->funcs.dsc_pg_control(hws, dsc->inst, false); 1449 } 1450 } 1451 } 1452 } 1453