1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 27 #include "dm_services.h" 28 #include "dm_helpers.h" 29 #include "core_types.h" 30 #include "resource.h" 31 #include "dccg.h" 32 #include "dce/dce_hwseq.h" 33 #include "dcn30/dcn30_cm_common.h" 34 #include "reg_helper.h" 35 #include "abm.h" 36 #include "hubp.h" 37 #include "dchubbub.h" 38 #include "timing_generator.h" 39 #include "opp.h" 40 #include "ipp.h" 41 #include "mpc.h" 42 #include "mcif_wb.h" 43 #include "dc_dmub_srv.h" 44 #include "link_hwss.h" 45 #include "dpcd_defs.h" 46 #include "dcn32_hwseq.h" 47 #include "clk_mgr.h" 48 #include "dsc.h" 49 #include "dcn20/dcn20_optc.h" 50 #include "dmub_subvp_state.h" 51 #include "dce/dmub_hw_lock_mgr.h" 52 #include "dc_link_dp.h" 53 #include "dmub/inc/dmub_subvp_state.h" 54 55 #define DC_LOGGER_INIT(logger) 56 57 #define CTX \ 58 hws->ctx 59 #define REG(reg)\ 60 hws->regs->reg 61 #define DC_LOGGER \ 62 dc->ctx->logger 63 64 65 #undef FN 66 #define FN(reg_name, field_name) \ 67 hws->shifts->field_name, hws->masks->field_name 68 69 void dcn32_dsc_pg_control( 70 struct dce_hwseq *hws, 71 unsigned int dsc_inst, 72 bool power_on) 73 { 74 uint32_t power_gate = power_on ? 0 : 1; 75 uint32_t pwr_status = power_on ? 0 : 2; 76 uint32_t org_ip_request_cntl = 0; 77 78 if (hws->ctx->dc->debug.disable_dsc_power_gate) 79 return; 80 81 REG_GET(DC_IP_REQUEST_CNTL, IP_REQUEST_EN, &org_ip_request_cntl); 82 if (org_ip_request_cntl == 0) 83 REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 1); 84 85 switch (dsc_inst) { 86 case 0: /* DSC0 */ 87 REG_UPDATE(DOMAIN16_PG_CONFIG, 88 DOMAIN_POWER_GATE, power_gate); 89 90 REG_WAIT(DOMAIN16_PG_STATUS, 91 DOMAIN_PGFSM_PWR_STATUS, pwr_status, 92 1, 1000); 93 break; 94 case 1: /* DSC1 */ 95 REG_UPDATE(DOMAIN17_PG_CONFIG, 96 DOMAIN_POWER_GATE, power_gate); 97 98 REG_WAIT(DOMAIN17_PG_STATUS, 99 DOMAIN_PGFSM_PWR_STATUS, pwr_status, 100 1, 1000); 101 break; 102 case 2: /* DSC2 */ 103 REG_UPDATE(DOMAIN18_PG_CONFIG, 104 DOMAIN_POWER_GATE, power_gate); 105 106 REG_WAIT(DOMAIN18_PG_STATUS, 107 DOMAIN_PGFSM_PWR_STATUS, pwr_status, 108 1, 1000); 109 break; 110 case 3: /* DSC3 */ 111 REG_UPDATE(DOMAIN19_PG_CONFIG, 112 DOMAIN_POWER_GATE, power_gate); 113 114 REG_WAIT(DOMAIN19_PG_STATUS, 115 DOMAIN_PGFSM_PWR_STATUS, pwr_status, 116 1, 1000); 117 break; 118 default: 119 BREAK_TO_DEBUGGER(); 120 break; 121 } 122 123 if (org_ip_request_cntl == 0) 124 REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 0); 125 } 126 127 128 void dcn32_enable_power_gating_plane( 129 struct dce_hwseq *hws, 130 bool enable) 131 { 132 bool force_on = true; /* disable power gating */ 133 134 if (enable) 135 force_on = false; 136 137 /* DCHUBP0/1/2/3 */ 138 REG_UPDATE(DOMAIN0_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on); 139 REG_UPDATE(DOMAIN1_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on); 140 REG_UPDATE(DOMAIN2_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on); 141 REG_UPDATE(DOMAIN3_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on); 142 143 /* DCS0/1/2/3 */ 144 REG_UPDATE(DOMAIN16_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on); 145 REG_UPDATE(DOMAIN17_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on); 146 REG_UPDATE(DOMAIN18_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on); 147 REG_UPDATE(DOMAIN19_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on); 148 } 149 150 void dcn32_hubp_pg_control(struct dce_hwseq *hws, unsigned int hubp_inst, bool power_on) 151 { 152 uint32_t power_gate = power_on ? 0 : 1; 153 uint32_t pwr_status = power_on ? 0 : 2; 154 155 if (hws->ctx->dc->debug.disable_hubp_power_gate) 156 return; 157 158 if (REG(DOMAIN0_PG_CONFIG) == 0) 159 return; 160 161 switch (hubp_inst) { 162 case 0: 163 REG_SET(DOMAIN0_PG_CONFIG, 0, DOMAIN_POWER_GATE, power_gate); 164 REG_WAIT(DOMAIN0_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, pwr_status, 1, 1000); 165 break; 166 case 1: 167 REG_SET(DOMAIN1_PG_CONFIG, 0, DOMAIN_POWER_GATE, power_gate); 168 REG_WAIT(DOMAIN1_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, pwr_status, 1, 1000); 169 break; 170 case 2: 171 REG_SET(DOMAIN2_PG_CONFIG, 0, DOMAIN_POWER_GATE, power_gate); 172 REG_WAIT(DOMAIN2_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, pwr_status, 1, 1000); 173 break; 174 case 3: 175 REG_SET(DOMAIN3_PG_CONFIG, 0, DOMAIN_POWER_GATE, power_gate); 176 REG_WAIT(DOMAIN3_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, pwr_status, 1, 1000); 177 break; 178 default: 179 BREAK_TO_DEBUGGER(); 180 break; 181 } 182 } 183 184 static bool dcn32_check_no_memory_request_for_cab(struct dc *dc) 185 { 186 int i; 187 188 /* First, check no-memory-request case */ 189 for (i = 0; i < dc->current_state->stream_count; i++) { 190 if (dc->current_state->stream_status[i].plane_count) 191 /* Fail eligibility on a visible stream */ 192 break; 193 } 194 195 if (i == dc->current_state->stream_count) 196 return true; 197 198 return false; 199 } 200 201 /* This function takes in the start address and surface size to be cached in CAB 202 * and calculates the total number of cache lines required to store the surface. 203 * The number of cache lines used for each surface is calculated independently of 204 * one another. For example, if there is a primary surface(1), meta surface(2), and 205 * cursor(3), this function should be called 3 times to calculate the number of cache 206 * lines used for each of those surfaces. 207 */ 208 static uint32_t dcn32_cache_lines_for_surface(struct dc *dc, uint32_t surface_size, uint64_t start_address) 209 { 210 uint32_t lines_used = 1; 211 uint32_t num_cached_bytes = 0; 212 uint32_t remaining_size = 0; 213 uint32_t cache_line_size = dc->caps.cache_line_size; 214 uint32_t remainder = 0; 215 216 /* 1. Calculate surface size minus the number of bytes stored 217 * in the first cache line (all bytes in first cache line might 218 * not be fully used). 219 */ 220 div_u64_rem(start_address, cache_line_size, &remainder); 221 num_cached_bytes = cache_line_size - remainder; 222 remaining_size = surface_size - num_cached_bytes; 223 224 /* 2. Calculate number of cache lines that will be fully used with 225 * the remaining number of bytes to be stored. 226 */ 227 lines_used += (remaining_size / cache_line_size); 228 229 /* 3. Check if we need an extra line due to the remaining size not being 230 * a multiple of CACHE_LINE_SIZE. 231 */ 232 if (remaining_size % cache_line_size > 0) 233 lines_used++; 234 235 return lines_used; 236 } 237 238 /* This function loops through every surface that needs to be cached in CAB for SS, 239 * and calculates the total number of ways required to store all surfaces (primary, 240 * meta, cursor). 241 */ 242 static uint32_t dcn32_calculate_cab_allocation(struct dc *dc, struct dc_state *ctx) 243 { 244 uint8_t i, j; 245 struct dc_stream_state *stream = NULL; 246 struct dc_plane_state *plane = NULL; 247 uint32_t surface_size = 0; 248 uint32_t cursor_size = 0; 249 uint32_t cache_lines_used = 0; 250 uint32_t total_lines = 0; 251 uint32_t lines_per_way = 0; 252 uint32_t num_ways = 0; 253 uint32_t prev_addr_low = 0; 254 255 for (i = 0; i < ctx->stream_count; i++) { 256 stream = ctx->streams[i]; 257 258 // Don't include PSR surface in the total surface size for CAB allocation 259 if (stream->link->psr_settings.psr_version != DC_PSR_VERSION_UNSUPPORTED) 260 continue; 261 262 if (ctx->stream_status[i].plane_count == 0) 263 continue; 264 265 // For each stream, loop through each plane to calculate the number of cache 266 // lines required to store the surface in CAB 267 for (j = 0; j < ctx->stream_status[i].plane_count; j++) { 268 plane = ctx->stream_status[i].plane_states[j]; 269 270 // Calculate total surface size 271 if (prev_addr_low != plane->address.grph.addr.u.low_part) { 272 /* if plane address are different from prev FB, then userspace allocated separate FBs*/ 273 surface_size += plane->plane_size.surface_pitch * 274 plane->plane_size.surface_size.height * 275 (plane->format >= SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616 ? 8 : 4); 276 277 prev_addr_low = plane->address.grph.addr.u.low_part; 278 } else { 279 /* We have the same fb for all the planes. 280 * Xorg always creates one giant fb that holds all surfaces, 281 * so allocating it once is sufficient. 282 * */ 283 continue; 284 } 285 // Convert surface size + starting address to number of cache lines required 286 // (alignment accounted for) 287 cache_lines_used += dcn32_cache_lines_for_surface(dc, surface_size, 288 plane->address.grph.addr.quad_part); 289 290 if (plane->address.grph.meta_addr.quad_part) { 291 // Meta surface 292 cache_lines_used += dcn32_cache_lines_for_surface(dc, surface_size, 293 plane->address.grph.meta_addr.quad_part); 294 } 295 } 296 297 // Include cursor size for CAB allocation 298 for (j = 0; j < dc->res_pool->pipe_count; j++) { 299 struct pipe_ctx *pipe = &ctx->res_ctx.pipe_ctx[j]; 300 struct hubp *hubp = pipe->plane_res.hubp; 301 302 if (pipe->stream && pipe->plane_state && hubp) 303 /* Find the cursor plane and use the exact size instead of 304 * using the max for calculation 305 */ 306 if (hubp->curs_attr.width > 0) { 307 cursor_size = hubp->curs_attr.width * hubp->curs_attr.height; 308 break; 309 } 310 } 311 312 switch (stream->cursor_attributes.color_format) { 313 case CURSOR_MODE_MONO: 314 cursor_size /= 2; 315 break; 316 case CURSOR_MODE_COLOR_1BIT_AND: 317 case CURSOR_MODE_COLOR_PRE_MULTIPLIED_ALPHA: 318 case CURSOR_MODE_COLOR_UN_PRE_MULTIPLIED_ALPHA: 319 cursor_size *= 4; 320 break; 321 322 case CURSOR_MODE_COLOR_64BIT_FP_PRE_MULTIPLIED: 323 case CURSOR_MODE_COLOR_64BIT_FP_UN_PRE_MULTIPLIED: 324 cursor_size *= 8; 325 break; 326 } 327 328 if (stream->cursor_position.enable && plane->address.grph.cursor_cache_addr.quad_part) { 329 cache_lines_used += dcn32_cache_lines_for_surface(dc, cursor_size, 330 plane->address.grph.cursor_cache_addr.quad_part); 331 } 332 } 333 334 // Convert number of cache lines required to number of ways 335 total_lines = dc->caps.max_cab_allocation_bytes / dc->caps.cache_line_size; 336 lines_per_way = total_lines / dc->caps.cache_num_ways; 337 num_ways = cache_lines_used / lines_per_way; 338 339 if (cache_lines_used % lines_per_way > 0) 340 num_ways++; 341 342 for (i = 0; i < ctx->stream_count; i++) { 343 stream = ctx->streams[i]; 344 for (j = 0; j < ctx->stream_status[i].plane_count; j++) { 345 plane = ctx->stream_status[i].plane_states[j]; 346 347 if (stream->cursor_position.enable && plane && 348 !plane->address.grph.cursor_cache_addr.quad_part && 349 cursor_size > 16384) { 350 /* Cursor caching is not supported since it won't be on the same line. 351 * So we need an extra line to accommodate it. With large cursors and a single 4k monitor 352 * this case triggers corruption. If we're at the edge, then dont trigger display refresh 353 * from MALL. We only need to cache cursor if its greater that 64x64 at 4 bpp. 354 */ 355 num_ways++; 356 /* We only expect one cursor plane */ 357 break; 358 } 359 } 360 } 361 362 return num_ways; 363 } 364 365 bool dcn32_apply_idle_power_optimizations(struct dc *dc, bool enable) 366 { 367 union dmub_rb_cmd cmd; 368 uint8_t ways, i; 369 int j; 370 bool stereo_in_use = false; 371 struct dc_plane_state *plane = NULL; 372 373 if (!dc->ctx->dmub_srv) 374 return false; 375 376 if (enable) { 377 if (dc->current_state) { 378 379 /* 1. Check no memory request case for CAB. 380 * If no memory request case, send CAB_ACTION NO_DF_REQ DMUB message 381 */ 382 if (dcn32_check_no_memory_request_for_cab(dc)) { 383 /* Enable no-memory-requests case */ 384 memset(&cmd, 0, sizeof(cmd)); 385 cmd.cab.header.type = DMUB_CMD__CAB_FOR_SS; 386 cmd.cab.header.sub_type = DMUB_CMD__CAB_NO_DCN_REQ; 387 cmd.cab.header.payload_bytes = sizeof(cmd.cab) - sizeof(cmd.cab.header); 388 389 dc_dmub_srv_cmd_queue(dc->ctx->dmub_srv, &cmd); 390 dc_dmub_srv_cmd_execute(dc->ctx->dmub_srv); 391 392 return true; 393 } 394 395 /* 2. Check if all surfaces can fit in CAB. 396 * If surfaces can fit into CAB, send CAB_ACTION_ALLOW DMUB message 397 * and configure HUBP's to fetch from MALL 398 */ 399 ways = dcn32_calculate_cab_allocation(dc, dc->current_state); 400 401 /* MALL not supported with Stereo3D. If any plane is using stereo, 402 * don't try to enter MALL. 403 */ 404 for (i = 0; i < dc->current_state->stream_count; i++) { 405 for (j = 0; j < dc->current_state->stream_status[i].plane_count; j++) { 406 plane = dc->current_state->stream_status[i].plane_states[j]; 407 408 if (plane->address.type == PLN_ADDR_TYPE_GRPH_STEREO) { 409 stereo_in_use = true; 410 break; 411 } 412 } 413 if (stereo_in_use) 414 break; 415 } 416 if (ways <= dc->caps.cache_num_ways && !stereo_in_use) { 417 memset(&cmd, 0, sizeof(cmd)); 418 cmd.cab.header.type = DMUB_CMD__CAB_FOR_SS; 419 cmd.cab.header.sub_type = DMUB_CMD__CAB_DCN_SS_FIT_IN_CAB; 420 cmd.cab.header.payload_bytes = sizeof(cmd.cab) - sizeof(cmd.cab.header); 421 cmd.cab.cab_alloc_ways = ways; 422 423 dc_dmub_srv_cmd_queue(dc->ctx->dmub_srv, &cmd); 424 dc_dmub_srv_cmd_execute(dc->ctx->dmub_srv); 425 426 return true; 427 } 428 429 } 430 return false; 431 } 432 433 /* Disable CAB */ 434 memset(&cmd, 0, sizeof(cmd)); 435 cmd.cab.header.type = DMUB_CMD__CAB_FOR_SS; 436 cmd.cab.header.sub_type = DMUB_CMD__CAB_NO_IDLE_OPTIMIZATION; 437 cmd.cab.header.payload_bytes = 438 sizeof(cmd.cab) - sizeof(cmd.cab.header); 439 440 dc_dmub_srv_cmd_queue(dc->ctx->dmub_srv, &cmd); 441 dc_dmub_srv_cmd_execute(dc->ctx->dmub_srv); 442 dc_dmub_srv_wait_idle(dc->ctx->dmub_srv); 443 444 return true; 445 } 446 447 /* Send DMCUB message with SubVP pipe info 448 * - For each pipe in context, populate payload with required SubVP information 449 * if the pipe is using SubVP for MCLK switch 450 * - This function must be called while the DMUB HW lock is acquired by driver 451 */ 452 void dcn32_commit_subvp_config(struct dc *dc, struct dc_state *context) 453 { 454 /* 455 int i; 456 bool enable_subvp = false; 457 458 if (!dc->ctx || !dc->ctx->dmub_srv) 459 return; 460 461 for (i = 0; i < dc->res_pool->pipe_count; i++) { 462 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; 463 464 if (pipe_ctx->stream && pipe_ctx->stream->mall_stream_config.paired_stream && 465 pipe_ctx->stream->mall_stream_config.type == SUBVP_MAIN) { 466 // There is at least 1 SubVP pipe, so enable SubVP 467 enable_subvp = true; 468 break; 469 } 470 } 471 dc_dmub_setup_subvp_dmub_command(dc, context, enable_subvp); 472 */ 473 } 474 475 /* Sub-Viewport DMUB lock needs to be acquired by driver whenever SubVP is active and: 476 * 1. Any full update for any SubVP main pipe 477 * 2. Any immediate flip for any SubVP pipe 478 * 3. Any flip for DRR pipe 479 * 4. If SubVP was previously in use (i.e. in old context) 480 */ 481 void dcn32_subvp_pipe_control_lock(struct dc *dc, 482 struct dc_state *context, 483 bool lock, 484 bool should_lock_all_pipes, 485 struct pipe_ctx *top_pipe_to_program, 486 bool subvp_prev_use) 487 { 488 unsigned int i = 0; 489 bool subvp_immediate_flip = false; 490 bool subvp_in_use = false; 491 struct pipe_ctx *pipe; 492 493 for (i = 0; i < dc->res_pool->pipe_count; i++) { 494 pipe = &context->res_ctx.pipe_ctx[i]; 495 496 if (pipe->stream && pipe->plane_state && pipe->stream->mall_stream_config.type == SUBVP_MAIN) { 497 subvp_in_use = true; 498 break; 499 } 500 } 501 502 if (top_pipe_to_program && top_pipe_to_program->stream && top_pipe_to_program->plane_state) { 503 if (top_pipe_to_program->stream->mall_stream_config.type == SUBVP_MAIN && 504 top_pipe_to_program->plane_state->flip_immediate) 505 subvp_immediate_flip = true; 506 } 507 508 // Don't need to lock for DRR VSYNC flips -- FW will wait for DRR pending update cleared. 509 if ((subvp_in_use && (should_lock_all_pipes || subvp_immediate_flip)) || (!subvp_in_use && subvp_prev_use)) { 510 union dmub_inbox0_cmd_lock_hw hw_lock_cmd = { 0 }; 511 512 if (!lock) { 513 for (i = 0; i < dc->res_pool->pipe_count; i++) { 514 pipe = &context->res_ctx.pipe_ctx[i]; 515 if (pipe->stream && pipe->plane_state && pipe->stream->mall_stream_config.type == SUBVP_MAIN && 516 should_lock_all_pipes) 517 pipe->stream_res.tg->funcs->wait_for_state(pipe->stream_res.tg, CRTC_STATE_VBLANK); 518 } 519 } 520 521 hw_lock_cmd.bits.command_code = DMUB_INBOX0_CMD__HW_LOCK; 522 hw_lock_cmd.bits.hw_lock_client = HW_LOCK_CLIENT_DRIVER; 523 hw_lock_cmd.bits.lock = lock; 524 hw_lock_cmd.bits.should_release = !lock; 525 dmub_hw_lock_mgr_inbox0_cmd(dc->ctx->dmub_srv, hw_lock_cmd); 526 } 527 } 528 529 530 static bool dcn32_set_mpc_shaper_3dlut( 531 struct pipe_ctx *pipe_ctx, const struct dc_stream_state *stream) 532 { 533 struct dpp *dpp_base = pipe_ctx->plane_res.dpp; 534 int mpcc_id = pipe_ctx->plane_res.hubp->inst; 535 struct mpc *mpc = pipe_ctx->stream_res.opp->ctx->dc->res_pool->mpc; 536 bool result = false; 537 538 const struct pwl_params *shaper_lut = NULL; 539 //get the shaper lut params 540 if (stream->func_shaper) { 541 if (stream->func_shaper->type == TF_TYPE_HWPWL) 542 shaper_lut = &stream->func_shaper->pwl; 543 else if (stream->func_shaper->type == TF_TYPE_DISTRIBUTED_POINTS) { 544 cm_helper_translate_curve_to_hw_format( 545 stream->func_shaper, 546 &dpp_base->shaper_params, true); 547 shaper_lut = &dpp_base->shaper_params; 548 } 549 } 550 551 if (stream->lut3d_func && 552 stream->lut3d_func->state.bits.initialized == 1) { 553 554 result = mpc->funcs->program_3dlut(mpc, 555 &stream->lut3d_func->lut_3d, 556 mpcc_id); 557 558 result = mpc->funcs->program_shaper(mpc, 559 shaper_lut, 560 mpcc_id); 561 } 562 563 return result; 564 } 565 566 bool dcn32_set_mcm_luts( 567 struct pipe_ctx *pipe_ctx, const struct dc_plane_state *plane_state) 568 { 569 struct dpp *dpp_base = pipe_ctx->plane_res.dpp; 570 int mpcc_id = pipe_ctx->plane_res.hubp->inst; 571 struct mpc *mpc = pipe_ctx->stream_res.opp->ctx->dc->res_pool->mpc; 572 bool result = true; 573 struct pwl_params *lut_params = NULL; 574 575 // 1D LUT 576 if (plane_state->blend_tf) { 577 if (plane_state->blend_tf->type == TF_TYPE_HWPWL) 578 lut_params = &plane_state->blend_tf->pwl; 579 else if (plane_state->blend_tf->type == TF_TYPE_DISTRIBUTED_POINTS) { 580 cm_helper_translate_curve_to_hw_format( 581 plane_state->blend_tf, 582 &dpp_base->regamma_params, false); 583 lut_params = &dpp_base->regamma_params; 584 } 585 } 586 result = mpc->funcs->program_1dlut(mpc, lut_params, mpcc_id); 587 588 // Shaper 589 if (plane_state->in_shaper_func) { 590 if (plane_state->in_shaper_func->type == TF_TYPE_HWPWL) 591 lut_params = &plane_state->in_shaper_func->pwl; 592 else if (plane_state->in_shaper_func->type == TF_TYPE_DISTRIBUTED_POINTS) { 593 // TODO: dpp_base replace 594 ASSERT(false); 595 cm_helper_translate_curve_to_hw_format( 596 plane_state->in_shaper_func, 597 &dpp_base->shaper_params, true); 598 lut_params = &dpp_base->shaper_params; 599 } 600 } 601 602 result = mpc->funcs->program_shaper(mpc, lut_params, mpcc_id); 603 604 // 3D 605 if (plane_state->lut3d_func && plane_state->lut3d_func->state.bits.initialized == 1) 606 result = mpc->funcs->program_3dlut(mpc, &plane_state->lut3d_func->lut_3d, mpcc_id); 607 else 608 result = mpc->funcs->program_3dlut(mpc, NULL, mpcc_id); 609 610 return result; 611 } 612 613 bool dcn32_set_input_transfer_func(struct dc *dc, 614 struct pipe_ctx *pipe_ctx, 615 const struct dc_plane_state *plane_state) 616 { 617 struct dce_hwseq *hws = dc->hwseq; 618 struct mpc *mpc = dc->res_pool->mpc; 619 struct dpp *dpp_base = pipe_ctx->plane_res.dpp; 620 621 enum dc_transfer_func_predefined tf; 622 bool result = true; 623 struct pwl_params *params = NULL; 624 625 if (mpc == NULL || plane_state == NULL) 626 return false; 627 628 tf = TRANSFER_FUNCTION_UNITY; 629 630 if (plane_state->in_transfer_func && 631 plane_state->in_transfer_func->type == TF_TYPE_PREDEFINED) 632 tf = plane_state->in_transfer_func->tf; 633 634 dpp_base->funcs->dpp_set_pre_degam(dpp_base, tf); 635 636 if (plane_state->in_transfer_func) { 637 if (plane_state->in_transfer_func->type == TF_TYPE_HWPWL) 638 params = &plane_state->in_transfer_func->pwl; 639 else if (plane_state->in_transfer_func->type == TF_TYPE_DISTRIBUTED_POINTS && 640 cm3_helper_translate_curve_to_hw_format(plane_state->in_transfer_func, 641 &dpp_base->degamma_params, false)) 642 params = &dpp_base->degamma_params; 643 } 644 645 result = dpp_base->funcs->dpp_program_gamcor_lut(dpp_base, params); 646 647 if (result && 648 pipe_ctx->stream_res.opp && 649 pipe_ctx->stream_res.opp->ctx && 650 hws->funcs.set_mcm_luts) 651 result = hws->funcs.set_mcm_luts(pipe_ctx, plane_state); 652 653 return result; 654 } 655 656 bool dcn32_set_output_transfer_func(struct dc *dc, 657 struct pipe_ctx *pipe_ctx, 658 const struct dc_stream_state *stream) 659 { 660 int mpcc_id = pipe_ctx->plane_res.hubp->inst; 661 struct mpc *mpc = pipe_ctx->stream_res.opp->ctx->dc->res_pool->mpc; 662 struct pwl_params *params = NULL; 663 bool ret = false; 664 665 /* program OGAM or 3DLUT only for the top pipe*/ 666 if (pipe_ctx->top_pipe == NULL) { 667 /*program shaper and 3dlut in MPC*/ 668 ret = dcn32_set_mpc_shaper_3dlut(pipe_ctx, stream); 669 if (ret == false && mpc->funcs->set_output_gamma && stream->out_transfer_func) { 670 if (stream->out_transfer_func->type == TF_TYPE_HWPWL) 671 params = &stream->out_transfer_func->pwl; 672 else if (pipe_ctx->stream->out_transfer_func->type == 673 TF_TYPE_DISTRIBUTED_POINTS && 674 cm3_helper_translate_curve_to_hw_format( 675 stream->out_transfer_func, 676 &mpc->blender_params, false)) 677 params = &mpc->blender_params; 678 /* there are no ROM LUTs in OUTGAM */ 679 if (stream->out_transfer_func->type == TF_TYPE_PREDEFINED) 680 BREAK_TO_DEBUGGER(); 681 } 682 } 683 684 mpc->funcs->set_output_gamma(mpc, mpcc_id, params); 685 return ret; 686 } 687 688 /* Program P-State force value according to if pipe is using SubVP or not: 689 * 1. Reset P-State force on all pipes first 690 * 2. For each main pipe, force P-State disallow (P-State allow moderated by DMUB) 691 */ 692 void dcn32_subvp_update_force_pstate(struct dc *dc, struct dc_state *context) 693 { 694 int i; 695 int num_subvp = 0; 696 /* Unforce p-state for each pipe 697 */ 698 for (i = 0; i < dc->res_pool->pipe_count; i++) { 699 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; 700 struct hubp *hubp = pipe->plane_res.hubp; 701 702 if (hubp && hubp->funcs->hubp_update_force_pstate_disallow) 703 hubp->funcs->hubp_update_force_pstate_disallow(hubp, false); 704 if (pipe->stream && pipe->stream->mall_stream_config.type == SUBVP_MAIN) 705 num_subvp++; 706 } 707 708 if (num_subvp == 0) 709 return; 710 711 /* Loop through each pipe -- for each subvp main pipe force p-state allow equal to false. 712 */ 713 for (i = 0; i < dc->res_pool->pipe_count; i++) { 714 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; 715 716 // For SubVP + DRR, also force disallow on the DRR pipe 717 // (We will force allow in the DMUB sequence -- some DRR timings by default won't allow P-State so we have 718 // to force once the vblank is stretched). 719 if (pipe->stream && pipe->plane_state && (pipe->stream->mall_stream_config.type == SUBVP_MAIN || 720 (pipe->stream->mall_stream_config.type == SUBVP_NONE && pipe->stream->ignore_msa_timing_param))) { 721 struct hubp *hubp = pipe->plane_res.hubp; 722 723 if (hubp && hubp->funcs->hubp_update_force_pstate_disallow) 724 hubp->funcs->hubp_update_force_pstate_disallow(hubp, true); 725 } 726 } 727 } 728 729 /* Update MALL_SEL register based on if pipe / plane 730 * is a phantom pipe, main pipe, and if using MALL 731 * for SS. 732 */ 733 void dcn32_update_mall_sel(struct dc *dc, struct dc_state *context) 734 { 735 int i; 736 unsigned int num_ways = dcn32_calculate_cab_allocation(dc, context); 737 bool cache_cursor = false; 738 739 for (i = 0; i < dc->res_pool->pipe_count; i++) { 740 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; 741 struct hubp *hubp = pipe->plane_res.hubp; 742 743 if (pipe->stream && pipe->plane_state && hubp && hubp->funcs->hubp_update_mall_sel) { 744 //Round cursor width up to next multiple of 64 745 int cursor_width = ((hubp->curs_attr.width + 63) / 64) * 64; 746 int cursor_height = hubp->curs_attr.height; 747 int cursor_size = cursor_width * cursor_height; 748 749 switch (hubp->curs_attr.color_format) { 750 case CURSOR_MODE_MONO: 751 cursor_size /= 2; 752 break; 753 case CURSOR_MODE_COLOR_1BIT_AND: 754 case CURSOR_MODE_COLOR_PRE_MULTIPLIED_ALPHA: 755 case CURSOR_MODE_COLOR_UN_PRE_MULTIPLIED_ALPHA: 756 cursor_size *= 4; 757 break; 758 759 case CURSOR_MODE_COLOR_64BIT_FP_PRE_MULTIPLIED: 760 case CURSOR_MODE_COLOR_64BIT_FP_UN_PRE_MULTIPLIED: 761 default: 762 cursor_size *= 8; 763 break; 764 } 765 766 if (cursor_size > 16384) 767 cache_cursor = true; 768 769 if (pipe->stream->mall_stream_config.type == SUBVP_PHANTOM) { 770 hubp->funcs->hubp_update_mall_sel(hubp, 1, false); 771 } else { 772 // MALL not supported with Stereo3D 773 hubp->funcs->hubp_update_mall_sel(hubp, 774 num_ways <= dc->caps.cache_num_ways && 775 pipe->stream->link->psr_settings.psr_version == DC_PSR_VERSION_UNSUPPORTED && 776 pipe->plane_state->address.type != PLN_ADDR_TYPE_GRPH_STEREO ? 2 : 0, 777 cache_cursor); 778 } 779 } 780 } 781 } 782 783 /* Program the sub-viewport pipe configuration after the main / phantom pipes 784 * have been programmed in hardware. 785 * 1. Update force P-State for all the main pipes (disallow P-state) 786 * 2. Update MALL_SEL register 787 * 3. Program FORCE_ONE_ROW_FOR_FRAME for main subvp pipes 788 */ 789 void dcn32_program_mall_pipe_config(struct dc *dc, struct dc_state *context) 790 { 791 int i; 792 struct dce_hwseq *hws = dc->hwseq; 793 794 // Don't force p-state disallow -- can't block dummy p-state 795 796 // Update MALL_SEL register for each pipe 797 if (hws && hws->funcs.update_mall_sel) 798 hws->funcs.update_mall_sel(dc, context); 799 800 // Program FORCE_ONE_ROW_FOR_FRAME and CURSOR_REQ_MODE for main subvp pipes 801 for (i = 0; i < dc->res_pool->pipe_count; i++) { 802 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; 803 struct hubp *hubp = pipe->plane_res.hubp; 804 805 if (pipe->stream && hubp && hubp->funcs->hubp_prepare_subvp_buffering) { 806 /* TODO - remove setting CURSOR_REQ_MODE to 0 for legacy cases 807 * - need to investigate single pipe MPO + SubVP case to 808 * see if CURSOR_REQ_MODE will be back to 1 for SubVP 809 * when it should be 0 for MPO 810 */ 811 if (pipe->stream->mall_stream_config.type == SUBVP_MAIN) { 812 hubp->funcs->hubp_prepare_subvp_buffering(hubp, true); 813 } 814 } 815 } 816 } 817 818 void dcn32_init_hw(struct dc *dc) 819 { 820 struct abm **abms = dc->res_pool->multiple_abms; 821 struct dce_hwseq *hws = dc->hwseq; 822 struct dc_bios *dcb = dc->ctx->dc_bios; 823 struct resource_pool *res_pool = dc->res_pool; 824 int i; 825 int edp_num; 826 uint32_t backlight = MAX_BACKLIGHT_LEVEL; 827 828 if (dc->clk_mgr && dc->clk_mgr->funcs->init_clocks) 829 dc->clk_mgr->funcs->init_clocks(dc->clk_mgr); 830 831 // Initialize the dccg 832 if (res_pool->dccg->funcs->dccg_init) 833 res_pool->dccg->funcs->dccg_init(res_pool->dccg); 834 835 if (!dcb->funcs->is_accelerated_mode(dcb)) { 836 hws->funcs.bios_golden_init(dc); 837 hws->funcs.disable_vga(dc->hwseq); 838 } 839 840 // Set default OPTC memory power states 841 if (dc->debug.enable_mem_low_power.bits.optc) { 842 // Shutdown when unassigned and light sleep in VBLANK 843 REG_SET_2(ODM_MEM_PWR_CTRL3, 0, ODM_MEM_UNASSIGNED_PWR_MODE, 3, ODM_MEM_VBLANK_PWR_MODE, 1); 844 } 845 846 if (dc->debug.enable_mem_low_power.bits.vga) { 847 // Power down VGA memory 848 REG_UPDATE(MMHUBBUB_MEM_PWR_CNTL, VGA_MEM_PWR_FORCE, 1); 849 } 850 851 if (dc->ctx->dc_bios->fw_info_valid) { 852 res_pool->ref_clocks.xtalin_clock_inKhz = 853 dc->ctx->dc_bios->fw_info.pll_info.crystal_frequency; 854 855 if (res_pool->dccg && res_pool->hubbub) { 856 (res_pool->dccg->funcs->get_dccg_ref_freq)(res_pool->dccg, 857 dc->ctx->dc_bios->fw_info.pll_info.crystal_frequency, 858 &res_pool->ref_clocks.dccg_ref_clock_inKhz); 859 860 (res_pool->hubbub->funcs->get_dchub_ref_freq)(res_pool->hubbub, 861 res_pool->ref_clocks.dccg_ref_clock_inKhz, 862 &res_pool->ref_clocks.dchub_ref_clock_inKhz); 863 } else { 864 // Not all ASICs have DCCG sw component 865 res_pool->ref_clocks.dccg_ref_clock_inKhz = 866 res_pool->ref_clocks.xtalin_clock_inKhz; 867 res_pool->ref_clocks.dchub_ref_clock_inKhz = 868 res_pool->ref_clocks.xtalin_clock_inKhz; 869 } 870 } else 871 ASSERT_CRITICAL(false); 872 873 for (i = 0; i < dc->link_count; i++) { 874 /* Power up AND update implementation according to the 875 * required signal (which may be different from the 876 * default signal on connector). 877 */ 878 struct dc_link *link = dc->links[i]; 879 880 link->link_enc->funcs->hw_init(link->link_enc); 881 882 /* Check for enabled DIG to identify enabled display */ 883 if (link->link_enc->funcs->is_dig_enabled && 884 link->link_enc->funcs->is_dig_enabled(link->link_enc)) { 885 link->link_status.link_active = true; 886 if (link->link_enc->funcs->fec_is_active && 887 link->link_enc->funcs->fec_is_active(link->link_enc)) 888 link->fec_state = dc_link_fec_enabled; 889 } 890 } 891 892 /* Power gate DSCs */ 893 for (i = 0; i < res_pool->res_cap->num_dsc; i++) 894 if (hws->funcs.dsc_pg_control != NULL) 895 hws->funcs.dsc_pg_control(hws, res_pool->dscs[i]->inst, false); 896 897 /* we want to turn off all dp displays before doing detection */ 898 dc_link_blank_all_dp_displays(dc); 899 900 /* If taking control over from VBIOS, we may want to optimize our first 901 * mode set, so we need to skip powering down pipes until we know which 902 * pipes we want to use. 903 * Otherwise, if taking control is not possible, we need to power 904 * everything down. 905 */ 906 if (dcb->funcs->is_accelerated_mode(dcb) || !dc->config.seamless_boot_edp_requested) { 907 hws->funcs.init_pipes(dc, dc->current_state); 908 if (dc->res_pool->hubbub->funcs->allow_self_refresh_control) 909 dc->res_pool->hubbub->funcs->allow_self_refresh_control(dc->res_pool->hubbub, 910 !dc->res_pool->hubbub->ctx->dc->debug.disable_stutter); 911 } 912 913 /* In headless boot cases, DIG may be turned 914 * on which causes HW/SW discrepancies. 915 * To avoid this, power down hardware on boot 916 * if DIG is turned on and seamless boot not enabled 917 */ 918 if (!dc->config.seamless_boot_edp_requested) { 919 struct dc_link *edp_links[MAX_NUM_EDP]; 920 struct dc_link *edp_link; 921 922 get_edp_links(dc, edp_links, &edp_num); 923 if (edp_num) { 924 for (i = 0; i < edp_num; i++) { 925 edp_link = edp_links[i]; 926 if (edp_link->link_enc->funcs->is_dig_enabled && 927 edp_link->link_enc->funcs->is_dig_enabled(edp_link->link_enc) && 928 dc->hwss.edp_backlight_control && 929 dc->hwss.power_down && 930 dc->hwss.edp_power_control) { 931 dc->hwss.edp_backlight_control(edp_link, false); 932 dc->hwss.power_down(dc); 933 dc->hwss.edp_power_control(edp_link, false); 934 } 935 } 936 } else { 937 for (i = 0; i < dc->link_count; i++) { 938 struct dc_link *link = dc->links[i]; 939 940 if (link->link_enc->funcs->is_dig_enabled && 941 link->link_enc->funcs->is_dig_enabled(link->link_enc) && 942 dc->hwss.power_down) { 943 dc->hwss.power_down(dc); 944 break; 945 } 946 947 } 948 } 949 } 950 951 for (i = 0; i < res_pool->audio_count; i++) { 952 struct audio *audio = res_pool->audios[i]; 953 954 audio->funcs->hw_init(audio); 955 } 956 957 for (i = 0; i < dc->link_count; i++) { 958 struct dc_link *link = dc->links[i]; 959 960 if (link->panel_cntl) 961 backlight = link->panel_cntl->funcs->hw_init(link->panel_cntl); 962 } 963 964 for (i = 0; i < dc->res_pool->pipe_count; i++) { 965 if (abms[i] != NULL && abms[i]->funcs != NULL) 966 abms[i]->funcs->abm_init(abms[i], backlight); 967 } 968 969 /* power AFMT HDMI memory TODO: may move to dis/en output save power*/ 970 REG_WRITE(DIO_MEM_PWR_CTRL, 0); 971 972 if (!dc->debug.disable_clock_gate) { 973 /* enable all DCN clock gating */ 974 REG_WRITE(DCCG_GATE_DISABLE_CNTL, 0); 975 976 REG_WRITE(DCCG_GATE_DISABLE_CNTL2, 0); 977 978 REG_UPDATE(DCFCLK_CNTL, DCFCLK_GATE_DIS, 0); 979 } 980 if (hws->funcs.enable_power_gating_plane) 981 hws->funcs.enable_power_gating_plane(dc->hwseq, true); 982 983 if (!dcb->funcs->is_accelerated_mode(dcb) && dc->res_pool->hubbub->funcs->init_watermarks) 984 dc->res_pool->hubbub->funcs->init_watermarks(dc->res_pool->hubbub); 985 986 if (dc->clk_mgr->funcs->notify_wm_ranges) 987 dc->clk_mgr->funcs->notify_wm_ranges(dc->clk_mgr); 988 989 if (dc->clk_mgr->funcs->set_hard_max_memclk) 990 dc->clk_mgr->funcs->set_hard_max_memclk(dc->clk_mgr); 991 992 if (dc->res_pool->hubbub->funcs->force_pstate_change_control) 993 dc->res_pool->hubbub->funcs->force_pstate_change_control( 994 dc->res_pool->hubbub, false, false); 995 996 if (dc->res_pool->hubbub->funcs->init_crb) 997 dc->res_pool->hubbub->funcs->init_crb(dc->res_pool->hubbub); 998 999 // Get DMCUB capabilities 1000 if (dc->ctx->dmub_srv) { 1001 dc_dmub_srv_query_caps_cmd(dc->ctx->dmub_srv->dmub); 1002 dc->caps.dmub_caps.psr = dc->ctx->dmub_srv->dmub->feature_caps.psr; 1003 } 1004 } 1005 1006 static int calc_mpc_flow_ctrl_cnt(const struct dc_stream_state *stream, 1007 int opp_cnt) 1008 { 1009 bool hblank_halved = optc2_is_two_pixels_per_containter(&stream->timing); 1010 int flow_ctrl_cnt; 1011 1012 if (opp_cnt >= 2) 1013 hblank_halved = true; 1014 1015 flow_ctrl_cnt = stream->timing.h_total - stream->timing.h_addressable - 1016 stream->timing.h_border_left - 1017 stream->timing.h_border_right; 1018 1019 if (hblank_halved) 1020 flow_ctrl_cnt /= 2; 1021 1022 /* ODM combine 4:1 case */ 1023 if (opp_cnt == 4) 1024 flow_ctrl_cnt /= 2; 1025 1026 return flow_ctrl_cnt; 1027 } 1028 1029 static void update_dsc_on_stream(struct pipe_ctx *pipe_ctx, bool enable) 1030 { 1031 struct display_stream_compressor *dsc = pipe_ctx->stream_res.dsc; 1032 struct dc_stream_state *stream = pipe_ctx->stream; 1033 struct pipe_ctx *odm_pipe; 1034 int opp_cnt = 1; 1035 1036 ASSERT(dsc); 1037 for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) 1038 opp_cnt++; 1039 1040 if (enable) { 1041 struct dsc_config dsc_cfg; 1042 struct dsc_optc_config dsc_optc_cfg; 1043 enum optc_dsc_mode optc_dsc_mode; 1044 1045 /* Enable DSC hw block */ 1046 dsc_cfg.pic_width = (stream->timing.h_addressable + stream->timing.h_border_left + stream->timing.h_border_right) / opp_cnt; 1047 dsc_cfg.pic_height = stream->timing.v_addressable + stream->timing.v_border_top + stream->timing.v_border_bottom; 1048 dsc_cfg.pixel_encoding = stream->timing.pixel_encoding; 1049 dsc_cfg.color_depth = stream->timing.display_color_depth; 1050 dsc_cfg.is_odm = pipe_ctx->next_odm_pipe ? true : false; 1051 dsc_cfg.dc_dsc_cfg = stream->timing.dsc_cfg; 1052 ASSERT(dsc_cfg.dc_dsc_cfg.num_slices_h % opp_cnt == 0); 1053 dsc_cfg.dc_dsc_cfg.num_slices_h /= opp_cnt; 1054 1055 dsc->funcs->dsc_set_config(dsc, &dsc_cfg, &dsc_optc_cfg); 1056 dsc->funcs->dsc_enable(dsc, pipe_ctx->stream_res.opp->inst); 1057 for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) { 1058 struct display_stream_compressor *odm_dsc = odm_pipe->stream_res.dsc; 1059 1060 ASSERT(odm_dsc); 1061 odm_dsc->funcs->dsc_set_config(odm_dsc, &dsc_cfg, &dsc_optc_cfg); 1062 odm_dsc->funcs->dsc_enable(odm_dsc, odm_pipe->stream_res.opp->inst); 1063 } 1064 dsc_cfg.dc_dsc_cfg.num_slices_h *= opp_cnt; 1065 dsc_cfg.pic_width *= opp_cnt; 1066 1067 optc_dsc_mode = dsc_optc_cfg.is_pixel_format_444 ? OPTC_DSC_ENABLED_444 : OPTC_DSC_ENABLED_NATIVE_SUBSAMPLED; 1068 1069 /* Enable DSC in OPTC */ 1070 DC_LOG_DSC("Setting optc DSC config for tg instance %d:", pipe_ctx->stream_res.tg->inst); 1071 pipe_ctx->stream_res.tg->funcs->set_dsc_config(pipe_ctx->stream_res.tg, 1072 optc_dsc_mode, 1073 dsc_optc_cfg.bytes_per_pixel, 1074 dsc_optc_cfg.slice_width); 1075 } else { 1076 /* disable DSC in OPTC */ 1077 pipe_ctx->stream_res.tg->funcs->set_dsc_config( 1078 pipe_ctx->stream_res.tg, 1079 OPTC_DSC_DISABLED, 0, 0); 1080 1081 /* disable DSC block */ 1082 dsc->funcs->dsc_disable(pipe_ctx->stream_res.dsc); 1083 for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) { 1084 ASSERT(odm_pipe->stream_res.dsc); 1085 odm_pipe->stream_res.dsc->funcs->dsc_disable(odm_pipe->stream_res.dsc); 1086 } 1087 } 1088 } 1089 1090 /* 1091 * Given any pipe_ctx, return the total ODM combine factor, and optionally return 1092 * the OPPids which are used 1093 * */ 1094 static unsigned int get_odm_config(struct pipe_ctx *pipe_ctx, unsigned int *opp_instances) 1095 { 1096 unsigned int opp_count = 1; 1097 struct pipe_ctx *odm_pipe; 1098 1099 /* First get to the top pipe */ 1100 for (odm_pipe = pipe_ctx; odm_pipe->prev_odm_pipe; odm_pipe = odm_pipe->prev_odm_pipe) 1101 ; 1102 1103 /* First pipe is always used */ 1104 if (opp_instances) 1105 opp_instances[0] = odm_pipe->stream_res.opp->inst; 1106 1107 /* Find and count odm pipes, if any */ 1108 for (odm_pipe = odm_pipe->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) { 1109 if (opp_instances) 1110 opp_instances[opp_count] = odm_pipe->stream_res.opp->inst; 1111 opp_count++; 1112 } 1113 1114 return opp_count; 1115 } 1116 1117 void dcn32_update_odm(struct dc *dc, struct dc_state *context, struct pipe_ctx *pipe_ctx) 1118 { 1119 struct pipe_ctx *odm_pipe; 1120 int opp_cnt = 0; 1121 int opp_inst[MAX_PIPES] = {0}; 1122 bool rate_control_2x_pclk = (pipe_ctx->stream->timing.flags.INTERLACE || optc2_is_two_pixels_per_containter(&pipe_ctx->stream->timing)); 1123 struct mpc_dwb_flow_control flow_control; 1124 struct mpc *mpc = dc->res_pool->mpc; 1125 int i; 1126 1127 opp_cnt = get_odm_config(pipe_ctx, opp_inst); 1128 1129 if (opp_cnt > 1) 1130 pipe_ctx->stream_res.tg->funcs->set_odm_combine( 1131 pipe_ctx->stream_res.tg, 1132 opp_inst, opp_cnt, 1133 &pipe_ctx->stream->timing); 1134 else 1135 pipe_ctx->stream_res.tg->funcs->set_odm_bypass( 1136 pipe_ctx->stream_res.tg, &pipe_ctx->stream->timing); 1137 1138 rate_control_2x_pclk = rate_control_2x_pclk || opp_cnt > 1; 1139 flow_control.flow_ctrl_mode = 0; 1140 flow_control.flow_ctrl_cnt0 = 0x80; 1141 flow_control.flow_ctrl_cnt1 = calc_mpc_flow_ctrl_cnt(pipe_ctx->stream, opp_cnt); 1142 if (mpc->funcs->set_out_rate_control) { 1143 for (i = 0; i < opp_cnt; ++i) { 1144 mpc->funcs->set_out_rate_control( 1145 mpc, opp_inst[i], 1146 true, 1147 rate_control_2x_pclk, 1148 &flow_control); 1149 } 1150 } 1151 1152 for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) { 1153 odm_pipe->stream_res.opp->funcs->opp_pipe_clock_control( 1154 odm_pipe->stream_res.opp, 1155 true); 1156 } 1157 1158 // Don't program pixel clock after link is already enabled 1159 /* if (false == pipe_ctx->clock_source->funcs->program_pix_clk( 1160 pipe_ctx->clock_source, 1161 &pipe_ctx->stream_res.pix_clk_params, 1162 &pipe_ctx->pll_settings)) { 1163 BREAK_TO_DEBUGGER(); 1164 }*/ 1165 1166 if (pipe_ctx->stream_res.dsc) 1167 update_dsc_on_stream(pipe_ctx, pipe_ctx->stream->timing.flags.DSC); 1168 } 1169 1170 unsigned int dcn32_calculate_dccg_k1_k2_values(struct pipe_ctx *pipe_ctx, unsigned int *k1_div, unsigned int *k2_div) 1171 { 1172 struct dc_stream_state *stream = pipe_ctx->stream; 1173 unsigned int odm_combine_factor = 0; 1174 struct dc *dc = pipe_ctx->stream->ctx->dc; 1175 bool two_pix_per_container = false; 1176 1177 // For phantom pipes, use the same programming as the main pipes 1178 if (pipe_ctx->stream->mall_stream_config.type == SUBVP_PHANTOM) { 1179 stream = pipe_ctx->stream->mall_stream_config.paired_stream; 1180 } 1181 two_pix_per_container = optc2_is_two_pixels_per_containter(&stream->timing); 1182 odm_combine_factor = get_odm_config(pipe_ctx, NULL); 1183 1184 if (is_dp_128b_132b_signal(pipe_ctx)) { 1185 *k2_div = PIXEL_RATE_DIV_BY_1; 1186 } else if (dc_is_hdmi_tmds_signal(pipe_ctx->stream->signal) || dc_is_dvi_signal(pipe_ctx->stream->signal)) { 1187 *k1_div = PIXEL_RATE_DIV_BY_1; 1188 if (stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR420) 1189 *k2_div = PIXEL_RATE_DIV_BY_2; 1190 else 1191 *k2_div = PIXEL_RATE_DIV_BY_4; 1192 } else if (dc_is_dp_signal(pipe_ctx->stream->signal)) { 1193 if (two_pix_per_container) { 1194 *k1_div = PIXEL_RATE_DIV_BY_1; 1195 *k2_div = PIXEL_RATE_DIV_BY_2; 1196 } else { 1197 *k1_div = PIXEL_RATE_DIV_BY_1; 1198 *k2_div = PIXEL_RATE_DIV_BY_4; 1199 if ((odm_combine_factor == 2) || dc->debug.enable_dp_dig_pixel_rate_div_policy) 1200 *k2_div = PIXEL_RATE_DIV_BY_2; 1201 } 1202 } 1203 1204 if ((*k1_div == PIXEL_RATE_DIV_NA) && (*k2_div == PIXEL_RATE_DIV_NA)) 1205 ASSERT(false); 1206 1207 return odm_combine_factor; 1208 } 1209 1210 void dcn32_set_pixels_per_cycle(struct pipe_ctx *pipe_ctx) 1211 { 1212 uint32_t pix_per_cycle = 1; 1213 uint32_t odm_combine_factor = 1; 1214 1215 if (!pipe_ctx || !pipe_ctx->stream || !pipe_ctx->stream_res.stream_enc) 1216 return; 1217 1218 odm_combine_factor = get_odm_config(pipe_ctx, NULL); 1219 if (optc2_is_two_pixels_per_containter(&pipe_ctx->stream->timing) || odm_combine_factor > 1 1220 || dcn32_is_dp_dig_pixel_rate_div_policy(pipe_ctx)) 1221 pix_per_cycle = 2; 1222 1223 if (pipe_ctx->stream_res.stream_enc->funcs->set_input_mode) 1224 pipe_ctx->stream_res.stream_enc->funcs->set_input_mode(pipe_ctx->stream_res.stream_enc, 1225 pix_per_cycle); 1226 } 1227 1228 void dcn32_unblank_stream(struct pipe_ctx *pipe_ctx, 1229 struct dc_link_settings *link_settings) 1230 { 1231 struct encoder_unblank_param params = {0}; 1232 struct dc_stream_state *stream = pipe_ctx->stream; 1233 struct dc_link *link = stream->link; 1234 struct dce_hwseq *hws = link->dc->hwseq; 1235 struct pipe_ctx *odm_pipe; 1236 struct dc *dc = pipe_ctx->stream->ctx->dc; 1237 uint32_t pix_per_cycle = 1; 1238 1239 params.opp_cnt = 1; 1240 for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) 1241 params.opp_cnt++; 1242 1243 /* only 3 items below are used by unblank */ 1244 params.timing = pipe_ctx->stream->timing; 1245 1246 params.link_settings.link_rate = link_settings->link_rate; 1247 1248 if (is_dp_128b_132b_signal(pipe_ctx)) { 1249 /* TODO - DP2.0 HW: Set ODM mode in dp hpo encoder here */ 1250 pipe_ctx->stream_res.hpo_dp_stream_enc->funcs->dp_unblank( 1251 pipe_ctx->stream_res.hpo_dp_stream_enc, 1252 pipe_ctx->stream_res.tg->inst); 1253 } else if (dc_is_dp_signal(pipe_ctx->stream->signal)) { 1254 if (optc2_is_two_pixels_per_containter(&stream->timing) || params.opp_cnt > 1 1255 || dc->debug.enable_dp_dig_pixel_rate_div_policy) { 1256 params.timing.pix_clk_100hz /= 2; 1257 pix_per_cycle = 2; 1258 } 1259 pipe_ctx->stream_res.stream_enc->funcs->dp_set_odm_combine( 1260 pipe_ctx->stream_res.stream_enc, pix_per_cycle > 1); 1261 pipe_ctx->stream_res.stream_enc->funcs->dp_unblank(link, pipe_ctx->stream_res.stream_enc, ¶ms); 1262 } 1263 1264 if (link->local_sink && link->local_sink->sink_signal == SIGNAL_TYPE_EDP) 1265 hws->funcs.edp_backlight_control(link, true); 1266 } 1267 1268 bool dcn32_is_dp_dig_pixel_rate_div_policy(struct pipe_ctx *pipe_ctx) 1269 { 1270 struct dc *dc = pipe_ctx->stream->ctx->dc; 1271 1272 if (dc_is_dp_signal(pipe_ctx->stream->signal) && !is_dp_128b_132b_signal(pipe_ctx) && 1273 dc->debug.enable_dp_dig_pixel_rate_div_policy) 1274 return true; 1275 return false; 1276 } 1277