1 /*
2  * Copyright 2012-20 Advanced Micro Devices, Inc.
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice shall be included in
12  * all copies or substantial portions of the Software.
13  *
14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20  * OTHER DEALINGS IN THE SOFTWARE.
21  *
22  * Authors: AMD
23  *
24  */
25 
26 #ifndef __DC_HUBP_DCN32_H__
27 #define __DC_HUBP_DCN32_H__
28 
29 #include "dcn20/dcn20_hubp.h"
30 #include "dcn21/dcn21_hubp.h"
31 #include "dcn30/dcn30_hubp.h"
32 #include "dcn31/dcn31_hubp.h"
33 
34 #define HUBP_REG_LIST_DCN32(id)\
35 	HUBP_REG_LIST_DCN30(id),\
36 	SRI(DCHUBP_MALL_CONFIG, HUBP, id),\
37 	SRI(DCHUBP_VMPG_CONFIG, HUBP, id),\
38 	SRI(UCLK_PSTATE_FORCE, HUBPREQ, id)
39 
40 #define HUBP_MASK_SH_LIST_DCN32(mask_sh)\
41 	HUBP_MASK_SH_LIST_DCN31(mask_sh),\
42 	HUBP_SF(HUBP0_DCHUBP_MALL_CONFIG, USE_MALL_SEL, mask_sh),\
43 	HUBP_SF(HUBP0_DCHUBP_MALL_CONFIG, USE_MALL_FOR_CURSOR, mask_sh),\
44 	HUBP_SF(HUBP0_DCHUBP_VMPG_CONFIG, VMPG_SIZE, mask_sh),\
45 	HUBP_SF(HUBP0_DCHUBP_VMPG_CONFIG, PTE_BUFFER_MODE, mask_sh),\
46 	HUBP_SF(HUBP0_DCHUBP_VMPG_CONFIG, BIGK_FRAGMENT_SIZE, mask_sh),\
47 	HUBP_SF(HUBP0_DCHUBP_VMPG_CONFIG, FORCE_ONE_ROW_FOR_FRAME, mask_sh),\
48 	HUBP_SF(HUBPREQ0_UCLK_PSTATE_FORCE, DATA_UCLK_PSTATE_FORCE_EN, mask_sh),\
49 	HUBP_SF(HUBPREQ0_UCLK_PSTATE_FORCE, DATA_UCLK_PSTATE_FORCE_VALUE, mask_sh),\
50 	HUBP_SF(HUBPREQ0_UCLK_PSTATE_FORCE, CURSOR_UCLK_PSTATE_FORCE_EN, mask_sh),\
51 	HUBP_SF(HUBPREQ0_UCLK_PSTATE_FORCE, CURSOR_UCLK_PSTATE_FORCE_VALUE, mask_sh)
52 
53 void hubp32_update_force_pstate_disallow(struct hubp *hubp, bool pstate_disallow);
54 
55 void hubp32_update_mall_sel(struct hubp *hubp, uint32_t mall_sel, bool c_cursor);
56 
57 void hubp32_prepare_subvp_buffering(struct hubp *hubp, bool enable);
58 
59 void hubp32_phantom_hubp_post_enable(struct hubp *hubp);
60 
61 void hubp32_cursor_set_attributes(struct hubp *hubp,
62 		const struct dc_cursor_attributes *attr);
63 
64 bool hubp32_construct(
65 	struct dcn20_hubp *hubp2,
66 	struct dc_context *ctx,
67 	uint32_t inst,
68 	const struct dcn_hubp2_registers *hubp_regs,
69 	const struct dcn_hubp2_shift *hubp_shift,
70 	const struct dcn_hubp2_mask *hubp_mask);
71 
72 #endif /* __DC_HUBP_DCN32_H__ */
73