1 /* 2 * Copyright 2012-20 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #include "dm_services.h" 27 #include "dce_calcs.h" 28 #include "reg_helper.h" 29 #include "basics/conversion.h" 30 #include "dcn32_hubp.h" 31 32 #define REG(reg)\ 33 hubp2->hubp_regs->reg 34 35 #define CTX \ 36 hubp2->base.ctx 37 38 #undef FN 39 #define FN(reg_name, field_name) \ 40 hubp2->hubp_shift->field_name, hubp2->hubp_mask->field_name 41 42 void hubp32_update_force_pstate_disallow(struct hubp *hubp, bool pstate_disallow) 43 { 44 struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); 45 REG_UPDATE_2(UCLK_PSTATE_FORCE, 46 DATA_UCLK_PSTATE_FORCE_EN, pstate_disallow, 47 DATA_UCLK_PSTATE_FORCE_VALUE, 0); 48 } 49 50 void hubp32_update_mall_sel(struct hubp *hubp, uint32_t mall_sel, bool c_cursor) 51 { 52 struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); 53 54 // Also cache cursor in MALL if using MALL for SS 55 REG_UPDATE_2(DCHUBP_MALL_CONFIG, USE_MALL_SEL, mall_sel, 56 USE_MALL_FOR_CURSOR, c_cursor); 57 } 58 59 void hubp32_prepare_subvp_buffering(struct hubp *hubp, bool enable) 60 { 61 struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); 62 REG_UPDATE(DCHUBP_VMPG_CONFIG, FORCE_ONE_ROW_FOR_FRAME, enable); 63 64 /* Programming guide suggests CURSOR_REQ_MODE = 1 for SubVP: 65 * For Pstate change using the MALL with sub-viewport buffering, 66 * the cursor does not use the MALL (USE_MALL_FOR_CURSOR is ignored) 67 * and sub-viewport positioning by Display FW has to avoid the cursor 68 * requests to DRAM (set CURSOR_REQ_MODE = 1 to minimize this exclusion). 69 * 70 * CURSOR_REQ_MODE = 1 begins fetching cursor data at the beginning of display prefetch. 71 * Setting this should allow the sub-viewport position to always avoid the cursor because 72 * we do not allow the sub-viewport region to overlap with display prefetch (i.e. during blank). 73 */ 74 REG_UPDATE(CURSOR_CONTROL, CURSOR_REQ_MODE, enable); 75 } 76 77 void hubp32_phantom_hubp_post_enable(struct hubp *hubp) 78 { 79 uint32_t reg_val; 80 struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); 81 82 REG_UPDATE(DCHUBP_CNTL, HUBP_BLANK_EN, 1); 83 reg_val = REG_READ(DCHUBP_CNTL); 84 if (reg_val) { 85 /* init sequence workaround: in case HUBP is 86 * power gated, this wait would timeout. 87 * 88 * we just wrote reg_val to non-0, if it stay 0 89 * it means HUBP is gated 90 */ 91 REG_WAIT(DCHUBP_CNTL, 92 HUBP_NO_OUTSTANDING_REQ, 1, 93 1, 200); 94 } 95 } 96 97 void hubp32_cursor_set_attributes( 98 struct hubp *hubp, 99 const struct dc_cursor_attributes *attr) 100 { 101 struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); 102 enum cursor_pitch hw_pitch = hubp1_get_cursor_pitch(attr->pitch); 103 enum cursor_lines_per_chunk lpc = hubp2_get_lines_per_chunk( 104 attr->width, attr->color_format); 105 106 hubp->curs_attr = *attr; 107 108 REG_UPDATE(CURSOR_SURFACE_ADDRESS_HIGH, 109 CURSOR_SURFACE_ADDRESS_HIGH, attr->address.high_part); 110 REG_UPDATE(CURSOR_SURFACE_ADDRESS, 111 CURSOR_SURFACE_ADDRESS, attr->address.low_part); 112 113 REG_UPDATE_2(CURSOR_SIZE, 114 CURSOR_WIDTH, attr->width, 115 CURSOR_HEIGHT, attr->height); 116 117 REG_UPDATE_4(CURSOR_CONTROL, 118 CURSOR_MODE, attr->color_format, 119 CURSOR_2X_MAGNIFY, attr->attribute_flags.bits.ENABLE_MAGNIFICATION, 120 CURSOR_PITCH, hw_pitch, 121 CURSOR_LINES_PER_CHUNK, lpc); 122 123 REG_SET_2(CURSOR_SETTINGS, 0, 124 /* no shift of the cursor HDL schedule */ 125 CURSOR0_DST_Y_OFFSET, 0, 126 /* used to shift the cursor chunk request deadline */ 127 CURSOR0_CHUNK_HDL_ADJUST, 3); 128 129 if (attr->width * attr->height * 4 > 16384) 130 REG_UPDATE(DCHUBP_MALL_CONFIG, USE_MALL_FOR_CURSOR, true); 131 else 132 REG_UPDATE(DCHUBP_MALL_CONFIG, USE_MALL_FOR_CURSOR, false); 133 } 134 135 static struct hubp_funcs dcn32_hubp_funcs = { 136 .hubp_enable_tripleBuffer = hubp2_enable_triplebuffer, 137 .hubp_is_triplebuffer_enabled = hubp2_is_triplebuffer_enabled, 138 .hubp_program_surface_flip_and_addr = hubp3_program_surface_flip_and_addr, 139 .hubp_program_surface_config = hubp3_program_surface_config, 140 .hubp_is_flip_pending = hubp2_is_flip_pending, 141 .hubp_setup = hubp3_setup, 142 .hubp_setup_interdependent = hubp2_setup_interdependent, 143 .hubp_set_vm_system_aperture_settings = hubp3_set_vm_system_aperture_settings, 144 .set_blank = hubp2_set_blank, 145 .dcc_control = hubp3_dcc_control, 146 .mem_program_viewport = min_set_viewport, 147 .set_cursor_attributes = hubp32_cursor_set_attributes, 148 .set_cursor_position = hubp2_cursor_set_position, 149 .hubp_clk_cntl = hubp2_clk_cntl, 150 .hubp_vtg_sel = hubp2_vtg_sel, 151 .dmdata_set_attributes = hubp3_dmdata_set_attributes, 152 .dmdata_load = hubp2_dmdata_load, 153 .dmdata_status_done = hubp2_dmdata_status_done, 154 .hubp_read_state = hubp3_read_state, 155 .hubp_clear_underflow = hubp2_clear_underflow, 156 .hubp_set_flip_control_surface_gsl = hubp2_set_flip_control_surface_gsl, 157 .hubp_init = hubp3_init, 158 .set_unbounded_requesting = hubp31_set_unbounded_requesting, 159 .hubp_soft_reset = hubp31_soft_reset, 160 .hubp_in_blank = hubp1_in_blank, 161 .hubp_update_force_pstate_disallow = hubp32_update_force_pstate_disallow, 162 .phantom_hubp_post_enable = hubp32_phantom_hubp_post_enable, 163 .hubp_update_mall_sel = hubp32_update_mall_sel, 164 .hubp_prepare_subvp_buffering = hubp32_prepare_subvp_buffering, 165 .hubp_set_flip_int = hubp1_set_flip_int 166 }; 167 168 bool hubp32_construct( 169 struct dcn20_hubp *hubp2, 170 struct dc_context *ctx, 171 uint32_t inst, 172 const struct dcn_hubp2_registers *hubp_regs, 173 const struct dcn_hubp2_shift *hubp_shift, 174 const struct dcn_hubp2_mask *hubp_mask) 175 { 176 hubp2->base.funcs = &dcn32_hubp_funcs; 177 hubp2->base.ctx = ctx; 178 hubp2->hubp_regs = hubp_regs; 179 hubp2->hubp_shift = hubp_shift; 180 hubp2->hubp_mask = hubp_mask; 181 hubp2->base.inst = inst; 182 hubp2->base.opp_id = OPP_ID_INVALID; 183 hubp2->base.mpcc_id = 0xf; 184 185 return true; 186 } 187