1 /* 2 * Copyright 2012-20 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #include "dm_services.h" 27 #include "dce_calcs.h" 28 #include "reg_helper.h" 29 #include "basics/conversion.h" 30 #include "dcn32_hubp.h" 31 32 #define REG(reg)\ 33 hubp2->hubp_regs->reg 34 35 #define CTX \ 36 hubp2->base.ctx 37 38 #undef FN 39 #define FN(reg_name, field_name) \ 40 hubp2->hubp_shift->field_name, hubp2->hubp_mask->field_name 41 42 void hubp32_update_force_pstate_disallow(struct hubp *hubp, bool pstate_disallow) 43 { 44 struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); 45 REG_UPDATE_2(UCLK_PSTATE_FORCE, 46 DATA_UCLK_PSTATE_FORCE_EN, pstate_disallow, 47 DATA_UCLK_PSTATE_FORCE_VALUE, 0); 48 } 49 50 void hubp32_update_mall_sel(struct hubp *hubp, uint32_t mall_sel) 51 { 52 struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); 53 54 // Also cache cursor in MALL if using MALL for SS 55 REG_UPDATE_2(DCHUBP_MALL_CONFIG, USE_MALL_SEL, mall_sel, 56 USE_MALL_FOR_CURSOR, mall_sel == 2 ? 1 : 0); 57 } 58 59 void hubp32_prepare_subvp_buffering(struct hubp *hubp, bool enable) 60 { 61 struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); 62 REG_UPDATE(DCHUBP_VMPG_CONFIG, FORCE_ONE_ROW_FOR_FRAME, enable); 63 64 /* Programming guide suggests CURSOR_REQ_MODE = 1 for SubVP: 65 * For Pstate change using the MALL with sub-viewport buffering, 66 * the cursor does not use the MALL (USE_MALL_FOR_CURSOR is ignored) 67 * and sub-viewport positioning by Display FW has to avoid the cursor 68 * requests to DRAM (set CURSOR_REQ_MODE = 1 to minimize this exclusion). 69 * 70 * CURSOR_REQ_MODE = 1 begins fetching cursor data at the beginning of display prefetch. 71 * Setting this should allow the sub-viewport position to always avoid the cursor because 72 * we do not allow the sub-viewport region to overlap with display prefetch (i.e. during blank). 73 */ 74 REG_UPDATE(CURSOR_CONTROL, CURSOR_REQ_MODE, enable); 75 } 76 77 void hubp32_phantom_hubp_post_enable(struct hubp *hubp) 78 { 79 uint32_t reg_val; 80 struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); 81 82 REG_UPDATE(DCHUBP_CNTL, HUBP_BLANK_EN, 1); 83 reg_val = REG_READ(DCHUBP_CNTL); 84 if (reg_val) { 85 /* init sequence workaround: in case HUBP is 86 * power gated, this wait would timeout. 87 * 88 * we just wrote reg_val to non-0, if it stay 0 89 * it means HUBP is gated 90 */ 91 REG_WAIT(DCHUBP_CNTL, 92 HUBP_NO_OUTSTANDING_REQ, 1, 93 1, 200); 94 } 95 } 96 97 static struct hubp_funcs dcn32_hubp_funcs = { 98 .hubp_enable_tripleBuffer = hubp2_enable_triplebuffer, 99 .hubp_is_triplebuffer_enabled = hubp2_is_triplebuffer_enabled, 100 .hubp_program_surface_flip_and_addr = hubp3_program_surface_flip_and_addr, 101 .hubp_program_surface_config = hubp3_program_surface_config, 102 .hubp_is_flip_pending = hubp2_is_flip_pending, 103 .hubp_setup = hubp3_setup, 104 .hubp_setup_interdependent = hubp2_setup_interdependent, 105 .hubp_set_vm_system_aperture_settings = hubp3_set_vm_system_aperture_settings, 106 .set_blank = hubp2_set_blank, 107 .dcc_control = hubp3_dcc_control, 108 .mem_program_viewport = min_set_viewport, 109 .set_cursor_attributes = hubp2_cursor_set_attributes, 110 .set_cursor_position = hubp2_cursor_set_position, 111 .hubp_clk_cntl = hubp2_clk_cntl, 112 .hubp_vtg_sel = hubp2_vtg_sel, 113 .dmdata_set_attributes = hubp3_dmdata_set_attributes, 114 .dmdata_load = hubp2_dmdata_load, 115 .dmdata_status_done = hubp2_dmdata_status_done, 116 .hubp_read_state = hubp3_read_state, 117 .hubp_clear_underflow = hubp2_clear_underflow, 118 .hubp_set_flip_control_surface_gsl = hubp2_set_flip_control_surface_gsl, 119 .hubp_init = hubp3_init, 120 .set_unbounded_requesting = hubp31_set_unbounded_requesting, 121 .hubp_soft_reset = hubp31_soft_reset, 122 .hubp_in_blank = hubp1_in_blank, 123 .hubp_update_force_pstate_disallow = hubp32_update_force_pstate_disallow, 124 .phantom_hubp_post_enable = hubp32_phantom_hubp_post_enable, 125 .hubp_update_mall_sel = hubp32_update_mall_sel, 126 .hubp_prepare_subvp_buffering = hubp32_prepare_subvp_buffering, 127 .hubp_set_flip_int = hubp1_set_flip_int 128 }; 129 130 bool hubp32_construct( 131 struct dcn20_hubp *hubp2, 132 struct dc_context *ctx, 133 uint32_t inst, 134 const struct dcn_hubp2_registers *hubp_regs, 135 const struct dcn_hubp2_shift *hubp_shift, 136 const struct dcn_hubp2_mask *hubp_mask) 137 { 138 hubp2->base.funcs = &dcn32_hubp_funcs; 139 hubp2->base.ctx = ctx; 140 hubp2->hubp_regs = hubp_regs; 141 hubp2->hubp_shift = hubp_shift; 142 hubp2->hubp_mask = hubp_mask; 143 hubp2->base.inst = inst; 144 hubp2->base.opp_id = OPP_ID_INVALID; 145 hubp2->base.mpcc_id = 0xf; 146 147 return true; 148 } 149