1 /* 2 * Copyright 2021 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #include "reg_helper.h" 27 #include "core_types.h" 28 #include "dcn32_dccg.h" 29 30 #define TO_DCN_DCCG(dccg)\ 31 container_of(dccg, struct dcn_dccg, base) 32 33 #define REG(reg) \ 34 (dccg_dcn->regs->reg) 35 36 #undef FN 37 #define FN(reg_name, field_name) \ 38 dccg_dcn->dccg_shift->field_name, dccg_dcn->dccg_mask->field_name 39 40 #define CTX \ 41 dccg_dcn->base.ctx 42 #define DC_LOGGER \ 43 dccg->ctx->logger 44 45 /* This function is a workaround for writing to OTG_PIXEL_RATE_DIV 46 * without the probability of causing a DIG FIFO error. 47 */ 48 static void dccg32_wait_for_dentist_change_done( 49 struct dccg *dccg) 50 { 51 struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg); 52 53 uint32_t dentist_dispclk_value = REG_READ(DENTIST_DISPCLK_CNTL); 54 55 REG_WRITE(DENTIST_DISPCLK_CNTL, dentist_dispclk_value); 56 REG_WAIT(DENTIST_DISPCLK_CNTL, DENTIST_DISPCLK_CHG_DONE, 1, 50, 2000); 57 } 58 59 static void dccg32_get_pixel_rate_div( 60 struct dccg *dccg, 61 uint32_t otg_inst, 62 enum pixel_rate_div *k1, 63 enum pixel_rate_div *k2) 64 { 65 struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg); 66 uint32_t val_k1 = PIXEL_RATE_DIV_NA, val_k2 = PIXEL_RATE_DIV_NA; 67 68 *k1 = PIXEL_RATE_DIV_NA; 69 *k2 = PIXEL_RATE_DIV_NA; 70 71 switch (otg_inst) { 72 case 0: 73 REG_GET_2(OTG_PIXEL_RATE_DIV, 74 OTG0_PIXEL_RATE_DIVK1, &val_k1, 75 OTG0_PIXEL_RATE_DIVK2, &val_k2); 76 break; 77 case 1: 78 REG_GET_2(OTG_PIXEL_RATE_DIV, 79 OTG1_PIXEL_RATE_DIVK1, &val_k1, 80 OTG1_PIXEL_RATE_DIVK2, &val_k2); 81 break; 82 case 2: 83 REG_GET_2(OTG_PIXEL_RATE_DIV, 84 OTG2_PIXEL_RATE_DIVK1, &val_k1, 85 OTG2_PIXEL_RATE_DIVK2, &val_k2); 86 break; 87 case 3: 88 REG_GET_2(OTG_PIXEL_RATE_DIV, 89 OTG3_PIXEL_RATE_DIVK1, &val_k1, 90 OTG3_PIXEL_RATE_DIVK2, &val_k2); 91 break; 92 default: 93 BREAK_TO_DEBUGGER(); 94 return; 95 } 96 97 *k1 = (enum pixel_rate_div)val_k1; 98 *k2 = (enum pixel_rate_div)val_k2; 99 } 100 101 static void dccg32_set_pixel_rate_div( 102 struct dccg *dccg, 103 uint32_t otg_inst, 104 enum pixel_rate_div k1, 105 enum pixel_rate_div k2) 106 { 107 struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg); 108 109 enum pixel_rate_div cur_k1 = PIXEL_RATE_DIV_NA, cur_k2 = PIXEL_RATE_DIV_NA; 110 111 // Don't program 0xF into the register field. Not valid since 112 // K1 / K2 field is only 1 / 2 bits wide 113 if (k1 == PIXEL_RATE_DIV_NA || k2 == PIXEL_RATE_DIV_NA) { 114 BREAK_TO_DEBUGGER(); 115 return; 116 } 117 118 dccg32_get_pixel_rate_div(dccg, otg_inst, &cur_k1, &cur_k2); 119 if (k1 == cur_k1 && k2 == cur_k2) 120 return; 121 122 switch (otg_inst) { 123 case 0: 124 REG_UPDATE_2(OTG_PIXEL_RATE_DIV, 125 OTG0_PIXEL_RATE_DIVK1, k1, 126 OTG0_PIXEL_RATE_DIVK2, k2); 127 128 dccg32_wait_for_dentist_change_done(dccg); 129 break; 130 case 1: 131 REG_UPDATE_2(OTG_PIXEL_RATE_DIV, 132 OTG1_PIXEL_RATE_DIVK1, k1, 133 OTG1_PIXEL_RATE_DIVK2, k2); 134 135 dccg32_wait_for_dentist_change_done(dccg); 136 break; 137 case 2: 138 REG_UPDATE_2(OTG_PIXEL_RATE_DIV, 139 OTG2_PIXEL_RATE_DIVK1, k1, 140 OTG2_PIXEL_RATE_DIVK2, k2); 141 142 dccg32_wait_for_dentist_change_done(dccg); 143 break; 144 case 3: 145 REG_UPDATE_2(OTG_PIXEL_RATE_DIV, 146 OTG3_PIXEL_RATE_DIVK1, k1, 147 OTG3_PIXEL_RATE_DIVK2, k2); 148 149 dccg32_wait_for_dentist_change_done(dccg); 150 break; 151 default: 152 BREAK_TO_DEBUGGER(); 153 return; 154 } 155 } 156 157 static void dccg32_set_dtbclk_p_src( 158 struct dccg *dccg, 159 enum streamclk_source src, 160 uint32_t otg_inst) 161 { 162 struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg); 163 164 uint32_t p_src_sel = 0; /* selects dprefclk */ 165 if (src == DTBCLK0) 166 p_src_sel = 2; /* selects dtbclk0 */ 167 168 switch (otg_inst) { 169 case 0: 170 if (src == REFCLK) 171 REG_UPDATE(DTBCLK_P_CNTL, 172 DTBCLK_P0_EN, 0); 173 else 174 REG_UPDATE_2(DTBCLK_P_CNTL, 175 DTBCLK_P0_SRC_SEL, p_src_sel, 176 DTBCLK_P0_EN, 1); 177 break; 178 case 1: 179 if (src == REFCLK) 180 REG_UPDATE(DTBCLK_P_CNTL, 181 DTBCLK_P1_EN, 0); 182 else 183 REG_UPDATE_2(DTBCLK_P_CNTL, 184 DTBCLK_P1_SRC_SEL, p_src_sel, 185 DTBCLK_P1_EN, 1); 186 break; 187 case 2: 188 if (src == REFCLK) 189 REG_UPDATE(DTBCLK_P_CNTL, 190 DTBCLK_P2_EN, 0); 191 else 192 REG_UPDATE_2(DTBCLK_P_CNTL, 193 DTBCLK_P2_SRC_SEL, p_src_sel, 194 DTBCLK_P2_EN, 1); 195 break; 196 case 3: 197 if (src == REFCLK) 198 REG_UPDATE(DTBCLK_P_CNTL, 199 DTBCLK_P3_EN, 0); 200 else 201 REG_UPDATE_2(DTBCLK_P_CNTL, 202 DTBCLK_P3_SRC_SEL, p_src_sel, 203 DTBCLK_P3_EN, 1); 204 break; 205 default: 206 BREAK_TO_DEBUGGER(); 207 return; 208 } 209 210 } 211 212 /* Controls the generation of pixel valid for OTG in (OTG -> HPO case) */ 213 static void dccg32_set_dtbclk_dto( 214 struct dccg *dccg, 215 const struct dtbclk_dto_params *params) 216 { 217 struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg); 218 /* DTO Output Rate / Pixel Rate = 1/4 */ 219 int req_dtbclk_khz = params->pixclk_khz / 4; 220 221 if (params->ref_dtbclk_khz && req_dtbclk_khz) { 222 uint32_t modulo, phase; 223 224 // phase / modulo = dtbclk / dtbclk ref 225 modulo = params->ref_dtbclk_khz * 1000; 226 phase = req_dtbclk_khz * 1000; 227 228 REG_WRITE(DTBCLK_DTO_MODULO[params->otg_inst], modulo); 229 REG_WRITE(DTBCLK_DTO_PHASE[params->otg_inst], phase); 230 231 REG_UPDATE(OTG_PIXEL_RATE_CNTL[params->otg_inst], 232 DTBCLK_DTO_ENABLE[params->otg_inst], 1); 233 234 REG_WAIT(OTG_PIXEL_RATE_CNTL[params->otg_inst], 235 DTBCLKDTO_ENABLE_STATUS[params->otg_inst], 1, 236 1, 100); 237 238 /* program OTG_PIXEL_RATE_DIV for DIVK1 and DIVK2 fields */ 239 dccg32_set_pixel_rate_div(dccg, params->otg_inst, PIXEL_RATE_DIV_BY_1, PIXEL_RATE_DIV_BY_1); 240 241 /* The recommended programming sequence to enable DTBCLK DTO to generate 242 * valid pixel HPO DPSTREAM ENCODER, specifies that DTO source select should 243 * be set only after DTO is enabled 244 */ 245 REG_UPDATE(OTG_PIXEL_RATE_CNTL[params->otg_inst], 246 PIPE_DTO_SRC_SEL[params->otg_inst], 2); 247 } else { 248 REG_UPDATE_2(OTG_PIXEL_RATE_CNTL[params->otg_inst], 249 DTBCLK_DTO_ENABLE[params->otg_inst], 0, 250 PIPE_DTO_SRC_SEL[params->otg_inst], params->is_hdmi ? 0 : 1); 251 REG_WRITE(DTBCLK_DTO_MODULO[params->otg_inst], 0); 252 REG_WRITE(DTBCLK_DTO_PHASE[params->otg_inst], 0); 253 } 254 } 255 256 static void dccg32_set_valid_pixel_rate( 257 struct dccg *dccg, 258 int ref_dtbclk_khz, 259 int otg_inst, 260 int pixclk_khz) 261 { 262 struct dtbclk_dto_params dto_params = {0}; 263 264 dto_params.ref_dtbclk_khz = ref_dtbclk_khz; 265 dto_params.otg_inst = otg_inst; 266 dto_params.pixclk_khz = pixclk_khz; 267 dto_params.is_hdmi = true; 268 269 dccg32_set_dtbclk_dto(dccg, &dto_params); 270 } 271 272 static void dccg32_get_dccg_ref_freq(struct dccg *dccg, 273 unsigned int xtalin_freq_inKhz, 274 unsigned int *dccg_ref_freq_inKhz) 275 { 276 /* 277 * Assume refclk is sourced from xtalin 278 * expect 100MHz 279 */ 280 *dccg_ref_freq_inKhz = xtalin_freq_inKhz; 281 return; 282 } 283 284 static void dccg32_set_dpstreamclk( 285 struct dccg *dccg, 286 enum streamclk_source src, 287 int otg_inst, 288 int dp_hpo_inst) 289 { 290 struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg); 291 292 /* set the dtbclk_p source */ 293 dccg32_set_dtbclk_p_src(dccg, src, otg_inst); 294 295 /* enabled to select one of the DTBCLKs for pipe */ 296 switch (dp_hpo_inst) { 297 case 0: 298 REG_UPDATE_2(DPSTREAMCLK_CNTL, 299 DPSTREAMCLK0_EN, 300 (src == REFCLK) ? 0 : 1, DPSTREAMCLK0_SRC_SEL, otg_inst); 301 break; 302 case 1: 303 REG_UPDATE_2(DPSTREAMCLK_CNTL, DPSTREAMCLK1_EN, 304 (src == REFCLK) ? 0 : 1, DPSTREAMCLK1_SRC_SEL, otg_inst); 305 break; 306 case 2: 307 REG_UPDATE_2(DPSTREAMCLK_CNTL, DPSTREAMCLK2_EN, 308 (src == REFCLK) ? 0 : 1, DPSTREAMCLK2_SRC_SEL, otg_inst); 309 break; 310 case 3: 311 REG_UPDATE_2(DPSTREAMCLK_CNTL, DPSTREAMCLK3_EN, 312 (src == REFCLK) ? 0 : 1, DPSTREAMCLK3_SRC_SEL, otg_inst); 313 break; 314 default: 315 BREAK_TO_DEBUGGER(); 316 return; 317 } 318 } 319 320 static void dccg32_otg_add_pixel(struct dccg *dccg, 321 uint32_t otg_inst) 322 { 323 struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg); 324 325 REG_UPDATE(OTG_PIXEL_RATE_CNTL[otg_inst], 326 OTG_ADD_PIXEL[otg_inst], 1); 327 } 328 329 static void dccg32_otg_drop_pixel(struct dccg *dccg, 330 uint32_t otg_inst) 331 { 332 struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg); 333 334 REG_UPDATE(OTG_PIXEL_RATE_CNTL[otg_inst], 335 OTG_DROP_PIXEL[otg_inst], 1); 336 } 337 338 static const struct dccg_funcs dccg32_funcs = { 339 .update_dpp_dto = dccg2_update_dpp_dto, 340 .get_dccg_ref_freq = dccg32_get_dccg_ref_freq, 341 .dccg_init = dccg31_init, 342 .set_dpstreamclk = dccg32_set_dpstreamclk, 343 .enable_symclk32_se = dccg31_enable_symclk32_se, 344 .disable_symclk32_se = dccg31_disable_symclk32_se, 345 .enable_symclk32_le = dccg31_enable_symclk32_le, 346 .disable_symclk32_le = dccg31_disable_symclk32_le, 347 .set_physymclk = dccg31_set_physymclk, 348 .set_dtbclk_dto = dccg32_set_dtbclk_dto, 349 .set_valid_pixel_rate = dccg32_set_valid_pixel_rate, 350 .set_fifo_errdet_ovr_en = dccg2_set_fifo_errdet_ovr_en, 351 .set_audio_dtbclk_dto = dccg31_set_audio_dtbclk_dto, 352 .otg_add_pixel = dccg32_otg_add_pixel, 353 .otg_drop_pixel = dccg32_otg_drop_pixel, 354 .set_pixel_rate_div = dccg32_set_pixel_rate_div, 355 }; 356 357 struct dccg *dccg32_create( 358 struct dc_context *ctx, 359 const struct dccg_registers *regs, 360 const struct dccg_shift *dccg_shift, 361 const struct dccg_mask *dccg_mask) 362 { 363 struct dcn_dccg *dccg_dcn = kzalloc(sizeof(*dccg_dcn), GFP_KERNEL); 364 struct dccg *base; 365 366 if (dccg_dcn == NULL) { 367 BREAK_TO_DEBUGGER(); 368 return NULL; 369 } 370 371 base = &dccg_dcn->base; 372 base->ctx = ctx; 373 base->funcs = &dccg32_funcs; 374 375 dccg_dcn->regs = regs; 376 dccg_dcn->dccg_shift = dccg_shift; 377 dccg_dcn->dccg_mask = dccg_mask; 378 379 return &dccg_dcn->base; 380 } 381