1 /* 2 * Copyright 2021 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #include "reg_helper.h" 27 #include "core_types.h" 28 #include "dcn32_dccg.h" 29 30 #define TO_DCN_DCCG(dccg)\ 31 container_of(dccg, struct dcn_dccg, base) 32 33 #define REG(reg) \ 34 (dccg_dcn->regs->reg) 35 36 #undef FN 37 #define FN(reg_name, field_name) \ 38 dccg_dcn->dccg_shift->field_name, dccg_dcn->dccg_mask->field_name 39 40 #define CTX \ 41 dccg_dcn->base.ctx 42 #define DC_LOGGER \ 43 dccg->ctx->logger 44 45 static void dccg32_get_pixel_rate_div( 46 struct dccg *dccg, 47 uint32_t otg_inst, 48 enum pixel_rate_div *k1, 49 enum pixel_rate_div *k2) 50 { 51 struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg); 52 uint32_t val_k1 = PIXEL_RATE_DIV_NA, val_k2 = PIXEL_RATE_DIV_NA; 53 54 *k1 = PIXEL_RATE_DIV_NA; 55 *k2 = PIXEL_RATE_DIV_NA; 56 57 switch (otg_inst) { 58 case 0: 59 REG_GET_2(OTG_PIXEL_RATE_DIV, 60 OTG0_PIXEL_RATE_DIVK1, &val_k1, 61 OTG0_PIXEL_RATE_DIVK2, &val_k2); 62 break; 63 case 1: 64 REG_GET_2(OTG_PIXEL_RATE_DIV, 65 OTG1_PIXEL_RATE_DIVK1, &val_k1, 66 OTG1_PIXEL_RATE_DIVK2, &val_k2); 67 break; 68 case 2: 69 REG_GET_2(OTG_PIXEL_RATE_DIV, 70 OTG2_PIXEL_RATE_DIVK1, &val_k1, 71 OTG2_PIXEL_RATE_DIVK2, &val_k2); 72 break; 73 case 3: 74 REG_GET_2(OTG_PIXEL_RATE_DIV, 75 OTG3_PIXEL_RATE_DIVK1, &val_k1, 76 OTG3_PIXEL_RATE_DIVK2, &val_k2); 77 break; 78 default: 79 BREAK_TO_DEBUGGER(); 80 return; 81 } 82 83 *k1 = (enum pixel_rate_div)val_k1; 84 *k2 = (enum pixel_rate_div)val_k2; 85 } 86 87 static void dccg32_set_pixel_rate_div( 88 struct dccg *dccg, 89 uint32_t otg_inst, 90 enum pixel_rate_div k1, 91 enum pixel_rate_div k2) 92 { 93 struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg); 94 95 enum pixel_rate_div cur_k1 = PIXEL_RATE_DIV_NA, cur_k2 = PIXEL_RATE_DIV_NA; 96 97 // Don't program 0xF into the register field. Not valid since 98 // K1 / K2 field is only 1 / 2 bits wide 99 if (k1 == PIXEL_RATE_DIV_NA || k2 == PIXEL_RATE_DIV_NA) 100 return; 101 102 dccg32_get_pixel_rate_div(dccg, otg_inst, &cur_k1, &cur_k2); 103 if (k1 == cur_k1 && k2 == cur_k2) 104 return; 105 106 switch (otg_inst) { 107 case 0: 108 REG_UPDATE_2(OTG_PIXEL_RATE_DIV, 109 OTG0_PIXEL_RATE_DIVK1, k1, 110 OTG0_PIXEL_RATE_DIVK2, k2); 111 break; 112 case 1: 113 REG_UPDATE_2(OTG_PIXEL_RATE_DIV, 114 OTG1_PIXEL_RATE_DIVK1, k1, 115 OTG1_PIXEL_RATE_DIVK2, k2); 116 break; 117 case 2: 118 REG_UPDATE_2(OTG_PIXEL_RATE_DIV, 119 OTG2_PIXEL_RATE_DIVK1, k1, 120 OTG2_PIXEL_RATE_DIVK2, k2); 121 break; 122 case 3: 123 REG_UPDATE_2(OTG_PIXEL_RATE_DIV, 124 OTG3_PIXEL_RATE_DIVK1, k1, 125 OTG3_PIXEL_RATE_DIVK2, k2); 126 break; 127 default: 128 BREAK_TO_DEBUGGER(); 129 return; 130 } 131 } 132 133 static void dccg32_set_dtbclk_p_src( 134 struct dccg *dccg, 135 enum streamclk_source src, 136 uint32_t otg_inst) 137 { 138 struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg); 139 140 uint32_t p_src_sel = 0; /* selects dprefclk */ 141 if (src == DTBCLK0) 142 p_src_sel = 2; /* selects dtbclk0 */ 143 144 switch (otg_inst) { 145 case 0: 146 if (src == REFCLK) 147 REG_UPDATE(DTBCLK_P_CNTL, 148 DTBCLK_P0_EN, 0); 149 else 150 REG_UPDATE_2(DTBCLK_P_CNTL, 151 DTBCLK_P0_SRC_SEL, p_src_sel, 152 DTBCLK_P0_EN, 1); 153 break; 154 case 1: 155 if (src == REFCLK) 156 REG_UPDATE(DTBCLK_P_CNTL, 157 DTBCLK_P1_EN, 0); 158 else 159 REG_UPDATE_2(DTBCLK_P_CNTL, 160 DTBCLK_P1_SRC_SEL, p_src_sel, 161 DTBCLK_P1_EN, 1); 162 break; 163 case 2: 164 if (src == REFCLK) 165 REG_UPDATE(DTBCLK_P_CNTL, 166 DTBCLK_P2_EN, 0); 167 else 168 REG_UPDATE_2(DTBCLK_P_CNTL, 169 DTBCLK_P2_SRC_SEL, p_src_sel, 170 DTBCLK_P2_EN, 1); 171 break; 172 case 3: 173 if (src == REFCLK) 174 REG_UPDATE(DTBCLK_P_CNTL, 175 DTBCLK_P3_EN, 0); 176 else 177 REG_UPDATE_2(DTBCLK_P_CNTL, 178 DTBCLK_P3_SRC_SEL, p_src_sel, 179 DTBCLK_P3_EN, 1); 180 break; 181 default: 182 BREAK_TO_DEBUGGER(); 183 return; 184 } 185 186 } 187 188 /* Controls the generation of pixel valid for OTG in (OTG -> HPO case) */ 189 static void dccg32_set_dtbclk_dto( 190 struct dccg *dccg, 191 const struct dtbclk_dto_params *params) 192 { 193 struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg); 194 /* DTO Output Rate / Pixel Rate = 1/4 */ 195 int req_dtbclk_khz = params->pixclk_khz / 4; 196 197 if (params->ref_dtbclk_khz && req_dtbclk_khz) { 198 uint32_t modulo, phase; 199 200 // phase / modulo = dtbclk / dtbclk ref 201 modulo = params->ref_dtbclk_khz * 1000; 202 phase = req_dtbclk_khz * 1000; 203 204 REG_WRITE(DTBCLK_DTO_MODULO[params->otg_inst], modulo); 205 REG_WRITE(DTBCLK_DTO_PHASE[params->otg_inst], phase); 206 207 REG_UPDATE(OTG_PIXEL_RATE_CNTL[params->otg_inst], 208 DTBCLK_DTO_ENABLE[params->otg_inst], 1); 209 210 REG_WAIT(OTG_PIXEL_RATE_CNTL[params->otg_inst], 211 DTBCLKDTO_ENABLE_STATUS[params->otg_inst], 1, 212 1, 100); 213 214 /* program OTG_PIXEL_RATE_DIV for DIVK1 and DIVK2 fields */ 215 dccg32_set_pixel_rate_div(dccg, params->otg_inst, PIXEL_RATE_DIV_BY_1, PIXEL_RATE_DIV_BY_1); 216 217 /* The recommended programming sequence to enable DTBCLK DTO to generate 218 * valid pixel HPO DPSTREAM ENCODER, specifies that DTO source select should 219 * be set only after DTO is enabled 220 */ 221 REG_UPDATE(OTG_PIXEL_RATE_CNTL[params->otg_inst], 222 PIPE_DTO_SRC_SEL[params->otg_inst], 2); 223 } else { 224 REG_UPDATE_2(OTG_PIXEL_RATE_CNTL[params->otg_inst], 225 DTBCLK_DTO_ENABLE[params->otg_inst], 0, 226 PIPE_DTO_SRC_SEL[params->otg_inst], 1); 227 if (params->is_hdmi) 228 REG_UPDATE(OTG_PIXEL_RATE_CNTL[params->otg_inst], 229 PIPE_DTO_SRC_SEL[params->otg_inst], 0); 230 231 REG_WRITE(DTBCLK_DTO_MODULO[params->otg_inst], 0); 232 REG_WRITE(DTBCLK_DTO_PHASE[params->otg_inst], 0); 233 } 234 } 235 236 static void dccg32_set_valid_pixel_rate( 237 struct dccg *dccg, 238 int ref_dtbclk_khz, 239 int otg_inst, 240 int pixclk_khz) 241 { 242 struct dtbclk_dto_params dto_params = {0}; 243 244 dto_params.ref_dtbclk_khz = ref_dtbclk_khz; 245 dto_params.otg_inst = otg_inst; 246 dto_params.pixclk_khz = pixclk_khz; 247 dto_params.is_hdmi = true; 248 249 dccg32_set_dtbclk_dto(dccg, &dto_params); 250 } 251 252 static void dccg32_get_dccg_ref_freq(struct dccg *dccg, 253 unsigned int xtalin_freq_inKhz, 254 unsigned int *dccg_ref_freq_inKhz) 255 { 256 /* 257 * Assume refclk is sourced from xtalin 258 * expect 100MHz 259 */ 260 *dccg_ref_freq_inKhz = xtalin_freq_inKhz; 261 return; 262 } 263 264 static void dccg32_set_dpstreamclk( 265 struct dccg *dccg, 266 enum streamclk_source src, 267 int otg_inst, 268 int dp_hpo_inst) 269 { 270 struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg); 271 272 /* set the dtbclk_p source */ 273 dccg32_set_dtbclk_p_src(dccg, src, otg_inst); 274 275 /* enabled to select one of the DTBCLKs for pipe */ 276 switch (otg_inst) 277 { 278 case 0: 279 REG_UPDATE_2(DPSTREAMCLK_CNTL, 280 DPSTREAMCLK0_EN, 281 (src == REFCLK) ? 0 : 1, DPSTREAMCLK0_SRC_SEL, otg_inst); 282 break; 283 case 1: 284 REG_UPDATE_2(DPSTREAMCLK_CNTL, DPSTREAMCLK1_EN, 285 (src == REFCLK) ? 0 : 1, DPSTREAMCLK1_SRC_SEL, otg_inst); 286 break; 287 case 2: 288 REG_UPDATE_2(DPSTREAMCLK_CNTL, DPSTREAMCLK2_EN, 289 (src == REFCLK) ? 0 : 1, DPSTREAMCLK2_SRC_SEL, otg_inst); 290 break; 291 case 3: 292 REG_UPDATE_2(DPSTREAMCLK_CNTL, DPSTREAMCLK3_EN, 293 (src == REFCLK) ? 0 : 1, DPSTREAMCLK3_SRC_SEL, otg_inst); 294 break; 295 default: 296 BREAK_TO_DEBUGGER(); 297 return; 298 } 299 } 300 301 static void dccg32_otg_add_pixel(struct dccg *dccg, 302 uint32_t otg_inst) 303 { 304 struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg); 305 306 REG_UPDATE(OTG_PIXEL_RATE_CNTL[otg_inst], 307 OTG_ADD_PIXEL[otg_inst], 1); 308 } 309 310 static void dccg32_otg_drop_pixel(struct dccg *dccg, 311 uint32_t otg_inst) 312 { 313 struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg); 314 315 REG_UPDATE(OTG_PIXEL_RATE_CNTL[otg_inst], 316 OTG_DROP_PIXEL[otg_inst], 1); 317 } 318 319 static const struct dccg_funcs dccg32_funcs = { 320 .update_dpp_dto = dccg2_update_dpp_dto, 321 .get_dccg_ref_freq = dccg32_get_dccg_ref_freq, 322 .dccg_init = dccg31_init, 323 .set_dpstreamclk = dccg32_set_dpstreamclk, 324 .enable_symclk32_se = dccg31_enable_symclk32_se, 325 .disable_symclk32_se = dccg31_disable_symclk32_se, 326 .enable_symclk32_le = dccg31_enable_symclk32_le, 327 .disable_symclk32_le = dccg31_disable_symclk32_le, 328 .set_physymclk = dccg31_set_physymclk, 329 .set_dtbclk_dto = dccg32_set_dtbclk_dto, 330 .set_valid_pixel_rate = dccg32_set_valid_pixel_rate, 331 .set_fifo_errdet_ovr_en = dccg2_set_fifo_errdet_ovr_en, 332 .set_audio_dtbclk_dto = dccg31_set_audio_dtbclk_dto, 333 .otg_add_pixel = dccg32_otg_add_pixel, 334 .otg_drop_pixel = dccg32_otg_drop_pixel, 335 .set_pixel_rate_div = dccg32_set_pixel_rate_div, 336 }; 337 338 struct dccg *dccg32_create( 339 struct dc_context *ctx, 340 const struct dccg_registers *regs, 341 const struct dccg_shift *dccg_shift, 342 const struct dccg_mask *dccg_mask) 343 { 344 struct dcn_dccg *dccg_dcn = kzalloc(sizeof(*dccg_dcn), GFP_KERNEL); 345 struct dccg *base; 346 347 if (dccg_dcn == NULL) { 348 BREAK_TO_DEBUGGER(); 349 return NULL; 350 } 351 352 base = &dccg_dcn->base; 353 base->ctx = ctx; 354 base->funcs = &dccg32_funcs; 355 356 dccg_dcn->regs = regs; 357 dccg_dcn->dccg_shift = dccg_shift; 358 dccg_dcn->dccg_mask = dccg_mask; 359 360 return &dccg_dcn->base; 361 } 362