1 /* 2 * Copyright 2021 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 27 #include "dm_services.h" 28 #include "dc.h" 29 30 #include "dcn31/dcn31_init.h" 31 32 #include "resource.h" 33 #include "include/irq_service_interface.h" 34 #include "dcn316_resource.h" 35 36 #include "dcn20/dcn20_resource.h" 37 #include "dcn30/dcn30_resource.h" 38 #include "dcn31/dcn31_resource.h" 39 40 #include "dcn10/dcn10_ipp.h" 41 #include "dcn30/dcn30_hubbub.h" 42 #include "dcn31/dcn31_hubbub.h" 43 #include "dcn30/dcn30_mpc.h" 44 #include "dcn31/dcn31_hubp.h" 45 #include "irq/dcn31/irq_service_dcn31.h" 46 #include "dcn30/dcn30_dpp.h" 47 #include "dcn31/dcn31_optc.h" 48 #include "dcn20/dcn20_hwseq.h" 49 #include "dcn30/dcn30_hwseq.h" 50 #include "dce110/dce110_hw_sequencer.h" 51 #include "dcn30/dcn30_opp.h" 52 #include "dcn20/dcn20_dsc.h" 53 #include "dcn30/dcn30_vpg.h" 54 #include "dcn30/dcn30_afmt.h" 55 #include "dcn30/dcn30_dio_stream_encoder.h" 56 #include "dcn31/dcn31_hpo_dp_stream_encoder.h" 57 #include "dcn31/dcn31_hpo_dp_link_encoder.h" 58 #include "dcn31/dcn31_apg.h" 59 #include "dcn31/dcn31_dio_link_encoder.h" 60 #include "dcn31/dcn31_vpg.h" 61 #include "dcn31/dcn31_afmt.h" 62 #include "dce/dce_clock_source.h" 63 #include "dce/dce_audio.h" 64 #include "dce/dce_hwseq.h" 65 #include "clk_mgr.h" 66 #include "virtual/virtual_stream_encoder.h" 67 #include "dce110/dce110_resource.h" 68 #include "dml/display_mode_vba.h" 69 #include "dcn31/dcn31_dccg.h" 70 #include "dcn10/dcn10_resource.h" 71 #include "dcn31/dcn31_panel_cntl.h" 72 73 #include "dcn30/dcn30_dwb.h" 74 #include "dcn30/dcn30_mmhubbub.h" 75 76 #include "dcn/dcn_3_1_6_offset.h" 77 #include "dcn/dcn_3_1_6_sh_mask.h" 78 #include "dpcs/dpcs_4_2_3_offset.h" 79 #include "dpcs/dpcs_4_2_3_sh_mask.h" 80 81 #define regBIF_BX1_BIOS_SCRATCH_2 0x003a 82 #define regBIF_BX1_BIOS_SCRATCH_2_BASE_IDX 1 83 #define regBIF_BX1_BIOS_SCRATCH_3 0x003b 84 #define regBIF_BX1_BIOS_SCRATCH_3_BASE_IDX 1 85 #define regBIF_BX1_BIOS_SCRATCH_6 0x003e 86 #define regBIF_BX1_BIOS_SCRATCH_6_BASE_IDX 1 87 88 #define regDCHUBBUB_DEBUG_CTRL_0 0x04d6 89 #define regDCHUBBUB_DEBUG_CTRL_0_BASE_IDX 2 90 #define DCHUBBUB_DEBUG_CTRL_0__DET_DEPTH__SHIFT 0x10 91 #define DCHUBBUB_DEBUG_CTRL_0__DET_DEPTH_MASK 0x01FF0000L 92 93 #define DCN_BASE__INST0_SEG0 0x00000012 94 #define DCN_BASE__INST0_SEG1 0x000000C0 95 #define DCN_BASE__INST0_SEG2 0x000034C0 96 #define DCN_BASE__INST0_SEG3 0x00009000 97 #define DCN_BASE__INST0_SEG4 0x02403C00 98 #define DCN_BASE__INST0_SEG5 0 99 100 #define DPCS_BASE__INST0_SEG0 0x00000012 101 #define DPCS_BASE__INST0_SEG1 0x000000C0 102 #define DPCS_BASE__INST0_SEG2 0x000034C0 103 #define DPCS_BASE__INST0_SEG3 0x00009000 104 #define DPCS_BASE__INST0_SEG4 0x02403C00 105 #define DPCS_BASE__INST0_SEG5 0 106 107 #define NBIO_BASE__INST0_SEG0 0x00000000 108 #define NBIO_BASE__INST0_SEG1 0x00000014 109 #define NBIO_BASE__INST0_SEG2 0x00000D20 110 #define NBIO_BASE__INST0_SEG3 0x00010400 111 #define NBIO_BASE__INST0_SEG4 0x0241B000 112 #define NBIO_BASE__INST0_SEG5 0x04040000 113 114 #include "reg_helper.h" 115 #include "dce/dmub_abm.h" 116 #include "dce/dmub_psr.h" 117 #include "dce/dce_aux.h" 118 #include "dce/dce_i2c.h" 119 120 #include "dml/dcn30/display_mode_vba_30.h" 121 #include "vm_helper.h" 122 #include "dcn20/dcn20_vmid.h" 123 124 #include "link_enc_cfg.h" 125 126 #define DC_LOGGER_INIT(logger) 127 128 #define DCN3_16_DEFAULT_DET_SIZE 192 129 #define DCN3_16_MAX_DET_SIZE 384 130 #define DCN3_16_MIN_COMPBUF_SIZE_KB 128 131 #define DCN3_16_CRB_SEGMENT_SIZE_KB 64 132 133 struct _vcs_dpi_ip_params_st dcn3_16_ip = { 134 .gpuvm_enable = 1, 135 .gpuvm_max_page_table_levels = 1, 136 .hostvm_enable = 1, 137 .hostvm_max_page_table_levels = 2, 138 .rob_buffer_size_kbytes = 64, 139 .det_buffer_size_kbytes = DCN3_16_DEFAULT_DET_SIZE, 140 .config_return_buffer_size_in_kbytes = 1024, 141 .compressed_buffer_segment_size_in_kbytes = 64, 142 .meta_fifo_size_in_kentries = 32, 143 .zero_size_buffer_entries = 512, 144 .compbuf_reserved_space_64b = 256, 145 .compbuf_reserved_space_zs = 64, 146 .dpp_output_buffer_pixels = 2560, 147 .opp_output_buffer_lines = 1, 148 .pixel_chunk_size_kbytes = 8, 149 .meta_chunk_size_kbytes = 2, 150 .min_meta_chunk_size_bytes = 256, 151 .writeback_chunk_size_kbytes = 8, 152 .ptoi_supported = false, 153 .num_dsc = 3, 154 .maximum_dsc_bits_per_component = 10, 155 .dsc422_native_support = false, 156 .is_line_buffer_bpp_fixed = true, 157 .line_buffer_fixed_bpp = 48, 158 .line_buffer_size_bits = 789504, 159 .max_line_buffer_lines = 12, 160 .writeback_interface_buffer_size_kbytes = 90, 161 .max_num_dpp = 4, 162 .max_num_otg = 4, 163 .max_num_hdmi_frl_outputs = 1, 164 .max_num_wb = 1, 165 .max_dchub_pscl_bw_pix_per_clk = 4, 166 .max_pscl_lb_bw_pix_per_clk = 2, 167 .max_lb_vscl_bw_pix_per_clk = 4, 168 .max_vscl_hscl_bw_pix_per_clk = 4, 169 .max_hscl_ratio = 6, 170 .max_vscl_ratio = 6, 171 .max_hscl_taps = 8, 172 .max_vscl_taps = 8, 173 .dpte_buffer_size_in_pte_reqs_luma = 64, 174 .dpte_buffer_size_in_pte_reqs_chroma = 34, 175 .dispclk_ramp_margin_percent = 1, 176 .max_inter_dcn_tile_repeaters = 8, 177 .cursor_buffer_size = 16, 178 .cursor_chunk_size = 2, 179 .writeback_line_buffer_buffer_size = 0, 180 .writeback_min_hscl_ratio = 1, 181 .writeback_min_vscl_ratio = 1, 182 .writeback_max_hscl_ratio = 1, 183 .writeback_max_vscl_ratio = 1, 184 .writeback_max_hscl_taps = 1, 185 .writeback_max_vscl_taps = 1, 186 .dppclk_delay_subtotal = 46, 187 .dppclk_delay_scl = 50, 188 .dppclk_delay_scl_lb_only = 16, 189 .dppclk_delay_cnvc_formatter = 27, 190 .dppclk_delay_cnvc_cursor = 6, 191 .dispclk_delay_subtotal = 119, 192 .dynamic_metadata_vm_enabled = false, 193 .odm_combine_4to1_supported = false, 194 .dcc_supported = true, 195 }; 196 197 struct _vcs_dpi_soc_bounding_box_st dcn3_16_soc = { 198 /*TODO: correct dispclk/dppclk voltage level determination*/ 199 .clock_limits = { 200 { 201 .state = 0, 202 .dispclk_mhz = 556.0, 203 .dppclk_mhz = 556.0, 204 .phyclk_mhz = 600.0, 205 .phyclk_d18_mhz = 445.0, 206 .dscclk_mhz = 186.0, 207 .dtbclk_mhz = 625.0, 208 }, 209 { 210 .state = 1, 211 .dispclk_mhz = 625.0, 212 .dppclk_mhz = 625.0, 213 .phyclk_mhz = 810.0, 214 .phyclk_d18_mhz = 667.0, 215 .dscclk_mhz = 209.0, 216 .dtbclk_mhz = 625.0, 217 }, 218 { 219 .state = 2, 220 .dispclk_mhz = 625.0, 221 .dppclk_mhz = 625.0, 222 .phyclk_mhz = 810.0, 223 .phyclk_d18_mhz = 667.0, 224 .dscclk_mhz = 209.0, 225 .dtbclk_mhz = 625.0, 226 }, 227 { 228 .state = 3, 229 .dispclk_mhz = 1112.0, 230 .dppclk_mhz = 1112.0, 231 .phyclk_mhz = 810.0, 232 .phyclk_d18_mhz = 667.0, 233 .dscclk_mhz = 371.0, 234 .dtbclk_mhz = 625.0, 235 }, 236 { 237 .state = 4, 238 .dispclk_mhz = 1250.0, 239 .dppclk_mhz = 1250.0, 240 .phyclk_mhz = 810.0, 241 .phyclk_d18_mhz = 667.0, 242 .dscclk_mhz = 417.0, 243 .dtbclk_mhz = 625.0, 244 }, 245 }, 246 .num_states = 5, 247 .sr_exit_time_us = 9.0, 248 .sr_enter_plus_exit_time_us = 11.0, 249 .sr_exit_z8_time_us = 442.0, 250 .sr_enter_plus_exit_z8_time_us = 560.0, 251 .writeback_latency_us = 12.0, 252 .dram_channel_width_bytes = 4, 253 .round_trip_ping_latency_dcfclk_cycles = 106, 254 .urgent_latency_pixel_data_only_us = 4.0, 255 .urgent_latency_pixel_mixed_with_vm_data_us = 4.0, 256 .urgent_latency_vm_data_only_us = 4.0, 257 .urgent_out_of_order_return_per_channel_pixel_only_bytes = 4096, 258 .urgent_out_of_order_return_per_channel_pixel_and_vm_bytes = 4096, 259 .urgent_out_of_order_return_per_channel_vm_only_bytes = 4096, 260 .pct_ideal_sdp_bw_after_urgent = 80.0, 261 .pct_ideal_dram_sdp_bw_after_urgent_pixel_only = 65.0, 262 .pct_ideal_dram_sdp_bw_after_urgent_pixel_and_vm = 60.0, 263 .pct_ideal_dram_sdp_bw_after_urgent_vm_only = 30.0, 264 .max_avg_sdp_bw_use_normal_percent = 60.0, 265 .max_avg_dram_bw_use_normal_percent = 60.0, 266 .fabric_datapath_to_dcn_data_return_bytes = 32, 267 .return_bus_width_bytes = 64, 268 .downspread_percent = 0.38, 269 .dcn_downspread_percent = 0.5, 270 .gpuvm_min_page_size_bytes = 4096, 271 .hostvm_min_page_size_bytes = 4096, 272 .do_urgent_latency_adjustment = false, 273 .urgent_latency_adjustment_fabric_clock_component_us = 0, 274 .urgent_latency_adjustment_fabric_clock_reference_mhz = 0, 275 }; 276 277 enum dcn31_clk_src_array_id { 278 DCN31_CLK_SRC_PLL0, 279 DCN31_CLK_SRC_PLL1, 280 DCN31_CLK_SRC_PLL2, 281 DCN31_CLK_SRC_PLL3, 282 DCN31_CLK_SRC_PLL4, 283 DCN30_CLK_SRC_TOTAL 284 }; 285 286 /* begin ********************* 287 * macros to expend register list macro defined in HW object header file 288 */ 289 290 /* DCN */ 291 /* TODO awful hack. fixup dcn20_dwb.h */ 292 #undef BASE_INNER 293 #define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg 294 295 #define BASE(seg) BASE_INNER(seg) 296 297 #define SR(reg_name)\ 298 .reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \ 299 reg ## reg_name 300 301 #define SRI(reg_name, block, id)\ 302 .reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 303 reg ## block ## id ## _ ## reg_name 304 305 #define SRI2(reg_name, block, id)\ 306 .reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \ 307 reg ## reg_name 308 309 #define SRIR(var_name, reg_name, block, id)\ 310 .var_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 311 reg ## block ## id ## _ ## reg_name 312 313 #define SRII(reg_name, block, id)\ 314 .reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 315 reg ## block ## id ## _ ## reg_name 316 317 #define SRII_MPC_RMU(reg_name, block, id)\ 318 .RMU##_##reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 319 reg ## block ## id ## _ ## reg_name 320 321 #define SRII_DWB(reg_name, temp_name, block, id)\ 322 .reg_name[id] = BASE(reg ## block ## id ## _ ## temp_name ## _BASE_IDX) + \ 323 reg ## block ## id ## _ ## temp_name 324 325 #define DCCG_SRII(reg_name, block, id)\ 326 .block ## _ ## reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 327 reg ## block ## id ## _ ## reg_name 328 329 #define VUPDATE_SRII(reg_name, block, id)\ 330 .reg_name[id] = BASE(reg ## reg_name ## _ ## block ## id ## _BASE_IDX) + \ 331 reg ## reg_name ## _ ## block ## id 332 333 /* NBIO */ 334 #define NBIO_BASE_INNER(seg) \ 335 NBIO_BASE__INST0_SEG ## seg 336 337 #define NBIO_BASE(seg) \ 338 NBIO_BASE_INNER(seg) 339 340 #define NBIO_SR(reg_name)\ 341 .reg_name = NBIO_BASE(regBIF_BX1_ ## reg_name ## _BASE_IDX) + \ 342 regBIF_BX1_ ## reg_name 343 344 static const struct bios_registers bios_regs = { 345 NBIO_SR(BIOS_SCRATCH_3), 346 NBIO_SR(BIOS_SCRATCH_6) 347 }; 348 349 #define clk_src_regs(index, pllid)\ 350 [index] = {\ 351 CS_COMMON_REG_LIST_DCN3_0(index, pllid),\ 352 } 353 354 static const struct dce110_clk_src_regs clk_src_regs[] = { 355 clk_src_regs(0, A), 356 clk_src_regs(1, B), 357 clk_src_regs(2, C), 358 clk_src_regs(3, D), 359 clk_src_regs(4, E) 360 }; 361 362 static const struct dce110_clk_src_shift cs_shift = { 363 CS_COMMON_MASK_SH_LIST_DCN2_0(__SHIFT) 364 }; 365 366 static const struct dce110_clk_src_mask cs_mask = { 367 CS_COMMON_MASK_SH_LIST_DCN2_0(_MASK) 368 }; 369 370 #define abm_regs(id)\ 371 [id] = {\ 372 ABM_DCN302_REG_LIST(id)\ 373 } 374 375 static const struct dce_abm_registers abm_regs[] = { 376 abm_regs(0), 377 abm_regs(1), 378 abm_regs(2), 379 abm_regs(3), 380 }; 381 382 static const struct dce_abm_shift abm_shift = { 383 ABM_MASK_SH_LIST_DCN30(__SHIFT) 384 }; 385 386 static const struct dce_abm_mask abm_mask = { 387 ABM_MASK_SH_LIST_DCN30(_MASK) 388 }; 389 390 #define audio_regs(id)\ 391 [id] = {\ 392 AUD_COMMON_REG_LIST(id)\ 393 } 394 395 static const struct dce_audio_registers audio_regs[] = { 396 audio_regs(0), 397 audio_regs(1), 398 audio_regs(2), 399 audio_regs(3), 400 audio_regs(4), 401 audio_regs(5), 402 audio_regs(6) 403 }; 404 405 #define DCE120_AUD_COMMON_MASK_SH_LIST(mask_sh)\ 406 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX, AZALIA_ENDPOINT_REG_INDEX, mask_sh),\ 407 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA, AZALIA_ENDPOINT_REG_DATA, mask_sh),\ 408 AUD_COMMON_MASK_SH_LIST_BASE(mask_sh) 409 410 static const struct dce_audio_shift audio_shift = { 411 DCE120_AUD_COMMON_MASK_SH_LIST(__SHIFT) 412 }; 413 414 static const struct dce_audio_mask audio_mask = { 415 DCE120_AUD_COMMON_MASK_SH_LIST(_MASK) 416 }; 417 418 #define vpg_regs(id)\ 419 [id] = {\ 420 VPG_DCN31_REG_LIST(id)\ 421 } 422 423 static const struct dcn31_vpg_registers vpg_regs[] = { 424 vpg_regs(0), 425 vpg_regs(1), 426 vpg_regs(2), 427 vpg_regs(3), 428 vpg_regs(4), 429 vpg_regs(5), 430 vpg_regs(6), 431 vpg_regs(7), 432 vpg_regs(8), 433 vpg_regs(9), 434 }; 435 436 static const struct dcn31_vpg_shift vpg_shift = { 437 DCN31_VPG_MASK_SH_LIST(__SHIFT) 438 }; 439 440 static const struct dcn31_vpg_mask vpg_mask = { 441 DCN31_VPG_MASK_SH_LIST(_MASK) 442 }; 443 444 #define afmt_regs(id)\ 445 [id] = {\ 446 AFMT_DCN31_REG_LIST(id)\ 447 } 448 449 static const struct dcn31_afmt_registers afmt_regs[] = { 450 afmt_regs(0), 451 afmt_regs(1), 452 afmt_regs(2), 453 afmt_regs(3), 454 afmt_regs(4), 455 afmt_regs(5) 456 }; 457 458 static const struct dcn31_afmt_shift afmt_shift = { 459 DCN31_AFMT_MASK_SH_LIST(__SHIFT) 460 }; 461 462 static const struct dcn31_afmt_mask afmt_mask = { 463 DCN31_AFMT_MASK_SH_LIST(_MASK) 464 }; 465 466 467 #define apg_regs(id)\ 468 [id] = {\ 469 APG_DCN31_REG_LIST(id)\ 470 } 471 472 static const struct dcn31_apg_registers apg_regs[] = { 473 apg_regs(0), 474 apg_regs(1), 475 apg_regs(2), 476 apg_regs(3) 477 }; 478 479 static const struct dcn31_apg_shift apg_shift = { 480 DCN31_APG_MASK_SH_LIST(__SHIFT) 481 }; 482 483 static const struct dcn31_apg_mask apg_mask = { 484 DCN31_APG_MASK_SH_LIST(_MASK) 485 }; 486 487 488 #define stream_enc_regs(id)\ 489 [id] = {\ 490 SE_DCN3_REG_LIST(id)\ 491 } 492 493 static const struct dcn10_stream_enc_registers stream_enc_regs[] = { 494 stream_enc_regs(0), 495 stream_enc_regs(1), 496 stream_enc_regs(2), 497 stream_enc_regs(3), 498 stream_enc_regs(4) 499 }; 500 501 static const struct dcn10_stream_encoder_shift se_shift = { 502 SE_COMMON_MASK_SH_LIST_DCN30(__SHIFT) 503 }; 504 505 static const struct dcn10_stream_encoder_mask se_mask = { 506 SE_COMMON_MASK_SH_LIST_DCN30(_MASK) 507 }; 508 509 510 #define aux_regs(id)\ 511 [id] = {\ 512 DCN2_AUX_REG_LIST(id)\ 513 } 514 515 static const struct dcn10_link_enc_aux_registers link_enc_aux_regs[] = { 516 aux_regs(0), 517 aux_regs(1), 518 aux_regs(2), 519 aux_regs(3), 520 aux_regs(4) 521 }; 522 523 #define hpd_regs(id)\ 524 [id] = {\ 525 HPD_REG_LIST(id)\ 526 } 527 528 static const struct dcn10_link_enc_hpd_registers link_enc_hpd_regs[] = { 529 hpd_regs(0), 530 hpd_regs(1), 531 hpd_regs(2), 532 hpd_regs(3), 533 hpd_regs(4) 534 }; 535 536 #define link_regs(id, phyid)\ 537 [id] = {\ 538 LE_DCN31_REG_LIST(id), \ 539 UNIPHY_DCN2_REG_LIST(phyid), \ 540 DPCS_DCN31_REG_LIST(id), \ 541 } 542 543 static const struct dce110_aux_registers_shift aux_shift = { 544 DCN_AUX_MASK_SH_LIST(__SHIFT) 545 }; 546 547 static const struct dce110_aux_registers_mask aux_mask = { 548 DCN_AUX_MASK_SH_LIST(_MASK) 549 }; 550 551 static const struct dcn10_link_enc_registers link_enc_regs[] = { 552 link_regs(0, A), 553 link_regs(1, B), 554 link_regs(2, C), 555 link_regs(3, D), 556 link_regs(4, E) 557 }; 558 559 static const struct dcn10_link_enc_shift le_shift = { 560 LINK_ENCODER_MASK_SH_LIST_DCN31(__SHIFT), \ 561 DPCS_DCN31_MASK_SH_LIST(__SHIFT) 562 }; 563 564 static const struct dcn10_link_enc_mask le_mask = { 565 LINK_ENCODER_MASK_SH_LIST_DCN31(_MASK), \ 566 DPCS_DCN31_MASK_SH_LIST(_MASK) 567 }; 568 569 570 571 #define hpo_dp_stream_encoder_reg_list(id)\ 572 [id] = {\ 573 DCN3_1_HPO_DP_STREAM_ENC_REG_LIST(id)\ 574 } 575 576 static const struct dcn31_hpo_dp_stream_encoder_registers hpo_dp_stream_enc_regs[] = { 577 hpo_dp_stream_encoder_reg_list(0), 578 hpo_dp_stream_encoder_reg_list(1), 579 hpo_dp_stream_encoder_reg_list(2), 580 hpo_dp_stream_encoder_reg_list(3), 581 }; 582 583 static const struct dcn31_hpo_dp_stream_encoder_shift hpo_dp_se_shift = { 584 DCN3_1_HPO_DP_STREAM_ENC_MASK_SH_LIST(__SHIFT) 585 }; 586 587 static const struct dcn31_hpo_dp_stream_encoder_mask hpo_dp_se_mask = { 588 DCN3_1_HPO_DP_STREAM_ENC_MASK_SH_LIST(_MASK) 589 }; 590 591 592 #define hpo_dp_link_encoder_reg_list(id)\ 593 [id] = {\ 594 DCN3_1_HPO_DP_LINK_ENC_REG_LIST(id),\ 595 DCN3_1_RDPCSTX_REG_LIST(0),\ 596 DCN3_1_RDPCSTX_REG_LIST(1),\ 597 DCN3_1_RDPCSTX_REG_LIST(2),\ 598 DCN3_1_RDPCSTX_REG_LIST(3),\ 599 DCN3_1_RDPCSTX_REG_LIST(4)\ 600 } 601 602 static const struct dcn31_hpo_dp_link_encoder_registers hpo_dp_link_enc_regs[] = { 603 hpo_dp_link_encoder_reg_list(0), 604 hpo_dp_link_encoder_reg_list(1), 605 }; 606 607 static const struct dcn31_hpo_dp_link_encoder_shift hpo_dp_le_shift = { 608 DCN3_1_HPO_DP_LINK_ENC_MASK_SH_LIST(__SHIFT) 609 }; 610 611 static const struct dcn31_hpo_dp_link_encoder_mask hpo_dp_le_mask = { 612 DCN3_1_HPO_DP_LINK_ENC_MASK_SH_LIST(_MASK) 613 }; 614 615 616 #define dpp_regs(id)\ 617 [id] = {\ 618 DPP_REG_LIST_DCN30(id),\ 619 } 620 621 static const struct dcn3_dpp_registers dpp_regs[] = { 622 dpp_regs(0), 623 dpp_regs(1), 624 dpp_regs(2), 625 dpp_regs(3) 626 }; 627 628 static const struct dcn3_dpp_shift tf_shift = { 629 DPP_REG_LIST_SH_MASK_DCN30(__SHIFT) 630 }; 631 632 static const struct dcn3_dpp_mask tf_mask = { 633 DPP_REG_LIST_SH_MASK_DCN30(_MASK) 634 }; 635 636 #define opp_regs(id)\ 637 [id] = {\ 638 OPP_REG_LIST_DCN30(id),\ 639 } 640 641 static const struct dcn20_opp_registers opp_regs[] = { 642 opp_regs(0), 643 opp_regs(1), 644 opp_regs(2), 645 opp_regs(3) 646 }; 647 648 static const struct dcn20_opp_shift opp_shift = { 649 OPP_MASK_SH_LIST_DCN20(__SHIFT) 650 }; 651 652 static const struct dcn20_opp_mask opp_mask = { 653 OPP_MASK_SH_LIST_DCN20(_MASK) 654 }; 655 656 #define aux_engine_regs(id)\ 657 [id] = {\ 658 AUX_COMMON_REG_LIST0(id), \ 659 .AUXN_IMPCAL = 0, \ 660 .AUXP_IMPCAL = 0, \ 661 .AUX_RESET_MASK = DP_AUX0_AUX_CONTROL__AUX_RESET_MASK, \ 662 } 663 664 static const struct dce110_aux_registers aux_engine_regs[] = { 665 aux_engine_regs(0), 666 aux_engine_regs(1), 667 aux_engine_regs(2), 668 aux_engine_regs(3), 669 aux_engine_regs(4) 670 }; 671 672 #define dwbc_regs_dcn3(id)\ 673 [id] = {\ 674 DWBC_COMMON_REG_LIST_DCN30(id),\ 675 } 676 677 static const struct dcn30_dwbc_registers dwbc30_regs[] = { 678 dwbc_regs_dcn3(0), 679 }; 680 681 static const struct dcn30_dwbc_shift dwbc30_shift = { 682 DWBC_COMMON_MASK_SH_LIST_DCN30(__SHIFT) 683 }; 684 685 static const struct dcn30_dwbc_mask dwbc30_mask = { 686 DWBC_COMMON_MASK_SH_LIST_DCN30(_MASK) 687 }; 688 689 #define mcif_wb_regs_dcn3(id)\ 690 [id] = {\ 691 MCIF_WB_COMMON_REG_LIST_DCN30(id),\ 692 } 693 694 static const struct dcn30_mmhubbub_registers mcif_wb30_regs[] = { 695 mcif_wb_regs_dcn3(0) 696 }; 697 698 static const struct dcn30_mmhubbub_shift mcif_wb30_shift = { 699 MCIF_WB_COMMON_MASK_SH_LIST_DCN30(__SHIFT) 700 }; 701 702 static const struct dcn30_mmhubbub_mask mcif_wb30_mask = { 703 MCIF_WB_COMMON_MASK_SH_LIST_DCN30(_MASK) 704 }; 705 706 #define dsc_regsDCN20(id)\ 707 [id] = {\ 708 DSC_REG_LIST_DCN20(id)\ 709 } 710 711 static const struct dcn20_dsc_registers dsc_regs[] = { 712 dsc_regsDCN20(0), 713 dsc_regsDCN20(1), 714 dsc_regsDCN20(2) 715 }; 716 717 static const struct dcn20_dsc_shift dsc_shift = { 718 DSC_REG_LIST_SH_MASK_DCN20(__SHIFT) 719 }; 720 721 static const struct dcn20_dsc_mask dsc_mask = { 722 DSC_REG_LIST_SH_MASK_DCN20(_MASK) 723 }; 724 725 static const struct dcn30_mpc_registers mpc_regs = { 726 MPC_REG_LIST_DCN3_0(0), 727 MPC_REG_LIST_DCN3_0(1), 728 MPC_REG_LIST_DCN3_0(2), 729 MPC_REG_LIST_DCN3_0(3), 730 MPC_OUT_MUX_REG_LIST_DCN3_0(0), 731 MPC_OUT_MUX_REG_LIST_DCN3_0(1), 732 MPC_OUT_MUX_REG_LIST_DCN3_0(2), 733 MPC_OUT_MUX_REG_LIST_DCN3_0(3), 734 MPC_RMU_GLOBAL_REG_LIST_DCN3AG, 735 MPC_RMU_REG_LIST_DCN3AG(0), 736 MPC_RMU_REG_LIST_DCN3AG(1), 737 //MPC_RMU_REG_LIST_DCN3AG(2), 738 MPC_DWB_MUX_REG_LIST_DCN3_0(0), 739 }; 740 741 static const struct dcn30_mpc_shift mpc_shift = { 742 MPC_COMMON_MASK_SH_LIST_DCN30(__SHIFT) 743 }; 744 745 static const struct dcn30_mpc_mask mpc_mask = { 746 MPC_COMMON_MASK_SH_LIST_DCN30(_MASK) 747 }; 748 749 #define optc_regs(id)\ 750 [id] = {OPTC_COMMON_REG_LIST_DCN3_1(id)} 751 752 static const struct dcn_optc_registers optc_regs[] = { 753 optc_regs(0), 754 optc_regs(1), 755 optc_regs(2), 756 optc_regs(3) 757 }; 758 759 static const struct dcn_optc_shift optc_shift = { 760 OPTC_COMMON_MASK_SH_LIST_DCN3_1(__SHIFT) 761 }; 762 763 static const struct dcn_optc_mask optc_mask = { 764 OPTC_COMMON_MASK_SH_LIST_DCN3_1(_MASK) 765 }; 766 767 #define hubp_regs(id)\ 768 [id] = {\ 769 HUBP_REG_LIST_DCN30(id)\ 770 } 771 772 static const struct dcn_hubp2_registers hubp_regs[] = { 773 hubp_regs(0), 774 hubp_regs(1), 775 hubp_regs(2), 776 hubp_regs(3) 777 }; 778 779 780 static const struct dcn_hubp2_shift hubp_shift = { 781 HUBP_MASK_SH_LIST_DCN31(__SHIFT) 782 }; 783 784 static const struct dcn_hubp2_mask hubp_mask = { 785 HUBP_MASK_SH_LIST_DCN31(_MASK) 786 }; 787 static const struct dcn_hubbub_registers hubbub_reg = { 788 HUBBUB_REG_LIST_DCN31(0) 789 }; 790 791 static const struct dcn_hubbub_shift hubbub_shift = { 792 HUBBUB_MASK_SH_LIST_DCN31(__SHIFT) 793 }; 794 795 static const struct dcn_hubbub_mask hubbub_mask = { 796 HUBBUB_MASK_SH_LIST_DCN31(_MASK) 797 }; 798 799 static const struct dccg_registers dccg_regs = { 800 DCCG_REG_LIST_DCN31() 801 }; 802 803 static const struct dccg_shift dccg_shift = { 804 DCCG_MASK_SH_LIST_DCN31(__SHIFT) 805 }; 806 807 static const struct dccg_mask dccg_mask = { 808 DCCG_MASK_SH_LIST_DCN31(_MASK) 809 }; 810 811 812 #define SRII2(reg_name_pre, reg_name_post, id)\ 813 .reg_name_pre ## _ ## reg_name_post[id] = BASE(reg ## reg_name_pre \ 814 ## id ## _ ## reg_name_post ## _BASE_IDX) + \ 815 reg ## reg_name_pre ## id ## _ ## reg_name_post 816 817 818 #define HWSEQ_DCN31_REG_LIST()\ 819 SR(DCHUBBUB_GLOBAL_TIMER_CNTL), \ 820 SR(DCHUBBUB_ARB_HOSTVM_CNTL), \ 821 SR(DIO_MEM_PWR_CTRL), \ 822 SR(ODM_MEM_PWR_CTRL3), \ 823 SR(DMU_MEM_PWR_CNTL), \ 824 SR(MMHUBBUB_MEM_PWR_CNTL), \ 825 SR(DCCG_GATE_DISABLE_CNTL), \ 826 SR(DCCG_GATE_DISABLE_CNTL2), \ 827 SR(DCFCLK_CNTL),\ 828 SR(DC_MEM_GLOBAL_PWR_REQ_CNTL), \ 829 SRII(PIXEL_RATE_CNTL, OTG, 0), \ 830 SRII(PIXEL_RATE_CNTL, OTG, 1),\ 831 SRII(PIXEL_RATE_CNTL, OTG, 2),\ 832 SRII(PIXEL_RATE_CNTL, OTG, 3),\ 833 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 0),\ 834 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 1),\ 835 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 2),\ 836 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 3),\ 837 SR(MICROSECOND_TIME_BASE_DIV), \ 838 SR(MILLISECOND_TIME_BASE_DIV), \ 839 SR(DISPCLK_FREQ_CHANGE_CNTL), \ 840 SR(RBBMIF_TIMEOUT_DIS), \ 841 SR(RBBMIF_TIMEOUT_DIS_2), \ 842 SR(DCHUBBUB_CRC_CTRL), \ 843 SR(DPP_TOP0_DPP_CRC_CTRL), \ 844 SR(DPP_TOP0_DPP_CRC_VAL_B_A), \ 845 SR(DPP_TOP0_DPP_CRC_VAL_R_G), \ 846 SR(MPC_CRC_CTRL), \ 847 SR(MPC_CRC_RESULT_GB), \ 848 SR(MPC_CRC_RESULT_C), \ 849 SR(MPC_CRC_RESULT_AR), \ 850 SR(DOMAIN0_PG_CONFIG), \ 851 SR(DOMAIN1_PG_CONFIG), \ 852 SR(DOMAIN2_PG_CONFIG), \ 853 SR(DOMAIN3_PG_CONFIG), \ 854 SR(DOMAIN16_PG_CONFIG), \ 855 SR(DOMAIN17_PG_CONFIG), \ 856 SR(DOMAIN18_PG_CONFIG), \ 857 SR(DOMAIN0_PG_STATUS), \ 858 SR(DOMAIN1_PG_STATUS), \ 859 SR(DOMAIN2_PG_STATUS), \ 860 SR(DOMAIN3_PG_STATUS), \ 861 SR(DOMAIN16_PG_STATUS), \ 862 SR(DOMAIN17_PG_STATUS), \ 863 SR(DOMAIN18_PG_STATUS), \ 864 SR(D1VGA_CONTROL), \ 865 SR(D2VGA_CONTROL), \ 866 SR(D3VGA_CONTROL), \ 867 SR(D4VGA_CONTROL), \ 868 SR(D5VGA_CONTROL), \ 869 SR(D6VGA_CONTROL), \ 870 SR(DC_IP_REQUEST_CNTL), \ 871 SR(AZALIA_AUDIO_DTO), \ 872 SR(AZALIA_CONTROLLER_CLOCK_GATING), \ 873 SR(HPO_TOP_HW_CONTROL) 874 875 static const struct dce_hwseq_registers hwseq_reg = { 876 HWSEQ_DCN31_REG_LIST() 877 }; 878 879 #define HWSEQ_DCN31_MASK_SH_LIST(mask_sh)\ 880 HWSEQ_DCN_MASK_SH_LIST(mask_sh), \ 881 HWS_SF(, DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_REFDIV, mask_sh), \ 882 HWS_SF(, DCHUBBUB_ARB_HOSTVM_CNTL, DISABLE_HOSTVM_FORCE_ALLOW_PSTATE, mask_sh), \ 883 HWS_SF(, DOMAIN0_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ 884 HWS_SF(, DOMAIN0_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ 885 HWS_SF(, DOMAIN1_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ 886 HWS_SF(, DOMAIN1_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ 887 HWS_SF(, DOMAIN2_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ 888 HWS_SF(, DOMAIN2_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ 889 HWS_SF(, DOMAIN3_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ 890 HWS_SF(, DOMAIN3_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ 891 HWS_SF(, DOMAIN16_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ 892 HWS_SF(, DOMAIN16_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ 893 HWS_SF(, DOMAIN17_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ 894 HWS_SF(, DOMAIN17_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ 895 HWS_SF(, DOMAIN18_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ 896 HWS_SF(, DOMAIN18_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ 897 HWS_SF(, DOMAIN0_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ 898 HWS_SF(, DOMAIN1_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ 899 HWS_SF(, DOMAIN2_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ 900 HWS_SF(, DOMAIN3_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ 901 HWS_SF(, DOMAIN16_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ 902 HWS_SF(, DOMAIN17_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ 903 HWS_SF(, DOMAIN18_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ 904 HWS_SF(, DC_IP_REQUEST_CNTL, IP_REQUEST_EN, mask_sh), \ 905 HWS_SF(, AZALIA_AUDIO_DTO, AZALIA_AUDIO_DTO_MODULE, mask_sh), \ 906 HWS_SF(, HPO_TOP_CLOCK_CONTROL, HPO_HDMISTREAMCLK_G_GATE_DIS, mask_sh), \ 907 HWS_SF(, DMU_MEM_PWR_CNTL, DMCU_ERAM_MEM_PWR_FORCE, mask_sh), \ 908 HWS_SF(, ODM_MEM_PWR_CTRL3, ODM_MEM_UNASSIGNED_PWR_MODE, mask_sh), \ 909 HWS_SF(, ODM_MEM_PWR_CTRL3, ODM_MEM_VBLANK_PWR_MODE, mask_sh), \ 910 HWS_SF(, MMHUBBUB_MEM_PWR_CNTL, VGA_MEM_PWR_FORCE, mask_sh), \ 911 HWS_SF(, DIO_MEM_PWR_CTRL, I2C_LIGHT_SLEEP_FORCE, mask_sh), \ 912 HWS_SF(, HPO_TOP_HW_CONTROL, HPO_IO_EN, mask_sh) 913 914 static const struct dce_hwseq_shift hwseq_shift = { 915 HWSEQ_DCN31_MASK_SH_LIST(__SHIFT) 916 }; 917 918 static const struct dce_hwseq_mask hwseq_mask = { 919 HWSEQ_DCN31_MASK_SH_LIST(_MASK) 920 }; 921 #define vmid_regs(id)\ 922 [id] = {\ 923 DCN20_VMID_REG_LIST(id)\ 924 } 925 926 static const struct dcn_vmid_registers vmid_regs[] = { 927 vmid_regs(0), 928 vmid_regs(1), 929 vmid_regs(2), 930 vmid_regs(3), 931 vmid_regs(4), 932 vmid_regs(5), 933 vmid_regs(6), 934 vmid_regs(7), 935 vmid_regs(8), 936 vmid_regs(9), 937 vmid_regs(10), 938 vmid_regs(11), 939 vmid_regs(12), 940 vmid_regs(13), 941 vmid_regs(14), 942 vmid_regs(15) 943 }; 944 945 static const struct dcn20_vmid_shift vmid_shifts = { 946 DCN20_VMID_MASK_SH_LIST(__SHIFT) 947 }; 948 949 static const struct dcn20_vmid_mask vmid_masks = { 950 DCN20_VMID_MASK_SH_LIST(_MASK) 951 }; 952 953 static const struct resource_caps res_cap_dcn31 = { 954 .num_timing_generator = 4, 955 .num_opp = 4, 956 .num_video_plane = 4, 957 .num_audio = 5, 958 .num_stream_encoder = 5, 959 .num_dig_link_enc = 5, 960 .num_hpo_dp_stream_encoder = 4, 961 .num_hpo_dp_link_encoder = 2, 962 .num_pll = 5, 963 .num_dwb = 1, 964 .num_ddc = 5, 965 .num_vmid = 16, 966 .num_mpc_3dlut = 2, 967 .num_dsc = 3, 968 }; 969 970 static const struct dc_plane_cap plane_cap = { 971 .type = DC_PLANE_TYPE_DCN_UNIVERSAL, 972 .blends_with_above = true, 973 .blends_with_below = true, 974 .per_pixel_alpha = true, 975 976 .pixel_format_support = { 977 .argb8888 = true, 978 .nv12 = true, 979 .fp16 = true, 980 .p010 = true, 981 .ayuv = false, 982 }, 983 984 .max_upscale_factor = { 985 .argb8888 = 16000, 986 .nv12 = 16000, 987 .fp16 = 16000 988 }, 989 990 // 6:1 downscaling ratio: 1000/6 = 166.666 991 .max_downscale_factor = { 992 .argb8888 = 167, 993 .nv12 = 167, 994 .fp16 = 167 995 }, 996 64, 997 64 998 }; 999 1000 static const struct dc_debug_options debug_defaults_drv = { 1001 .disable_z10 = true, /*hw not support it*/ 1002 .disable_dmcu = true, 1003 .force_abm_enable = false, 1004 .timing_trace = false, 1005 .clock_trace = true, 1006 .disable_pplib_clock_request = false, 1007 .pipe_split_policy = MPC_SPLIT_DYNAMIC, 1008 .force_single_disp_pipe_split = false, 1009 .disable_dcc = DCC_ENABLE, 1010 .vsr_support = true, 1011 .performance_trace = false, 1012 .max_downscale_src_width = 4096,/*upto true 4k*/ 1013 .disable_pplib_wm_range = false, 1014 .scl_reset_length10 = true, 1015 .sanity_checks = false, 1016 .underflow_assert_delay_us = 0xFFFFFFFF, 1017 .dwb_fi_phase = -1, // -1 = disable, 1018 .dmub_command_table = true, 1019 .pstate_enabled = true, 1020 .use_max_lb = true, 1021 .enable_mem_low_power = { 1022 .bits = { 1023 .vga = true, 1024 .i2c = true, 1025 .dmcu = false, // This is previously known to cause hang on S3 cycles if enabled 1026 .dscl = true, 1027 .cm = true, 1028 .mpc = true, 1029 .optc = true, 1030 .vpg = true, 1031 .afmt = true, 1032 } 1033 }, 1034 .optimize_edp_link_rate = true, 1035 .enable_sw_cntl_psr = true, 1036 }; 1037 1038 static const struct dc_debug_options debug_defaults_diags = { 1039 .disable_dmcu = true, 1040 .force_abm_enable = false, 1041 .timing_trace = true, 1042 .clock_trace = true, 1043 .disable_dpp_power_gate = true, 1044 .disable_hubp_power_gate = true, 1045 .disable_clock_gate = true, 1046 .disable_pplib_clock_request = true, 1047 .disable_pplib_wm_range = true, 1048 .disable_stutter = false, 1049 .scl_reset_length10 = true, 1050 .dwb_fi_phase = -1, // -1 = disable 1051 .dmub_command_table = true, 1052 .enable_tri_buf = true, 1053 .use_max_lb = true 1054 }; 1055 1056 static void dcn31_dpp_destroy(struct dpp **dpp) 1057 { 1058 kfree(TO_DCN20_DPP(*dpp)); 1059 *dpp = NULL; 1060 } 1061 1062 static struct dpp *dcn31_dpp_create( 1063 struct dc_context *ctx, 1064 uint32_t inst) 1065 { 1066 struct dcn3_dpp *dpp = 1067 kzalloc(sizeof(struct dcn3_dpp), GFP_KERNEL); 1068 1069 if (!dpp) 1070 return NULL; 1071 1072 if (dpp3_construct(dpp, ctx, inst, 1073 &dpp_regs[inst], &tf_shift, &tf_mask)) 1074 return &dpp->base; 1075 1076 BREAK_TO_DEBUGGER(); 1077 kfree(dpp); 1078 return NULL; 1079 } 1080 1081 static struct output_pixel_processor *dcn31_opp_create( 1082 struct dc_context *ctx, uint32_t inst) 1083 { 1084 struct dcn20_opp *opp = 1085 kzalloc(sizeof(struct dcn20_opp), GFP_KERNEL); 1086 1087 if (!opp) { 1088 BREAK_TO_DEBUGGER(); 1089 return NULL; 1090 } 1091 1092 dcn20_opp_construct(opp, ctx, inst, 1093 &opp_regs[inst], &opp_shift, &opp_mask); 1094 return &opp->base; 1095 } 1096 1097 static struct dce_aux *dcn31_aux_engine_create( 1098 struct dc_context *ctx, 1099 uint32_t inst) 1100 { 1101 struct aux_engine_dce110 *aux_engine = 1102 kzalloc(sizeof(struct aux_engine_dce110), GFP_KERNEL); 1103 1104 if (!aux_engine) 1105 return NULL; 1106 1107 dce110_aux_engine_construct(aux_engine, ctx, inst, 1108 SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD, 1109 &aux_engine_regs[inst], 1110 &aux_mask, 1111 &aux_shift, 1112 ctx->dc->caps.extended_aux_timeout_support); 1113 1114 return &aux_engine->base; 1115 } 1116 #define i2c_inst_regs(id) { I2C_HW_ENGINE_COMMON_REG_LIST_DCN30(id) } 1117 1118 static const struct dce_i2c_registers i2c_hw_regs[] = { 1119 i2c_inst_regs(1), 1120 i2c_inst_regs(2), 1121 i2c_inst_regs(3), 1122 i2c_inst_regs(4), 1123 i2c_inst_regs(5), 1124 }; 1125 1126 static const struct dce_i2c_shift i2c_shifts = { 1127 I2C_COMMON_MASK_SH_LIST_DCN30(__SHIFT) 1128 }; 1129 1130 static const struct dce_i2c_mask i2c_masks = { 1131 I2C_COMMON_MASK_SH_LIST_DCN30(_MASK) 1132 }; 1133 1134 static struct dce_i2c_hw *dcn31_i2c_hw_create( 1135 struct dc_context *ctx, 1136 uint32_t inst) 1137 { 1138 struct dce_i2c_hw *dce_i2c_hw = 1139 kzalloc(sizeof(struct dce_i2c_hw), GFP_KERNEL); 1140 1141 if (!dce_i2c_hw) 1142 return NULL; 1143 1144 dcn2_i2c_hw_construct(dce_i2c_hw, ctx, inst, 1145 &i2c_hw_regs[inst], &i2c_shifts, &i2c_masks); 1146 1147 return dce_i2c_hw; 1148 } 1149 static struct mpc *dcn31_mpc_create( 1150 struct dc_context *ctx, 1151 int num_mpcc, 1152 int num_rmu) 1153 { 1154 struct dcn30_mpc *mpc30 = kzalloc(sizeof(struct dcn30_mpc), 1155 GFP_KERNEL); 1156 1157 if (!mpc30) 1158 return NULL; 1159 1160 dcn30_mpc_construct(mpc30, ctx, 1161 &mpc_regs, 1162 &mpc_shift, 1163 &mpc_mask, 1164 num_mpcc, 1165 num_rmu); 1166 1167 return &mpc30->base; 1168 } 1169 1170 static struct hubbub *dcn31_hubbub_create(struct dc_context *ctx) 1171 { 1172 int i; 1173 1174 struct dcn20_hubbub *hubbub3 = kzalloc(sizeof(struct dcn20_hubbub), 1175 GFP_KERNEL); 1176 1177 if (!hubbub3) 1178 return NULL; 1179 1180 hubbub31_construct(hubbub3, ctx, 1181 &hubbub_reg, 1182 &hubbub_shift, 1183 &hubbub_mask, 1184 dcn3_16_ip.det_buffer_size_kbytes, 1185 dcn3_16_ip.pixel_chunk_size_kbytes, 1186 dcn3_16_ip.config_return_buffer_size_in_kbytes); 1187 1188 1189 for (i = 0; i < res_cap_dcn31.num_vmid; i++) { 1190 struct dcn20_vmid *vmid = &hubbub3->vmid[i]; 1191 1192 vmid->ctx = ctx; 1193 1194 vmid->regs = &vmid_regs[i]; 1195 vmid->shifts = &vmid_shifts; 1196 vmid->masks = &vmid_masks; 1197 } 1198 1199 return &hubbub3->base; 1200 } 1201 1202 static struct timing_generator *dcn31_timing_generator_create( 1203 struct dc_context *ctx, 1204 uint32_t instance) 1205 { 1206 struct optc *tgn10 = 1207 kzalloc(sizeof(struct optc), GFP_KERNEL); 1208 1209 if (!tgn10) 1210 return NULL; 1211 1212 tgn10->base.inst = instance; 1213 tgn10->base.ctx = ctx; 1214 1215 tgn10->tg_regs = &optc_regs[instance]; 1216 tgn10->tg_shift = &optc_shift; 1217 tgn10->tg_mask = &optc_mask; 1218 1219 dcn31_timing_generator_init(tgn10); 1220 1221 return &tgn10->base; 1222 } 1223 1224 static const struct encoder_feature_support link_enc_feature = { 1225 .max_hdmi_deep_color = COLOR_DEPTH_121212, 1226 .max_hdmi_pixel_clock = 600000, 1227 .hdmi_ycbcr420_supported = true, 1228 .dp_ycbcr420_supported = true, 1229 .fec_supported = true, 1230 .flags.bits.IS_HBR2_CAPABLE = true, 1231 .flags.bits.IS_HBR3_CAPABLE = true, 1232 .flags.bits.IS_TPS3_CAPABLE = true, 1233 .flags.bits.IS_TPS4_CAPABLE = true 1234 }; 1235 1236 static struct link_encoder *dcn31_link_encoder_create( 1237 const struct encoder_init_data *enc_init_data) 1238 { 1239 struct dcn20_link_encoder *enc20 = 1240 kzalloc(sizeof(struct dcn20_link_encoder), GFP_KERNEL); 1241 1242 if (!enc20) 1243 return NULL; 1244 1245 dcn31_link_encoder_construct(enc20, 1246 enc_init_data, 1247 &link_enc_feature, 1248 &link_enc_regs[enc_init_data->transmitter], 1249 &link_enc_aux_regs[enc_init_data->channel - 1], 1250 &link_enc_hpd_regs[enc_init_data->hpd_source], 1251 &le_shift, 1252 &le_mask); 1253 1254 return &enc20->enc10.base; 1255 } 1256 1257 /* Create a minimal link encoder object not associated with a particular 1258 * physical connector. 1259 * resource_funcs.link_enc_create_minimal 1260 */ 1261 static struct link_encoder *dcn31_link_enc_create_minimal( 1262 struct dc_context *ctx, enum engine_id eng_id) 1263 { 1264 struct dcn20_link_encoder *enc20; 1265 1266 if ((eng_id - ENGINE_ID_DIGA) > ctx->dc->res_pool->res_cap->num_dig_link_enc) 1267 return NULL; 1268 1269 enc20 = kzalloc(sizeof(struct dcn20_link_encoder), GFP_KERNEL); 1270 if (!enc20) 1271 return NULL; 1272 1273 dcn31_link_encoder_construct_minimal( 1274 enc20, 1275 ctx, 1276 &link_enc_feature, 1277 &link_enc_regs[eng_id - ENGINE_ID_DIGA], 1278 eng_id); 1279 1280 return &enc20->enc10.base; 1281 } 1282 1283 static struct panel_cntl *dcn31_panel_cntl_create(const struct panel_cntl_init_data *init_data) 1284 { 1285 struct dcn31_panel_cntl *panel_cntl = 1286 kzalloc(sizeof(struct dcn31_panel_cntl), GFP_KERNEL); 1287 1288 if (!panel_cntl) 1289 return NULL; 1290 1291 dcn31_panel_cntl_construct(panel_cntl, init_data); 1292 1293 return &panel_cntl->base; 1294 } 1295 1296 static void read_dce_straps( 1297 struct dc_context *ctx, 1298 struct resource_straps *straps) 1299 { 1300 generic_reg_get(ctx, regDC_PINSTRAPS + BASE(regDC_PINSTRAPS_BASE_IDX), 1301 FN(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO), &straps->dc_pinstraps_audio); 1302 1303 } 1304 1305 static struct audio *dcn31_create_audio( 1306 struct dc_context *ctx, unsigned int inst) 1307 { 1308 return dce_audio_create(ctx, inst, 1309 &audio_regs[inst], &audio_shift, &audio_mask); 1310 } 1311 1312 static struct vpg *dcn31_vpg_create( 1313 struct dc_context *ctx, 1314 uint32_t inst) 1315 { 1316 struct dcn31_vpg *vpg31 = kzalloc(sizeof(struct dcn31_vpg), GFP_KERNEL); 1317 1318 if (!vpg31) 1319 return NULL; 1320 1321 vpg31_construct(vpg31, ctx, inst, 1322 &vpg_regs[inst], 1323 &vpg_shift, 1324 &vpg_mask); 1325 1326 return &vpg31->base; 1327 } 1328 1329 static struct afmt *dcn31_afmt_create( 1330 struct dc_context *ctx, 1331 uint32_t inst) 1332 { 1333 struct dcn31_afmt *afmt31 = kzalloc(sizeof(struct dcn31_afmt), GFP_KERNEL); 1334 1335 if (!afmt31) 1336 return NULL; 1337 1338 afmt31_construct(afmt31, ctx, inst, 1339 &afmt_regs[inst], 1340 &afmt_shift, 1341 &afmt_mask); 1342 1343 // Light sleep by default, no need to power down here 1344 1345 return &afmt31->base; 1346 } 1347 1348 1349 static struct apg *dcn31_apg_create( 1350 struct dc_context *ctx, 1351 uint32_t inst) 1352 { 1353 struct dcn31_apg *apg31 = kzalloc(sizeof(struct dcn31_apg), GFP_KERNEL); 1354 1355 if (!apg31) 1356 return NULL; 1357 1358 apg31_construct(apg31, ctx, inst, 1359 &apg_regs[inst], 1360 &apg_shift, 1361 &apg_mask); 1362 1363 return &apg31->base; 1364 } 1365 1366 1367 static struct stream_encoder *dcn316_stream_encoder_create( 1368 enum engine_id eng_id, 1369 struct dc_context *ctx) 1370 { 1371 struct dcn10_stream_encoder *enc1; 1372 struct vpg *vpg; 1373 struct afmt *afmt; 1374 int vpg_inst; 1375 int afmt_inst; 1376 1377 /* Mapping of VPG, AFMT, DME register blocks to DIO block instance */ 1378 if (eng_id <= ENGINE_ID_DIGF) { 1379 vpg_inst = eng_id; 1380 afmt_inst = eng_id; 1381 } else 1382 return NULL; 1383 1384 enc1 = kzalloc(sizeof(struct dcn10_stream_encoder), GFP_KERNEL); 1385 vpg = dcn31_vpg_create(ctx, vpg_inst); 1386 afmt = dcn31_afmt_create(ctx, afmt_inst); 1387 1388 if (!enc1 || !vpg || !afmt) { 1389 kfree(enc1); 1390 kfree(vpg); 1391 kfree(afmt); 1392 return NULL; 1393 } 1394 1395 dcn30_dio_stream_encoder_construct(enc1, ctx, ctx->dc_bios, 1396 eng_id, vpg, afmt, 1397 &stream_enc_regs[eng_id], 1398 &se_shift, &se_mask); 1399 1400 return &enc1->base; 1401 } 1402 1403 1404 static struct hpo_dp_stream_encoder *dcn31_hpo_dp_stream_encoder_create( 1405 enum engine_id eng_id, 1406 struct dc_context *ctx) 1407 { 1408 struct dcn31_hpo_dp_stream_encoder *hpo_dp_enc31; 1409 struct vpg *vpg; 1410 struct apg *apg; 1411 uint32_t hpo_dp_inst; 1412 uint32_t vpg_inst; 1413 uint32_t apg_inst; 1414 1415 ASSERT((eng_id >= ENGINE_ID_HPO_DP_0) && (eng_id <= ENGINE_ID_HPO_DP_3)); 1416 hpo_dp_inst = eng_id - ENGINE_ID_HPO_DP_0; 1417 1418 /* Mapping of VPG register blocks to HPO DP block instance: 1419 * VPG[6] -> HPO_DP[0] 1420 * VPG[7] -> HPO_DP[1] 1421 * VPG[8] -> HPO_DP[2] 1422 * VPG[9] -> HPO_DP[3] 1423 */ 1424 vpg_inst = hpo_dp_inst + 6; 1425 1426 /* Mapping of APG register blocks to HPO DP block instance: 1427 * APG[0] -> HPO_DP[0] 1428 * APG[1] -> HPO_DP[1] 1429 * APG[2] -> HPO_DP[2] 1430 * APG[3] -> HPO_DP[3] 1431 */ 1432 apg_inst = hpo_dp_inst; 1433 1434 /* allocate HPO stream encoder and create VPG sub-block */ 1435 hpo_dp_enc31 = kzalloc(sizeof(struct dcn31_hpo_dp_stream_encoder), GFP_KERNEL); 1436 vpg = dcn31_vpg_create(ctx, vpg_inst); 1437 apg = dcn31_apg_create(ctx, apg_inst); 1438 1439 if (!hpo_dp_enc31 || !vpg || !apg) { 1440 kfree(hpo_dp_enc31); 1441 kfree(vpg); 1442 kfree(apg); 1443 return NULL; 1444 } 1445 1446 dcn31_hpo_dp_stream_encoder_construct(hpo_dp_enc31, ctx, ctx->dc_bios, 1447 hpo_dp_inst, eng_id, vpg, apg, 1448 &hpo_dp_stream_enc_regs[hpo_dp_inst], 1449 &hpo_dp_se_shift, &hpo_dp_se_mask); 1450 1451 return &hpo_dp_enc31->base; 1452 } 1453 1454 static struct hpo_dp_link_encoder *dcn31_hpo_dp_link_encoder_create( 1455 uint8_t inst, 1456 struct dc_context *ctx) 1457 { 1458 struct dcn31_hpo_dp_link_encoder *hpo_dp_enc31; 1459 1460 /* allocate HPO link encoder */ 1461 hpo_dp_enc31 = kzalloc(sizeof(struct dcn31_hpo_dp_link_encoder), GFP_KERNEL); 1462 1463 hpo_dp_link_encoder31_construct(hpo_dp_enc31, ctx, inst, 1464 &hpo_dp_link_enc_regs[inst], 1465 &hpo_dp_le_shift, &hpo_dp_le_mask); 1466 1467 return &hpo_dp_enc31->base; 1468 } 1469 1470 1471 static struct dce_hwseq *dcn31_hwseq_create( 1472 struct dc_context *ctx) 1473 { 1474 struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_KERNEL); 1475 1476 if (hws) { 1477 hws->ctx = ctx; 1478 hws->regs = &hwseq_reg; 1479 hws->shifts = &hwseq_shift; 1480 hws->masks = &hwseq_mask; 1481 /* DCN3.1 FPGA Workaround 1482 * Need to enable HPO DP Stream Encoder before setting OTG master enable. 1483 * To do so, move calling function enable_stream_timing to only be done AFTER calling 1484 * function core_link_enable_stream 1485 */ 1486 if (IS_FPGA_MAXIMUS_DC(ctx->dce_environment)) 1487 hws->wa.dp_hpo_and_otg_sequence = true; 1488 } 1489 return hws; 1490 } 1491 static const struct resource_create_funcs res_create_funcs = { 1492 .read_dce_straps = read_dce_straps, 1493 .create_audio = dcn31_create_audio, 1494 .create_stream_encoder = dcn316_stream_encoder_create, 1495 .create_hpo_dp_stream_encoder = dcn31_hpo_dp_stream_encoder_create, 1496 .create_hpo_dp_link_encoder = dcn31_hpo_dp_link_encoder_create, 1497 .create_hwseq = dcn31_hwseq_create, 1498 }; 1499 1500 static const struct resource_create_funcs res_create_maximus_funcs = { 1501 .read_dce_straps = NULL, 1502 .create_audio = NULL, 1503 .create_stream_encoder = NULL, 1504 .create_hpo_dp_stream_encoder = dcn31_hpo_dp_stream_encoder_create, 1505 .create_hpo_dp_link_encoder = dcn31_hpo_dp_link_encoder_create, 1506 .create_hwseq = dcn31_hwseq_create, 1507 }; 1508 1509 static void dcn316_resource_destruct(struct dcn316_resource_pool *pool) 1510 { 1511 unsigned int i; 1512 1513 for (i = 0; i < pool->base.stream_enc_count; i++) { 1514 if (pool->base.stream_enc[i] != NULL) { 1515 if (pool->base.stream_enc[i]->vpg != NULL) { 1516 kfree(DCN30_VPG_FROM_VPG(pool->base.stream_enc[i]->vpg)); 1517 pool->base.stream_enc[i]->vpg = NULL; 1518 } 1519 if (pool->base.stream_enc[i]->afmt != NULL) { 1520 kfree(DCN30_AFMT_FROM_AFMT(pool->base.stream_enc[i]->afmt)); 1521 pool->base.stream_enc[i]->afmt = NULL; 1522 } 1523 kfree(DCN10STRENC_FROM_STRENC(pool->base.stream_enc[i])); 1524 pool->base.stream_enc[i] = NULL; 1525 } 1526 } 1527 1528 for (i = 0; i < pool->base.hpo_dp_stream_enc_count; i++) { 1529 if (pool->base.hpo_dp_stream_enc[i] != NULL) { 1530 if (pool->base.hpo_dp_stream_enc[i]->vpg != NULL) { 1531 kfree(DCN30_VPG_FROM_VPG(pool->base.hpo_dp_stream_enc[i]->vpg)); 1532 pool->base.hpo_dp_stream_enc[i]->vpg = NULL; 1533 } 1534 if (pool->base.hpo_dp_stream_enc[i]->apg != NULL) { 1535 kfree(DCN31_APG_FROM_APG(pool->base.hpo_dp_stream_enc[i]->apg)); 1536 pool->base.hpo_dp_stream_enc[i]->apg = NULL; 1537 } 1538 kfree(DCN3_1_HPO_DP_STREAM_ENC_FROM_HPO_STREAM_ENC(pool->base.hpo_dp_stream_enc[i])); 1539 pool->base.hpo_dp_stream_enc[i] = NULL; 1540 } 1541 } 1542 1543 for (i = 0; i < pool->base.hpo_dp_link_enc_count; i++) { 1544 if (pool->base.hpo_dp_link_enc[i] != NULL) { 1545 kfree(DCN3_1_HPO_DP_LINK_ENC_FROM_HPO_LINK_ENC(pool->base.hpo_dp_link_enc[i])); 1546 pool->base.hpo_dp_link_enc[i] = NULL; 1547 } 1548 } 1549 1550 for (i = 0; i < pool->base.res_cap->num_dsc; i++) { 1551 if (pool->base.dscs[i] != NULL) 1552 dcn20_dsc_destroy(&pool->base.dscs[i]); 1553 } 1554 1555 if (pool->base.mpc != NULL) { 1556 kfree(TO_DCN20_MPC(pool->base.mpc)); 1557 pool->base.mpc = NULL; 1558 } 1559 if (pool->base.hubbub != NULL) { 1560 kfree(pool->base.hubbub); 1561 pool->base.hubbub = NULL; 1562 } 1563 for (i = 0; i < pool->base.pipe_count; i++) { 1564 if (pool->base.dpps[i] != NULL) 1565 dcn31_dpp_destroy(&pool->base.dpps[i]); 1566 1567 if (pool->base.ipps[i] != NULL) 1568 pool->base.ipps[i]->funcs->ipp_destroy(&pool->base.ipps[i]); 1569 1570 if (pool->base.hubps[i] != NULL) { 1571 kfree(TO_DCN20_HUBP(pool->base.hubps[i])); 1572 pool->base.hubps[i] = NULL; 1573 } 1574 1575 if (pool->base.irqs != NULL) { 1576 dal_irq_service_destroy(&pool->base.irqs); 1577 } 1578 } 1579 1580 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { 1581 if (pool->base.engines[i] != NULL) 1582 dce110_engine_destroy(&pool->base.engines[i]); 1583 if (pool->base.hw_i2cs[i] != NULL) { 1584 kfree(pool->base.hw_i2cs[i]); 1585 pool->base.hw_i2cs[i] = NULL; 1586 } 1587 if (pool->base.sw_i2cs[i] != NULL) { 1588 kfree(pool->base.sw_i2cs[i]); 1589 pool->base.sw_i2cs[i] = NULL; 1590 } 1591 } 1592 1593 for (i = 0; i < pool->base.res_cap->num_opp; i++) { 1594 if (pool->base.opps[i] != NULL) 1595 pool->base.opps[i]->funcs->opp_destroy(&pool->base.opps[i]); 1596 } 1597 1598 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { 1599 if (pool->base.timing_generators[i] != NULL) { 1600 kfree(DCN10TG_FROM_TG(pool->base.timing_generators[i])); 1601 pool->base.timing_generators[i] = NULL; 1602 } 1603 } 1604 1605 for (i = 0; i < pool->base.res_cap->num_dwb; i++) { 1606 if (pool->base.dwbc[i] != NULL) { 1607 kfree(TO_DCN30_DWBC(pool->base.dwbc[i])); 1608 pool->base.dwbc[i] = NULL; 1609 } 1610 if (pool->base.mcif_wb[i] != NULL) { 1611 kfree(TO_DCN30_MMHUBBUB(pool->base.mcif_wb[i])); 1612 pool->base.mcif_wb[i] = NULL; 1613 } 1614 } 1615 1616 for (i = 0; i < pool->base.audio_count; i++) { 1617 if (pool->base.audios[i]) 1618 dce_aud_destroy(&pool->base.audios[i]); 1619 } 1620 1621 for (i = 0; i < pool->base.clk_src_count; i++) { 1622 if (pool->base.clock_sources[i] != NULL) { 1623 dcn20_clock_source_destroy(&pool->base.clock_sources[i]); 1624 pool->base.clock_sources[i] = NULL; 1625 } 1626 } 1627 1628 for (i = 0; i < pool->base.res_cap->num_mpc_3dlut; i++) { 1629 if (pool->base.mpc_lut[i] != NULL) { 1630 dc_3dlut_func_release(pool->base.mpc_lut[i]); 1631 pool->base.mpc_lut[i] = NULL; 1632 } 1633 if (pool->base.mpc_shaper[i] != NULL) { 1634 dc_transfer_func_release(pool->base.mpc_shaper[i]); 1635 pool->base.mpc_shaper[i] = NULL; 1636 } 1637 } 1638 1639 if (pool->base.dp_clock_source != NULL) { 1640 dcn20_clock_source_destroy(&pool->base.dp_clock_source); 1641 pool->base.dp_clock_source = NULL; 1642 } 1643 1644 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { 1645 if (pool->base.multiple_abms[i] != NULL) 1646 dce_abm_destroy(&pool->base.multiple_abms[i]); 1647 } 1648 1649 if (pool->base.psr != NULL) 1650 dmub_psr_destroy(&pool->base.psr); 1651 1652 if (pool->base.dccg != NULL) 1653 dcn_dccg_destroy(&pool->base.dccg); 1654 } 1655 1656 static struct hubp *dcn31_hubp_create( 1657 struct dc_context *ctx, 1658 uint32_t inst) 1659 { 1660 struct dcn20_hubp *hubp2 = 1661 kzalloc(sizeof(struct dcn20_hubp), GFP_KERNEL); 1662 1663 if (!hubp2) 1664 return NULL; 1665 1666 if (hubp31_construct(hubp2, ctx, inst, 1667 &hubp_regs[inst], &hubp_shift, &hubp_mask)) 1668 return &hubp2->base; 1669 1670 BREAK_TO_DEBUGGER(); 1671 kfree(hubp2); 1672 return NULL; 1673 } 1674 1675 static bool dcn31_dwbc_create(struct dc_context *ctx, struct resource_pool *pool) 1676 { 1677 int i; 1678 uint32_t pipe_count = pool->res_cap->num_dwb; 1679 1680 for (i = 0; i < pipe_count; i++) { 1681 struct dcn30_dwbc *dwbc30 = kzalloc(sizeof(struct dcn30_dwbc), 1682 GFP_KERNEL); 1683 1684 if (!dwbc30) { 1685 dm_error("DC: failed to create dwbc30!\n"); 1686 return false; 1687 } 1688 1689 dcn30_dwbc_construct(dwbc30, ctx, 1690 &dwbc30_regs[i], 1691 &dwbc30_shift, 1692 &dwbc30_mask, 1693 i); 1694 1695 pool->dwbc[i] = &dwbc30->base; 1696 } 1697 return true; 1698 } 1699 1700 static bool dcn31_mmhubbub_create(struct dc_context *ctx, struct resource_pool *pool) 1701 { 1702 int i; 1703 uint32_t pipe_count = pool->res_cap->num_dwb; 1704 1705 for (i = 0; i < pipe_count; i++) { 1706 struct dcn30_mmhubbub *mcif_wb30 = kzalloc(sizeof(struct dcn30_mmhubbub), 1707 GFP_KERNEL); 1708 1709 if (!mcif_wb30) { 1710 dm_error("DC: failed to create mcif_wb30!\n"); 1711 return false; 1712 } 1713 1714 dcn30_mmhubbub_construct(mcif_wb30, ctx, 1715 &mcif_wb30_regs[i], 1716 &mcif_wb30_shift, 1717 &mcif_wb30_mask, 1718 i); 1719 1720 pool->mcif_wb[i] = &mcif_wb30->base; 1721 } 1722 return true; 1723 } 1724 1725 static struct display_stream_compressor *dcn31_dsc_create( 1726 struct dc_context *ctx, uint32_t inst) 1727 { 1728 struct dcn20_dsc *dsc = 1729 kzalloc(sizeof(struct dcn20_dsc), GFP_KERNEL); 1730 1731 if (!dsc) { 1732 BREAK_TO_DEBUGGER(); 1733 return NULL; 1734 } 1735 1736 dsc2_construct(dsc, ctx, inst, &dsc_regs[inst], &dsc_shift, &dsc_mask); 1737 return &dsc->base; 1738 } 1739 1740 static void dcn316_destroy_resource_pool(struct resource_pool **pool) 1741 { 1742 struct dcn316_resource_pool *dcn31_pool = TO_DCN316_RES_POOL(*pool); 1743 1744 dcn316_resource_destruct(dcn31_pool); 1745 kfree(dcn31_pool); 1746 *pool = NULL; 1747 } 1748 1749 static struct clock_source *dcn31_clock_source_create( 1750 struct dc_context *ctx, 1751 struct dc_bios *bios, 1752 enum clock_source_id id, 1753 const struct dce110_clk_src_regs *regs, 1754 bool dp_clk_src) 1755 { 1756 struct dce110_clk_src *clk_src = 1757 kzalloc(sizeof(struct dce110_clk_src), GFP_KERNEL); 1758 1759 if (!clk_src) 1760 return NULL; 1761 1762 if (dcn31_clk_src_construct(clk_src, ctx, bios, id, 1763 regs, &cs_shift, &cs_mask)) { 1764 clk_src->base.dp_clk_src = dp_clk_src; 1765 return &clk_src->base; 1766 } 1767 1768 kfree(clk_src); 1769 1770 BREAK_TO_DEBUGGER(); 1771 return NULL; 1772 } 1773 1774 static bool is_dual_plane(enum surface_pixel_format format) 1775 { 1776 return format >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN || format == SURFACE_PIXEL_FORMAT_GRPH_RGBE_ALPHA; 1777 } 1778 1779 static int dcn316_populate_dml_pipes_from_context( 1780 struct dc *dc, struct dc_state *context, 1781 display_e2e_pipe_params_st *pipes, 1782 bool fast_validate) 1783 { 1784 int i, pipe_cnt; 1785 struct resource_context *res_ctx = &context->res_ctx; 1786 struct pipe_ctx *pipe; 1787 const int max_usable_det = context->bw_ctx.dml.ip.config_return_buffer_size_in_kbytes - DCN3_16_MIN_COMPBUF_SIZE_KB; 1788 1789 DC_FP_START(); 1790 dcn20_populate_dml_pipes_from_context(dc, context, pipes, fast_validate); 1791 DC_FP_END(); 1792 1793 for (i = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) { 1794 struct dc_crtc_timing *timing; 1795 1796 if (!res_ctx->pipe_ctx[i].stream) 1797 continue; 1798 pipe = &res_ctx->pipe_ctx[i]; 1799 timing = &pipe->stream->timing; 1800 1801 /* 1802 * Immediate flip can be set dynamically after enabling the plane. 1803 * We need to require support for immediate flip or underflow can be 1804 * intermittently experienced depending on peak b/w requirements. 1805 */ 1806 pipes[pipe_cnt].pipe.src.immediate_flip = true; 1807 1808 pipes[pipe_cnt].pipe.src.unbounded_req_mode = false; 1809 pipes[pipe_cnt].pipe.src.gpuvm = true; 1810 pipes[pipe_cnt].pipe.src.dcc_fraction_of_zs_req_luma = 0; 1811 pipes[pipe_cnt].pipe.src.dcc_fraction_of_zs_req_chroma = 0; 1812 pipes[pipe_cnt].pipe.dest.vfront_porch = timing->v_front_porch; 1813 pipes[pipe_cnt].pipe.src.dcc_rate = 3; 1814 pipes[pipe_cnt].dout.dsc_input_bpc = 0; 1815 1816 if (pipes[pipe_cnt].dout.dsc_enable) { 1817 switch (timing->display_color_depth) { 1818 case COLOR_DEPTH_888: 1819 pipes[pipe_cnt].dout.dsc_input_bpc = 8; 1820 break; 1821 case COLOR_DEPTH_101010: 1822 pipes[pipe_cnt].dout.dsc_input_bpc = 10; 1823 break; 1824 case COLOR_DEPTH_121212: 1825 pipes[pipe_cnt].dout.dsc_input_bpc = 12; 1826 break; 1827 default: 1828 ASSERT(0); 1829 break; 1830 } 1831 } 1832 1833 pipe_cnt++; 1834 } 1835 1836 if (pipe_cnt) 1837 context->bw_ctx.dml.ip.det_buffer_size_kbytes = 1838 (max_usable_det / DCN3_16_CRB_SEGMENT_SIZE_KB / pipe_cnt) * DCN3_16_CRB_SEGMENT_SIZE_KB; 1839 if (context->bw_ctx.dml.ip.det_buffer_size_kbytes > DCN3_16_MAX_DET_SIZE) 1840 context->bw_ctx.dml.ip.det_buffer_size_kbytes = DCN3_16_MAX_DET_SIZE; 1841 ASSERT(context->bw_ctx.dml.ip.det_buffer_size_kbytes >= DCN3_16_DEFAULT_DET_SIZE); 1842 dc->config.enable_4to1MPC = false; 1843 if (pipe_cnt == 1 && pipe->plane_state && !dc->debug.disable_z9_mpc) { 1844 if (is_dual_plane(pipe->plane_state->format) 1845 && pipe->plane_state->src_rect.width <= 1920 && pipe->plane_state->src_rect.height <= 1080) { 1846 dc->config.enable_4to1MPC = true; 1847 context->bw_ctx.dml.ip.det_buffer_size_kbytes = 1848 (max_usable_det / DCN3_16_CRB_SEGMENT_SIZE_KB / 4) * DCN3_16_CRB_SEGMENT_SIZE_KB; 1849 } else if (!is_dual_plane(pipe->plane_state->format)) { 1850 context->bw_ctx.dml.ip.det_buffer_size_kbytes = 192; 1851 pipes[0].pipe.src.unbounded_req_mode = true; 1852 } 1853 } 1854 1855 return pipe_cnt; 1856 } 1857 1858 static struct dc_cap_funcs cap_funcs = { 1859 .get_dcc_compression_cap = dcn20_get_dcc_compression_cap 1860 }; 1861 1862 static void dcn316_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params) 1863 { 1864 struct clk_limit_table *clk_table = &bw_params->clk_table; 1865 struct _vcs_dpi_voltage_scaling_st clock_limits[DC__VOLTAGE_STATES]; 1866 unsigned int i, closest_clk_lvl; 1867 int max_dispclk_mhz = 0, max_dppclk_mhz = 0; 1868 int j; 1869 1870 // Default clock levels are used for diags, which may lead to overclocking. 1871 if (!IS_DIAG_DC(dc->ctx->dce_environment)) { 1872 1873 dcn3_16_ip.max_num_otg = dc->res_pool->res_cap->num_timing_generator; 1874 dcn3_16_ip.max_num_dpp = dc->res_pool->pipe_count; 1875 dcn3_16_soc.num_chans = bw_params->num_channels; 1876 1877 ASSERT(clk_table->num_entries); 1878 1879 /* Prepass to find max clocks independent of voltage level. */ 1880 for (i = 0; i < clk_table->num_entries; ++i) { 1881 if (clk_table->entries[i].dispclk_mhz > max_dispclk_mhz) 1882 max_dispclk_mhz = clk_table->entries[i].dispclk_mhz; 1883 if (clk_table->entries[i].dppclk_mhz > max_dppclk_mhz) 1884 max_dppclk_mhz = clk_table->entries[i].dppclk_mhz; 1885 } 1886 1887 for (i = 0; i < clk_table->num_entries; i++) { 1888 /* loop backwards*/ 1889 for (closest_clk_lvl = 0, j = dcn3_16_soc.num_states - 1; j >= 0; j--) { 1890 if ((unsigned int) dcn3_16_soc.clock_limits[j].dcfclk_mhz <= clk_table->entries[i].dcfclk_mhz) { 1891 closest_clk_lvl = j; 1892 break; 1893 } 1894 } 1895 // Ported from DCN315 1896 if (clk_table->num_entries == 1) { 1897 /*smu gives one DPM level, let's take the highest one*/ 1898 closest_clk_lvl = dcn3_16_soc.num_states - 1; 1899 } 1900 1901 clock_limits[i].state = i; 1902 1903 /* Clocks dependent on voltage level. */ 1904 clock_limits[i].dcfclk_mhz = clk_table->entries[i].dcfclk_mhz; 1905 if (clk_table->num_entries == 1 && 1906 clock_limits[i].dcfclk_mhz < dcn3_16_soc.clock_limits[closest_clk_lvl].dcfclk_mhz) { 1907 /*SMU fix not released yet*/ 1908 clock_limits[i].dcfclk_mhz = dcn3_16_soc.clock_limits[closest_clk_lvl].dcfclk_mhz; 1909 } 1910 clock_limits[i].fabricclk_mhz = clk_table->entries[i].fclk_mhz; 1911 clock_limits[i].socclk_mhz = clk_table->entries[i].socclk_mhz; 1912 clock_limits[i].dram_speed_mts = clk_table->entries[i].memclk_mhz * 2 * clk_table->entries[i].wck_ratio; 1913 1914 /* Clocks independent of voltage level. */ 1915 clock_limits[i].dispclk_mhz = max_dispclk_mhz ? max_dispclk_mhz : 1916 dcn3_16_soc.clock_limits[closest_clk_lvl].dispclk_mhz; 1917 1918 clock_limits[i].dppclk_mhz = max_dppclk_mhz ? max_dppclk_mhz : 1919 dcn3_16_soc.clock_limits[closest_clk_lvl].dppclk_mhz; 1920 1921 clock_limits[i].dram_bw_per_chan_gbps = dcn3_16_soc.clock_limits[closest_clk_lvl].dram_bw_per_chan_gbps; 1922 clock_limits[i].dscclk_mhz = dcn3_16_soc.clock_limits[closest_clk_lvl].dscclk_mhz; 1923 clock_limits[i].dtbclk_mhz = dcn3_16_soc.clock_limits[closest_clk_lvl].dtbclk_mhz; 1924 clock_limits[i].phyclk_d18_mhz = dcn3_16_soc.clock_limits[closest_clk_lvl].phyclk_d18_mhz; 1925 clock_limits[i].phyclk_mhz = dcn3_16_soc.clock_limits[closest_clk_lvl].phyclk_mhz; 1926 } 1927 for (i = 0; i < clk_table->num_entries; i++) 1928 dcn3_16_soc.clock_limits[i] = clock_limits[i]; 1929 if (clk_table->num_entries) { 1930 dcn3_16_soc.num_states = clk_table->num_entries; 1931 } 1932 } 1933 1934 if (max_dispclk_mhz) { 1935 dcn3_16_soc.dispclk_dppclk_vco_speed_mhz = max_dispclk_mhz * 2; 1936 dc->dml.soc.dispclk_dppclk_vco_speed_mhz = max_dispclk_mhz * 2; 1937 } 1938 1939 if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) 1940 dml_init_instance(&dc->dml, &dcn3_16_soc, &dcn3_16_ip, DML_PROJECT_DCN31); 1941 else 1942 dml_init_instance(&dc->dml, &dcn3_16_soc, &dcn3_16_ip, DML_PROJECT_DCN31_FPGA); 1943 } 1944 1945 static struct resource_funcs dcn316_res_pool_funcs = { 1946 .destroy = dcn316_destroy_resource_pool, 1947 .link_enc_create = dcn31_link_encoder_create, 1948 .link_enc_create_minimal = dcn31_link_enc_create_minimal, 1949 .link_encs_assign = link_enc_cfg_link_encs_assign, 1950 .link_enc_unassign = link_enc_cfg_link_enc_unassign, 1951 .panel_cntl_create = dcn31_panel_cntl_create, 1952 .validate_bandwidth = dcn31_validate_bandwidth, 1953 .calculate_wm_and_dlg = dcn31_calculate_wm_and_dlg, 1954 .update_soc_for_wm_a = dcn31_update_soc_for_wm_a, 1955 .populate_dml_pipes = dcn316_populate_dml_pipes_from_context, 1956 .acquire_idle_pipe_for_layer = dcn20_acquire_idle_pipe_for_layer, 1957 .add_stream_to_ctx = dcn30_add_stream_to_ctx, 1958 .add_dsc_to_stream_resource = dcn20_add_dsc_to_stream_resource, 1959 .remove_stream_from_ctx = dcn20_remove_stream_from_ctx, 1960 .populate_dml_writeback_from_context = dcn30_populate_dml_writeback_from_context, 1961 .set_mcif_arb_params = dcn30_set_mcif_arb_params, 1962 .find_first_free_match_stream_enc_for_link = dcn10_find_first_free_match_stream_enc_for_link, 1963 .acquire_post_bldn_3dlut = dcn30_acquire_post_bldn_3dlut, 1964 .release_post_bldn_3dlut = dcn30_release_post_bldn_3dlut, 1965 .update_bw_bounding_box = dcn316_update_bw_bounding_box, 1966 .patch_unknown_plane_state = dcn20_patch_unknown_plane_state, 1967 }; 1968 1969 static bool dcn316_resource_construct( 1970 uint8_t num_virtual_links, 1971 struct dc *dc, 1972 struct dcn316_resource_pool *pool) 1973 { 1974 int i; 1975 struct dc_context *ctx = dc->ctx; 1976 struct irq_service_init_data init_data; 1977 1978 ctx->dc_bios->regs = &bios_regs; 1979 1980 pool->base.res_cap = &res_cap_dcn31; 1981 1982 pool->base.funcs = &dcn316_res_pool_funcs; 1983 1984 /************************************************* 1985 * Resource + asic cap harcoding * 1986 *************************************************/ 1987 pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE; 1988 pool->base.pipe_count = pool->base.res_cap->num_timing_generator; 1989 pool->base.mpcc_count = pool->base.res_cap->num_timing_generator; 1990 dc->caps.max_downscale_ratio = 600; 1991 dc->caps.i2c_speed_in_khz = 100; 1992 dc->caps.i2c_speed_in_khz_hdcp = 5; /*1.4 w/a applied by default*/ 1993 dc->caps.max_cursor_size = 256; 1994 dc->caps.min_horizontal_blanking_period = 80; 1995 dc->caps.dmdata_alloc_size = 2048; 1996 1997 dc->caps.max_slave_planes = 1; 1998 dc->caps.max_slave_yuv_planes = 1; 1999 dc->caps.max_slave_rgb_planes = 1; 2000 dc->caps.post_blend_color_processing = true; 2001 dc->caps.force_dp_tps4_for_cp2520 = true; 2002 dc->caps.dp_hpo = true; 2003 dc->caps.edp_dsc_support = true; 2004 dc->caps.extended_aux_timeout_support = true; 2005 dc->caps.dmcub_support = true; 2006 dc->caps.is_apu = true; 2007 2008 /* Color pipeline capabilities */ 2009 dc->caps.color.dpp.dcn_arch = 1; 2010 dc->caps.color.dpp.input_lut_shared = 0; 2011 dc->caps.color.dpp.icsc = 1; 2012 dc->caps.color.dpp.dgam_ram = 0; // must use gamma_corr 2013 dc->caps.color.dpp.dgam_rom_caps.srgb = 1; 2014 dc->caps.color.dpp.dgam_rom_caps.bt2020 = 1; 2015 dc->caps.color.dpp.dgam_rom_caps.gamma2_2 = 1; 2016 dc->caps.color.dpp.dgam_rom_caps.pq = 1; 2017 dc->caps.color.dpp.dgam_rom_caps.hlg = 1; 2018 dc->caps.color.dpp.post_csc = 1; 2019 dc->caps.color.dpp.gamma_corr = 1; 2020 dc->caps.color.dpp.dgam_rom_for_yuv = 0; 2021 2022 dc->caps.color.dpp.hw_3d_lut = 1; 2023 dc->caps.color.dpp.ogam_ram = 1; 2024 // no OGAM ROM on DCN301 2025 dc->caps.color.dpp.ogam_rom_caps.srgb = 0; 2026 dc->caps.color.dpp.ogam_rom_caps.bt2020 = 0; 2027 dc->caps.color.dpp.ogam_rom_caps.gamma2_2 = 0; 2028 dc->caps.color.dpp.ogam_rom_caps.pq = 0; 2029 dc->caps.color.dpp.ogam_rom_caps.hlg = 0; 2030 dc->caps.color.dpp.ocsc = 0; 2031 2032 dc->caps.color.mpc.gamut_remap = 1; 2033 dc->caps.color.mpc.num_3dluts = pool->base.res_cap->num_mpc_3dlut; //2 2034 dc->caps.color.mpc.ogam_ram = 1; 2035 dc->caps.color.mpc.ogam_rom_caps.srgb = 0; 2036 dc->caps.color.mpc.ogam_rom_caps.bt2020 = 0; 2037 dc->caps.color.mpc.ogam_rom_caps.gamma2_2 = 0; 2038 dc->caps.color.mpc.ogam_rom_caps.pq = 0; 2039 dc->caps.color.mpc.ogam_rom_caps.hlg = 0; 2040 dc->caps.color.mpc.ocsc = 1; 2041 2042 /* read VBIOS LTTPR caps */ 2043 { 2044 if (ctx->dc_bios->funcs->get_lttpr_caps) { 2045 enum bp_result bp_query_result; 2046 uint8_t is_vbios_lttpr_enable = 0; 2047 2048 bp_query_result = ctx->dc_bios->funcs->get_lttpr_caps(ctx->dc_bios, &is_vbios_lttpr_enable); 2049 dc->caps.vbios_lttpr_enable = (bp_query_result == BP_RESULT_OK) && !!is_vbios_lttpr_enable; 2050 } 2051 2052 /* interop bit is implicit */ 2053 { 2054 dc->caps.vbios_lttpr_aware = true; 2055 } 2056 } 2057 2058 if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV) 2059 dc->debug = debug_defaults_drv; 2060 else if (dc->ctx->dce_environment == DCE_ENV_FPGA_MAXIMUS) { 2061 dc->debug = debug_defaults_diags; 2062 } else 2063 dc->debug = debug_defaults_diags; 2064 // Init the vm_helper 2065 if (dc->vm_helper) 2066 vm_helper_init(dc->vm_helper, 16); 2067 2068 /************************************************* 2069 * Create resources * 2070 *************************************************/ 2071 2072 /* Clock Sources for Pixel Clock*/ 2073 pool->base.clock_sources[DCN31_CLK_SRC_PLL0] = 2074 dcn31_clock_source_create(ctx, ctx->dc_bios, 2075 CLOCK_SOURCE_COMBO_PHY_PLL0, 2076 &clk_src_regs[0], false); 2077 pool->base.clock_sources[DCN31_CLK_SRC_PLL1] = 2078 dcn31_clock_source_create(ctx, ctx->dc_bios, 2079 CLOCK_SOURCE_COMBO_PHY_PLL1, 2080 &clk_src_regs[1], false); 2081 pool->base.clock_sources[DCN31_CLK_SRC_PLL2] = 2082 dcn31_clock_source_create(ctx, ctx->dc_bios, 2083 CLOCK_SOURCE_COMBO_PHY_PLL2, 2084 &clk_src_regs[2], false); 2085 pool->base.clock_sources[DCN31_CLK_SRC_PLL3] = 2086 dcn31_clock_source_create(ctx, ctx->dc_bios, 2087 CLOCK_SOURCE_COMBO_PHY_PLL3, 2088 &clk_src_regs[3], false); 2089 pool->base.clock_sources[DCN31_CLK_SRC_PLL4] = 2090 dcn31_clock_source_create(ctx, ctx->dc_bios, 2091 CLOCK_SOURCE_COMBO_PHY_PLL4, 2092 &clk_src_regs[4], false); 2093 2094 pool->base.clk_src_count = DCN30_CLK_SRC_TOTAL; 2095 2096 /* todo: not reuse phy_pll registers */ 2097 pool->base.dp_clock_source = 2098 dcn31_clock_source_create(ctx, ctx->dc_bios, 2099 CLOCK_SOURCE_ID_DP_DTO, 2100 &clk_src_regs[0], true); 2101 2102 for (i = 0; i < pool->base.clk_src_count; i++) { 2103 if (pool->base.clock_sources[i] == NULL) { 2104 dm_error("DC: failed to create clock sources!\n"); 2105 BREAK_TO_DEBUGGER(); 2106 goto create_fail; 2107 } 2108 } 2109 2110 /* TODO: DCCG */ 2111 pool->base.dccg = dccg31_create(ctx, &dccg_regs, &dccg_shift, &dccg_mask); 2112 if (pool->base.dccg == NULL) { 2113 dm_error("DC: failed to create dccg!\n"); 2114 BREAK_TO_DEBUGGER(); 2115 goto create_fail; 2116 } 2117 2118 /* TODO: IRQ */ 2119 init_data.ctx = dc->ctx; 2120 pool->base.irqs = dal_irq_service_dcn31_create(&init_data); 2121 if (!pool->base.irqs) 2122 goto create_fail; 2123 2124 /* HUBBUB */ 2125 pool->base.hubbub = dcn31_hubbub_create(ctx); 2126 if (pool->base.hubbub == NULL) { 2127 BREAK_TO_DEBUGGER(); 2128 dm_error("DC: failed to create hubbub!\n"); 2129 goto create_fail; 2130 } 2131 2132 /* HUBPs, DPPs, OPPs and TGs */ 2133 for (i = 0; i < pool->base.pipe_count; i++) { 2134 pool->base.hubps[i] = dcn31_hubp_create(ctx, i); 2135 if (pool->base.hubps[i] == NULL) { 2136 BREAK_TO_DEBUGGER(); 2137 dm_error( 2138 "DC: failed to create hubps!\n"); 2139 goto create_fail; 2140 } 2141 2142 pool->base.dpps[i] = dcn31_dpp_create(ctx, i); 2143 if (pool->base.dpps[i] == NULL) { 2144 BREAK_TO_DEBUGGER(); 2145 dm_error( 2146 "DC: failed to create dpps!\n"); 2147 goto create_fail; 2148 } 2149 } 2150 2151 for (i = 0; i < pool->base.res_cap->num_opp; i++) { 2152 pool->base.opps[i] = dcn31_opp_create(ctx, i); 2153 if (pool->base.opps[i] == NULL) { 2154 BREAK_TO_DEBUGGER(); 2155 dm_error( 2156 "DC: failed to create output pixel processor!\n"); 2157 goto create_fail; 2158 } 2159 } 2160 2161 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { 2162 pool->base.timing_generators[i] = dcn31_timing_generator_create( 2163 ctx, i); 2164 if (pool->base.timing_generators[i] == NULL) { 2165 BREAK_TO_DEBUGGER(); 2166 dm_error("DC: failed to create tg!\n"); 2167 goto create_fail; 2168 } 2169 } 2170 pool->base.timing_generator_count = i; 2171 2172 /* PSR */ 2173 pool->base.psr = dmub_psr_create(ctx); 2174 if (pool->base.psr == NULL) { 2175 dm_error("DC: failed to create psr obj!\n"); 2176 BREAK_TO_DEBUGGER(); 2177 goto create_fail; 2178 } 2179 2180 /* ABM */ 2181 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { 2182 pool->base.multiple_abms[i] = dmub_abm_create(ctx, 2183 &abm_regs[i], 2184 &abm_shift, 2185 &abm_mask); 2186 if (pool->base.multiple_abms[i] == NULL) { 2187 dm_error("DC: failed to create abm for pipe %d!\n", i); 2188 BREAK_TO_DEBUGGER(); 2189 goto create_fail; 2190 } 2191 } 2192 2193 /* MPC and DSC */ 2194 pool->base.mpc = dcn31_mpc_create(ctx, pool->base.mpcc_count, pool->base.res_cap->num_mpc_3dlut); 2195 if (pool->base.mpc == NULL) { 2196 BREAK_TO_DEBUGGER(); 2197 dm_error("DC: failed to create mpc!\n"); 2198 goto create_fail; 2199 } 2200 2201 for (i = 0; i < pool->base.res_cap->num_dsc; i++) { 2202 pool->base.dscs[i] = dcn31_dsc_create(ctx, i); 2203 if (pool->base.dscs[i] == NULL) { 2204 BREAK_TO_DEBUGGER(); 2205 dm_error("DC: failed to create display stream compressor %d!\n", i); 2206 goto create_fail; 2207 } 2208 } 2209 2210 /* DWB and MMHUBBUB */ 2211 if (!dcn31_dwbc_create(ctx, &pool->base)) { 2212 BREAK_TO_DEBUGGER(); 2213 dm_error("DC: failed to create dwbc!\n"); 2214 goto create_fail; 2215 } 2216 2217 if (!dcn31_mmhubbub_create(ctx, &pool->base)) { 2218 BREAK_TO_DEBUGGER(); 2219 dm_error("DC: failed to create mcif_wb!\n"); 2220 goto create_fail; 2221 } 2222 2223 /* AUX and I2C */ 2224 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { 2225 pool->base.engines[i] = dcn31_aux_engine_create(ctx, i); 2226 if (pool->base.engines[i] == NULL) { 2227 BREAK_TO_DEBUGGER(); 2228 dm_error( 2229 "DC:failed to create aux engine!!\n"); 2230 goto create_fail; 2231 } 2232 pool->base.hw_i2cs[i] = dcn31_i2c_hw_create(ctx, i); 2233 if (pool->base.hw_i2cs[i] == NULL) { 2234 BREAK_TO_DEBUGGER(); 2235 dm_error( 2236 "DC:failed to create hw i2c!!\n"); 2237 goto create_fail; 2238 } 2239 pool->base.sw_i2cs[i] = NULL; 2240 } 2241 2242 /* Audio, Stream Encoders including HPO and virtual, MPC 3D LUTs */ 2243 if (!resource_construct(num_virtual_links, dc, &pool->base, 2244 (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment) ? 2245 &res_create_funcs : &res_create_maximus_funcs))) 2246 goto create_fail; 2247 2248 /* HW Sequencer and Plane caps */ 2249 dcn31_hw_sequencer_construct(dc); 2250 2251 dc->caps.max_planes = pool->base.pipe_count; 2252 2253 for (i = 0; i < dc->caps.max_planes; ++i) 2254 dc->caps.planes[i] = plane_cap; 2255 2256 dc->cap_funcs = cap_funcs; 2257 2258 dc->dcn_ip->max_num_dpp = dcn3_16_ip.max_num_dpp; 2259 2260 return true; 2261 2262 create_fail: 2263 2264 dcn316_resource_destruct(pool); 2265 2266 return false; 2267 } 2268 2269 struct resource_pool *dcn316_create_resource_pool( 2270 const struct dc_init_data *init_data, 2271 struct dc *dc) 2272 { 2273 struct dcn316_resource_pool *pool = 2274 kzalloc(sizeof(struct dcn316_resource_pool), GFP_KERNEL); 2275 2276 if (!pool) 2277 return NULL; 2278 2279 if (dcn316_resource_construct(init_data->num_virtual_links, dc, pool)) 2280 return &pool->base; 2281 2282 BREAK_TO_DEBUGGER(); 2283 kfree(pool); 2284 return NULL; 2285 } 2286