1 /* 2 * Copyright 2021 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 27 #include "dm_services.h" 28 #include "dc.h" 29 30 #include "dcn31/dcn31_init.h" 31 32 #include "resource.h" 33 #include "include/irq_service_interface.h" 34 #include "dcn316_resource.h" 35 36 #include "dcn20/dcn20_resource.h" 37 #include "dcn30/dcn30_resource.h" 38 #include "dcn31/dcn31_resource.h" 39 40 #include "dcn10/dcn10_ipp.h" 41 #include "dcn30/dcn30_hubbub.h" 42 #include "dcn31/dcn31_hubbub.h" 43 #include "dcn30/dcn30_mpc.h" 44 #include "dcn31/dcn31_hubp.h" 45 #include "irq/dcn31/irq_service_dcn31.h" 46 #include "dcn30/dcn30_dpp.h" 47 #include "dcn31/dcn31_optc.h" 48 #include "dcn20/dcn20_hwseq.h" 49 #include "dcn30/dcn30_hwseq.h" 50 #include "dce110/dce110_hw_sequencer.h" 51 #include "dcn30/dcn30_opp.h" 52 #include "dcn20/dcn20_dsc.h" 53 #include "dcn30/dcn30_vpg.h" 54 #include "dcn30/dcn30_afmt.h" 55 #include "dcn30/dcn30_dio_stream_encoder.h" 56 #include "dcn31/dcn31_hpo_dp_stream_encoder.h" 57 #include "dcn31/dcn31_hpo_dp_link_encoder.h" 58 #include "dcn31/dcn31_apg.h" 59 #include "dcn31/dcn31_dio_link_encoder.h" 60 #include "dcn31/dcn31_vpg.h" 61 #include "dcn31/dcn31_afmt.h" 62 #include "dce/dce_clock_source.h" 63 #include "dce/dce_audio.h" 64 #include "dce/dce_hwseq.h" 65 #include "clk_mgr.h" 66 #include "virtual/virtual_stream_encoder.h" 67 #include "dce110/dce110_resource.h" 68 #include "dml/display_mode_vba.h" 69 #include "dml/dcn31/dcn31_fpu.h" 70 #include "dcn31/dcn31_dccg.h" 71 #include "dcn10/dcn10_resource.h" 72 #include "dcn31/dcn31_panel_cntl.h" 73 74 #include "dcn30/dcn30_dwb.h" 75 #include "dcn30/dcn30_mmhubbub.h" 76 77 #include "dcn/dcn_3_1_6_offset.h" 78 #include "dcn/dcn_3_1_6_sh_mask.h" 79 #include "dpcs/dpcs_4_2_3_offset.h" 80 #include "dpcs/dpcs_4_2_3_sh_mask.h" 81 82 #define regBIF_BX1_BIOS_SCRATCH_2 0x003a 83 #define regBIF_BX1_BIOS_SCRATCH_2_BASE_IDX 1 84 #define regBIF_BX1_BIOS_SCRATCH_3 0x003b 85 #define regBIF_BX1_BIOS_SCRATCH_3_BASE_IDX 1 86 #define regBIF_BX1_BIOS_SCRATCH_6 0x003e 87 #define regBIF_BX1_BIOS_SCRATCH_6_BASE_IDX 1 88 89 #define regDCHUBBUB_DEBUG_CTRL_0 0x04d6 90 #define regDCHUBBUB_DEBUG_CTRL_0_BASE_IDX 2 91 #define DCHUBBUB_DEBUG_CTRL_0__DET_DEPTH__SHIFT 0x10 92 #define DCHUBBUB_DEBUG_CTRL_0__DET_DEPTH_MASK 0x01FF0000L 93 94 #define DCN_BASE__INST0_SEG0 0x00000012 95 #define DCN_BASE__INST0_SEG1 0x000000C0 96 #define DCN_BASE__INST0_SEG2 0x000034C0 97 #define DCN_BASE__INST0_SEG3 0x00009000 98 #define DCN_BASE__INST0_SEG4 0x02403C00 99 #define DCN_BASE__INST0_SEG5 0 100 101 #define DPCS_BASE__INST0_SEG0 0x00000012 102 #define DPCS_BASE__INST0_SEG1 0x000000C0 103 #define DPCS_BASE__INST0_SEG2 0x000034C0 104 #define DPCS_BASE__INST0_SEG3 0x00009000 105 #define DPCS_BASE__INST0_SEG4 0x02403C00 106 #define DPCS_BASE__INST0_SEG5 0 107 108 #define NBIO_BASE__INST0_SEG0 0x00000000 109 #define NBIO_BASE__INST0_SEG1 0x00000014 110 #define NBIO_BASE__INST0_SEG2 0x00000D20 111 #define NBIO_BASE__INST0_SEG3 0x00010400 112 #define NBIO_BASE__INST0_SEG4 0x0241B000 113 #define NBIO_BASE__INST0_SEG5 0x04040000 114 115 #include "reg_helper.h" 116 #include "dce/dmub_abm.h" 117 #include "dce/dmub_psr.h" 118 #include "dce/dce_aux.h" 119 #include "dce/dce_i2c.h" 120 121 #include "dml/dcn30/display_mode_vba_30.h" 122 #include "vm_helper.h" 123 #include "dcn20/dcn20_vmid.h" 124 125 #include "link_enc_cfg.h" 126 127 #define DCN3_16_MAX_DET_SIZE 384 128 #define DCN3_16_MIN_COMPBUF_SIZE_KB 128 129 #define DCN3_16_CRB_SEGMENT_SIZE_KB 64 130 131 enum dcn31_clk_src_array_id { 132 DCN31_CLK_SRC_PLL0, 133 DCN31_CLK_SRC_PLL1, 134 DCN31_CLK_SRC_PLL2, 135 DCN31_CLK_SRC_PLL3, 136 DCN31_CLK_SRC_PLL4, 137 DCN30_CLK_SRC_TOTAL 138 }; 139 140 /* begin ********************* 141 * macros to expend register list macro defined in HW object header file 142 */ 143 144 /* DCN */ 145 #define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg 146 147 #define BASE(seg) BASE_INNER(seg) 148 149 #define SR(reg_name)\ 150 .reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \ 151 reg ## reg_name 152 153 #define SRI(reg_name, block, id)\ 154 .reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 155 reg ## block ## id ## _ ## reg_name 156 157 #define SRI2(reg_name, block, id)\ 158 .reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \ 159 reg ## reg_name 160 161 #define SRIR(var_name, reg_name, block, id)\ 162 .var_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 163 reg ## block ## id ## _ ## reg_name 164 165 #define SRII(reg_name, block, id)\ 166 .reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 167 reg ## block ## id ## _ ## reg_name 168 169 #define SRII_MPC_RMU(reg_name, block, id)\ 170 .RMU##_##reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 171 reg ## block ## id ## _ ## reg_name 172 173 #define SRII_DWB(reg_name, temp_name, block, id)\ 174 .reg_name[id] = BASE(reg ## block ## id ## _ ## temp_name ## _BASE_IDX) + \ 175 reg ## block ## id ## _ ## temp_name 176 177 #define SF_DWB2(reg_name, block, id, field_name, post_fix) \ 178 .field_name = reg_name ## __ ## field_name ## post_fix 179 180 #define DCCG_SRII(reg_name, block, id)\ 181 .block ## _ ## reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 182 reg ## block ## id ## _ ## reg_name 183 184 #define VUPDATE_SRII(reg_name, block, id)\ 185 .reg_name[id] = BASE(reg ## reg_name ## _ ## block ## id ## _BASE_IDX) + \ 186 reg ## reg_name ## _ ## block ## id 187 188 /* NBIO */ 189 #define NBIO_BASE_INNER(seg) \ 190 NBIO_BASE__INST0_SEG ## seg 191 192 #define NBIO_BASE(seg) \ 193 NBIO_BASE_INNER(seg) 194 195 #define NBIO_SR(reg_name)\ 196 .reg_name = NBIO_BASE(regBIF_BX1_ ## reg_name ## _BASE_IDX) + \ 197 regBIF_BX1_ ## reg_name 198 199 static const struct bios_registers bios_regs = { 200 NBIO_SR(BIOS_SCRATCH_3), 201 NBIO_SR(BIOS_SCRATCH_6) 202 }; 203 204 #define clk_src_regs(index, pllid)\ 205 [index] = {\ 206 CS_COMMON_REG_LIST_DCN3_0(index, pllid),\ 207 } 208 209 static const struct dce110_clk_src_regs clk_src_regs[] = { 210 clk_src_regs(0, A), 211 clk_src_regs(1, B), 212 clk_src_regs(2, C), 213 clk_src_regs(3, D), 214 clk_src_regs(4, E) 215 }; 216 217 static const struct dce110_clk_src_shift cs_shift = { 218 CS_COMMON_MASK_SH_LIST_DCN2_0(__SHIFT) 219 }; 220 221 static const struct dce110_clk_src_mask cs_mask = { 222 CS_COMMON_MASK_SH_LIST_DCN2_0(_MASK) 223 }; 224 225 #define abm_regs(id)\ 226 [id] = {\ 227 ABM_DCN302_REG_LIST(id)\ 228 } 229 230 static const struct dce_abm_registers abm_regs[] = { 231 abm_regs(0), 232 abm_regs(1), 233 abm_regs(2), 234 abm_regs(3), 235 }; 236 237 static const struct dce_abm_shift abm_shift = { 238 ABM_MASK_SH_LIST_DCN30(__SHIFT) 239 }; 240 241 static const struct dce_abm_mask abm_mask = { 242 ABM_MASK_SH_LIST_DCN30(_MASK) 243 }; 244 245 #define audio_regs(id)\ 246 [id] = {\ 247 AUD_COMMON_REG_LIST(id)\ 248 } 249 250 static const struct dce_audio_registers audio_regs[] = { 251 audio_regs(0), 252 audio_regs(1), 253 audio_regs(2), 254 audio_regs(3), 255 audio_regs(4), 256 audio_regs(5), 257 audio_regs(6) 258 }; 259 260 #define DCE120_AUD_COMMON_MASK_SH_LIST(mask_sh)\ 261 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX, AZALIA_ENDPOINT_REG_INDEX, mask_sh),\ 262 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA, AZALIA_ENDPOINT_REG_DATA, mask_sh),\ 263 AUD_COMMON_MASK_SH_LIST_BASE(mask_sh) 264 265 static const struct dce_audio_shift audio_shift = { 266 DCE120_AUD_COMMON_MASK_SH_LIST(__SHIFT) 267 }; 268 269 static const struct dce_audio_mask audio_mask = { 270 DCE120_AUD_COMMON_MASK_SH_LIST(_MASK) 271 }; 272 273 #define vpg_regs(id)\ 274 [id] = {\ 275 VPG_DCN31_REG_LIST(id)\ 276 } 277 278 static const struct dcn31_vpg_registers vpg_regs[] = { 279 vpg_regs(0), 280 vpg_regs(1), 281 vpg_regs(2), 282 vpg_regs(3), 283 vpg_regs(4), 284 vpg_regs(5), 285 vpg_regs(6), 286 vpg_regs(7), 287 vpg_regs(8), 288 vpg_regs(9), 289 }; 290 291 static const struct dcn31_vpg_shift vpg_shift = { 292 DCN31_VPG_MASK_SH_LIST(__SHIFT) 293 }; 294 295 static const struct dcn31_vpg_mask vpg_mask = { 296 DCN31_VPG_MASK_SH_LIST(_MASK) 297 }; 298 299 #define afmt_regs(id)\ 300 [id] = {\ 301 AFMT_DCN31_REG_LIST(id)\ 302 } 303 304 static const struct dcn31_afmt_registers afmt_regs[] = { 305 afmt_regs(0), 306 afmt_regs(1), 307 afmt_regs(2), 308 afmt_regs(3), 309 afmt_regs(4), 310 afmt_regs(5) 311 }; 312 313 static const struct dcn31_afmt_shift afmt_shift = { 314 DCN31_AFMT_MASK_SH_LIST(__SHIFT) 315 }; 316 317 static const struct dcn31_afmt_mask afmt_mask = { 318 DCN31_AFMT_MASK_SH_LIST(_MASK) 319 }; 320 321 322 #define apg_regs(id)\ 323 [id] = {\ 324 APG_DCN31_REG_LIST(id)\ 325 } 326 327 static const struct dcn31_apg_registers apg_regs[] = { 328 apg_regs(0), 329 apg_regs(1), 330 apg_regs(2), 331 apg_regs(3) 332 }; 333 334 static const struct dcn31_apg_shift apg_shift = { 335 DCN31_APG_MASK_SH_LIST(__SHIFT) 336 }; 337 338 static const struct dcn31_apg_mask apg_mask = { 339 DCN31_APG_MASK_SH_LIST(_MASK) 340 }; 341 342 343 #define stream_enc_regs(id)\ 344 [id] = {\ 345 SE_DCN3_REG_LIST(id)\ 346 } 347 348 static const struct dcn10_stream_enc_registers stream_enc_regs[] = { 349 stream_enc_regs(0), 350 stream_enc_regs(1), 351 stream_enc_regs(2), 352 stream_enc_regs(3), 353 stream_enc_regs(4) 354 }; 355 356 static const struct dcn10_stream_encoder_shift se_shift = { 357 SE_COMMON_MASK_SH_LIST_DCN30(__SHIFT) 358 }; 359 360 static const struct dcn10_stream_encoder_mask se_mask = { 361 SE_COMMON_MASK_SH_LIST_DCN30(_MASK) 362 }; 363 364 365 #define aux_regs(id)\ 366 [id] = {\ 367 DCN2_AUX_REG_LIST(id)\ 368 } 369 370 static const struct dcn10_link_enc_aux_registers link_enc_aux_regs[] = { 371 aux_regs(0), 372 aux_regs(1), 373 aux_regs(2), 374 aux_regs(3), 375 aux_regs(4) 376 }; 377 378 #define hpd_regs(id)\ 379 [id] = {\ 380 HPD_REG_LIST(id)\ 381 } 382 383 static const struct dcn10_link_enc_hpd_registers link_enc_hpd_regs[] = { 384 hpd_regs(0), 385 hpd_regs(1), 386 hpd_regs(2), 387 hpd_regs(3), 388 hpd_regs(4) 389 }; 390 391 #define link_regs(id, phyid)\ 392 [id] = {\ 393 LE_DCN31_REG_LIST(id), \ 394 UNIPHY_DCN2_REG_LIST(phyid), \ 395 DPCS_DCN31_REG_LIST(id), \ 396 } 397 398 static const struct dce110_aux_registers_shift aux_shift = { 399 DCN_AUX_MASK_SH_LIST(__SHIFT) 400 }; 401 402 static const struct dce110_aux_registers_mask aux_mask = { 403 DCN_AUX_MASK_SH_LIST(_MASK) 404 }; 405 406 static const struct dcn10_link_enc_registers link_enc_regs[] = { 407 link_regs(0, A), 408 link_regs(1, B), 409 link_regs(2, C), 410 link_regs(3, D), 411 link_regs(4, E) 412 }; 413 414 static const struct dcn10_link_enc_shift le_shift = { 415 LINK_ENCODER_MASK_SH_LIST_DCN31(__SHIFT), \ 416 DPCS_DCN31_MASK_SH_LIST(__SHIFT) 417 }; 418 419 static const struct dcn10_link_enc_mask le_mask = { 420 LINK_ENCODER_MASK_SH_LIST_DCN31(_MASK), \ 421 DPCS_DCN31_MASK_SH_LIST(_MASK) 422 }; 423 424 425 426 #define hpo_dp_stream_encoder_reg_list(id)\ 427 [id] = {\ 428 DCN3_1_HPO_DP_STREAM_ENC_REG_LIST(id)\ 429 } 430 431 static const struct dcn31_hpo_dp_stream_encoder_registers hpo_dp_stream_enc_regs[] = { 432 hpo_dp_stream_encoder_reg_list(0), 433 hpo_dp_stream_encoder_reg_list(1), 434 hpo_dp_stream_encoder_reg_list(2), 435 hpo_dp_stream_encoder_reg_list(3), 436 }; 437 438 static const struct dcn31_hpo_dp_stream_encoder_shift hpo_dp_se_shift = { 439 DCN3_1_HPO_DP_STREAM_ENC_MASK_SH_LIST(__SHIFT) 440 }; 441 442 static const struct dcn31_hpo_dp_stream_encoder_mask hpo_dp_se_mask = { 443 DCN3_1_HPO_DP_STREAM_ENC_MASK_SH_LIST(_MASK) 444 }; 445 446 447 #define hpo_dp_link_encoder_reg_list(id)\ 448 [id] = {\ 449 DCN3_1_HPO_DP_LINK_ENC_REG_LIST(id),\ 450 DCN3_1_RDPCSTX_REG_LIST(0),\ 451 DCN3_1_RDPCSTX_REG_LIST(1),\ 452 DCN3_1_RDPCSTX_REG_LIST(2),\ 453 DCN3_1_RDPCSTX_REG_LIST(3),\ 454 DCN3_1_RDPCSTX_REG_LIST(4)\ 455 } 456 457 static const struct dcn31_hpo_dp_link_encoder_registers hpo_dp_link_enc_regs[] = { 458 hpo_dp_link_encoder_reg_list(0), 459 hpo_dp_link_encoder_reg_list(1), 460 }; 461 462 static const struct dcn31_hpo_dp_link_encoder_shift hpo_dp_le_shift = { 463 DCN3_1_HPO_DP_LINK_ENC_MASK_SH_LIST(__SHIFT) 464 }; 465 466 static const struct dcn31_hpo_dp_link_encoder_mask hpo_dp_le_mask = { 467 DCN3_1_HPO_DP_LINK_ENC_MASK_SH_LIST(_MASK) 468 }; 469 470 471 #define dpp_regs(id)\ 472 [id] = {\ 473 DPP_REG_LIST_DCN30(id),\ 474 } 475 476 static const struct dcn3_dpp_registers dpp_regs[] = { 477 dpp_regs(0), 478 dpp_regs(1), 479 dpp_regs(2), 480 dpp_regs(3) 481 }; 482 483 static const struct dcn3_dpp_shift tf_shift = { 484 DPP_REG_LIST_SH_MASK_DCN30(__SHIFT) 485 }; 486 487 static const struct dcn3_dpp_mask tf_mask = { 488 DPP_REG_LIST_SH_MASK_DCN30(_MASK) 489 }; 490 491 #define opp_regs(id)\ 492 [id] = {\ 493 OPP_REG_LIST_DCN30(id),\ 494 } 495 496 static const struct dcn20_opp_registers opp_regs[] = { 497 opp_regs(0), 498 opp_regs(1), 499 opp_regs(2), 500 opp_regs(3) 501 }; 502 503 static const struct dcn20_opp_shift opp_shift = { 504 OPP_MASK_SH_LIST_DCN20(__SHIFT) 505 }; 506 507 static const struct dcn20_opp_mask opp_mask = { 508 OPP_MASK_SH_LIST_DCN20(_MASK) 509 }; 510 511 #define aux_engine_regs(id)\ 512 [id] = {\ 513 AUX_COMMON_REG_LIST0(id), \ 514 .AUXN_IMPCAL = 0, \ 515 .AUXP_IMPCAL = 0, \ 516 .AUX_RESET_MASK = DP_AUX0_AUX_CONTROL__AUX_RESET_MASK, \ 517 } 518 519 static const struct dce110_aux_registers aux_engine_regs[] = { 520 aux_engine_regs(0), 521 aux_engine_regs(1), 522 aux_engine_regs(2), 523 aux_engine_regs(3), 524 aux_engine_regs(4) 525 }; 526 527 #define dwbc_regs_dcn3(id)\ 528 [id] = {\ 529 DWBC_COMMON_REG_LIST_DCN30(id),\ 530 } 531 532 static const struct dcn30_dwbc_registers dwbc30_regs[] = { 533 dwbc_regs_dcn3(0), 534 }; 535 536 static const struct dcn30_dwbc_shift dwbc30_shift = { 537 DWBC_COMMON_MASK_SH_LIST_DCN30(__SHIFT) 538 }; 539 540 static const struct dcn30_dwbc_mask dwbc30_mask = { 541 DWBC_COMMON_MASK_SH_LIST_DCN30(_MASK) 542 }; 543 544 #define mcif_wb_regs_dcn3(id)\ 545 [id] = {\ 546 MCIF_WB_COMMON_REG_LIST_DCN30(id),\ 547 } 548 549 static const struct dcn30_mmhubbub_registers mcif_wb30_regs[] = { 550 mcif_wb_regs_dcn3(0) 551 }; 552 553 static const struct dcn30_mmhubbub_shift mcif_wb30_shift = { 554 MCIF_WB_COMMON_MASK_SH_LIST_DCN30(__SHIFT) 555 }; 556 557 static const struct dcn30_mmhubbub_mask mcif_wb30_mask = { 558 MCIF_WB_COMMON_MASK_SH_LIST_DCN30(_MASK) 559 }; 560 561 #define dsc_regsDCN20(id)\ 562 [id] = {\ 563 DSC_REG_LIST_DCN20(id)\ 564 } 565 566 static const struct dcn20_dsc_registers dsc_regs[] = { 567 dsc_regsDCN20(0), 568 dsc_regsDCN20(1), 569 dsc_regsDCN20(2) 570 }; 571 572 static const struct dcn20_dsc_shift dsc_shift = { 573 DSC_REG_LIST_SH_MASK_DCN20(__SHIFT) 574 }; 575 576 static const struct dcn20_dsc_mask dsc_mask = { 577 DSC_REG_LIST_SH_MASK_DCN20(_MASK) 578 }; 579 580 static const struct dcn30_mpc_registers mpc_regs = { 581 MPC_REG_LIST_DCN3_0(0), 582 MPC_REG_LIST_DCN3_0(1), 583 MPC_REG_LIST_DCN3_0(2), 584 MPC_REG_LIST_DCN3_0(3), 585 MPC_OUT_MUX_REG_LIST_DCN3_0(0), 586 MPC_OUT_MUX_REG_LIST_DCN3_0(1), 587 MPC_OUT_MUX_REG_LIST_DCN3_0(2), 588 MPC_OUT_MUX_REG_LIST_DCN3_0(3), 589 MPC_RMU_GLOBAL_REG_LIST_DCN3AG, 590 MPC_RMU_REG_LIST_DCN3AG(0), 591 MPC_RMU_REG_LIST_DCN3AG(1), 592 //MPC_RMU_REG_LIST_DCN3AG(2), 593 MPC_DWB_MUX_REG_LIST_DCN3_0(0), 594 }; 595 596 static const struct dcn30_mpc_shift mpc_shift = { 597 MPC_COMMON_MASK_SH_LIST_DCN30(__SHIFT) 598 }; 599 600 static const struct dcn30_mpc_mask mpc_mask = { 601 MPC_COMMON_MASK_SH_LIST_DCN30(_MASK) 602 }; 603 604 #define optc_regs(id)\ 605 [id] = {OPTC_COMMON_REG_LIST_DCN3_1(id)} 606 607 static const struct dcn_optc_registers optc_regs[] = { 608 optc_regs(0), 609 optc_regs(1), 610 optc_regs(2), 611 optc_regs(3) 612 }; 613 614 static const struct dcn_optc_shift optc_shift = { 615 OPTC_COMMON_MASK_SH_LIST_DCN3_1(__SHIFT) 616 }; 617 618 static const struct dcn_optc_mask optc_mask = { 619 OPTC_COMMON_MASK_SH_LIST_DCN3_1(_MASK) 620 }; 621 622 #define hubp_regs(id)\ 623 [id] = {\ 624 HUBP_REG_LIST_DCN30(id)\ 625 } 626 627 static const struct dcn_hubp2_registers hubp_regs[] = { 628 hubp_regs(0), 629 hubp_regs(1), 630 hubp_regs(2), 631 hubp_regs(3) 632 }; 633 634 635 static const struct dcn_hubp2_shift hubp_shift = { 636 HUBP_MASK_SH_LIST_DCN31(__SHIFT) 637 }; 638 639 static const struct dcn_hubp2_mask hubp_mask = { 640 HUBP_MASK_SH_LIST_DCN31(_MASK) 641 }; 642 static const struct dcn_hubbub_registers hubbub_reg = { 643 HUBBUB_REG_LIST_DCN31(0) 644 }; 645 646 static const struct dcn_hubbub_shift hubbub_shift = { 647 HUBBUB_MASK_SH_LIST_DCN31(__SHIFT) 648 }; 649 650 static const struct dcn_hubbub_mask hubbub_mask = { 651 HUBBUB_MASK_SH_LIST_DCN31(_MASK) 652 }; 653 654 static const struct dccg_registers dccg_regs = { 655 DCCG_REG_LIST_DCN31() 656 }; 657 658 static const struct dccg_shift dccg_shift = { 659 DCCG_MASK_SH_LIST_DCN31(__SHIFT) 660 }; 661 662 static const struct dccg_mask dccg_mask = { 663 DCCG_MASK_SH_LIST_DCN31(_MASK) 664 }; 665 666 667 #define SRII2(reg_name_pre, reg_name_post, id)\ 668 .reg_name_pre ## _ ## reg_name_post[id] = BASE(reg ## reg_name_pre \ 669 ## id ## _ ## reg_name_post ## _BASE_IDX) + \ 670 reg ## reg_name_pre ## id ## _ ## reg_name_post 671 672 673 #define HWSEQ_DCN31_REG_LIST()\ 674 SR(DCHUBBUB_GLOBAL_TIMER_CNTL), \ 675 SR(DCHUBBUB_ARB_HOSTVM_CNTL), \ 676 SR(DIO_MEM_PWR_CTRL), \ 677 SR(ODM_MEM_PWR_CTRL3), \ 678 SR(DMU_MEM_PWR_CNTL), \ 679 SR(MMHUBBUB_MEM_PWR_CNTL), \ 680 SR(DCCG_GATE_DISABLE_CNTL), \ 681 SR(DCCG_GATE_DISABLE_CNTL2), \ 682 SR(DCFCLK_CNTL),\ 683 SR(DC_MEM_GLOBAL_PWR_REQ_CNTL), \ 684 SRII(PIXEL_RATE_CNTL, OTG, 0), \ 685 SRII(PIXEL_RATE_CNTL, OTG, 1),\ 686 SRII(PIXEL_RATE_CNTL, OTG, 2),\ 687 SRII(PIXEL_RATE_CNTL, OTG, 3),\ 688 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 0),\ 689 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 1),\ 690 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 2),\ 691 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 3),\ 692 SR(MICROSECOND_TIME_BASE_DIV), \ 693 SR(MILLISECOND_TIME_BASE_DIV), \ 694 SR(DISPCLK_FREQ_CHANGE_CNTL), \ 695 SR(RBBMIF_TIMEOUT_DIS), \ 696 SR(RBBMIF_TIMEOUT_DIS_2), \ 697 SR(DCHUBBUB_CRC_CTRL), \ 698 SR(DPP_TOP0_DPP_CRC_CTRL), \ 699 SR(DPP_TOP0_DPP_CRC_VAL_B_A), \ 700 SR(DPP_TOP0_DPP_CRC_VAL_R_G), \ 701 SR(MPC_CRC_CTRL), \ 702 SR(MPC_CRC_RESULT_GB), \ 703 SR(MPC_CRC_RESULT_C), \ 704 SR(MPC_CRC_RESULT_AR), \ 705 SR(DOMAIN0_PG_CONFIG), \ 706 SR(DOMAIN1_PG_CONFIG), \ 707 SR(DOMAIN2_PG_CONFIG), \ 708 SR(DOMAIN3_PG_CONFIG), \ 709 SR(DOMAIN16_PG_CONFIG), \ 710 SR(DOMAIN17_PG_CONFIG), \ 711 SR(DOMAIN18_PG_CONFIG), \ 712 SR(DOMAIN0_PG_STATUS), \ 713 SR(DOMAIN1_PG_STATUS), \ 714 SR(DOMAIN2_PG_STATUS), \ 715 SR(DOMAIN3_PG_STATUS), \ 716 SR(DOMAIN16_PG_STATUS), \ 717 SR(DOMAIN17_PG_STATUS), \ 718 SR(DOMAIN18_PG_STATUS), \ 719 SR(D1VGA_CONTROL), \ 720 SR(D2VGA_CONTROL), \ 721 SR(D3VGA_CONTROL), \ 722 SR(D4VGA_CONTROL), \ 723 SR(D5VGA_CONTROL), \ 724 SR(D6VGA_CONTROL), \ 725 SR(DC_IP_REQUEST_CNTL), \ 726 SR(AZALIA_AUDIO_DTO), \ 727 SR(AZALIA_CONTROLLER_CLOCK_GATING), \ 728 SR(HPO_TOP_HW_CONTROL) 729 730 static const struct dce_hwseq_registers hwseq_reg = { 731 HWSEQ_DCN31_REG_LIST() 732 }; 733 734 #define HWSEQ_DCN31_MASK_SH_LIST(mask_sh)\ 735 HWSEQ_DCN_MASK_SH_LIST(mask_sh), \ 736 HWS_SF(, DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_REFDIV, mask_sh), \ 737 HWS_SF(, DCHUBBUB_ARB_HOSTVM_CNTL, DISABLE_HOSTVM_FORCE_ALLOW_PSTATE, mask_sh), \ 738 HWS_SF(, DOMAIN0_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ 739 HWS_SF(, DOMAIN0_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ 740 HWS_SF(, DOMAIN1_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ 741 HWS_SF(, DOMAIN1_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ 742 HWS_SF(, DOMAIN2_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ 743 HWS_SF(, DOMAIN2_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ 744 HWS_SF(, DOMAIN3_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ 745 HWS_SF(, DOMAIN3_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ 746 HWS_SF(, DOMAIN16_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ 747 HWS_SF(, DOMAIN16_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ 748 HWS_SF(, DOMAIN17_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ 749 HWS_SF(, DOMAIN17_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ 750 HWS_SF(, DOMAIN18_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ 751 HWS_SF(, DOMAIN18_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ 752 HWS_SF(, DOMAIN0_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ 753 HWS_SF(, DOMAIN1_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ 754 HWS_SF(, DOMAIN2_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ 755 HWS_SF(, DOMAIN3_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ 756 HWS_SF(, DOMAIN16_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ 757 HWS_SF(, DOMAIN17_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ 758 HWS_SF(, DOMAIN18_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ 759 HWS_SF(, DC_IP_REQUEST_CNTL, IP_REQUEST_EN, mask_sh), \ 760 HWS_SF(, AZALIA_AUDIO_DTO, AZALIA_AUDIO_DTO_MODULE, mask_sh), \ 761 HWS_SF(, HPO_TOP_CLOCK_CONTROL, HPO_HDMISTREAMCLK_G_GATE_DIS, mask_sh), \ 762 HWS_SF(, DMU_MEM_PWR_CNTL, DMCU_ERAM_MEM_PWR_FORCE, mask_sh), \ 763 HWS_SF(, ODM_MEM_PWR_CTRL3, ODM_MEM_UNASSIGNED_PWR_MODE, mask_sh), \ 764 HWS_SF(, ODM_MEM_PWR_CTRL3, ODM_MEM_VBLANK_PWR_MODE, mask_sh), \ 765 HWS_SF(, MMHUBBUB_MEM_PWR_CNTL, VGA_MEM_PWR_FORCE, mask_sh), \ 766 HWS_SF(, DIO_MEM_PWR_CTRL, I2C_LIGHT_SLEEP_FORCE, mask_sh), \ 767 HWS_SF(, HPO_TOP_HW_CONTROL, HPO_IO_EN, mask_sh) 768 769 static const struct dce_hwseq_shift hwseq_shift = { 770 HWSEQ_DCN31_MASK_SH_LIST(__SHIFT) 771 }; 772 773 static const struct dce_hwseq_mask hwseq_mask = { 774 HWSEQ_DCN31_MASK_SH_LIST(_MASK) 775 }; 776 #define vmid_regs(id)\ 777 [id] = {\ 778 DCN20_VMID_REG_LIST(id)\ 779 } 780 781 static const struct dcn_vmid_registers vmid_regs[] = { 782 vmid_regs(0), 783 vmid_regs(1), 784 vmid_regs(2), 785 vmid_regs(3), 786 vmid_regs(4), 787 vmid_regs(5), 788 vmid_regs(6), 789 vmid_regs(7), 790 vmid_regs(8), 791 vmid_regs(9), 792 vmid_regs(10), 793 vmid_regs(11), 794 vmid_regs(12), 795 vmid_regs(13), 796 vmid_regs(14), 797 vmid_regs(15) 798 }; 799 800 static const struct dcn20_vmid_shift vmid_shifts = { 801 DCN20_VMID_MASK_SH_LIST(__SHIFT) 802 }; 803 804 static const struct dcn20_vmid_mask vmid_masks = { 805 DCN20_VMID_MASK_SH_LIST(_MASK) 806 }; 807 808 static const struct resource_caps res_cap_dcn31 = { 809 .num_timing_generator = 4, 810 .num_opp = 4, 811 .num_video_plane = 4, 812 .num_audio = 5, 813 .num_stream_encoder = 5, 814 .num_dig_link_enc = 5, 815 .num_hpo_dp_stream_encoder = 4, 816 .num_hpo_dp_link_encoder = 2, 817 .num_pll = 5, 818 .num_dwb = 1, 819 .num_ddc = 5, 820 .num_vmid = 16, 821 .num_mpc_3dlut = 2, 822 .num_dsc = 3, 823 }; 824 825 static const struct dc_plane_cap plane_cap = { 826 .type = DC_PLANE_TYPE_DCN_UNIVERSAL, 827 .blends_with_above = true, 828 .blends_with_below = true, 829 .per_pixel_alpha = true, 830 831 .pixel_format_support = { 832 .argb8888 = true, 833 .nv12 = true, 834 .fp16 = true, 835 .p010 = true, 836 .ayuv = false, 837 }, 838 839 .max_upscale_factor = { 840 .argb8888 = 16000, 841 .nv12 = 16000, 842 .fp16 = 16000 843 }, 844 845 // 6:1 downscaling ratio: 1000/6 = 166.666 846 .max_downscale_factor = { 847 .argb8888 = 167, 848 .nv12 = 167, 849 .fp16 = 167 850 }, 851 64, 852 64 853 }; 854 855 static const struct dc_debug_options debug_defaults_drv = { 856 .disable_z10 = true, /*hw not support it*/ 857 .disable_dmcu = true, 858 .force_abm_enable = false, 859 .timing_trace = false, 860 .clock_trace = true, 861 .disable_pplib_clock_request = false, 862 .pipe_split_policy = MPC_SPLIT_DYNAMIC, 863 .force_single_disp_pipe_split = false, 864 .disable_dcc = DCC_ENABLE, 865 .vsr_support = true, 866 .performance_trace = false, 867 .max_downscale_src_width = 4096,/*upto true 4k*/ 868 .disable_pplib_wm_range = false, 869 .scl_reset_length10 = true, 870 .sanity_checks = false, 871 .underflow_assert_delay_us = 0xFFFFFFFF, 872 .dwb_fi_phase = -1, // -1 = disable, 873 .dmub_command_table = true, 874 .pstate_enabled = true, 875 .use_max_lb = true, 876 .enable_mem_low_power = { 877 .bits = { 878 .vga = true, 879 .i2c = true, 880 .dmcu = false, // This is previously known to cause hang on S3 cycles if enabled 881 .dscl = true, 882 .cm = true, 883 .mpc = true, 884 .optc = true, 885 .vpg = true, 886 .afmt = true, 887 } 888 }, 889 }; 890 891 static const struct dc_debug_options debug_defaults_diags = { 892 .disable_dmcu = true, 893 .force_abm_enable = false, 894 .timing_trace = true, 895 .clock_trace = true, 896 .disable_dpp_power_gate = true, 897 .disable_hubp_power_gate = true, 898 .disable_clock_gate = true, 899 .disable_pplib_clock_request = true, 900 .disable_pplib_wm_range = true, 901 .disable_stutter = false, 902 .scl_reset_length10 = true, 903 .dwb_fi_phase = -1, // -1 = disable 904 .dmub_command_table = true, 905 .enable_tri_buf = true, 906 .use_max_lb = true 907 }; 908 909 static const struct dc_panel_config panel_config_defaults = { 910 .psr = { 911 .disable_psr = false, 912 .disallow_psrsu = false, 913 }, 914 .ilr = { 915 .optimize_edp_link_rate = true, 916 }, 917 }; 918 919 static void dcn31_dpp_destroy(struct dpp **dpp) 920 { 921 kfree(TO_DCN20_DPP(*dpp)); 922 *dpp = NULL; 923 } 924 925 static struct dpp *dcn31_dpp_create( 926 struct dc_context *ctx, 927 uint32_t inst) 928 { 929 struct dcn3_dpp *dpp = 930 kzalloc(sizeof(struct dcn3_dpp), GFP_KERNEL); 931 932 if (!dpp) 933 return NULL; 934 935 if (dpp3_construct(dpp, ctx, inst, 936 &dpp_regs[inst], &tf_shift, &tf_mask)) 937 return &dpp->base; 938 939 BREAK_TO_DEBUGGER(); 940 kfree(dpp); 941 return NULL; 942 } 943 944 static struct output_pixel_processor *dcn31_opp_create( 945 struct dc_context *ctx, uint32_t inst) 946 { 947 struct dcn20_opp *opp = 948 kzalloc(sizeof(struct dcn20_opp), GFP_KERNEL); 949 950 if (!opp) { 951 BREAK_TO_DEBUGGER(); 952 return NULL; 953 } 954 955 dcn20_opp_construct(opp, ctx, inst, 956 &opp_regs[inst], &opp_shift, &opp_mask); 957 return &opp->base; 958 } 959 960 static struct dce_aux *dcn31_aux_engine_create( 961 struct dc_context *ctx, 962 uint32_t inst) 963 { 964 struct aux_engine_dce110 *aux_engine = 965 kzalloc(sizeof(struct aux_engine_dce110), GFP_KERNEL); 966 967 if (!aux_engine) 968 return NULL; 969 970 dce110_aux_engine_construct(aux_engine, ctx, inst, 971 SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD, 972 &aux_engine_regs[inst], 973 &aux_mask, 974 &aux_shift, 975 ctx->dc->caps.extended_aux_timeout_support); 976 977 return &aux_engine->base; 978 } 979 #define i2c_inst_regs(id) { I2C_HW_ENGINE_COMMON_REG_LIST_DCN30(id) } 980 981 static const struct dce_i2c_registers i2c_hw_regs[] = { 982 i2c_inst_regs(1), 983 i2c_inst_regs(2), 984 i2c_inst_regs(3), 985 i2c_inst_regs(4), 986 i2c_inst_regs(5), 987 }; 988 989 static const struct dce_i2c_shift i2c_shifts = { 990 I2C_COMMON_MASK_SH_LIST_DCN30(__SHIFT) 991 }; 992 993 static const struct dce_i2c_mask i2c_masks = { 994 I2C_COMMON_MASK_SH_LIST_DCN30(_MASK) 995 }; 996 997 static struct dce_i2c_hw *dcn31_i2c_hw_create( 998 struct dc_context *ctx, 999 uint32_t inst) 1000 { 1001 struct dce_i2c_hw *dce_i2c_hw = 1002 kzalloc(sizeof(struct dce_i2c_hw), GFP_KERNEL); 1003 1004 if (!dce_i2c_hw) 1005 return NULL; 1006 1007 dcn2_i2c_hw_construct(dce_i2c_hw, ctx, inst, 1008 &i2c_hw_regs[inst], &i2c_shifts, &i2c_masks); 1009 1010 return dce_i2c_hw; 1011 } 1012 static struct mpc *dcn31_mpc_create( 1013 struct dc_context *ctx, 1014 int num_mpcc, 1015 int num_rmu) 1016 { 1017 struct dcn30_mpc *mpc30 = kzalloc(sizeof(struct dcn30_mpc), 1018 GFP_KERNEL); 1019 1020 if (!mpc30) 1021 return NULL; 1022 1023 dcn30_mpc_construct(mpc30, ctx, 1024 &mpc_regs, 1025 &mpc_shift, 1026 &mpc_mask, 1027 num_mpcc, 1028 num_rmu); 1029 1030 return &mpc30->base; 1031 } 1032 1033 static struct hubbub *dcn31_hubbub_create(struct dc_context *ctx) 1034 { 1035 int i; 1036 1037 struct dcn20_hubbub *hubbub3 = kzalloc(sizeof(struct dcn20_hubbub), 1038 GFP_KERNEL); 1039 1040 if (!hubbub3) 1041 return NULL; 1042 1043 hubbub31_construct(hubbub3, ctx, 1044 &hubbub_reg, 1045 &hubbub_shift, 1046 &hubbub_mask, 1047 dcn3_16_ip.det_buffer_size_kbytes, 1048 dcn3_16_ip.pixel_chunk_size_kbytes, 1049 dcn3_16_ip.config_return_buffer_size_in_kbytes); 1050 1051 1052 for (i = 0; i < res_cap_dcn31.num_vmid; i++) { 1053 struct dcn20_vmid *vmid = &hubbub3->vmid[i]; 1054 1055 vmid->ctx = ctx; 1056 1057 vmid->regs = &vmid_regs[i]; 1058 vmid->shifts = &vmid_shifts; 1059 vmid->masks = &vmid_masks; 1060 } 1061 1062 return &hubbub3->base; 1063 } 1064 1065 static struct timing_generator *dcn31_timing_generator_create( 1066 struct dc_context *ctx, 1067 uint32_t instance) 1068 { 1069 struct optc *tgn10 = 1070 kzalloc(sizeof(struct optc), GFP_KERNEL); 1071 1072 if (!tgn10) 1073 return NULL; 1074 1075 tgn10->base.inst = instance; 1076 tgn10->base.ctx = ctx; 1077 1078 tgn10->tg_regs = &optc_regs[instance]; 1079 tgn10->tg_shift = &optc_shift; 1080 tgn10->tg_mask = &optc_mask; 1081 1082 dcn31_timing_generator_init(tgn10); 1083 1084 return &tgn10->base; 1085 } 1086 1087 static const struct encoder_feature_support link_enc_feature = { 1088 .max_hdmi_deep_color = COLOR_DEPTH_121212, 1089 .max_hdmi_pixel_clock = 600000, 1090 .hdmi_ycbcr420_supported = true, 1091 .dp_ycbcr420_supported = true, 1092 .fec_supported = true, 1093 .flags.bits.IS_HBR2_CAPABLE = true, 1094 .flags.bits.IS_HBR3_CAPABLE = true, 1095 .flags.bits.IS_TPS3_CAPABLE = true, 1096 .flags.bits.IS_TPS4_CAPABLE = true 1097 }; 1098 1099 static struct link_encoder *dcn31_link_encoder_create( 1100 struct dc_context *ctx, 1101 const struct encoder_init_data *enc_init_data) 1102 { 1103 struct dcn20_link_encoder *enc20 = 1104 kzalloc(sizeof(struct dcn20_link_encoder), GFP_KERNEL); 1105 1106 if (!enc20) 1107 return NULL; 1108 1109 dcn31_link_encoder_construct(enc20, 1110 enc_init_data, 1111 &link_enc_feature, 1112 &link_enc_regs[enc_init_data->transmitter], 1113 &link_enc_aux_regs[enc_init_data->channel - 1], 1114 &link_enc_hpd_regs[enc_init_data->hpd_source], 1115 &le_shift, 1116 &le_mask); 1117 1118 return &enc20->enc10.base; 1119 } 1120 1121 /* Create a minimal link encoder object not associated with a particular 1122 * physical connector. 1123 * resource_funcs.link_enc_create_minimal 1124 */ 1125 static struct link_encoder *dcn31_link_enc_create_minimal( 1126 struct dc_context *ctx, enum engine_id eng_id) 1127 { 1128 struct dcn20_link_encoder *enc20; 1129 1130 if ((eng_id - ENGINE_ID_DIGA) > ctx->dc->res_pool->res_cap->num_dig_link_enc) 1131 return NULL; 1132 1133 enc20 = kzalloc(sizeof(struct dcn20_link_encoder), GFP_KERNEL); 1134 if (!enc20) 1135 return NULL; 1136 1137 dcn31_link_encoder_construct_minimal( 1138 enc20, 1139 ctx, 1140 &link_enc_feature, 1141 &link_enc_regs[eng_id - ENGINE_ID_DIGA], 1142 eng_id); 1143 1144 return &enc20->enc10.base; 1145 } 1146 1147 static struct panel_cntl *dcn31_panel_cntl_create(const struct panel_cntl_init_data *init_data) 1148 { 1149 struct dcn31_panel_cntl *panel_cntl = 1150 kzalloc(sizeof(struct dcn31_panel_cntl), GFP_KERNEL); 1151 1152 if (!panel_cntl) 1153 return NULL; 1154 1155 dcn31_panel_cntl_construct(panel_cntl, init_data); 1156 1157 return &panel_cntl->base; 1158 } 1159 1160 static void read_dce_straps( 1161 struct dc_context *ctx, 1162 struct resource_straps *straps) 1163 { 1164 generic_reg_get(ctx, regDC_PINSTRAPS + BASE(regDC_PINSTRAPS_BASE_IDX), 1165 FN(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO), &straps->dc_pinstraps_audio); 1166 1167 } 1168 1169 static struct audio *dcn31_create_audio( 1170 struct dc_context *ctx, unsigned int inst) 1171 { 1172 return dce_audio_create(ctx, inst, 1173 &audio_regs[inst], &audio_shift, &audio_mask); 1174 } 1175 1176 static struct vpg *dcn31_vpg_create( 1177 struct dc_context *ctx, 1178 uint32_t inst) 1179 { 1180 struct dcn31_vpg *vpg31 = kzalloc(sizeof(struct dcn31_vpg), GFP_KERNEL); 1181 1182 if (!vpg31) 1183 return NULL; 1184 1185 vpg31_construct(vpg31, ctx, inst, 1186 &vpg_regs[inst], 1187 &vpg_shift, 1188 &vpg_mask); 1189 1190 return &vpg31->base; 1191 } 1192 1193 static struct afmt *dcn31_afmt_create( 1194 struct dc_context *ctx, 1195 uint32_t inst) 1196 { 1197 struct dcn31_afmt *afmt31 = kzalloc(sizeof(struct dcn31_afmt), GFP_KERNEL); 1198 1199 if (!afmt31) 1200 return NULL; 1201 1202 afmt31_construct(afmt31, ctx, inst, 1203 &afmt_regs[inst], 1204 &afmt_shift, 1205 &afmt_mask); 1206 1207 // Light sleep by default, no need to power down here 1208 1209 return &afmt31->base; 1210 } 1211 1212 1213 static struct apg *dcn31_apg_create( 1214 struct dc_context *ctx, 1215 uint32_t inst) 1216 { 1217 struct dcn31_apg *apg31 = kzalloc(sizeof(struct dcn31_apg), GFP_KERNEL); 1218 1219 if (!apg31) 1220 return NULL; 1221 1222 apg31_construct(apg31, ctx, inst, 1223 &apg_regs[inst], 1224 &apg_shift, 1225 &apg_mask); 1226 1227 return &apg31->base; 1228 } 1229 1230 1231 static struct stream_encoder *dcn316_stream_encoder_create( 1232 enum engine_id eng_id, 1233 struct dc_context *ctx) 1234 { 1235 struct dcn10_stream_encoder *enc1; 1236 struct vpg *vpg; 1237 struct afmt *afmt; 1238 int vpg_inst; 1239 int afmt_inst; 1240 1241 /* Mapping of VPG, AFMT, DME register blocks to DIO block instance */ 1242 if (eng_id <= ENGINE_ID_DIGF) { 1243 vpg_inst = eng_id; 1244 afmt_inst = eng_id; 1245 } else 1246 return NULL; 1247 1248 enc1 = kzalloc(sizeof(struct dcn10_stream_encoder), GFP_KERNEL); 1249 vpg = dcn31_vpg_create(ctx, vpg_inst); 1250 afmt = dcn31_afmt_create(ctx, afmt_inst); 1251 1252 if (!enc1 || !vpg || !afmt) { 1253 kfree(enc1); 1254 kfree(vpg); 1255 kfree(afmt); 1256 return NULL; 1257 } 1258 1259 dcn30_dio_stream_encoder_construct(enc1, ctx, ctx->dc_bios, 1260 eng_id, vpg, afmt, 1261 &stream_enc_regs[eng_id], 1262 &se_shift, &se_mask); 1263 1264 return &enc1->base; 1265 } 1266 1267 1268 static struct hpo_dp_stream_encoder *dcn31_hpo_dp_stream_encoder_create( 1269 enum engine_id eng_id, 1270 struct dc_context *ctx) 1271 { 1272 struct dcn31_hpo_dp_stream_encoder *hpo_dp_enc31; 1273 struct vpg *vpg; 1274 struct apg *apg; 1275 uint32_t hpo_dp_inst; 1276 uint32_t vpg_inst; 1277 uint32_t apg_inst; 1278 1279 ASSERT((eng_id >= ENGINE_ID_HPO_DP_0) && (eng_id <= ENGINE_ID_HPO_DP_3)); 1280 hpo_dp_inst = eng_id - ENGINE_ID_HPO_DP_0; 1281 1282 /* Mapping of VPG register blocks to HPO DP block instance: 1283 * VPG[6] -> HPO_DP[0] 1284 * VPG[7] -> HPO_DP[1] 1285 * VPG[8] -> HPO_DP[2] 1286 * VPG[9] -> HPO_DP[3] 1287 */ 1288 vpg_inst = hpo_dp_inst + 6; 1289 1290 /* Mapping of APG register blocks to HPO DP block instance: 1291 * APG[0] -> HPO_DP[0] 1292 * APG[1] -> HPO_DP[1] 1293 * APG[2] -> HPO_DP[2] 1294 * APG[3] -> HPO_DP[3] 1295 */ 1296 apg_inst = hpo_dp_inst; 1297 1298 /* allocate HPO stream encoder and create VPG sub-block */ 1299 hpo_dp_enc31 = kzalloc(sizeof(struct dcn31_hpo_dp_stream_encoder), GFP_KERNEL); 1300 vpg = dcn31_vpg_create(ctx, vpg_inst); 1301 apg = dcn31_apg_create(ctx, apg_inst); 1302 1303 if (!hpo_dp_enc31 || !vpg || !apg) { 1304 kfree(hpo_dp_enc31); 1305 kfree(vpg); 1306 kfree(apg); 1307 return NULL; 1308 } 1309 1310 dcn31_hpo_dp_stream_encoder_construct(hpo_dp_enc31, ctx, ctx->dc_bios, 1311 hpo_dp_inst, eng_id, vpg, apg, 1312 &hpo_dp_stream_enc_regs[hpo_dp_inst], 1313 &hpo_dp_se_shift, &hpo_dp_se_mask); 1314 1315 return &hpo_dp_enc31->base; 1316 } 1317 1318 static struct hpo_dp_link_encoder *dcn31_hpo_dp_link_encoder_create( 1319 uint8_t inst, 1320 struct dc_context *ctx) 1321 { 1322 struct dcn31_hpo_dp_link_encoder *hpo_dp_enc31; 1323 1324 /* allocate HPO link encoder */ 1325 hpo_dp_enc31 = kzalloc(sizeof(struct dcn31_hpo_dp_link_encoder), GFP_KERNEL); 1326 1327 hpo_dp_link_encoder31_construct(hpo_dp_enc31, ctx, inst, 1328 &hpo_dp_link_enc_regs[inst], 1329 &hpo_dp_le_shift, &hpo_dp_le_mask); 1330 1331 return &hpo_dp_enc31->base; 1332 } 1333 1334 1335 static struct dce_hwseq *dcn31_hwseq_create( 1336 struct dc_context *ctx) 1337 { 1338 struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_KERNEL); 1339 1340 if (hws) { 1341 hws->ctx = ctx; 1342 hws->regs = &hwseq_reg; 1343 hws->shifts = &hwseq_shift; 1344 hws->masks = &hwseq_mask; 1345 /* DCN3.1 FPGA Workaround 1346 * Need to enable HPO DP Stream Encoder before setting OTG master enable. 1347 * To do so, move calling function enable_stream_timing to only be done AFTER calling 1348 * function core_link_enable_stream 1349 */ 1350 if (IS_FPGA_MAXIMUS_DC(ctx->dce_environment)) 1351 hws->wa.dp_hpo_and_otg_sequence = true; 1352 } 1353 return hws; 1354 } 1355 static const struct resource_create_funcs res_create_funcs = { 1356 .read_dce_straps = read_dce_straps, 1357 .create_audio = dcn31_create_audio, 1358 .create_stream_encoder = dcn316_stream_encoder_create, 1359 .create_hpo_dp_stream_encoder = dcn31_hpo_dp_stream_encoder_create, 1360 .create_hpo_dp_link_encoder = dcn31_hpo_dp_link_encoder_create, 1361 .create_hwseq = dcn31_hwseq_create, 1362 }; 1363 1364 static const struct resource_create_funcs res_create_maximus_funcs = { 1365 .read_dce_straps = NULL, 1366 .create_audio = NULL, 1367 .create_stream_encoder = NULL, 1368 .create_hpo_dp_stream_encoder = dcn31_hpo_dp_stream_encoder_create, 1369 .create_hpo_dp_link_encoder = dcn31_hpo_dp_link_encoder_create, 1370 .create_hwseq = dcn31_hwseq_create, 1371 }; 1372 1373 static void dcn316_resource_destruct(struct dcn316_resource_pool *pool) 1374 { 1375 unsigned int i; 1376 1377 for (i = 0; i < pool->base.stream_enc_count; i++) { 1378 if (pool->base.stream_enc[i] != NULL) { 1379 if (pool->base.stream_enc[i]->vpg != NULL) { 1380 kfree(DCN30_VPG_FROM_VPG(pool->base.stream_enc[i]->vpg)); 1381 pool->base.stream_enc[i]->vpg = NULL; 1382 } 1383 if (pool->base.stream_enc[i]->afmt != NULL) { 1384 kfree(DCN30_AFMT_FROM_AFMT(pool->base.stream_enc[i]->afmt)); 1385 pool->base.stream_enc[i]->afmt = NULL; 1386 } 1387 kfree(DCN10STRENC_FROM_STRENC(pool->base.stream_enc[i])); 1388 pool->base.stream_enc[i] = NULL; 1389 } 1390 } 1391 1392 for (i = 0; i < pool->base.hpo_dp_stream_enc_count; i++) { 1393 if (pool->base.hpo_dp_stream_enc[i] != NULL) { 1394 if (pool->base.hpo_dp_stream_enc[i]->vpg != NULL) { 1395 kfree(DCN30_VPG_FROM_VPG(pool->base.hpo_dp_stream_enc[i]->vpg)); 1396 pool->base.hpo_dp_stream_enc[i]->vpg = NULL; 1397 } 1398 if (pool->base.hpo_dp_stream_enc[i]->apg != NULL) { 1399 kfree(DCN31_APG_FROM_APG(pool->base.hpo_dp_stream_enc[i]->apg)); 1400 pool->base.hpo_dp_stream_enc[i]->apg = NULL; 1401 } 1402 kfree(DCN3_1_HPO_DP_STREAM_ENC_FROM_HPO_STREAM_ENC(pool->base.hpo_dp_stream_enc[i])); 1403 pool->base.hpo_dp_stream_enc[i] = NULL; 1404 } 1405 } 1406 1407 for (i = 0; i < pool->base.hpo_dp_link_enc_count; i++) { 1408 if (pool->base.hpo_dp_link_enc[i] != NULL) { 1409 kfree(DCN3_1_HPO_DP_LINK_ENC_FROM_HPO_LINK_ENC(pool->base.hpo_dp_link_enc[i])); 1410 pool->base.hpo_dp_link_enc[i] = NULL; 1411 } 1412 } 1413 1414 for (i = 0; i < pool->base.res_cap->num_dsc; i++) { 1415 if (pool->base.dscs[i] != NULL) 1416 dcn20_dsc_destroy(&pool->base.dscs[i]); 1417 } 1418 1419 if (pool->base.mpc != NULL) { 1420 kfree(TO_DCN20_MPC(pool->base.mpc)); 1421 pool->base.mpc = NULL; 1422 } 1423 if (pool->base.hubbub != NULL) { 1424 kfree(pool->base.hubbub); 1425 pool->base.hubbub = NULL; 1426 } 1427 for (i = 0; i < pool->base.pipe_count; i++) { 1428 if (pool->base.dpps[i] != NULL) 1429 dcn31_dpp_destroy(&pool->base.dpps[i]); 1430 1431 if (pool->base.ipps[i] != NULL) 1432 pool->base.ipps[i]->funcs->ipp_destroy(&pool->base.ipps[i]); 1433 1434 if (pool->base.hubps[i] != NULL) { 1435 kfree(TO_DCN20_HUBP(pool->base.hubps[i])); 1436 pool->base.hubps[i] = NULL; 1437 } 1438 1439 if (pool->base.irqs != NULL) { 1440 dal_irq_service_destroy(&pool->base.irqs); 1441 } 1442 } 1443 1444 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { 1445 if (pool->base.engines[i] != NULL) 1446 dce110_engine_destroy(&pool->base.engines[i]); 1447 if (pool->base.hw_i2cs[i] != NULL) { 1448 kfree(pool->base.hw_i2cs[i]); 1449 pool->base.hw_i2cs[i] = NULL; 1450 } 1451 if (pool->base.sw_i2cs[i] != NULL) { 1452 kfree(pool->base.sw_i2cs[i]); 1453 pool->base.sw_i2cs[i] = NULL; 1454 } 1455 } 1456 1457 for (i = 0; i < pool->base.res_cap->num_opp; i++) { 1458 if (pool->base.opps[i] != NULL) 1459 pool->base.opps[i]->funcs->opp_destroy(&pool->base.opps[i]); 1460 } 1461 1462 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { 1463 if (pool->base.timing_generators[i] != NULL) { 1464 kfree(DCN10TG_FROM_TG(pool->base.timing_generators[i])); 1465 pool->base.timing_generators[i] = NULL; 1466 } 1467 } 1468 1469 for (i = 0; i < pool->base.res_cap->num_dwb; i++) { 1470 if (pool->base.dwbc[i] != NULL) { 1471 kfree(TO_DCN30_DWBC(pool->base.dwbc[i])); 1472 pool->base.dwbc[i] = NULL; 1473 } 1474 if (pool->base.mcif_wb[i] != NULL) { 1475 kfree(TO_DCN30_MMHUBBUB(pool->base.mcif_wb[i])); 1476 pool->base.mcif_wb[i] = NULL; 1477 } 1478 } 1479 1480 for (i = 0; i < pool->base.audio_count; i++) { 1481 if (pool->base.audios[i]) 1482 dce_aud_destroy(&pool->base.audios[i]); 1483 } 1484 1485 for (i = 0; i < pool->base.clk_src_count; i++) { 1486 if (pool->base.clock_sources[i] != NULL) { 1487 dcn20_clock_source_destroy(&pool->base.clock_sources[i]); 1488 pool->base.clock_sources[i] = NULL; 1489 } 1490 } 1491 1492 for (i = 0; i < pool->base.res_cap->num_mpc_3dlut; i++) { 1493 if (pool->base.mpc_lut[i] != NULL) { 1494 dc_3dlut_func_release(pool->base.mpc_lut[i]); 1495 pool->base.mpc_lut[i] = NULL; 1496 } 1497 if (pool->base.mpc_shaper[i] != NULL) { 1498 dc_transfer_func_release(pool->base.mpc_shaper[i]); 1499 pool->base.mpc_shaper[i] = NULL; 1500 } 1501 } 1502 1503 if (pool->base.dp_clock_source != NULL) { 1504 dcn20_clock_source_destroy(&pool->base.dp_clock_source); 1505 pool->base.dp_clock_source = NULL; 1506 } 1507 1508 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { 1509 if (pool->base.multiple_abms[i] != NULL) 1510 dce_abm_destroy(&pool->base.multiple_abms[i]); 1511 } 1512 1513 if (pool->base.psr != NULL) 1514 dmub_psr_destroy(&pool->base.psr); 1515 1516 if (pool->base.dccg != NULL) 1517 dcn_dccg_destroy(&pool->base.dccg); 1518 } 1519 1520 static struct hubp *dcn31_hubp_create( 1521 struct dc_context *ctx, 1522 uint32_t inst) 1523 { 1524 struct dcn20_hubp *hubp2 = 1525 kzalloc(sizeof(struct dcn20_hubp), GFP_KERNEL); 1526 1527 if (!hubp2) 1528 return NULL; 1529 1530 if (hubp31_construct(hubp2, ctx, inst, 1531 &hubp_regs[inst], &hubp_shift, &hubp_mask)) 1532 return &hubp2->base; 1533 1534 BREAK_TO_DEBUGGER(); 1535 kfree(hubp2); 1536 return NULL; 1537 } 1538 1539 static bool dcn31_dwbc_create(struct dc_context *ctx, struct resource_pool *pool) 1540 { 1541 int i; 1542 uint32_t pipe_count = pool->res_cap->num_dwb; 1543 1544 for (i = 0; i < pipe_count; i++) { 1545 struct dcn30_dwbc *dwbc30 = kzalloc(sizeof(struct dcn30_dwbc), 1546 GFP_KERNEL); 1547 1548 if (!dwbc30) { 1549 dm_error("DC: failed to create dwbc30!\n"); 1550 return false; 1551 } 1552 1553 dcn30_dwbc_construct(dwbc30, ctx, 1554 &dwbc30_regs[i], 1555 &dwbc30_shift, 1556 &dwbc30_mask, 1557 i); 1558 1559 pool->dwbc[i] = &dwbc30->base; 1560 } 1561 return true; 1562 } 1563 1564 static bool dcn31_mmhubbub_create(struct dc_context *ctx, struct resource_pool *pool) 1565 { 1566 int i; 1567 uint32_t pipe_count = pool->res_cap->num_dwb; 1568 1569 for (i = 0; i < pipe_count; i++) { 1570 struct dcn30_mmhubbub *mcif_wb30 = kzalloc(sizeof(struct dcn30_mmhubbub), 1571 GFP_KERNEL); 1572 1573 if (!mcif_wb30) { 1574 dm_error("DC: failed to create mcif_wb30!\n"); 1575 return false; 1576 } 1577 1578 dcn30_mmhubbub_construct(mcif_wb30, ctx, 1579 &mcif_wb30_regs[i], 1580 &mcif_wb30_shift, 1581 &mcif_wb30_mask, 1582 i); 1583 1584 pool->mcif_wb[i] = &mcif_wb30->base; 1585 } 1586 return true; 1587 } 1588 1589 static struct display_stream_compressor *dcn31_dsc_create( 1590 struct dc_context *ctx, uint32_t inst) 1591 { 1592 struct dcn20_dsc *dsc = 1593 kzalloc(sizeof(struct dcn20_dsc), GFP_KERNEL); 1594 1595 if (!dsc) { 1596 BREAK_TO_DEBUGGER(); 1597 return NULL; 1598 } 1599 1600 dsc2_construct(dsc, ctx, inst, &dsc_regs[inst], &dsc_shift, &dsc_mask); 1601 return &dsc->base; 1602 } 1603 1604 static void dcn316_destroy_resource_pool(struct resource_pool **pool) 1605 { 1606 struct dcn316_resource_pool *dcn31_pool = TO_DCN316_RES_POOL(*pool); 1607 1608 dcn316_resource_destruct(dcn31_pool); 1609 kfree(dcn31_pool); 1610 *pool = NULL; 1611 } 1612 1613 static struct clock_source *dcn31_clock_source_create( 1614 struct dc_context *ctx, 1615 struct dc_bios *bios, 1616 enum clock_source_id id, 1617 const struct dce110_clk_src_regs *regs, 1618 bool dp_clk_src) 1619 { 1620 struct dce110_clk_src *clk_src = 1621 kzalloc(sizeof(struct dce110_clk_src), GFP_KERNEL); 1622 1623 if (!clk_src) 1624 return NULL; 1625 1626 if (dcn31_clk_src_construct(clk_src, ctx, bios, id, 1627 regs, &cs_shift, &cs_mask)) { 1628 clk_src->base.dp_clk_src = dp_clk_src; 1629 return &clk_src->base; 1630 } 1631 1632 kfree(clk_src); 1633 1634 BREAK_TO_DEBUGGER(); 1635 return NULL; 1636 } 1637 1638 static bool is_dual_plane(enum surface_pixel_format format) 1639 { 1640 return format >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN || format == SURFACE_PIXEL_FORMAT_GRPH_RGBE_ALPHA; 1641 } 1642 1643 static int dcn316_populate_dml_pipes_from_context( 1644 struct dc *dc, struct dc_state *context, 1645 display_e2e_pipe_params_st *pipes, 1646 bool fast_validate) 1647 { 1648 int i, pipe_cnt; 1649 struct resource_context *res_ctx = &context->res_ctx; 1650 struct pipe_ctx *pipe; 1651 const int max_usable_det = context->bw_ctx.dml.ip.config_return_buffer_size_in_kbytes - DCN3_16_MIN_COMPBUF_SIZE_KB; 1652 1653 DC_FP_START(); 1654 dcn31x_populate_dml_pipes_from_context(dc, context, pipes, fast_validate); 1655 DC_FP_END(); 1656 1657 for (i = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) { 1658 struct dc_crtc_timing *timing; 1659 1660 if (!res_ctx->pipe_ctx[i].stream) 1661 continue; 1662 pipe = &res_ctx->pipe_ctx[i]; 1663 timing = &pipe->stream->timing; 1664 1665 /* 1666 * Immediate flip can be set dynamically after enabling the plane. 1667 * We need to require support for immediate flip or underflow can be 1668 * intermittently experienced depending on peak b/w requirements. 1669 */ 1670 pipes[pipe_cnt].pipe.src.immediate_flip = true; 1671 1672 pipes[pipe_cnt].pipe.src.unbounded_req_mode = false; 1673 pipes[pipe_cnt].pipe.dest.vfront_porch = timing->v_front_porch; 1674 pipes[pipe_cnt].pipe.src.dcc_rate = 3; 1675 pipes[pipe_cnt].dout.dsc_input_bpc = 0; 1676 DC_FP_START(); 1677 dcn31_zero_pipe_dcc_fraction(pipes, pipe_cnt); 1678 DC_FP_END(); 1679 1680 if (pipes[pipe_cnt].dout.dsc_enable) { 1681 switch (timing->display_color_depth) { 1682 case COLOR_DEPTH_888: 1683 pipes[pipe_cnt].dout.dsc_input_bpc = 8; 1684 break; 1685 case COLOR_DEPTH_101010: 1686 pipes[pipe_cnt].dout.dsc_input_bpc = 10; 1687 break; 1688 case COLOR_DEPTH_121212: 1689 pipes[pipe_cnt].dout.dsc_input_bpc = 12; 1690 break; 1691 default: 1692 ASSERT(0); 1693 break; 1694 } 1695 } 1696 1697 pipe_cnt++; 1698 } 1699 1700 if (pipe_cnt) 1701 context->bw_ctx.dml.ip.det_buffer_size_kbytes = 1702 (max_usable_det / DCN3_16_CRB_SEGMENT_SIZE_KB / pipe_cnt) * DCN3_16_CRB_SEGMENT_SIZE_KB; 1703 if (context->bw_ctx.dml.ip.det_buffer_size_kbytes > DCN3_16_MAX_DET_SIZE) 1704 context->bw_ctx.dml.ip.det_buffer_size_kbytes = DCN3_16_MAX_DET_SIZE; 1705 ASSERT(context->bw_ctx.dml.ip.det_buffer_size_kbytes >= DCN3_16_DEFAULT_DET_SIZE); 1706 dc->config.enable_4to1MPC = false; 1707 if (pipe_cnt == 1 && pipe->plane_state && !dc->debug.disable_z9_mpc) { 1708 if (is_dual_plane(pipe->plane_state->format) 1709 && pipe->plane_state->src_rect.width <= 1920 && pipe->plane_state->src_rect.height <= 1080) { 1710 dc->config.enable_4to1MPC = true; 1711 context->bw_ctx.dml.ip.det_buffer_size_kbytes = 1712 (max_usable_det / DCN3_16_CRB_SEGMENT_SIZE_KB / 4) * DCN3_16_CRB_SEGMENT_SIZE_KB; 1713 } else if (!is_dual_plane(pipe->plane_state->format)) { 1714 context->bw_ctx.dml.ip.det_buffer_size_kbytes = 192; 1715 pipes[0].pipe.src.unbounded_req_mode = true; 1716 } 1717 } 1718 1719 return pipe_cnt; 1720 } 1721 1722 static void dcn316_get_panel_config_defaults(struct dc_panel_config *panel_config) 1723 { 1724 *panel_config = panel_config_defaults; 1725 } 1726 1727 static struct dc_cap_funcs cap_funcs = { 1728 .get_dcc_compression_cap = dcn20_get_dcc_compression_cap 1729 }; 1730 1731 static struct resource_funcs dcn316_res_pool_funcs = { 1732 .destroy = dcn316_destroy_resource_pool, 1733 .link_enc_create = dcn31_link_encoder_create, 1734 .link_enc_create_minimal = dcn31_link_enc_create_minimal, 1735 .link_encs_assign = link_enc_cfg_link_encs_assign, 1736 .link_enc_unassign = link_enc_cfg_link_enc_unassign, 1737 .panel_cntl_create = dcn31_panel_cntl_create, 1738 .validate_bandwidth = dcn31_validate_bandwidth, 1739 .calculate_wm_and_dlg = dcn31_calculate_wm_and_dlg, 1740 .update_soc_for_wm_a = dcn31_update_soc_for_wm_a, 1741 .populate_dml_pipes = dcn316_populate_dml_pipes_from_context, 1742 .acquire_idle_pipe_for_layer = dcn20_acquire_idle_pipe_for_layer, 1743 .add_stream_to_ctx = dcn30_add_stream_to_ctx, 1744 .add_dsc_to_stream_resource = dcn20_add_dsc_to_stream_resource, 1745 .remove_stream_from_ctx = dcn20_remove_stream_from_ctx, 1746 .populate_dml_writeback_from_context = dcn31_populate_dml_writeback_from_context, 1747 .set_mcif_arb_params = dcn31_set_mcif_arb_params, 1748 .find_first_free_match_stream_enc_for_link = dcn10_find_first_free_match_stream_enc_for_link, 1749 .acquire_post_bldn_3dlut = dcn30_acquire_post_bldn_3dlut, 1750 .release_post_bldn_3dlut = dcn30_release_post_bldn_3dlut, 1751 .update_bw_bounding_box = dcn316_update_bw_bounding_box, 1752 .patch_unknown_plane_state = dcn20_patch_unknown_plane_state, 1753 .get_panel_config_defaults = dcn316_get_panel_config_defaults, 1754 }; 1755 1756 static bool dcn316_resource_construct( 1757 uint8_t num_virtual_links, 1758 struct dc *dc, 1759 struct dcn316_resource_pool *pool) 1760 { 1761 int i; 1762 struct dc_context *ctx = dc->ctx; 1763 struct irq_service_init_data init_data; 1764 1765 ctx->dc_bios->regs = &bios_regs; 1766 1767 pool->base.res_cap = &res_cap_dcn31; 1768 1769 pool->base.funcs = &dcn316_res_pool_funcs; 1770 1771 /************************************************* 1772 * Resource + asic cap harcoding * 1773 *************************************************/ 1774 pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE; 1775 pool->base.pipe_count = pool->base.res_cap->num_timing_generator; 1776 pool->base.mpcc_count = pool->base.res_cap->num_timing_generator; 1777 dc->caps.max_downscale_ratio = 600; 1778 dc->caps.i2c_speed_in_khz = 100; 1779 dc->caps.i2c_speed_in_khz_hdcp = 100; 1780 dc->caps.max_cursor_size = 256; 1781 dc->caps.min_horizontal_blanking_period = 80; 1782 dc->caps.dmdata_alloc_size = 2048; 1783 dc->caps.max_slave_planes = 2; 1784 dc->caps.max_slave_yuv_planes = 2; 1785 dc->caps.max_slave_rgb_planes = 2; 1786 dc->caps.post_blend_color_processing = true; 1787 dc->caps.force_dp_tps4_for_cp2520 = true; 1788 if (dc->config.forceHBR2CP2520) 1789 dc->caps.force_dp_tps4_for_cp2520 = false; 1790 dc->caps.dp_hpo = true; 1791 dc->caps.dp_hdmi21_pcon_support = true; 1792 dc->caps.edp_dsc_support = true; 1793 dc->caps.extended_aux_timeout_support = true; 1794 dc->caps.dmcub_support = true; 1795 dc->caps.is_apu = true; 1796 1797 /* Color pipeline capabilities */ 1798 dc->caps.color.dpp.dcn_arch = 1; 1799 dc->caps.color.dpp.input_lut_shared = 0; 1800 dc->caps.color.dpp.icsc = 1; 1801 dc->caps.color.dpp.dgam_ram = 0; // must use gamma_corr 1802 dc->caps.color.dpp.dgam_rom_caps.srgb = 1; 1803 dc->caps.color.dpp.dgam_rom_caps.bt2020 = 1; 1804 dc->caps.color.dpp.dgam_rom_caps.gamma2_2 = 1; 1805 dc->caps.color.dpp.dgam_rom_caps.pq = 1; 1806 dc->caps.color.dpp.dgam_rom_caps.hlg = 1; 1807 dc->caps.color.dpp.post_csc = 1; 1808 dc->caps.color.dpp.gamma_corr = 1; 1809 dc->caps.color.dpp.dgam_rom_for_yuv = 0; 1810 1811 dc->caps.color.dpp.hw_3d_lut = 1; 1812 dc->caps.color.dpp.ogam_ram = 1; 1813 // no OGAM ROM on DCN301 1814 dc->caps.color.dpp.ogam_rom_caps.srgb = 0; 1815 dc->caps.color.dpp.ogam_rom_caps.bt2020 = 0; 1816 dc->caps.color.dpp.ogam_rom_caps.gamma2_2 = 0; 1817 dc->caps.color.dpp.ogam_rom_caps.pq = 0; 1818 dc->caps.color.dpp.ogam_rom_caps.hlg = 0; 1819 dc->caps.color.dpp.ocsc = 0; 1820 1821 dc->caps.color.mpc.gamut_remap = 1; 1822 dc->caps.color.mpc.num_3dluts = pool->base.res_cap->num_mpc_3dlut; //2 1823 dc->caps.color.mpc.ogam_ram = 1; 1824 dc->caps.color.mpc.ogam_rom_caps.srgb = 0; 1825 dc->caps.color.mpc.ogam_rom_caps.bt2020 = 0; 1826 dc->caps.color.mpc.ogam_rom_caps.gamma2_2 = 0; 1827 dc->caps.color.mpc.ogam_rom_caps.pq = 0; 1828 dc->caps.color.mpc.ogam_rom_caps.hlg = 0; 1829 dc->caps.color.mpc.ocsc = 1; 1830 1831 /* read VBIOS LTTPR caps */ 1832 { 1833 if (ctx->dc_bios->funcs->get_lttpr_caps) { 1834 enum bp_result bp_query_result; 1835 uint8_t is_vbios_lttpr_enable = 0; 1836 1837 bp_query_result = ctx->dc_bios->funcs->get_lttpr_caps(ctx->dc_bios, &is_vbios_lttpr_enable); 1838 dc->caps.vbios_lttpr_enable = (bp_query_result == BP_RESULT_OK) && !!is_vbios_lttpr_enable; 1839 } 1840 1841 /* interop bit is implicit */ 1842 { 1843 dc->caps.vbios_lttpr_aware = true; 1844 } 1845 } 1846 1847 if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV) 1848 dc->debug = debug_defaults_drv; 1849 else if (dc->ctx->dce_environment == DCE_ENV_FPGA_MAXIMUS) { 1850 dc->debug = debug_defaults_diags; 1851 } else 1852 dc->debug = debug_defaults_diags; 1853 // Init the vm_helper 1854 if (dc->vm_helper) 1855 vm_helper_init(dc->vm_helper, 16); 1856 1857 /************************************************* 1858 * Create resources * 1859 *************************************************/ 1860 1861 /* Clock Sources for Pixel Clock*/ 1862 pool->base.clock_sources[DCN31_CLK_SRC_PLL0] = 1863 dcn31_clock_source_create(ctx, ctx->dc_bios, 1864 CLOCK_SOURCE_COMBO_PHY_PLL0, 1865 &clk_src_regs[0], false); 1866 pool->base.clock_sources[DCN31_CLK_SRC_PLL1] = 1867 dcn31_clock_source_create(ctx, ctx->dc_bios, 1868 CLOCK_SOURCE_COMBO_PHY_PLL1, 1869 &clk_src_regs[1], false); 1870 pool->base.clock_sources[DCN31_CLK_SRC_PLL2] = 1871 dcn31_clock_source_create(ctx, ctx->dc_bios, 1872 CLOCK_SOURCE_COMBO_PHY_PLL2, 1873 &clk_src_regs[2], false); 1874 pool->base.clock_sources[DCN31_CLK_SRC_PLL3] = 1875 dcn31_clock_source_create(ctx, ctx->dc_bios, 1876 CLOCK_SOURCE_COMBO_PHY_PLL3, 1877 &clk_src_regs[3], false); 1878 pool->base.clock_sources[DCN31_CLK_SRC_PLL4] = 1879 dcn31_clock_source_create(ctx, ctx->dc_bios, 1880 CLOCK_SOURCE_COMBO_PHY_PLL4, 1881 &clk_src_regs[4], false); 1882 1883 pool->base.clk_src_count = DCN30_CLK_SRC_TOTAL; 1884 1885 /* todo: not reuse phy_pll registers */ 1886 pool->base.dp_clock_source = 1887 dcn31_clock_source_create(ctx, ctx->dc_bios, 1888 CLOCK_SOURCE_ID_DP_DTO, 1889 &clk_src_regs[0], true); 1890 1891 for (i = 0; i < pool->base.clk_src_count; i++) { 1892 if (pool->base.clock_sources[i] == NULL) { 1893 dm_error("DC: failed to create clock sources!\n"); 1894 BREAK_TO_DEBUGGER(); 1895 goto create_fail; 1896 } 1897 } 1898 1899 /* TODO: DCCG */ 1900 pool->base.dccg = dccg31_create(ctx, &dccg_regs, &dccg_shift, &dccg_mask); 1901 if (pool->base.dccg == NULL) { 1902 dm_error("DC: failed to create dccg!\n"); 1903 BREAK_TO_DEBUGGER(); 1904 goto create_fail; 1905 } 1906 1907 /* TODO: IRQ */ 1908 init_data.ctx = dc->ctx; 1909 pool->base.irqs = dal_irq_service_dcn31_create(&init_data); 1910 if (!pool->base.irqs) 1911 goto create_fail; 1912 1913 /* HUBBUB */ 1914 pool->base.hubbub = dcn31_hubbub_create(ctx); 1915 if (pool->base.hubbub == NULL) { 1916 BREAK_TO_DEBUGGER(); 1917 dm_error("DC: failed to create hubbub!\n"); 1918 goto create_fail; 1919 } 1920 1921 /* HUBPs, DPPs, OPPs and TGs */ 1922 for (i = 0; i < pool->base.pipe_count; i++) { 1923 pool->base.hubps[i] = dcn31_hubp_create(ctx, i); 1924 if (pool->base.hubps[i] == NULL) { 1925 BREAK_TO_DEBUGGER(); 1926 dm_error( 1927 "DC: failed to create hubps!\n"); 1928 goto create_fail; 1929 } 1930 1931 pool->base.dpps[i] = dcn31_dpp_create(ctx, i); 1932 if (pool->base.dpps[i] == NULL) { 1933 BREAK_TO_DEBUGGER(); 1934 dm_error( 1935 "DC: failed to create dpps!\n"); 1936 goto create_fail; 1937 } 1938 } 1939 1940 for (i = 0; i < pool->base.res_cap->num_opp; i++) { 1941 pool->base.opps[i] = dcn31_opp_create(ctx, i); 1942 if (pool->base.opps[i] == NULL) { 1943 BREAK_TO_DEBUGGER(); 1944 dm_error( 1945 "DC: failed to create output pixel processor!\n"); 1946 goto create_fail; 1947 } 1948 } 1949 1950 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { 1951 pool->base.timing_generators[i] = dcn31_timing_generator_create( 1952 ctx, i); 1953 if (pool->base.timing_generators[i] == NULL) { 1954 BREAK_TO_DEBUGGER(); 1955 dm_error("DC: failed to create tg!\n"); 1956 goto create_fail; 1957 } 1958 } 1959 pool->base.timing_generator_count = i; 1960 1961 /* PSR */ 1962 pool->base.psr = dmub_psr_create(ctx); 1963 if (pool->base.psr == NULL) { 1964 dm_error("DC: failed to create psr obj!\n"); 1965 BREAK_TO_DEBUGGER(); 1966 goto create_fail; 1967 } 1968 1969 /* ABM */ 1970 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { 1971 pool->base.multiple_abms[i] = dmub_abm_create(ctx, 1972 &abm_regs[i], 1973 &abm_shift, 1974 &abm_mask); 1975 if (pool->base.multiple_abms[i] == NULL) { 1976 dm_error("DC: failed to create abm for pipe %d!\n", i); 1977 BREAK_TO_DEBUGGER(); 1978 goto create_fail; 1979 } 1980 } 1981 1982 /* MPC and DSC */ 1983 pool->base.mpc = dcn31_mpc_create(ctx, pool->base.mpcc_count, pool->base.res_cap->num_mpc_3dlut); 1984 if (pool->base.mpc == NULL) { 1985 BREAK_TO_DEBUGGER(); 1986 dm_error("DC: failed to create mpc!\n"); 1987 goto create_fail; 1988 } 1989 1990 for (i = 0; i < pool->base.res_cap->num_dsc; i++) { 1991 pool->base.dscs[i] = dcn31_dsc_create(ctx, i); 1992 if (pool->base.dscs[i] == NULL) { 1993 BREAK_TO_DEBUGGER(); 1994 dm_error("DC: failed to create display stream compressor %d!\n", i); 1995 goto create_fail; 1996 } 1997 } 1998 1999 /* DWB and MMHUBBUB */ 2000 if (!dcn31_dwbc_create(ctx, &pool->base)) { 2001 BREAK_TO_DEBUGGER(); 2002 dm_error("DC: failed to create dwbc!\n"); 2003 goto create_fail; 2004 } 2005 2006 if (!dcn31_mmhubbub_create(ctx, &pool->base)) { 2007 BREAK_TO_DEBUGGER(); 2008 dm_error("DC: failed to create mcif_wb!\n"); 2009 goto create_fail; 2010 } 2011 2012 /* AUX and I2C */ 2013 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { 2014 pool->base.engines[i] = dcn31_aux_engine_create(ctx, i); 2015 if (pool->base.engines[i] == NULL) { 2016 BREAK_TO_DEBUGGER(); 2017 dm_error( 2018 "DC:failed to create aux engine!!\n"); 2019 goto create_fail; 2020 } 2021 pool->base.hw_i2cs[i] = dcn31_i2c_hw_create(ctx, i); 2022 if (pool->base.hw_i2cs[i] == NULL) { 2023 BREAK_TO_DEBUGGER(); 2024 dm_error( 2025 "DC:failed to create hw i2c!!\n"); 2026 goto create_fail; 2027 } 2028 pool->base.sw_i2cs[i] = NULL; 2029 } 2030 2031 /* Audio, Stream Encoders including HPO and virtual, MPC 3D LUTs */ 2032 if (!resource_construct(num_virtual_links, dc, &pool->base, 2033 (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment) ? 2034 &res_create_funcs : &res_create_maximus_funcs))) 2035 goto create_fail; 2036 2037 /* HW Sequencer and Plane caps */ 2038 dcn31_hw_sequencer_construct(dc); 2039 2040 dc->caps.max_planes = pool->base.pipe_count; 2041 2042 for (i = 0; i < dc->caps.max_planes; ++i) 2043 dc->caps.planes[i] = plane_cap; 2044 2045 dc->cap_funcs = cap_funcs; 2046 2047 dc->dcn_ip->max_num_dpp = dcn3_16_ip.max_num_dpp; 2048 2049 return true; 2050 2051 create_fail: 2052 2053 dcn316_resource_destruct(pool); 2054 2055 return false; 2056 } 2057 2058 struct resource_pool *dcn316_create_resource_pool( 2059 const struct dc_init_data *init_data, 2060 struct dc *dc) 2061 { 2062 struct dcn316_resource_pool *pool = 2063 kzalloc(sizeof(struct dcn316_resource_pool), GFP_KERNEL); 2064 2065 if (!pool) 2066 return NULL; 2067 2068 if (dcn316_resource_construct(init_data->num_virtual_links, dc, pool)) 2069 return &pool->base; 2070 2071 BREAK_TO_DEBUGGER(); 2072 kfree(pool); 2073 return NULL; 2074 } 2075