1 /* 2 * Copyright 2021 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 27 #include "dm_services.h" 28 #include "dc.h" 29 30 #include "dcn31/dcn31_init.h" 31 32 #include "resource.h" 33 #include "include/irq_service_interface.h" 34 #include "dcn316_resource.h" 35 36 #include "dcn20/dcn20_resource.h" 37 #include "dcn30/dcn30_resource.h" 38 #include "dcn31/dcn31_resource.h" 39 40 #include "dcn10/dcn10_ipp.h" 41 #include "dcn30/dcn30_hubbub.h" 42 #include "dcn31/dcn31_hubbub.h" 43 #include "dcn30/dcn30_mpc.h" 44 #include "dcn31/dcn31_hubp.h" 45 #include "irq/dcn31/irq_service_dcn31.h" 46 #include "dcn30/dcn30_dpp.h" 47 #include "dcn31/dcn31_optc.h" 48 #include "dcn20/dcn20_hwseq.h" 49 #include "dcn30/dcn30_hwseq.h" 50 #include "dce110/dce110_hw_sequencer.h" 51 #include "dcn30/dcn30_opp.h" 52 #include "dcn20/dcn20_dsc.h" 53 #include "dcn30/dcn30_vpg.h" 54 #include "dcn30/dcn30_afmt.h" 55 #include "dcn30/dcn30_dio_stream_encoder.h" 56 #include "dcn31/dcn31_hpo_dp_stream_encoder.h" 57 #include "dcn31/dcn31_hpo_dp_link_encoder.h" 58 #include "dcn31/dcn31_apg.h" 59 #include "dcn31/dcn31_dio_link_encoder.h" 60 #include "dcn31/dcn31_vpg.h" 61 #include "dcn31/dcn31_afmt.h" 62 #include "dce/dce_clock_source.h" 63 #include "dce/dce_audio.h" 64 #include "dce/dce_hwseq.h" 65 #include "clk_mgr.h" 66 #include "virtual/virtual_stream_encoder.h" 67 #include "dce110/dce110_resource.h" 68 #include "dml/display_mode_vba.h" 69 #include "dml/dcn31/dcn31_fpu.h" 70 #include "dcn31/dcn31_dccg.h" 71 #include "dcn10/dcn10_resource.h" 72 #include "dcn31/dcn31_panel_cntl.h" 73 74 #include "dcn30/dcn30_dwb.h" 75 #include "dcn30/dcn30_mmhubbub.h" 76 77 #include "dcn/dcn_3_1_6_offset.h" 78 #include "dcn/dcn_3_1_6_sh_mask.h" 79 #include "dpcs/dpcs_4_2_3_offset.h" 80 #include "dpcs/dpcs_4_2_3_sh_mask.h" 81 82 #define regBIF_BX1_BIOS_SCRATCH_2 0x003a 83 #define regBIF_BX1_BIOS_SCRATCH_2_BASE_IDX 1 84 #define regBIF_BX1_BIOS_SCRATCH_3 0x003b 85 #define regBIF_BX1_BIOS_SCRATCH_3_BASE_IDX 1 86 #define regBIF_BX1_BIOS_SCRATCH_6 0x003e 87 #define regBIF_BX1_BIOS_SCRATCH_6_BASE_IDX 1 88 89 #define regDCHUBBUB_DEBUG_CTRL_0 0x04d6 90 #define regDCHUBBUB_DEBUG_CTRL_0_BASE_IDX 2 91 #define DCHUBBUB_DEBUG_CTRL_0__DET_DEPTH__SHIFT 0x10 92 #define DCHUBBUB_DEBUG_CTRL_0__DET_DEPTH_MASK 0x01FF0000L 93 94 #define DCN_BASE__INST0_SEG0 0x00000012 95 #define DCN_BASE__INST0_SEG1 0x000000C0 96 #define DCN_BASE__INST0_SEG2 0x000034C0 97 #define DCN_BASE__INST0_SEG3 0x00009000 98 #define DCN_BASE__INST0_SEG4 0x02403C00 99 #define DCN_BASE__INST0_SEG5 0 100 101 #define DPCS_BASE__INST0_SEG0 0x00000012 102 #define DPCS_BASE__INST0_SEG1 0x000000C0 103 #define DPCS_BASE__INST0_SEG2 0x000034C0 104 #define DPCS_BASE__INST0_SEG3 0x00009000 105 #define DPCS_BASE__INST0_SEG4 0x02403C00 106 #define DPCS_BASE__INST0_SEG5 0 107 108 #define NBIO_BASE__INST0_SEG0 0x00000000 109 #define NBIO_BASE__INST0_SEG1 0x00000014 110 #define NBIO_BASE__INST0_SEG2 0x00000D20 111 #define NBIO_BASE__INST0_SEG3 0x00010400 112 #define NBIO_BASE__INST0_SEG4 0x0241B000 113 #define NBIO_BASE__INST0_SEG5 0x04040000 114 115 #include "reg_helper.h" 116 #include "dce/dmub_abm.h" 117 #include "dce/dmub_psr.h" 118 #include "dce/dce_aux.h" 119 #include "dce/dce_i2c.h" 120 121 #include "dml/dcn30/display_mode_vba_30.h" 122 #include "vm_helper.h" 123 #include "dcn20/dcn20_vmid.h" 124 125 #include "link_enc_cfg.h" 126 127 #define DCN3_16_MAX_DET_SIZE 384 128 #define DCN3_16_MIN_COMPBUF_SIZE_KB 128 129 #define DCN3_16_CRB_SEGMENT_SIZE_KB 64 130 131 enum dcn31_clk_src_array_id { 132 DCN31_CLK_SRC_PLL0, 133 DCN31_CLK_SRC_PLL1, 134 DCN31_CLK_SRC_PLL2, 135 DCN31_CLK_SRC_PLL3, 136 DCN31_CLK_SRC_PLL4, 137 DCN30_CLK_SRC_TOTAL 138 }; 139 140 /* begin ********************* 141 * macros to expend register list macro defined in HW object header file 142 */ 143 144 /* DCN */ 145 /* TODO awful hack. fixup dcn20_dwb.h */ 146 #undef BASE_INNER 147 #define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg 148 149 #define BASE(seg) BASE_INNER(seg) 150 151 #define SR(reg_name)\ 152 .reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \ 153 reg ## reg_name 154 155 #define SRI(reg_name, block, id)\ 156 .reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 157 reg ## block ## id ## _ ## reg_name 158 159 #define SRI2(reg_name, block, id)\ 160 .reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \ 161 reg ## reg_name 162 163 #define SRIR(var_name, reg_name, block, id)\ 164 .var_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 165 reg ## block ## id ## _ ## reg_name 166 167 #define SRII(reg_name, block, id)\ 168 .reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 169 reg ## block ## id ## _ ## reg_name 170 171 #define SRII_MPC_RMU(reg_name, block, id)\ 172 .RMU##_##reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 173 reg ## block ## id ## _ ## reg_name 174 175 #define SRII_DWB(reg_name, temp_name, block, id)\ 176 .reg_name[id] = BASE(reg ## block ## id ## _ ## temp_name ## _BASE_IDX) + \ 177 reg ## block ## id ## _ ## temp_name 178 179 #define DCCG_SRII(reg_name, block, id)\ 180 .block ## _ ## reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 181 reg ## block ## id ## _ ## reg_name 182 183 #define VUPDATE_SRII(reg_name, block, id)\ 184 .reg_name[id] = BASE(reg ## reg_name ## _ ## block ## id ## _BASE_IDX) + \ 185 reg ## reg_name ## _ ## block ## id 186 187 /* NBIO */ 188 #define NBIO_BASE_INNER(seg) \ 189 NBIO_BASE__INST0_SEG ## seg 190 191 #define NBIO_BASE(seg) \ 192 NBIO_BASE_INNER(seg) 193 194 #define NBIO_SR(reg_name)\ 195 .reg_name = NBIO_BASE(regBIF_BX1_ ## reg_name ## _BASE_IDX) + \ 196 regBIF_BX1_ ## reg_name 197 198 static const struct bios_registers bios_regs = { 199 NBIO_SR(BIOS_SCRATCH_3), 200 NBIO_SR(BIOS_SCRATCH_6) 201 }; 202 203 #define clk_src_regs(index, pllid)\ 204 [index] = {\ 205 CS_COMMON_REG_LIST_DCN3_0(index, pllid),\ 206 } 207 208 static const struct dce110_clk_src_regs clk_src_regs[] = { 209 clk_src_regs(0, A), 210 clk_src_regs(1, B), 211 clk_src_regs(2, C), 212 clk_src_regs(3, D), 213 clk_src_regs(4, E) 214 }; 215 216 static const struct dce110_clk_src_shift cs_shift = { 217 CS_COMMON_MASK_SH_LIST_DCN2_0(__SHIFT) 218 }; 219 220 static const struct dce110_clk_src_mask cs_mask = { 221 CS_COMMON_MASK_SH_LIST_DCN2_0(_MASK) 222 }; 223 224 #define abm_regs(id)\ 225 [id] = {\ 226 ABM_DCN302_REG_LIST(id)\ 227 } 228 229 static const struct dce_abm_registers abm_regs[] = { 230 abm_regs(0), 231 abm_regs(1), 232 abm_regs(2), 233 abm_regs(3), 234 }; 235 236 static const struct dce_abm_shift abm_shift = { 237 ABM_MASK_SH_LIST_DCN30(__SHIFT) 238 }; 239 240 static const struct dce_abm_mask abm_mask = { 241 ABM_MASK_SH_LIST_DCN30(_MASK) 242 }; 243 244 #define audio_regs(id)\ 245 [id] = {\ 246 AUD_COMMON_REG_LIST(id)\ 247 } 248 249 static const struct dce_audio_registers audio_regs[] = { 250 audio_regs(0), 251 audio_regs(1), 252 audio_regs(2), 253 audio_regs(3), 254 audio_regs(4), 255 audio_regs(5), 256 audio_regs(6) 257 }; 258 259 #define DCE120_AUD_COMMON_MASK_SH_LIST(mask_sh)\ 260 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX, AZALIA_ENDPOINT_REG_INDEX, mask_sh),\ 261 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA, AZALIA_ENDPOINT_REG_DATA, mask_sh),\ 262 AUD_COMMON_MASK_SH_LIST_BASE(mask_sh) 263 264 static const struct dce_audio_shift audio_shift = { 265 DCE120_AUD_COMMON_MASK_SH_LIST(__SHIFT) 266 }; 267 268 static const struct dce_audio_mask audio_mask = { 269 DCE120_AUD_COMMON_MASK_SH_LIST(_MASK) 270 }; 271 272 #define vpg_regs(id)\ 273 [id] = {\ 274 VPG_DCN31_REG_LIST(id)\ 275 } 276 277 static const struct dcn31_vpg_registers vpg_regs[] = { 278 vpg_regs(0), 279 vpg_regs(1), 280 vpg_regs(2), 281 vpg_regs(3), 282 vpg_regs(4), 283 vpg_regs(5), 284 vpg_regs(6), 285 vpg_regs(7), 286 vpg_regs(8), 287 vpg_regs(9), 288 }; 289 290 static const struct dcn31_vpg_shift vpg_shift = { 291 DCN31_VPG_MASK_SH_LIST(__SHIFT) 292 }; 293 294 static const struct dcn31_vpg_mask vpg_mask = { 295 DCN31_VPG_MASK_SH_LIST(_MASK) 296 }; 297 298 #define afmt_regs(id)\ 299 [id] = {\ 300 AFMT_DCN31_REG_LIST(id)\ 301 } 302 303 static const struct dcn31_afmt_registers afmt_regs[] = { 304 afmt_regs(0), 305 afmt_regs(1), 306 afmt_regs(2), 307 afmt_regs(3), 308 afmt_regs(4), 309 afmt_regs(5) 310 }; 311 312 static const struct dcn31_afmt_shift afmt_shift = { 313 DCN31_AFMT_MASK_SH_LIST(__SHIFT) 314 }; 315 316 static const struct dcn31_afmt_mask afmt_mask = { 317 DCN31_AFMT_MASK_SH_LIST(_MASK) 318 }; 319 320 321 #define apg_regs(id)\ 322 [id] = {\ 323 APG_DCN31_REG_LIST(id)\ 324 } 325 326 static const struct dcn31_apg_registers apg_regs[] = { 327 apg_regs(0), 328 apg_regs(1), 329 apg_regs(2), 330 apg_regs(3) 331 }; 332 333 static const struct dcn31_apg_shift apg_shift = { 334 DCN31_APG_MASK_SH_LIST(__SHIFT) 335 }; 336 337 static const struct dcn31_apg_mask apg_mask = { 338 DCN31_APG_MASK_SH_LIST(_MASK) 339 }; 340 341 342 #define stream_enc_regs(id)\ 343 [id] = {\ 344 SE_DCN3_REG_LIST(id)\ 345 } 346 347 static const struct dcn10_stream_enc_registers stream_enc_regs[] = { 348 stream_enc_regs(0), 349 stream_enc_regs(1), 350 stream_enc_regs(2), 351 stream_enc_regs(3), 352 stream_enc_regs(4) 353 }; 354 355 static const struct dcn10_stream_encoder_shift se_shift = { 356 SE_COMMON_MASK_SH_LIST_DCN30(__SHIFT) 357 }; 358 359 static const struct dcn10_stream_encoder_mask se_mask = { 360 SE_COMMON_MASK_SH_LIST_DCN30(_MASK) 361 }; 362 363 364 #define aux_regs(id)\ 365 [id] = {\ 366 DCN2_AUX_REG_LIST(id)\ 367 } 368 369 static const struct dcn10_link_enc_aux_registers link_enc_aux_regs[] = { 370 aux_regs(0), 371 aux_regs(1), 372 aux_regs(2), 373 aux_regs(3), 374 aux_regs(4) 375 }; 376 377 #define hpd_regs(id)\ 378 [id] = {\ 379 HPD_REG_LIST(id)\ 380 } 381 382 static const struct dcn10_link_enc_hpd_registers link_enc_hpd_regs[] = { 383 hpd_regs(0), 384 hpd_regs(1), 385 hpd_regs(2), 386 hpd_regs(3), 387 hpd_regs(4) 388 }; 389 390 #define link_regs(id, phyid)\ 391 [id] = {\ 392 LE_DCN31_REG_LIST(id), \ 393 UNIPHY_DCN2_REG_LIST(phyid), \ 394 DPCS_DCN31_REG_LIST(id), \ 395 } 396 397 static const struct dce110_aux_registers_shift aux_shift = { 398 DCN_AUX_MASK_SH_LIST(__SHIFT) 399 }; 400 401 static const struct dce110_aux_registers_mask aux_mask = { 402 DCN_AUX_MASK_SH_LIST(_MASK) 403 }; 404 405 static const struct dcn10_link_enc_registers link_enc_regs[] = { 406 link_regs(0, A), 407 link_regs(1, B), 408 link_regs(2, C), 409 link_regs(3, D), 410 link_regs(4, E) 411 }; 412 413 static const struct dcn10_link_enc_shift le_shift = { 414 LINK_ENCODER_MASK_SH_LIST_DCN31(__SHIFT), \ 415 DPCS_DCN31_MASK_SH_LIST(__SHIFT) 416 }; 417 418 static const struct dcn10_link_enc_mask le_mask = { 419 LINK_ENCODER_MASK_SH_LIST_DCN31(_MASK), \ 420 DPCS_DCN31_MASK_SH_LIST(_MASK) 421 }; 422 423 424 425 #define hpo_dp_stream_encoder_reg_list(id)\ 426 [id] = {\ 427 DCN3_1_HPO_DP_STREAM_ENC_REG_LIST(id)\ 428 } 429 430 static const struct dcn31_hpo_dp_stream_encoder_registers hpo_dp_stream_enc_regs[] = { 431 hpo_dp_stream_encoder_reg_list(0), 432 hpo_dp_stream_encoder_reg_list(1), 433 hpo_dp_stream_encoder_reg_list(2), 434 hpo_dp_stream_encoder_reg_list(3), 435 }; 436 437 static const struct dcn31_hpo_dp_stream_encoder_shift hpo_dp_se_shift = { 438 DCN3_1_HPO_DP_STREAM_ENC_MASK_SH_LIST(__SHIFT) 439 }; 440 441 static const struct dcn31_hpo_dp_stream_encoder_mask hpo_dp_se_mask = { 442 DCN3_1_HPO_DP_STREAM_ENC_MASK_SH_LIST(_MASK) 443 }; 444 445 446 #define hpo_dp_link_encoder_reg_list(id)\ 447 [id] = {\ 448 DCN3_1_HPO_DP_LINK_ENC_REG_LIST(id),\ 449 DCN3_1_RDPCSTX_REG_LIST(0),\ 450 DCN3_1_RDPCSTX_REG_LIST(1),\ 451 DCN3_1_RDPCSTX_REG_LIST(2),\ 452 DCN3_1_RDPCSTX_REG_LIST(3),\ 453 DCN3_1_RDPCSTX_REG_LIST(4)\ 454 } 455 456 static const struct dcn31_hpo_dp_link_encoder_registers hpo_dp_link_enc_regs[] = { 457 hpo_dp_link_encoder_reg_list(0), 458 hpo_dp_link_encoder_reg_list(1), 459 }; 460 461 static const struct dcn31_hpo_dp_link_encoder_shift hpo_dp_le_shift = { 462 DCN3_1_HPO_DP_LINK_ENC_MASK_SH_LIST(__SHIFT) 463 }; 464 465 static const struct dcn31_hpo_dp_link_encoder_mask hpo_dp_le_mask = { 466 DCN3_1_HPO_DP_LINK_ENC_MASK_SH_LIST(_MASK) 467 }; 468 469 470 #define dpp_regs(id)\ 471 [id] = {\ 472 DPP_REG_LIST_DCN30(id),\ 473 } 474 475 static const struct dcn3_dpp_registers dpp_regs[] = { 476 dpp_regs(0), 477 dpp_regs(1), 478 dpp_regs(2), 479 dpp_regs(3) 480 }; 481 482 static const struct dcn3_dpp_shift tf_shift = { 483 DPP_REG_LIST_SH_MASK_DCN30(__SHIFT) 484 }; 485 486 static const struct dcn3_dpp_mask tf_mask = { 487 DPP_REG_LIST_SH_MASK_DCN30(_MASK) 488 }; 489 490 #define opp_regs(id)\ 491 [id] = {\ 492 OPP_REG_LIST_DCN30(id),\ 493 } 494 495 static const struct dcn20_opp_registers opp_regs[] = { 496 opp_regs(0), 497 opp_regs(1), 498 opp_regs(2), 499 opp_regs(3) 500 }; 501 502 static const struct dcn20_opp_shift opp_shift = { 503 OPP_MASK_SH_LIST_DCN20(__SHIFT) 504 }; 505 506 static const struct dcn20_opp_mask opp_mask = { 507 OPP_MASK_SH_LIST_DCN20(_MASK) 508 }; 509 510 #define aux_engine_regs(id)\ 511 [id] = {\ 512 AUX_COMMON_REG_LIST0(id), \ 513 .AUXN_IMPCAL = 0, \ 514 .AUXP_IMPCAL = 0, \ 515 .AUX_RESET_MASK = DP_AUX0_AUX_CONTROL__AUX_RESET_MASK, \ 516 } 517 518 static const struct dce110_aux_registers aux_engine_regs[] = { 519 aux_engine_regs(0), 520 aux_engine_regs(1), 521 aux_engine_regs(2), 522 aux_engine_regs(3), 523 aux_engine_regs(4) 524 }; 525 526 #define dwbc_regs_dcn3(id)\ 527 [id] = {\ 528 DWBC_COMMON_REG_LIST_DCN30(id),\ 529 } 530 531 static const struct dcn30_dwbc_registers dwbc30_regs[] = { 532 dwbc_regs_dcn3(0), 533 }; 534 535 static const struct dcn30_dwbc_shift dwbc30_shift = { 536 DWBC_COMMON_MASK_SH_LIST_DCN30(__SHIFT) 537 }; 538 539 static const struct dcn30_dwbc_mask dwbc30_mask = { 540 DWBC_COMMON_MASK_SH_LIST_DCN30(_MASK) 541 }; 542 543 #define mcif_wb_regs_dcn3(id)\ 544 [id] = {\ 545 MCIF_WB_COMMON_REG_LIST_DCN30(id),\ 546 } 547 548 static const struct dcn30_mmhubbub_registers mcif_wb30_regs[] = { 549 mcif_wb_regs_dcn3(0) 550 }; 551 552 static const struct dcn30_mmhubbub_shift mcif_wb30_shift = { 553 MCIF_WB_COMMON_MASK_SH_LIST_DCN30(__SHIFT) 554 }; 555 556 static const struct dcn30_mmhubbub_mask mcif_wb30_mask = { 557 MCIF_WB_COMMON_MASK_SH_LIST_DCN30(_MASK) 558 }; 559 560 #define dsc_regsDCN20(id)\ 561 [id] = {\ 562 DSC_REG_LIST_DCN20(id)\ 563 } 564 565 static const struct dcn20_dsc_registers dsc_regs[] = { 566 dsc_regsDCN20(0), 567 dsc_regsDCN20(1), 568 dsc_regsDCN20(2) 569 }; 570 571 static const struct dcn20_dsc_shift dsc_shift = { 572 DSC_REG_LIST_SH_MASK_DCN20(__SHIFT) 573 }; 574 575 static const struct dcn20_dsc_mask dsc_mask = { 576 DSC_REG_LIST_SH_MASK_DCN20(_MASK) 577 }; 578 579 static const struct dcn30_mpc_registers mpc_regs = { 580 MPC_REG_LIST_DCN3_0(0), 581 MPC_REG_LIST_DCN3_0(1), 582 MPC_REG_LIST_DCN3_0(2), 583 MPC_REG_LIST_DCN3_0(3), 584 MPC_OUT_MUX_REG_LIST_DCN3_0(0), 585 MPC_OUT_MUX_REG_LIST_DCN3_0(1), 586 MPC_OUT_MUX_REG_LIST_DCN3_0(2), 587 MPC_OUT_MUX_REG_LIST_DCN3_0(3), 588 MPC_RMU_GLOBAL_REG_LIST_DCN3AG, 589 MPC_RMU_REG_LIST_DCN3AG(0), 590 MPC_RMU_REG_LIST_DCN3AG(1), 591 //MPC_RMU_REG_LIST_DCN3AG(2), 592 MPC_DWB_MUX_REG_LIST_DCN3_0(0), 593 }; 594 595 static const struct dcn30_mpc_shift mpc_shift = { 596 MPC_COMMON_MASK_SH_LIST_DCN30(__SHIFT) 597 }; 598 599 static const struct dcn30_mpc_mask mpc_mask = { 600 MPC_COMMON_MASK_SH_LIST_DCN30(_MASK) 601 }; 602 603 #define optc_regs(id)\ 604 [id] = {OPTC_COMMON_REG_LIST_DCN3_1(id)} 605 606 static const struct dcn_optc_registers optc_regs[] = { 607 optc_regs(0), 608 optc_regs(1), 609 optc_regs(2), 610 optc_regs(3) 611 }; 612 613 static const struct dcn_optc_shift optc_shift = { 614 OPTC_COMMON_MASK_SH_LIST_DCN3_1(__SHIFT) 615 }; 616 617 static const struct dcn_optc_mask optc_mask = { 618 OPTC_COMMON_MASK_SH_LIST_DCN3_1(_MASK) 619 }; 620 621 #define hubp_regs(id)\ 622 [id] = {\ 623 HUBP_REG_LIST_DCN30(id)\ 624 } 625 626 static const struct dcn_hubp2_registers hubp_regs[] = { 627 hubp_regs(0), 628 hubp_regs(1), 629 hubp_regs(2), 630 hubp_regs(3) 631 }; 632 633 634 static const struct dcn_hubp2_shift hubp_shift = { 635 HUBP_MASK_SH_LIST_DCN31(__SHIFT) 636 }; 637 638 static const struct dcn_hubp2_mask hubp_mask = { 639 HUBP_MASK_SH_LIST_DCN31(_MASK) 640 }; 641 static const struct dcn_hubbub_registers hubbub_reg = { 642 HUBBUB_REG_LIST_DCN31(0) 643 }; 644 645 static const struct dcn_hubbub_shift hubbub_shift = { 646 HUBBUB_MASK_SH_LIST_DCN31(__SHIFT) 647 }; 648 649 static const struct dcn_hubbub_mask hubbub_mask = { 650 HUBBUB_MASK_SH_LIST_DCN31(_MASK) 651 }; 652 653 static const struct dccg_registers dccg_regs = { 654 DCCG_REG_LIST_DCN31() 655 }; 656 657 static const struct dccg_shift dccg_shift = { 658 DCCG_MASK_SH_LIST_DCN31(__SHIFT) 659 }; 660 661 static const struct dccg_mask dccg_mask = { 662 DCCG_MASK_SH_LIST_DCN31(_MASK) 663 }; 664 665 666 #define SRII2(reg_name_pre, reg_name_post, id)\ 667 .reg_name_pre ## _ ## reg_name_post[id] = BASE(reg ## reg_name_pre \ 668 ## id ## _ ## reg_name_post ## _BASE_IDX) + \ 669 reg ## reg_name_pre ## id ## _ ## reg_name_post 670 671 672 #define HWSEQ_DCN31_REG_LIST()\ 673 SR(DCHUBBUB_GLOBAL_TIMER_CNTL), \ 674 SR(DCHUBBUB_ARB_HOSTVM_CNTL), \ 675 SR(DIO_MEM_PWR_CTRL), \ 676 SR(ODM_MEM_PWR_CTRL3), \ 677 SR(DMU_MEM_PWR_CNTL), \ 678 SR(MMHUBBUB_MEM_PWR_CNTL), \ 679 SR(DCCG_GATE_DISABLE_CNTL), \ 680 SR(DCCG_GATE_DISABLE_CNTL2), \ 681 SR(DCFCLK_CNTL),\ 682 SR(DC_MEM_GLOBAL_PWR_REQ_CNTL), \ 683 SRII(PIXEL_RATE_CNTL, OTG, 0), \ 684 SRII(PIXEL_RATE_CNTL, OTG, 1),\ 685 SRII(PIXEL_RATE_CNTL, OTG, 2),\ 686 SRII(PIXEL_RATE_CNTL, OTG, 3),\ 687 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 0),\ 688 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 1),\ 689 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 2),\ 690 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 3),\ 691 SR(MICROSECOND_TIME_BASE_DIV), \ 692 SR(MILLISECOND_TIME_BASE_DIV), \ 693 SR(DISPCLK_FREQ_CHANGE_CNTL), \ 694 SR(RBBMIF_TIMEOUT_DIS), \ 695 SR(RBBMIF_TIMEOUT_DIS_2), \ 696 SR(DCHUBBUB_CRC_CTRL), \ 697 SR(DPP_TOP0_DPP_CRC_CTRL), \ 698 SR(DPP_TOP0_DPP_CRC_VAL_B_A), \ 699 SR(DPP_TOP0_DPP_CRC_VAL_R_G), \ 700 SR(MPC_CRC_CTRL), \ 701 SR(MPC_CRC_RESULT_GB), \ 702 SR(MPC_CRC_RESULT_C), \ 703 SR(MPC_CRC_RESULT_AR), \ 704 SR(DOMAIN0_PG_CONFIG), \ 705 SR(DOMAIN1_PG_CONFIG), \ 706 SR(DOMAIN2_PG_CONFIG), \ 707 SR(DOMAIN3_PG_CONFIG), \ 708 SR(DOMAIN16_PG_CONFIG), \ 709 SR(DOMAIN17_PG_CONFIG), \ 710 SR(DOMAIN18_PG_CONFIG), \ 711 SR(DOMAIN0_PG_STATUS), \ 712 SR(DOMAIN1_PG_STATUS), \ 713 SR(DOMAIN2_PG_STATUS), \ 714 SR(DOMAIN3_PG_STATUS), \ 715 SR(DOMAIN16_PG_STATUS), \ 716 SR(DOMAIN17_PG_STATUS), \ 717 SR(DOMAIN18_PG_STATUS), \ 718 SR(D1VGA_CONTROL), \ 719 SR(D2VGA_CONTROL), \ 720 SR(D3VGA_CONTROL), \ 721 SR(D4VGA_CONTROL), \ 722 SR(D5VGA_CONTROL), \ 723 SR(D6VGA_CONTROL), \ 724 SR(DC_IP_REQUEST_CNTL), \ 725 SR(AZALIA_AUDIO_DTO), \ 726 SR(AZALIA_CONTROLLER_CLOCK_GATING), \ 727 SR(HPO_TOP_HW_CONTROL) 728 729 static const struct dce_hwseq_registers hwseq_reg = { 730 HWSEQ_DCN31_REG_LIST() 731 }; 732 733 #define HWSEQ_DCN31_MASK_SH_LIST(mask_sh)\ 734 HWSEQ_DCN_MASK_SH_LIST(mask_sh), \ 735 HWS_SF(, DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_REFDIV, mask_sh), \ 736 HWS_SF(, DCHUBBUB_ARB_HOSTVM_CNTL, DISABLE_HOSTVM_FORCE_ALLOW_PSTATE, mask_sh), \ 737 HWS_SF(, DOMAIN0_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ 738 HWS_SF(, DOMAIN0_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ 739 HWS_SF(, DOMAIN1_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ 740 HWS_SF(, DOMAIN1_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ 741 HWS_SF(, DOMAIN2_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ 742 HWS_SF(, DOMAIN2_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ 743 HWS_SF(, DOMAIN3_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ 744 HWS_SF(, DOMAIN3_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ 745 HWS_SF(, DOMAIN16_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ 746 HWS_SF(, DOMAIN16_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ 747 HWS_SF(, DOMAIN17_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ 748 HWS_SF(, DOMAIN17_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ 749 HWS_SF(, DOMAIN18_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ 750 HWS_SF(, DOMAIN18_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ 751 HWS_SF(, DOMAIN0_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ 752 HWS_SF(, DOMAIN1_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ 753 HWS_SF(, DOMAIN2_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ 754 HWS_SF(, DOMAIN3_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ 755 HWS_SF(, DOMAIN16_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ 756 HWS_SF(, DOMAIN17_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ 757 HWS_SF(, DOMAIN18_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ 758 HWS_SF(, DC_IP_REQUEST_CNTL, IP_REQUEST_EN, mask_sh), \ 759 HWS_SF(, AZALIA_AUDIO_DTO, AZALIA_AUDIO_DTO_MODULE, mask_sh), \ 760 HWS_SF(, HPO_TOP_CLOCK_CONTROL, HPO_HDMISTREAMCLK_G_GATE_DIS, mask_sh), \ 761 HWS_SF(, DMU_MEM_PWR_CNTL, DMCU_ERAM_MEM_PWR_FORCE, mask_sh), \ 762 HWS_SF(, ODM_MEM_PWR_CTRL3, ODM_MEM_UNASSIGNED_PWR_MODE, mask_sh), \ 763 HWS_SF(, ODM_MEM_PWR_CTRL3, ODM_MEM_VBLANK_PWR_MODE, mask_sh), \ 764 HWS_SF(, MMHUBBUB_MEM_PWR_CNTL, VGA_MEM_PWR_FORCE, mask_sh), \ 765 HWS_SF(, DIO_MEM_PWR_CTRL, I2C_LIGHT_SLEEP_FORCE, mask_sh), \ 766 HWS_SF(, HPO_TOP_HW_CONTROL, HPO_IO_EN, mask_sh) 767 768 static const struct dce_hwseq_shift hwseq_shift = { 769 HWSEQ_DCN31_MASK_SH_LIST(__SHIFT) 770 }; 771 772 static const struct dce_hwseq_mask hwseq_mask = { 773 HWSEQ_DCN31_MASK_SH_LIST(_MASK) 774 }; 775 #define vmid_regs(id)\ 776 [id] = {\ 777 DCN20_VMID_REG_LIST(id)\ 778 } 779 780 static const struct dcn_vmid_registers vmid_regs[] = { 781 vmid_regs(0), 782 vmid_regs(1), 783 vmid_regs(2), 784 vmid_regs(3), 785 vmid_regs(4), 786 vmid_regs(5), 787 vmid_regs(6), 788 vmid_regs(7), 789 vmid_regs(8), 790 vmid_regs(9), 791 vmid_regs(10), 792 vmid_regs(11), 793 vmid_regs(12), 794 vmid_regs(13), 795 vmid_regs(14), 796 vmid_regs(15) 797 }; 798 799 static const struct dcn20_vmid_shift vmid_shifts = { 800 DCN20_VMID_MASK_SH_LIST(__SHIFT) 801 }; 802 803 static const struct dcn20_vmid_mask vmid_masks = { 804 DCN20_VMID_MASK_SH_LIST(_MASK) 805 }; 806 807 static const struct resource_caps res_cap_dcn31 = { 808 .num_timing_generator = 4, 809 .num_opp = 4, 810 .num_video_plane = 4, 811 .num_audio = 5, 812 .num_stream_encoder = 5, 813 .num_dig_link_enc = 5, 814 .num_hpo_dp_stream_encoder = 4, 815 .num_hpo_dp_link_encoder = 2, 816 .num_pll = 5, 817 .num_dwb = 1, 818 .num_ddc = 5, 819 .num_vmid = 16, 820 .num_mpc_3dlut = 2, 821 .num_dsc = 3, 822 }; 823 824 static const struct dc_plane_cap plane_cap = { 825 .type = DC_PLANE_TYPE_DCN_UNIVERSAL, 826 .blends_with_above = true, 827 .blends_with_below = true, 828 .per_pixel_alpha = true, 829 830 .pixel_format_support = { 831 .argb8888 = true, 832 .nv12 = true, 833 .fp16 = true, 834 .p010 = true, 835 .ayuv = false, 836 }, 837 838 .max_upscale_factor = { 839 .argb8888 = 16000, 840 .nv12 = 16000, 841 .fp16 = 16000 842 }, 843 844 // 6:1 downscaling ratio: 1000/6 = 166.666 845 .max_downscale_factor = { 846 .argb8888 = 167, 847 .nv12 = 167, 848 .fp16 = 167 849 }, 850 64, 851 64 852 }; 853 854 static const struct dc_debug_options debug_defaults_drv = { 855 .disable_z10 = true, /*hw not support it*/ 856 .disable_dmcu = true, 857 .force_abm_enable = false, 858 .timing_trace = false, 859 .clock_trace = true, 860 .disable_pplib_clock_request = false, 861 .pipe_split_policy = MPC_SPLIT_DYNAMIC, 862 .force_single_disp_pipe_split = false, 863 .disable_dcc = DCC_ENABLE, 864 .vsr_support = true, 865 .performance_trace = false, 866 .max_downscale_src_width = 4096,/*upto true 4k*/ 867 .disable_pplib_wm_range = false, 868 .scl_reset_length10 = true, 869 .sanity_checks = false, 870 .underflow_assert_delay_us = 0xFFFFFFFF, 871 .dwb_fi_phase = -1, // -1 = disable, 872 .dmub_command_table = true, 873 .pstate_enabled = true, 874 .use_max_lb = true, 875 .enable_mem_low_power = { 876 .bits = { 877 .vga = true, 878 .i2c = true, 879 .dmcu = false, // This is previously known to cause hang on S3 cycles if enabled 880 .dscl = true, 881 .cm = true, 882 .mpc = true, 883 .optc = true, 884 .vpg = true, 885 .afmt = true, 886 } 887 }, 888 .optimize_edp_link_rate = true, 889 .enable_sw_cntl_psr = true, 890 }; 891 892 static const struct dc_debug_options debug_defaults_diags = { 893 .disable_dmcu = true, 894 .force_abm_enable = false, 895 .timing_trace = true, 896 .clock_trace = true, 897 .disable_dpp_power_gate = true, 898 .disable_hubp_power_gate = true, 899 .disable_clock_gate = true, 900 .disable_pplib_clock_request = true, 901 .disable_pplib_wm_range = true, 902 .disable_stutter = false, 903 .scl_reset_length10 = true, 904 .dwb_fi_phase = -1, // -1 = disable 905 .dmub_command_table = true, 906 .enable_tri_buf = true, 907 .use_max_lb = true 908 }; 909 910 static void dcn31_dpp_destroy(struct dpp **dpp) 911 { 912 kfree(TO_DCN20_DPP(*dpp)); 913 *dpp = NULL; 914 } 915 916 static struct dpp *dcn31_dpp_create( 917 struct dc_context *ctx, 918 uint32_t inst) 919 { 920 struct dcn3_dpp *dpp = 921 kzalloc(sizeof(struct dcn3_dpp), GFP_KERNEL); 922 923 if (!dpp) 924 return NULL; 925 926 if (dpp3_construct(dpp, ctx, inst, 927 &dpp_regs[inst], &tf_shift, &tf_mask)) 928 return &dpp->base; 929 930 BREAK_TO_DEBUGGER(); 931 kfree(dpp); 932 return NULL; 933 } 934 935 static struct output_pixel_processor *dcn31_opp_create( 936 struct dc_context *ctx, uint32_t inst) 937 { 938 struct dcn20_opp *opp = 939 kzalloc(sizeof(struct dcn20_opp), GFP_KERNEL); 940 941 if (!opp) { 942 BREAK_TO_DEBUGGER(); 943 return NULL; 944 } 945 946 dcn20_opp_construct(opp, ctx, inst, 947 &opp_regs[inst], &opp_shift, &opp_mask); 948 return &opp->base; 949 } 950 951 static struct dce_aux *dcn31_aux_engine_create( 952 struct dc_context *ctx, 953 uint32_t inst) 954 { 955 struct aux_engine_dce110 *aux_engine = 956 kzalloc(sizeof(struct aux_engine_dce110), GFP_KERNEL); 957 958 if (!aux_engine) 959 return NULL; 960 961 dce110_aux_engine_construct(aux_engine, ctx, inst, 962 SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD, 963 &aux_engine_regs[inst], 964 &aux_mask, 965 &aux_shift, 966 ctx->dc->caps.extended_aux_timeout_support); 967 968 return &aux_engine->base; 969 } 970 #define i2c_inst_regs(id) { I2C_HW_ENGINE_COMMON_REG_LIST_DCN30(id) } 971 972 static const struct dce_i2c_registers i2c_hw_regs[] = { 973 i2c_inst_regs(1), 974 i2c_inst_regs(2), 975 i2c_inst_regs(3), 976 i2c_inst_regs(4), 977 i2c_inst_regs(5), 978 }; 979 980 static const struct dce_i2c_shift i2c_shifts = { 981 I2C_COMMON_MASK_SH_LIST_DCN30(__SHIFT) 982 }; 983 984 static const struct dce_i2c_mask i2c_masks = { 985 I2C_COMMON_MASK_SH_LIST_DCN30(_MASK) 986 }; 987 988 static struct dce_i2c_hw *dcn31_i2c_hw_create( 989 struct dc_context *ctx, 990 uint32_t inst) 991 { 992 struct dce_i2c_hw *dce_i2c_hw = 993 kzalloc(sizeof(struct dce_i2c_hw), GFP_KERNEL); 994 995 if (!dce_i2c_hw) 996 return NULL; 997 998 dcn2_i2c_hw_construct(dce_i2c_hw, ctx, inst, 999 &i2c_hw_regs[inst], &i2c_shifts, &i2c_masks); 1000 1001 return dce_i2c_hw; 1002 } 1003 static struct mpc *dcn31_mpc_create( 1004 struct dc_context *ctx, 1005 int num_mpcc, 1006 int num_rmu) 1007 { 1008 struct dcn30_mpc *mpc30 = kzalloc(sizeof(struct dcn30_mpc), 1009 GFP_KERNEL); 1010 1011 if (!mpc30) 1012 return NULL; 1013 1014 dcn30_mpc_construct(mpc30, ctx, 1015 &mpc_regs, 1016 &mpc_shift, 1017 &mpc_mask, 1018 num_mpcc, 1019 num_rmu); 1020 1021 return &mpc30->base; 1022 } 1023 1024 static struct hubbub *dcn31_hubbub_create(struct dc_context *ctx) 1025 { 1026 int i; 1027 1028 struct dcn20_hubbub *hubbub3 = kzalloc(sizeof(struct dcn20_hubbub), 1029 GFP_KERNEL); 1030 1031 if (!hubbub3) 1032 return NULL; 1033 1034 hubbub31_construct(hubbub3, ctx, 1035 &hubbub_reg, 1036 &hubbub_shift, 1037 &hubbub_mask, 1038 dcn3_16_ip.det_buffer_size_kbytes, 1039 dcn3_16_ip.pixel_chunk_size_kbytes, 1040 dcn3_16_ip.config_return_buffer_size_in_kbytes); 1041 1042 1043 for (i = 0; i < res_cap_dcn31.num_vmid; i++) { 1044 struct dcn20_vmid *vmid = &hubbub3->vmid[i]; 1045 1046 vmid->ctx = ctx; 1047 1048 vmid->regs = &vmid_regs[i]; 1049 vmid->shifts = &vmid_shifts; 1050 vmid->masks = &vmid_masks; 1051 } 1052 1053 return &hubbub3->base; 1054 } 1055 1056 static struct timing_generator *dcn31_timing_generator_create( 1057 struct dc_context *ctx, 1058 uint32_t instance) 1059 { 1060 struct optc *tgn10 = 1061 kzalloc(sizeof(struct optc), GFP_KERNEL); 1062 1063 if (!tgn10) 1064 return NULL; 1065 1066 tgn10->base.inst = instance; 1067 tgn10->base.ctx = ctx; 1068 1069 tgn10->tg_regs = &optc_regs[instance]; 1070 tgn10->tg_shift = &optc_shift; 1071 tgn10->tg_mask = &optc_mask; 1072 1073 dcn31_timing_generator_init(tgn10); 1074 1075 return &tgn10->base; 1076 } 1077 1078 static const struct encoder_feature_support link_enc_feature = { 1079 .max_hdmi_deep_color = COLOR_DEPTH_121212, 1080 .max_hdmi_pixel_clock = 600000, 1081 .hdmi_ycbcr420_supported = true, 1082 .dp_ycbcr420_supported = true, 1083 .fec_supported = true, 1084 .flags.bits.IS_HBR2_CAPABLE = true, 1085 .flags.bits.IS_HBR3_CAPABLE = true, 1086 .flags.bits.IS_TPS3_CAPABLE = true, 1087 .flags.bits.IS_TPS4_CAPABLE = true 1088 }; 1089 1090 static struct link_encoder *dcn31_link_encoder_create( 1091 const struct encoder_init_data *enc_init_data) 1092 { 1093 struct dcn20_link_encoder *enc20 = 1094 kzalloc(sizeof(struct dcn20_link_encoder), GFP_KERNEL); 1095 1096 if (!enc20) 1097 return NULL; 1098 1099 dcn31_link_encoder_construct(enc20, 1100 enc_init_data, 1101 &link_enc_feature, 1102 &link_enc_regs[enc_init_data->transmitter], 1103 &link_enc_aux_regs[enc_init_data->channel - 1], 1104 &link_enc_hpd_regs[enc_init_data->hpd_source], 1105 &le_shift, 1106 &le_mask); 1107 1108 return &enc20->enc10.base; 1109 } 1110 1111 /* Create a minimal link encoder object not associated with a particular 1112 * physical connector. 1113 * resource_funcs.link_enc_create_minimal 1114 */ 1115 static struct link_encoder *dcn31_link_enc_create_minimal( 1116 struct dc_context *ctx, enum engine_id eng_id) 1117 { 1118 struct dcn20_link_encoder *enc20; 1119 1120 if ((eng_id - ENGINE_ID_DIGA) > ctx->dc->res_pool->res_cap->num_dig_link_enc) 1121 return NULL; 1122 1123 enc20 = kzalloc(sizeof(struct dcn20_link_encoder), GFP_KERNEL); 1124 if (!enc20) 1125 return NULL; 1126 1127 dcn31_link_encoder_construct_minimal( 1128 enc20, 1129 ctx, 1130 &link_enc_feature, 1131 &link_enc_regs[eng_id - ENGINE_ID_DIGA], 1132 eng_id); 1133 1134 return &enc20->enc10.base; 1135 } 1136 1137 static struct panel_cntl *dcn31_panel_cntl_create(const struct panel_cntl_init_data *init_data) 1138 { 1139 struct dcn31_panel_cntl *panel_cntl = 1140 kzalloc(sizeof(struct dcn31_panel_cntl), GFP_KERNEL); 1141 1142 if (!panel_cntl) 1143 return NULL; 1144 1145 dcn31_panel_cntl_construct(panel_cntl, init_data); 1146 1147 return &panel_cntl->base; 1148 } 1149 1150 static void read_dce_straps( 1151 struct dc_context *ctx, 1152 struct resource_straps *straps) 1153 { 1154 generic_reg_get(ctx, regDC_PINSTRAPS + BASE(regDC_PINSTRAPS_BASE_IDX), 1155 FN(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO), &straps->dc_pinstraps_audio); 1156 1157 } 1158 1159 static struct audio *dcn31_create_audio( 1160 struct dc_context *ctx, unsigned int inst) 1161 { 1162 return dce_audio_create(ctx, inst, 1163 &audio_regs[inst], &audio_shift, &audio_mask); 1164 } 1165 1166 static struct vpg *dcn31_vpg_create( 1167 struct dc_context *ctx, 1168 uint32_t inst) 1169 { 1170 struct dcn31_vpg *vpg31 = kzalloc(sizeof(struct dcn31_vpg), GFP_KERNEL); 1171 1172 if (!vpg31) 1173 return NULL; 1174 1175 vpg31_construct(vpg31, ctx, inst, 1176 &vpg_regs[inst], 1177 &vpg_shift, 1178 &vpg_mask); 1179 1180 return &vpg31->base; 1181 } 1182 1183 static struct afmt *dcn31_afmt_create( 1184 struct dc_context *ctx, 1185 uint32_t inst) 1186 { 1187 struct dcn31_afmt *afmt31 = kzalloc(sizeof(struct dcn31_afmt), GFP_KERNEL); 1188 1189 if (!afmt31) 1190 return NULL; 1191 1192 afmt31_construct(afmt31, ctx, inst, 1193 &afmt_regs[inst], 1194 &afmt_shift, 1195 &afmt_mask); 1196 1197 // Light sleep by default, no need to power down here 1198 1199 return &afmt31->base; 1200 } 1201 1202 1203 static struct apg *dcn31_apg_create( 1204 struct dc_context *ctx, 1205 uint32_t inst) 1206 { 1207 struct dcn31_apg *apg31 = kzalloc(sizeof(struct dcn31_apg), GFP_KERNEL); 1208 1209 if (!apg31) 1210 return NULL; 1211 1212 apg31_construct(apg31, ctx, inst, 1213 &apg_regs[inst], 1214 &apg_shift, 1215 &apg_mask); 1216 1217 return &apg31->base; 1218 } 1219 1220 1221 static struct stream_encoder *dcn316_stream_encoder_create( 1222 enum engine_id eng_id, 1223 struct dc_context *ctx) 1224 { 1225 struct dcn10_stream_encoder *enc1; 1226 struct vpg *vpg; 1227 struct afmt *afmt; 1228 int vpg_inst; 1229 int afmt_inst; 1230 1231 /* Mapping of VPG, AFMT, DME register blocks to DIO block instance */ 1232 if (eng_id <= ENGINE_ID_DIGF) { 1233 vpg_inst = eng_id; 1234 afmt_inst = eng_id; 1235 } else 1236 return NULL; 1237 1238 enc1 = kzalloc(sizeof(struct dcn10_stream_encoder), GFP_KERNEL); 1239 vpg = dcn31_vpg_create(ctx, vpg_inst); 1240 afmt = dcn31_afmt_create(ctx, afmt_inst); 1241 1242 if (!enc1 || !vpg || !afmt) { 1243 kfree(enc1); 1244 kfree(vpg); 1245 kfree(afmt); 1246 return NULL; 1247 } 1248 1249 dcn30_dio_stream_encoder_construct(enc1, ctx, ctx->dc_bios, 1250 eng_id, vpg, afmt, 1251 &stream_enc_regs[eng_id], 1252 &se_shift, &se_mask); 1253 1254 return &enc1->base; 1255 } 1256 1257 1258 static struct hpo_dp_stream_encoder *dcn31_hpo_dp_stream_encoder_create( 1259 enum engine_id eng_id, 1260 struct dc_context *ctx) 1261 { 1262 struct dcn31_hpo_dp_stream_encoder *hpo_dp_enc31; 1263 struct vpg *vpg; 1264 struct apg *apg; 1265 uint32_t hpo_dp_inst; 1266 uint32_t vpg_inst; 1267 uint32_t apg_inst; 1268 1269 ASSERT((eng_id >= ENGINE_ID_HPO_DP_0) && (eng_id <= ENGINE_ID_HPO_DP_3)); 1270 hpo_dp_inst = eng_id - ENGINE_ID_HPO_DP_0; 1271 1272 /* Mapping of VPG register blocks to HPO DP block instance: 1273 * VPG[6] -> HPO_DP[0] 1274 * VPG[7] -> HPO_DP[1] 1275 * VPG[8] -> HPO_DP[2] 1276 * VPG[9] -> HPO_DP[3] 1277 */ 1278 vpg_inst = hpo_dp_inst + 6; 1279 1280 /* Mapping of APG register blocks to HPO DP block instance: 1281 * APG[0] -> HPO_DP[0] 1282 * APG[1] -> HPO_DP[1] 1283 * APG[2] -> HPO_DP[2] 1284 * APG[3] -> HPO_DP[3] 1285 */ 1286 apg_inst = hpo_dp_inst; 1287 1288 /* allocate HPO stream encoder and create VPG sub-block */ 1289 hpo_dp_enc31 = kzalloc(sizeof(struct dcn31_hpo_dp_stream_encoder), GFP_KERNEL); 1290 vpg = dcn31_vpg_create(ctx, vpg_inst); 1291 apg = dcn31_apg_create(ctx, apg_inst); 1292 1293 if (!hpo_dp_enc31 || !vpg || !apg) { 1294 kfree(hpo_dp_enc31); 1295 kfree(vpg); 1296 kfree(apg); 1297 return NULL; 1298 } 1299 1300 dcn31_hpo_dp_stream_encoder_construct(hpo_dp_enc31, ctx, ctx->dc_bios, 1301 hpo_dp_inst, eng_id, vpg, apg, 1302 &hpo_dp_stream_enc_regs[hpo_dp_inst], 1303 &hpo_dp_se_shift, &hpo_dp_se_mask); 1304 1305 return &hpo_dp_enc31->base; 1306 } 1307 1308 static struct hpo_dp_link_encoder *dcn31_hpo_dp_link_encoder_create( 1309 uint8_t inst, 1310 struct dc_context *ctx) 1311 { 1312 struct dcn31_hpo_dp_link_encoder *hpo_dp_enc31; 1313 1314 /* allocate HPO link encoder */ 1315 hpo_dp_enc31 = kzalloc(sizeof(struct dcn31_hpo_dp_link_encoder), GFP_KERNEL); 1316 1317 hpo_dp_link_encoder31_construct(hpo_dp_enc31, ctx, inst, 1318 &hpo_dp_link_enc_regs[inst], 1319 &hpo_dp_le_shift, &hpo_dp_le_mask); 1320 1321 return &hpo_dp_enc31->base; 1322 } 1323 1324 1325 static struct dce_hwseq *dcn31_hwseq_create( 1326 struct dc_context *ctx) 1327 { 1328 struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_KERNEL); 1329 1330 if (hws) { 1331 hws->ctx = ctx; 1332 hws->regs = &hwseq_reg; 1333 hws->shifts = &hwseq_shift; 1334 hws->masks = &hwseq_mask; 1335 /* DCN3.1 FPGA Workaround 1336 * Need to enable HPO DP Stream Encoder before setting OTG master enable. 1337 * To do so, move calling function enable_stream_timing to only be done AFTER calling 1338 * function core_link_enable_stream 1339 */ 1340 if (IS_FPGA_MAXIMUS_DC(ctx->dce_environment)) 1341 hws->wa.dp_hpo_and_otg_sequence = true; 1342 } 1343 return hws; 1344 } 1345 static const struct resource_create_funcs res_create_funcs = { 1346 .read_dce_straps = read_dce_straps, 1347 .create_audio = dcn31_create_audio, 1348 .create_stream_encoder = dcn316_stream_encoder_create, 1349 .create_hpo_dp_stream_encoder = dcn31_hpo_dp_stream_encoder_create, 1350 .create_hpo_dp_link_encoder = dcn31_hpo_dp_link_encoder_create, 1351 .create_hwseq = dcn31_hwseq_create, 1352 }; 1353 1354 static const struct resource_create_funcs res_create_maximus_funcs = { 1355 .read_dce_straps = NULL, 1356 .create_audio = NULL, 1357 .create_stream_encoder = NULL, 1358 .create_hpo_dp_stream_encoder = dcn31_hpo_dp_stream_encoder_create, 1359 .create_hpo_dp_link_encoder = dcn31_hpo_dp_link_encoder_create, 1360 .create_hwseq = dcn31_hwseq_create, 1361 }; 1362 1363 static void dcn316_resource_destruct(struct dcn316_resource_pool *pool) 1364 { 1365 unsigned int i; 1366 1367 for (i = 0; i < pool->base.stream_enc_count; i++) { 1368 if (pool->base.stream_enc[i] != NULL) { 1369 if (pool->base.stream_enc[i]->vpg != NULL) { 1370 kfree(DCN30_VPG_FROM_VPG(pool->base.stream_enc[i]->vpg)); 1371 pool->base.stream_enc[i]->vpg = NULL; 1372 } 1373 if (pool->base.stream_enc[i]->afmt != NULL) { 1374 kfree(DCN30_AFMT_FROM_AFMT(pool->base.stream_enc[i]->afmt)); 1375 pool->base.stream_enc[i]->afmt = NULL; 1376 } 1377 kfree(DCN10STRENC_FROM_STRENC(pool->base.stream_enc[i])); 1378 pool->base.stream_enc[i] = NULL; 1379 } 1380 } 1381 1382 for (i = 0; i < pool->base.hpo_dp_stream_enc_count; i++) { 1383 if (pool->base.hpo_dp_stream_enc[i] != NULL) { 1384 if (pool->base.hpo_dp_stream_enc[i]->vpg != NULL) { 1385 kfree(DCN30_VPG_FROM_VPG(pool->base.hpo_dp_stream_enc[i]->vpg)); 1386 pool->base.hpo_dp_stream_enc[i]->vpg = NULL; 1387 } 1388 if (pool->base.hpo_dp_stream_enc[i]->apg != NULL) { 1389 kfree(DCN31_APG_FROM_APG(pool->base.hpo_dp_stream_enc[i]->apg)); 1390 pool->base.hpo_dp_stream_enc[i]->apg = NULL; 1391 } 1392 kfree(DCN3_1_HPO_DP_STREAM_ENC_FROM_HPO_STREAM_ENC(pool->base.hpo_dp_stream_enc[i])); 1393 pool->base.hpo_dp_stream_enc[i] = NULL; 1394 } 1395 } 1396 1397 for (i = 0; i < pool->base.hpo_dp_link_enc_count; i++) { 1398 if (pool->base.hpo_dp_link_enc[i] != NULL) { 1399 kfree(DCN3_1_HPO_DP_LINK_ENC_FROM_HPO_LINK_ENC(pool->base.hpo_dp_link_enc[i])); 1400 pool->base.hpo_dp_link_enc[i] = NULL; 1401 } 1402 } 1403 1404 for (i = 0; i < pool->base.res_cap->num_dsc; i++) { 1405 if (pool->base.dscs[i] != NULL) 1406 dcn20_dsc_destroy(&pool->base.dscs[i]); 1407 } 1408 1409 if (pool->base.mpc != NULL) { 1410 kfree(TO_DCN20_MPC(pool->base.mpc)); 1411 pool->base.mpc = NULL; 1412 } 1413 if (pool->base.hubbub != NULL) { 1414 kfree(pool->base.hubbub); 1415 pool->base.hubbub = NULL; 1416 } 1417 for (i = 0; i < pool->base.pipe_count; i++) { 1418 if (pool->base.dpps[i] != NULL) 1419 dcn31_dpp_destroy(&pool->base.dpps[i]); 1420 1421 if (pool->base.ipps[i] != NULL) 1422 pool->base.ipps[i]->funcs->ipp_destroy(&pool->base.ipps[i]); 1423 1424 if (pool->base.hubps[i] != NULL) { 1425 kfree(TO_DCN20_HUBP(pool->base.hubps[i])); 1426 pool->base.hubps[i] = NULL; 1427 } 1428 1429 if (pool->base.irqs != NULL) { 1430 dal_irq_service_destroy(&pool->base.irqs); 1431 } 1432 } 1433 1434 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { 1435 if (pool->base.engines[i] != NULL) 1436 dce110_engine_destroy(&pool->base.engines[i]); 1437 if (pool->base.hw_i2cs[i] != NULL) { 1438 kfree(pool->base.hw_i2cs[i]); 1439 pool->base.hw_i2cs[i] = NULL; 1440 } 1441 if (pool->base.sw_i2cs[i] != NULL) { 1442 kfree(pool->base.sw_i2cs[i]); 1443 pool->base.sw_i2cs[i] = NULL; 1444 } 1445 } 1446 1447 for (i = 0; i < pool->base.res_cap->num_opp; i++) { 1448 if (pool->base.opps[i] != NULL) 1449 pool->base.opps[i]->funcs->opp_destroy(&pool->base.opps[i]); 1450 } 1451 1452 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { 1453 if (pool->base.timing_generators[i] != NULL) { 1454 kfree(DCN10TG_FROM_TG(pool->base.timing_generators[i])); 1455 pool->base.timing_generators[i] = NULL; 1456 } 1457 } 1458 1459 for (i = 0; i < pool->base.res_cap->num_dwb; i++) { 1460 if (pool->base.dwbc[i] != NULL) { 1461 kfree(TO_DCN30_DWBC(pool->base.dwbc[i])); 1462 pool->base.dwbc[i] = NULL; 1463 } 1464 if (pool->base.mcif_wb[i] != NULL) { 1465 kfree(TO_DCN30_MMHUBBUB(pool->base.mcif_wb[i])); 1466 pool->base.mcif_wb[i] = NULL; 1467 } 1468 } 1469 1470 for (i = 0; i < pool->base.audio_count; i++) { 1471 if (pool->base.audios[i]) 1472 dce_aud_destroy(&pool->base.audios[i]); 1473 } 1474 1475 for (i = 0; i < pool->base.clk_src_count; i++) { 1476 if (pool->base.clock_sources[i] != NULL) { 1477 dcn20_clock_source_destroy(&pool->base.clock_sources[i]); 1478 pool->base.clock_sources[i] = NULL; 1479 } 1480 } 1481 1482 for (i = 0; i < pool->base.res_cap->num_mpc_3dlut; i++) { 1483 if (pool->base.mpc_lut[i] != NULL) { 1484 dc_3dlut_func_release(pool->base.mpc_lut[i]); 1485 pool->base.mpc_lut[i] = NULL; 1486 } 1487 if (pool->base.mpc_shaper[i] != NULL) { 1488 dc_transfer_func_release(pool->base.mpc_shaper[i]); 1489 pool->base.mpc_shaper[i] = NULL; 1490 } 1491 } 1492 1493 if (pool->base.dp_clock_source != NULL) { 1494 dcn20_clock_source_destroy(&pool->base.dp_clock_source); 1495 pool->base.dp_clock_source = NULL; 1496 } 1497 1498 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { 1499 if (pool->base.multiple_abms[i] != NULL) 1500 dce_abm_destroy(&pool->base.multiple_abms[i]); 1501 } 1502 1503 if (pool->base.psr != NULL) 1504 dmub_psr_destroy(&pool->base.psr); 1505 1506 if (pool->base.dccg != NULL) 1507 dcn_dccg_destroy(&pool->base.dccg); 1508 } 1509 1510 static struct hubp *dcn31_hubp_create( 1511 struct dc_context *ctx, 1512 uint32_t inst) 1513 { 1514 struct dcn20_hubp *hubp2 = 1515 kzalloc(sizeof(struct dcn20_hubp), GFP_KERNEL); 1516 1517 if (!hubp2) 1518 return NULL; 1519 1520 if (hubp31_construct(hubp2, ctx, inst, 1521 &hubp_regs[inst], &hubp_shift, &hubp_mask)) 1522 return &hubp2->base; 1523 1524 BREAK_TO_DEBUGGER(); 1525 kfree(hubp2); 1526 return NULL; 1527 } 1528 1529 static bool dcn31_dwbc_create(struct dc_context *ctx, struct resource_pool *pool) 1530 { 1531 int i; 1532 uint32_t pipe_count = pool->res_cap->num_dwb; 1533 1534 for (i = 0; i < pipe_count; i++) { 1535 struct dcn30_dwbc *dwbc30 = kzalloc(sizeof(struct dcn30_dwbc), 1536 GFP_KERNEL); 1537 1538 if (!dwbc30) { 1539 dm_error("DC: failed to create dwbc30!\n"); 1540 return false; 1541 } 1542 1543 dcn30_dwbc_construct(dwbc30, ctx, 1544 &dwbc30_regs[i], 1545 &dwbc30_shift, 1546 &dwbc30_mask, 1547 i); 1548 1549 pool->dwbc[i] = &dwbc30->base; 1550 } 1551 return true; 1552 } 1553 1554 static bool dcn31_mmhubbub_create(struct dc_context *ctx, struct resource_pool *pool) 1555 { 1556 int i; 1557 uint32_t pipe_count = pool->res_cap->num_dwb; 1558 1559 for (i = 0; i < pipe_count; i++) { 1560 struct dcn30_mmhubbub *mcif_wb30 = kzalloc(sizeof(struct dcn30_mmhubbub), 1561 GFP_KERNEL); 1562 1563 if (!mcif_wb30) { 1564 dm_error("DC: failed to create mcif_wb30!\n"); 1565 return false; 1566 } 1567 1568 dcn30_mmhubbub_construct(mcif_wb30, ctx, 1569 &mcif_wb30_regs[i], 1570 &mcif_wb30_shift, 1571 &mcif_wb30_mask, 1572 i); 1573 1574 pool->mcif_wb[i] = &mcif_wb30->base; 1575 } 1576 return true; 1577 } 1578 1579 static struct display_stream_compressor *dcn31_dsc_create( 1580 struct dc_context *ctx, uint32_t inst) 1581 { 1582 struct dcn20_dsc *dsc = 1583 kzalloc(sizeof(struct dcn20_dsc), GFP_KERNEL); 1584 1585 if (!dsc) { 1586 BREAK_TO_DEBUGGER(); 1587 return NULL; 1588 } 1589 1590 dsc2_construct(dsc, ctx, inst, &dsc_regs[inst], &dsc_shift, &dsc_mask); 1591 return &dsc->base; 1592 } 1593 1594 static void dcn316_destroy_resource_pool(struct resource_pool **pool) 1595 { 1596 struct dcn316_resource_pool *dcn31_pool = TO_DCN316_RES_POOL(*pool); 1597 1598 dcn316_resource_destruct(dcn31_pool); 1599 kfree(dcn31_pool); 1600 *pool = NULL; 1601 } 1602 1603 static struct clock_source *dcn31_clock_source_create( 1604 struct dc_context *ctx, 1605 struct dc_bios *bios, 1606 enum clock_source_id id, 1607 const struct dce110_clk_src_regs *regs, 1608 bool dp_clk_src) 1609 { 1610 struct dce110_clk_src *clk_src = 1611 kzalloc(sizeof(struct dce110_clk_src), GFP_KERNEL); 1612 1613 if (!clk_src) 1614 return NULL; 1615 1616 if (dcn31_clk_src_construct(clk_src, ctx, bios, id, 1617 regs, &cs_shift, &cs_mask)) { 1618 clk_src->base.dp_clk_src = dp_clk_src; 1619 return &clk_src->base; 1620 } 1621 1622 kfree(clk_src); 1623 1624 BREAK_TO_DEBUGGER(); 1625 return NULL; 1626 } 1627 1628 static bool is_dual_plane(enum surface_pixel_format format) 1629 { 1630 return format >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN || format == SURFACE_PIXEL_FORMAT_GRPH_RGBE_ALPHA; 1631 } 1632 1633 static int dcn316_populate_dml_pipes_from_context( 1634 struct dc *dc, struct dc_state *context, 1635 display_e2e_pipe_params_st *pipes, 1636 bool fast_validate) 1637 { 1638 int i, pipe_cnt; 1639 struct resource_context *res_ctx = &context->res_ctx; 1640 struct pipe_ctx *pipe; 1641 const int max_usable_det = context->bw_ctx.dml.ip.config_return_buffer_size_in_kbytes - DCN3_16_MIN_COMPBUF_SIZE_KB; 1642 1643 DC_FP_START(); 1644 dcn20_populate_dml_pipes_from_context(dc, context, pipes, fast_validate); 1645 DC_FP_END(); 1646 1647 for (i = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) { 1648 struct dc_crtc_timing *timing; 1649 1650 if (!res_ctx->pipe_ctx[i].stream) 1651 continue; 1652 pipe = &res_ctx->pipe_ctx[i]; 1653 timing = &pipe->stream->timing; 1654 1655 /* 1656 * Immediate flip can be set dynamically after enabling the plane. 1657 * We need to require support for immediate flip or underflow can be 1658 * intermittently experienced depending on peak b/w requirements. 1659 */ 1660 pipes[pipe_cnt].pipe.src.immediate_flip = true; 1661 1662 pipes[pipe_cnt].pipe.src.unbounded_req_mode = false; 1663 pipes[pipe_cnt].pipe.src.gpuvm = true; 1664 pipes[pipe_cnt].pipe.src.dcc_fraction_of_zs_req_luma = 0; 1665 pipes[pipe_cnt].pipe.src.dcc_fraction_of_zs_req_chroma = 0; 1666 pipes[pipe_cnt].pipe.dest.vfront_porch = timing->v_front_porch; 1667 pipes[pipe_cnt].pipe.src.dcc_rate = 3; 1668 pipes[pipe_cnt].dout.dsc_input_bpc = 0; 1669 1670 if (pipes[pipe_cnt].dout.dsc_enable) { 1671 switch (timing->display_color_depth) { 1672 case COLOR_DEPTH_888: 1673 pipes[pipe_cnt].dout.dsc_input_bpc = 8; 1674 break; 1675 case COLOR_DEPTH_101010: 1676 pipes[pipe_cnt].dout.dsc_input_bpc = 10; 1677 break; 1678 case COLOR_DEPTH_121212: 1679 pipes[pipe_cnt].dout.dsc_input_bpc = 12; 1680 break; 1681 default: 1682 ASSERT(0); 1683 break; 1684 } 1685 } 1686 1687 pipe_cnt++; 1688 } 1689 1690 if (pipe_cnt) 1691 context->bw_ctx.dml.ip.det_buffer_size_kbytes = 1692 (max_usable_det / DCN3_16_CRB_SEGMENT_SIZE_KB / pipe_cnt) * DCN3_16_CRB_SEGMENT_SIZE_KB; 1693 if (context->bw_ctx.dml.ip.det_buffer_size_kbytes > DCN3_16_MAX_DET_SIZE) 1694 context->bw_ctx.dml.ip.det_buffer_size_kbytes = DCN3_16_MAX_DET_SIZE; 1695 ASSERT(context->bw_ctx.dml.ip.det_buffer_size_kbytes >= DCN3_16_DEFAULT_DET_SIZE); 1696 dc->config.enable_4to1MPC = false; 1697 if (pipe_cnt == 1 && pipe->plane_state && !dc->debug.disable_z9_mpc) { 1698 if (is_dual_plane(pipe->plane_state->format) 1699 && pipe->plane_state->src_rect.width <= 1920 && pipe->plane_state->src_rect.height <= 1080) { 1700 dc->config.enable_4to1MPC = true; 1701 context->bw_ctx.dml.ip.det_buffer_size_kbytes = 1702 (max_usable_det / DCN3_16_CRB_SEGMENT_SIZE_KB / 4) * DCN3_16_CRB_SEGMENT_SIZE_KB; 1703 } else if (!is_dual_plane(pipe->plane_state->format)) { 1704 context->bw_ctx.dml.ip.det_buffer_size_kbytes = 192; 1705 pipes[0].pipe.src.unbounded_req_mode = true; 1706 } 1707 } 1708 1709 return pipe_cnt; 1710 } 1711 1712 static struct dc_cap_funcs cap_funcs = { 1713 .get_dcc_compression_cap = dcn20_get_dcc_compression_cap 1714 }; 1715 1716 static struct resource_funcs dcn316_res_pool_funcs = { 1717 .destroy = dcn316_destroy_resource_pool, 1718 .link_enc_create = dcn31_link_encoder_create, 1719 .link_enc_create_minimal = dcn31_link_enc_create_minimal, 1720 .link_encs_assign = link_enc_cfg_link_encs_assign, 1721 .link_enc_unassign = link_enc_cfg_link_enc_unassign, 1722 .panel_cntl_create = dcn31_panel_cntl_create, 1723 .validate_bandwidth = dcn31_validate_bandwidth, 1724 .calculate_wm_and_dlg = dcn31_calculate_wm_and_dlg, 1725 .update_soc_for_wm_a = dcn31_update_soc_for_wm_a, 1726 .populate_dml_pipes = dcn316_populate_dml_pipes_from_context, 1727 .acquire_idle_pipe_for_layer = dcn20_acquire_idle_pipe_for_layer, 1728 .add_stream_to_ctx = dcn30_add_stream_to_ctx, 1729 .add_dsc_to_stream_resource = dcn20_add_dsc_to_stream_resource, 1730 .remove_stream_from_ctx = dcn20_remove_stream_from_ctx, 1731 .populate_dml_writeback_from_context = dcn31_populate_dml_writeback_from_context, 1732 .set_mcif_arb_params = dcn31_set_mcif_arb_params, 1733 .find_first_free_match_stream_enc_for_link = dcn10_find_first_free_match_stream_enc_for_link, 1734 .acquire_post_bldn_3dlut = dcn30_acquire_post_bldn_3dlut, 1735 .release_post_bldn_3dlut = dcn30_release_post_bldn_3dlut, 1736 .update_bw_bounding_box = dcn316_update_bw_bounding_box, 1737 .patch_unknown_plane_state = dcn20_patch_unknown_plane_state, 1738 }; 1739 1740 static bool dcn316_resource_construct( 1741 uint8_t num_virtual_links, 1742 struct dc *dc, 1743 struct dcn316_resource_pool *pool) 1744 { 1745 int i; 1746 struct dc_context *ctx = dc->ctx; 1747 struct irq_service_init_data init_data; 1748 1749 ctx->dc_bios->regs = &bios_regs; 1750 1751 pool->base.res_cap = &res_cap_dcn31; 1752 1753 pool->base.funcs = &dcn316_res_pool_funcs; 1754 1755 /************************************************* 1756 * Resource + asic cap harcoding * 1757 *************************************************/ 1758 pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE; 1759 pool->base.pipe_count = pool->base.res_cap->num_timing_generator; 1760 pool->base.mpcc_count = pool->base.res_cap->num_timing_generator; 1761 dc->caps.max_downscale_ratio = 600; 1762 dc->caps.i2c_speed_in_khz = 100; 1763 dc->caps.i2c_speed_in_khz_hdcp = 100; 1764 dc->caps.max_cursor_size = 256; 1765 dc->caps.min_horizontal_blanking_period = 80; 1766 dc->caps.dmdata_alloc_size = 2048; 1767 dc->caps.max_slave_planes = 2; 1768 dc->caps.max_slave_yuv_planes = 2; 1769 dc->caps.max_slave_rgb_planes = 2; 1770 dc->caps.post_blend_color_processing = true; 1771 dc->caps.force_dp_tps4_for_cp2520 = true; 1772 dc->caps.dp_hpo = true; 1773 dc->caps.dp_hdmi21_pcon_support = true; 1774 dc->caps.edp_dsc_support = true; 1775 dc->caps.extended_aux_timeout_support = true; 1776 dc->caps.dmcub_support = true; 1777 dc->caps.is_apu = true; 1778 1779 /* Color pipeline capabilities */ 1780 dc->caps.color.dpp.dcn_arch = 1; 1781 dc->caps.color.dpp.input_lut_shared = 0; 1782 dc->caps.color.dpp.icsc = 1; 1783 dc->caps.color.dpp.dgam_ram = 0; // must use gamma_corr 1784 dc->caps.color.dpp.dgam_rom_caps.srgb = 1; 1785 dc->caps.color.dpp.dgam_rom_caps.bt2020 = 1; 1786 dc->caps.color.dpp.dgam_rom_caps.gamma2_2 = 1; 1787 dc->caps.color.dpp.dgam_rom_caps.pq = 1; 1788 dc->caps.color.dpp.dgam_rom_caps.hlg = 1; 1789 dc->caps.color.dpp.post_csc = 1; 1790 dc->caps.color.dpp.gamma_corr = 1; 1791 dc->caps.color.dpp.dgam_rom_for_yuv = 0; 1792 1793 dc->caps.color.dpp.hw_3d_lut = 1; 1794 dc->caps.color.dpp.ogam_ram = 1; 1795 // no OGAM ROM on DCN301 1796 dc->caps.color.dpp.ogam_rom_caps.srgb = 0; 1797 dc->caps.color.dpp.ogam_rom_caps.bt2020 = 0; 1798 dc->caps.color.dpp.ogam_rom_caps.gamma2_2 = 0; 1799 dc->caps.color.dpp.ogam_rom_caps.pq = 0; 1800 dc->caps.color.dpp.ogam_rom_caps.hlg = 0; 1801 dc->caps.color.dpp.ocsc = 0; 1802 1803 dc->caps.color.mpc.gamut_remap = 1; 1804 dc->caps.color.mpc.num_3dluts = pool->base.res_cap->num_mpc_3dlut; //2 1805 dc->caps.color.mpc.ogam_ram = 1; 1806 dc->caps.color.mpc.ogam_rom_caps.srgb = 0; 1807 dc->caps.color.mpc.ogam_rom_caps.bt2020 = 0; 1808 dc->caps.color.mpc.ogam_rom_caps.gamma2_2 = 0; 1809 dc->caps.color.mpc.ogam_rom_caps.pq = 0; 1810 dc->caps.color.mpc.ogam_rom_caps.hlg = 0; 1811 dc->caps.color.mpc.ocsc = 1; 1812 1813 /* read VBIOS LTTPR caps */ 1814 { 1815 if (ctx->dc_bios->funcs->get_lttpr_caps) { 1816 enum bp_result bp_query_result; 1817 uint8_t is_vbios_lttpr_enable = 0; 1818 1819 bp_query_result = ctx->dc_bios->funcs->get_lttpr_caps(ctx->dc_bios, &is_vbios_lttpr_enable); 1820 dc->caps.vbios_lttpr_enable = (bp_query_result == BP_RESULT_OK) && !!is_vbios_lttpr_enable; 1821 } 1822 1823 /* interop bit is implicit */ 1824 { 1825 dc->caps.vbios_lttpr_aware = true; 1826 } 1827 } 1828 1829 if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV) 1830 dc->debug = debug_defaults_drv; 1831 else if (dc->ctx->dce_environment == DCE_ENV_FPGA_MAXIMUS) { 1832 dc->debug = debug_defaults_diags; 1833 } else 1834 dc->debug = debug_defaults_diags; 1835 // Init the vm_helper 1836 if (dc->vm_helper) 1837 vm_helper_init(dc->vm_helper, 16); 1838 1839 /************************************************* 1840 * Create resources * 1841 *************************************************/ 1842 1843 /* Clock Sources for Pixel Clock*/ 1844 pool->base.clock_sources[DCN31_CLK_SRC_PLL0] = 1845 dcn31_clock_source_create(ctx, ctx->dc_bios, 1846 CLOCK_SOURCE_COMBO_PHY_PLL0, 1847 &clk_src_regs[0], false); 1848 pool->base.clock_sources[DCN31_CLK_SRC_PLL1] = 1849 dcn31_clock_source_create(ctx, ctx->dc_bios, 1850 CLOCK_SOURCE_COMBO_PHY_PLL1, 1851 &clk_src_regs[1], false); 1852 pool->base.clock_sources[DCN31_CLK_SRC_PLL2] = 1853 dcn31_clock_source_create(ctx, ctx->dc_bios, 1854 CLOCK_SOURCE_COMBO_PHY_PLL2, 1855 &clk_src_regs[2], false); 1856 pool->base.clock_sources[DCN31_CLK_SRC_PLL3] = 1857 dcn31_clock_source_create(ctx, ctx->dc_bios, 1858 CLOCK_SOURCE_COMBO_PHY_PLL3, 1859 &clk_src_regs[3], false); 1860 pool->base.clock_sources[DCN31_CLK_SRC_PLL4] = 1861 dcn31_clock_source_create(ctx, ctx->dc_bios, 1862 CLOCK_SOURCE_COMBO_PHY_PLL4, 1863 &clk_src_regs[4], false); 1864 1865 pool->base.clk_src_count = DCN30_CLK_SRC_TOTAL; 1866 1867 /* todo: not reuse phy_pll registers */ 1868 pool->base.dp_clock_source = 1869 dcn31_clock_source_create(ctx, ctx->dc_bios, 1870 CLOCK_SOURCE_ID_DP_DTO, 1871 &clk_src_regs[0], true); 1872 1873 for (i = 0; i < pool->base.clk_src_count; i++) { 1874 if (pool->base.clock_sources[i] == NULL) { 1875 dm_error("DC: failed to create clock sources!\n"); 1876 BREAK_TO_DEBUGGER(); 1877 goto create_fail; 1878 } 1879 } 1880 1881 /* TODO: DCCG */ 1882 pool->base.dccg = dccg31_create(ctx, &dccg_regs, &dccg_shift, &dccg_mask); 1883 if (pool->base.dccg == NULL) { 1884 dm_error("DC: failed to create dccg!\n"); 1885 BREAK_TO_DEBUGGER(); 1886 goto create_fail; 1887 } 1888 1889 /* TODO: IRQ */ 1890 init_data.ctx = dc->ctx; 1891 pool->base.irqs = dal_irq_service_dcn31_create(&init_data); 1892 if (!pool->base.irqs) 1893 goto create_fail; 1894 1895 /* HUBBUB */ 1896 pool->base.hubbub = dcn31_hubbub_create(ctx); 1897 if (pool->base.hubbub == NULL) { 1898 BREAK_TO_DEBUGGER(); 1899 dm_error("DC: failed to create hubbub!\n"); 1900 goto create_fail; 1901 } 1902 1903 /* HUBPs, DPPs, OPPs and TGs */ 1904 for (i = 0; i < pool->base.pipe_count; i++) { 1905 pool->base.hubps[i] = dcn31_hubp_create(ctx, i); 1906 if (pool->base.hubps[i] == NULL) { 1907 BREAK_TO_DEBUGGER(); 1908 dm_error( 1909 "DC: failed to create hubps!\n"); 1910 goto create_fail; 1911 } 1912 1913 pool->base.dpps[i] = dcn31_dpp_create(ctx, i); 1914 if (pool->base.dpps[i] == NULL) { 1915 BREAK_TO_DEBUGGER(); 1916 dm_error( 1917 "DC: failed to create dpps!\n"); 1918 goto create_fail; 1919 } 1920 } 1921 1922 for (i = 0; i < pool->base.res_cap->num_opp; i++) { 1923 pool->base.opps[i] = dcn31_opp_create(ctx, i); 1924 if (pool->base.opps[i] == NULL) { 1925 BREAK_TO_DEBUGGER(); 1926 dm_error( 1927 "DC: failed to create output pixel processor!\n"); 1928 goto create_fail; 1929 } 1930 } 1931 1932 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { 1933 pool->base.timing_generators[i] = dcn31_timing_generator_create( 1934 ctx, i); 1935 if (pool->base.timing_generators[i] == NULL) { 1936 BREAK_TO_DEBUGGER(); 1937 dm_error("DC: failed to create tg!\n"); 1938 goto create_fail; 1939 } 1940 } 1941 pool->base.timing_generator_count = i; 1942 1943 /* PSR */ 1944 pool->base.psr = dmub_psr_create(ctx); 1945 if (pool->base.psr == NULL) { 1946 dm_error("DC: failed to create psr obj!\n"); 1947 BREAK_TO_DEBUGGER(); 1948 goto create_fail; 1949 } 1950 1951 /* ABM */ 1952 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { 1953 pool->base.multiple_abms[i] = dmub_abm_create(ctx, 1954 &abm_regs[i], 1955 &abm_shift, 1956 &abm_mask); 1957 if (pool->base.multiple_abms[i] == NULL) { 1958 dm_error("DC: failed to create abm for pipe %d!\n", i); 1959 BREAK_TO_DEBUGGER(); 1960 goto create_fail; 1961 } 1962 } 1963 1964 /* MPC and DSC */ 1965 pool->base.mpc = dcn31_mpc_create(ctx, pool->base.mpcc_count, pool->base.res_cap->num_mpc_3dlut); 1966 if (pool->base.mpc == NULL) { 1967 BREAK_TO_DEBUGGER(); 1968 dm_error("DC: failed to create mpc!\n"); 1969 goto create_fail; 1970 } 1971 1972 for (i = 0; i < pool->base.res_cap->num_dsc; i++) { 1973 pool->base.dscs[i] = dcn31_dsc_create(ctx, i); 1974 if (pool->base.dscs[i] == NULL) { 1975 BREAK_TO_DEBUGGER(); 1976 dm_error("DC: failed to create display stream compressor %d!\n", i); 1977 goto create_fail; 1978 } 1979 } 1980 1981 /* DWB and MMHUBBUB */ 1982 if (!dcn31_dwbc_create(ctx, &pool->base)) { 1983 BREAK_TO_DEBUGGER(); 1984 dm_error("DC: failed to create dwbc!\n"); 1985 goto create_fail; 1986 } 1987 1988 if (!dcn31_mmhubbub_create(ctx, &pool->base)) { 1989 BREAK_TO_DEBUGGER(); 1990 dm_error("DC: failed to create mcif_wb!\n"); 1991 goto create_fail; 1992 } 1993 1994 /* AUX and I2C */ 1995 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { 1996 pool->base.engines[i] = dcn31_aux_engine_create(ctx, i); 1997 if (pool->base.engines[i] == NULL) { 1998 BREAK_TO_DEBUGGER(); 1999 dm_error( 2000 "DC:failed to create aux engine!!\n"); 2001 goto create_fail; 2002 } 2003 pool->base.hw_i2cs[i] = dcn31_i2c_hw_create(ctx, i); 2004 if (pool->base.hw_i2cs[i] == NULL) { 2005 BREAK_TO_DEBUGGER(); 2006 dm_error( 2007 "DC:failed to create hw i2c!!\n"); 2008 goto create_fail; 2009 } 2010 pool->base.sw_i2cs[i] = NULL; 2011 } 2012 2013 /* Audio, Stream Encoders including HPO and virtual, MPC 3D LUTs */ 2014 if (!resource_construct(num_virtual_links, dc, &pool->base, 2015 (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment) ? 2016 &res_create_funcs : &res_create_maximus_funcs))) 2017 goto create_fail; 2018 2019 /* HW Sequencer and Plane caps */ 2020 dcn31_hw_sequencer_construct(dc); 2021 2022 dc->caps.max_planes = pool->base.pipe_count; 2023 2024 for (i = 0; i < dc->caps.max_planes; ++i) 2025 dc->caps.planes[i] = plane_cap; 2026 2027 dc->cap_funcs = cap_funcs; 2028 2029 dc->dcn_ip->max_num_dpp = dcn3_16_ip.max_num_dpp; 2030 2031 return true; 2032 2033 create_fail: 2034 2035 dcn316_resource_destruct(pool); 2036 2037 return false; 2038 } 2039 2040 struct resource_pool *dcn316_create_resource_pool( 2041 const struct dc_init_data *init_data, 2042 struct dc *dc) 2043 { 2044 struct dcn316_resource_pool *pool = 2045 kzalloc(sizeof(struct dcn316_resource_pool), GFP_KERNEL); 2046 2047 if (!pool) 2048 return NULL; 2049 2050 if (dcn316_resource_construct(init_data->num_virtual_links, dc, pool)) 2051 return &pool->base; 2052 2053 BREAK_TO_DEBUGGER(); 2054 kfree(pool); 2055 return NULL; 2056 } 2057