1 /* 2 * Copyright 2021 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 27 #include "dm_services.h" 28 #include "dc.h" 29 30 #include "dcn31/dcn31_init.h" 31 32 #include "resource.h" 33 #include "include/irq_service_interface.h" 34 #include "dcn315_resource.h" 35 36 #include "dcn20/dcn20_resource.h" 37 #include "dcn30/dcn30_resource.h" 38 #include "dcn31/dcn31_resource.h" 39 40 #include "dcn10/dcn10_ipp.h" 41 #include "dcn30/dcn30_hubbub.h" 42 #include "dcn31/dcn31_hubbub.h" 43 #include "dcn30/dcn30_mpc.h" 44 #include "dcn31/dcn31_hubp.h" 45 #include "irq/dcn315/irq_service_dcn315.h" 46 #include "dcn30/dcn30_dpp.h" 47 #include "dcn31/dcn31_optc.h" 48 #include "dcn20/dcn20_hwseq.h" 49 #include "dcn30/dcn30_hwseq.h" 50 #include "dce110/dce110_hw_sequencer.h" 51 #include "dcn30/dcn30_opp.h" 52 #include "dcn20/dcn20_dsc.h" 53 #include "dcn30/dcn30_vpg.h" 54 #include "dcn30/dcn30_afmt.h" 55 #include "dcn30/dcn30_dio_stream_encoder.h" 56 #include "dcn31/dcn31_hpo_dp_stream_encoder.h" 57 #include "dcn31/dcn31_hpo_dp_link_encoder.h" 58 #include "dcn31/dcn31_apg.h" 59 #include "dcn31/dcn31_dio_link_encoder.h" 60 #include "dcn31/dcn31_vpg.h" 61 #include "dcn31/dcn31_afmt.h" 62 #include "dce/dce_clock_source.h" 63 #include "dce/dce_audio.h" 64 #include "dce/dce_hwseq.h" 65 #include "clk_mgr.h" 66 #include "virtual/virtual_stream_encoder.h" 67 #include "dce110/dce110_resource.h" 68 #include "dml/display_mode_vba.h" 69 #include "dcn31/dcn31_dccg.h" 70 #include "dcn10/dcn10_resource.h" 71 #include "dcn31/dcn31_panel_cntl.h" 72 73 #include "dcn30/dcn30_dwb.h" 74 #include "dcn30/dcn30_mmhubbub.h" 75 76 #include "dcn/dcn_3_1_5_offset.h" 77 #include "dcn/dcn_3_1_5_sh_mask.h" 78 #include "dpcs/dpcs_4_2_2_offset.h" 79 #include "dpcs/dpcs_4_2_2_sh_mask.h" 80 81 #define NBIO_BASE__INST0_SEG0 0x00000000 82 #define NBIO_BASE__INST0_SEG1 0x00000014 83 #define NBIO_BASE__INST0_SEG2 0x00000D20 84 #define NBIO_BASE__INST0_SEG3 0x00010400 85 #define NBIO_BASE__INST0_SEG4 0x0241B000 86 #define NBIO_BASE__INST0_SEG5 0x04040000 87 88 #define DPCS_BASE__INST0_SEG0 0x00000012 89 #define DPCS_BASE__INST0_SEG1 0x000000C0 90 #define DPCS_BASE__INST0_SEG2 0x000034C0 91 #define DPCS_BASE__INST0_SEG3 0x00009000 92 #define DPCS_BASE__INST0_SEG4 0x02403C00 93 #define DPCS_BASE__INST0_SEG5 0 94 95 #define DCN_BASE__INST0_SEG0 0x00000012 96 #define DCN_BASE__INST0_SEG1 0x000000C0 97 #define DCN_BASE__INST0_SEG2 0x000034C0 98 #define DCN_BASE__INST0_SEG3 0x00009000 99 #define DCN_BASE__INST0_SEG4 0x02403C00 100 #define DCN_BASE__INST0_SEG5 0 101 102 #define regBIF_BX_PF2_RSMU_INDEX 0x0000 103 #define regBIF_BX_PF2_RSMU_INDEX_BASE_IDX 1 104 #define regBIF_BX_PF2_RSMU_DATA 0x0001 105 #define regBIF_BX_PF2_RSMU_DATA_BASE_IDX 1 106 #define regBIF_BX2_BIOS_SCRATCH_6 0x003e 107 #define regBIF_BX2_BIOS_SCRATCH_6_BASE_IDX 1 108 #define BIF_BX2_BIOS_SCRATCH_6__BIOS_SCRATCH_6__SHIFT 0x0 109 #define BIF_BX2_BIOS_SCRATCH_6__BIOS_SCRATCH_6_MASK 0xFFFFFFFFL 110 #define regBIF_BX2_BIOS_SCRATCH_2 0x003a 111 #define regBIF_BX2_BIOS_SCRATCH_2_BASE_IDX 1 112 #define BIF_BX2_BIOS_SCRATCH_2__BIOS_SCRATCH_2__SHIFT 0x0 113 #define BIF_BX2_BIOS_SCRATCH_2__BIOS_SCRATCH_2_MASK 0xFFFFFFFFL 114 #define regBIF_BX2_BIOS_SCRATCH_3 0x003b 115 #define regBIF_BX2_BIOS_SCRATCH_3_BASE_IDX 1 116 #define BIF_BX2_BIOS_SCRATCH_3__BIOS_SCRATCH_3__SHIFT 0x0 117 #define BIF_BX2_BIOS_SCRATCH_3__BIOS_SCRATCH_3_MASK 0xFFFFFFFFL 118 119 #define regDCHUBBUB_DEBUG_CTRL_0 0x04d6 120 #define regDCHUBBUB_DEBUG_CTRL_0_BASE_IDX 2 121 #define DCHUBBUB_DEBUG_CTRL_0__DET_DEPTH__SHIFT 0x10 122 #define DCHUBBUB_DEBUG_CTRL_0__DET_DEPTH_MASK 0x01FF0000L 123 124 #include "reg_helper.h" 125 #include "dce/dmub_abm.h" 126 #include "dce/dmub_psr.h" 127 #include "dce/dce_aux.h" 128 #include "dce/dce_i2c.h" 129 130 #include "dml/dcn30/display_mode_vba_30.h" 131 #include "vm_helper.h" 132 #include "dcn20/dcn20_vmid.h" 133 134 #include "link_enc_cfg.h" 135 136 #define DC_LOGGER_INIT(logger) 137 138 #define DCN3_15_DEFAULT_DET_SIZE 192 139 #define DCN3_15_MAX_DET_SIZE 384 140 #define DCN3_15_MIN_COMPBUF_SIZE_KB 128 141 #define DCN3_15_CRB_SEGMENT_SIZE_KB 64 142 143 struct _vcs_dpi_ip_params_st dcn3_15_ip = { 144 .gpuvm_enable = 1, 145 .gpuvm_max_page_table_levels = 1, 146 .hostvm_enable = 1, 147 .hostvm_max_page_table_levels = 2, 148 .rob_buffer_size_kbytes = 64, 149 .det_buffer_size_kbytes = DCN3_15_DEFAULT_DET_SIZE, 150 .min_comp_buffer_size_kbytes = DCN3_15_MIN_COMPBUF_SIZE_KB, 151 .config_return_buffer_size_in_kbytes = 1024, 152 .compressed_buffer_segment_size_in_kbytes = 64, 153 .meta_fifo_size_in_kentries = 32, 154 .zero_size_buffer_entries = 512, 155 .compbuf_reserved_space_64b = 256, 156 .compbuf_reserved_space_zs = 64, 157 .dpp_output_buffer_pixels = 2560, 158 .opp_output_buffer_lines = 1, 159 .pixel_chunk_size_kbytes = 8, 160 .meta_chunk_size_kbytes = 2, 161 .min_meta_chunk_size_bytes = 256, 162 .writeback_chunk_size_kbytes = 8, 163 .ptoi_supported = false, 164 .num_dsc = 3, 165 .maximum_dsc_bits_per_component = 10, 166 .dsc422_native_support = false, 167 .is_line_buffer_bpp_fixed = true, 168 .line_buffer_fixed_bpp = 49, 169 .line_buffer_size_bits = 789504, 170 .max_line_buffer_lines = 12, 171 .writeback_interface_buffer_size_kbytes = 90, 172 .max_num_dpp = 4, 173 .max_num_otg = 4, 174 .max_num_hdmi_frl_outputs = 1, 175 .max_num_wb = 1, 176 .max_dchub_pscl_bw_pix_per_clk = 4, 177 .max_pscl_lb_bw_pix_per_clk = 2, 178 .max_lb_vscl_bw_pix_per_clk = 4, 179 .max_vscl_hscl_bw_pix_per_clk = 4, 180 .max_hscl_ratio = 6, 181 .max_vscl_ratio = 6, 182 .max_hscl_taps = 8, 183 .max_vscl_taps = 8, 184 .dpte_buffer_size_in_pte_reqs_luma = 64, 185 .dpte_buffer_size_in_pte_reqs_chroma = 34, 186 .dispclk_ramp_margin_percent = 1, 187 .max_inter_dcn_tile_repeaters = 9, 188 .cursor_buffer_size = 16, 189 .cursor_chunk_size = 2, 190 .writeback_line_buffer_buffer_size = 0, 191 .writeback_min_hscl_ratio = 1, 192 .writeback_min_vscl_ratio = 1, 193 .writeback_max_hscl_ratio = 1, 194 .writeback_max_vscl_ratio = 1, 195 .writeback_max_hscl_taps = 1, 196 .writeback_max_vscl_taps = 1, 197 .dppclk_delay_subtotal = 46, 198 .dppclk_delay_scl = 50, 199 .dppclk_delay_scl_lb_only = 16, 200 .dppclk_delay_cnvc_formatter = 27, 201 .dppclk_delay_cnvc_cursor = 6, 202 .dispclk_delay_subtotal = 119, 203 .dynamic_metadata_vm_enabled = false, 204 .odm_combine_4to1_supported = false, 205 .dcc_supported = true, 206 }; 207 208 struct _vcs_dpi_soc_bounding_box_st dcn3_15_soc = { 209 /*TODO: correct dispclk/dppclk voltage level determination*/ 210 .clock_limits = { 211 { 212 .state = 0, 213 .dispclk_mhz = 1372.0, 214 .dppclk_mhz = 1372.0, 215 .phyclk_mhz = 810.0, 216 .phyclk_d18_mhz = 667.0, 217 .dscclk_mhz = 417.0, 218 .dtbclk_mhz = 600.0, 219 }, 220 { 221 .state = 1, 222 .dispclk_mhz = 1372.0, 223 .dppclk_mhz = 1372.0, 224 .phyclk_mhz = 810.0, 225 .phyclk_d18_mhz = 667.0, 226 .dscclk_mhz = 417.0, 227 .dtbclk_mhz = 600.0, 228 }, 229 { 230 .state = 2, 231 .dispclk_mhz = 1372.0, 232 .dppclk_mhz = 1372.0, 233 .phyclk_mhz = 810.0, 234 .phyclk_d18_mhz = 667.0, 235 .dscclk_mhz = 417.0, 236 .dtbclk_mhz = 600.0, 237 }, 238 { 239 .state = 3, 240 .dispclk_mhz = 1372.0, 241 .dppclk_mhz = 1372.0, 242 .phyclk_mhz = 810.0, 243 .phyclk_d18_mhz = 667.0, 244 .dscclk_mhz = 417.0, 245 .dtbclk_mhz = 600.0, 246 }, 247 { 248 .state = 4, 249 .dispclk_mhz = 1372.0, 250 .dppclk_mhz = 1372.0, 251 .phyclk_mhz = 810.0, 252 .phyclk_d18_mhz = 667.0, 253 .dscclk_mhz = 417.0, 254 .dtbclk_mhz = 600.0, 255 }, 256 }, 257 .num_states = 5, 258 .sr_exit_time_us = 9.0, 259 .sr_enter_plus_exit_time_us = 11.0, 260 .sr_exit_z8_time_us = 50.0, 261 .sr_enter_plus_exit_z8_time_us = 50.0, 262 .writeback_latency_us = 12.0, 263 .dram_channel_width_bytes = 4, 264 .round_trip_ping_latency_dcfclk_cycles = 106, 265 .urgent_latency_pixel_data_only_us = 4.0, 266 .urgent_latency_pixel_mixed_with_vm_data_us = 4.0, 267 .urgent_latency_vm_data_only_us = 4.0, 268 .urgent_out_of_order_return_per_channel_pixel_only_bytes = 4096, 269 .urgent_out_of_order_return_per_channel_pixel_and_vm_bytes = 4096, 270 .urgent_out_of_order_return_per_channel_vm_only_bytes = 4096, 271 .pct_ideal_sdp_bw_after_urgent = 80.0, 272 .pct_ideal_dram_sdp_bw_after_urgent_pixel_only = 65.0, 273 .pct_ideal_dram_sdp_bw_after_urgent_pixel_and_vm = 60.0, 274 .pct_ideal_dram_sdp_bw_after_urgent_vm_only = 30.0, 275 .max_avg_sdp_bw_use_normal_percent = 60.0, 276 .max_avg_dram_bw_use_normal_percent = 60.0, 277 .fabric_datapath_to_dcn_data_return_bytes = 32, 278 .return_bus_width_bytes = 64, 279 .downspread_percent = 0.38, 280 .dcn_downspread_percent = 0.38, 281 .gpuvm_min_page_size_bytes = 4096, 282 .hostvm_min_page_size_bytes = 4096, 283 .do_urgent_latency_adjustment = false, 284 .urgent_latency_adjustment_fabric_clock_component_us = 0, 285 .urgent_latency_adjustment_fabric_clock_reference_mhz = 0, 286 }; 287 288 enum dcn31_clk_src_array_id { 289 DCN31_CLK_SRC_PLL0, 290 DCN31_CLK_SRC_PLL1, 291 DCN31_CLK_SRC_PLL2, 292 DCN31_CLK_SRC_PLL3, 293 DCN31_CLK_SRC_PLL4, 294 DCN30_CLK_SRC_TOTAL 295 }; 296 297 /* begin ********************* 298 * macros to expend register list macro defined in HW object header file 299 */ 300 301 /* DCN */ 302 /* TODO awful hack. fixup dcn20_dwb.h */ 303 #undef BASE_INNER 304 #define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg 305 306 #define BASE(seg) BASE_INNER(seg) 307 308 #define SR(reg_name)\ 309 .reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \ 310 reg ## reg_name 311 312 #define SRI(reg_name, block, id)\ 313 .reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 314 reg ## block ## id ## _ ## reg_name 315 316 #define SRI2(reg_name, block, id)\ 317 .reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \ 318 reg ## reg_name 319 320 #define SRIR(var_name, reg_name, block, id)\ 321 .var_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 322 reg ## block ## id ## _ ## reg_name 323 324 #define SRII(reg_name, block, id)\ 325 .reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 326 reg ## block ## id ## _ ## reg_name 327 328 #define SRII_MPC_RMU(reg_name, block, id)\ 329 .RMU##_##reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 330 reg ## block ## id ## _ ## reg_name 331 332 #define SRII_DWB(reg_name, temp_name, block, id)\ 333 .reg_name[id] = BASE(reg ## block ## id ## _ ## temp_name ## _BASE_IDX) + \ 334 reg ## block ## id ## _ ## temp_name 335 336 #define DCCG_SRII(reg_name, block, id)\ 337 .block ## _ ## reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 338 reg ## block ## id ## _ ## reg_name 339 340 #define VUPDATE_SRII(reg_name, block, id)\ 341 .reg_name[id] = BASE(reg ## reg_name ## _ ## block ## id ## _BASE_IDX) + \ 342 reg ## reg_name ## _ ## block ## id 343 344 /* NBIO */ 345 #define NBIO_BASE_INNER(seg) \ 346 NBIO_BASE__INST0_SEG ## seg 347 348 #define NBIO_BASE(seg) \ 349 NBIO_BASE_INNER(seg) 350 351 #define NBIO_SR(reg_name)\ 352 .reg_name = NBIO_BASE(regBIF_BX2_ ## reg_name ## _BASE_IDX) + \ 353 regBIF_BX2_ ## reg_name 354 355 static const struct bios_registers bios_regs = { 356 NBIO_SR(BIOS_SCRATCH_3), 357 NBIO_SR(BIOS_SCRATCH_6) 358 }; 359 360 #define clk_src_regs(index, pllid)\ 361 [index] = {\ 362 CS_COMMON_REG_LIST_DCN3_0(index, pllid),\ 363 } 364 365 static const struct dce110_clk_src_regs clk_src_regs[] = { 366 clk_src_regs(0, A), 367 clk_src_regs(1, B), 368 clk_src_regs(2, C), 369 clk_src_regs(3, D), 370 clk_src_regs(4, E) 371 }; 372 373 static const struct dce110_clk_src_shift cs_shift = { 374 CS_COMMON_MASK_SH_LIST_DCN2_0(__SHIFT) 375 }; 376 377 static const struct dce110_clk_src_mask cs_mask = { 378 CS_COMMON_MASK_SH_LIST_DCN2_0(_MASK) 379 }; 380 381 #define abm_regs(id)\ 382 [id] = {\ 383 ABM_DCN302_REG_LIST(id)\ 384 } 385 386 static const struct dce_abm_registers abm_regs[] = { 387 abm_regs(0), 388 abm_regs(1), 389 abm_regs(2), 390 abm_regs(3), 391 }; 392 393 static const struct dce_abm_shift abm_shift = { 394 ABM_MASK_SH_LIST_DCN30(__SHIFT) 395 }; 396 397 static const struct dce_abm_mask abm_mask = { 398 ABM_MASK_SH_LIST_DCN30(_MASK) 399 }; 400 401 #define audio_regs(id)\ 402 [id] = {\ 403 AUD_COMMON_REG_LIST(id)\ 404 } 405 406 static const struct dce_audio_registers audio_regs[] = { 407 audio_regs(0), 408 audio_regs(1), 409 audio_regs(2), 410 audio_regs(3), 411 audio_regs(4), 412 audio_regs(5), 413 audio_regs(6) 414 }; 415 416 #define DCE120_AUD_COMMON_MASK_SH_LIST(mask_sh)\ 417 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX, AZALIA_ENDPOINT_REG_INDEX, mask_sh),\ 418 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA, AZALIA_ENDPOINT_REG_DATA, mask_sh),\ 419 AUD_COMMON_MASK_SH_LIST_BASE(mask_sh) 420 421 static const struct dce_audio_shift audio_shift = { 422 DCE120_AUD_COMMON_MASK_SH_LIST(__SHIFT) 423 }; 424 425 static const struct dce_audio_mask audio_mask = { 426 DCE120_AUD_COMMON_MASK_SH_LIST(_MASK) 427 }; 428 429 #define vpg_regs(id)\ 430 [id] = {\ 431 VPG_DCN31_REG_LIST(id)\ 432 } 433 434 static const struct dcn31_vpg_registers vpg_regs[] = { 435 vpg_regs(0), 436 vpg_regs(1), 437 vpg_regs(2), 438 vpg_regs(3), 439 vpg_regs(4), 440 vpg_regs(5), 441 vpg_regs(6), 442 vpg_regs(7), 443 vpg_regs(8), 444 vpg_regs(9), 445 }; 446 447 static const struct dcn31_vpg_shift vpg_shift = { 448 DCN31_VPG_MASK_SH_LIST(__SHIFT) 449 }; 450 451 static const struct dcn31_vpg_mask vpg_mask = { 452 DCN31_VPG_MASK_SH_LIST(_MASK) 453 }; 454 455 #define afmt_regs(id)\ 456 [id] = {\ 457 AFMT_DCN31_REG_LIST(id)\ 458 } 459 460 static const struct dcn31_afmt_registers afmt_regs[] = { 461 afmt_regs(0), 462 afmt_regs(1), 463 afmt_regs(2), 464 afmt_regs(3), 465 afmt_regs(4), 466 afmt_regs(5) 467 }; 468 469 static const struct dcn31_afmt_shift afmt_shift = { 470 DCN31_AFMT_MASK_SH_LIST(__SHIFT) 471 }; 472 473 static const struct dcn31_afmt_mask afmt_mask = { 474 DCN31_AFMT_MASK_SH_LIST(_MASK) 475 }; 476 477 #define apg_regs(id)\ 478 [id] = {\ 479 APG_DCN31_REG_LIST(id)\ 480 } 481 482 static const struct dcn31_apg_registers apg_regs[] = { 483 apg_regs(0), 484 apg_regs(1), 485 apg_regs(2), 486 apg_regs(3) 487 }; 488 489 static const struct dcn31_apg_shift apg_shift = { 490 DCN31_APG_MASK_SH_LIST(__SHIFT) 491 }; 492 493 static const struct dcn31_apg_mask apg_mask = { 494 DCN31_APG_MASK_SH_LIST(_MASK) 495 }; 496 497 #define stream_enc_regs(id)\ 498 [id] = {\ 499 SE_DCN3_REG_LIST(id)\ 500 } 501 502 static const struct dcn10_stream_enc_registers stream_enc_regs[] = { 503 stream_enc_regs(0), 504 stream_enc_regs(1), 505 stream_enc_regs(2), 506 stream_enc_regs(3), 507 stream_enc_regs(4) 508 }; 509 510 static const struct dcn10_stream_encoder_shift se_shift = { 511 SE_COMMON_MASK_SH_LIST_DCN30(__SHIFT) 512 }; 513 514 static const struct dcn10_stream_encoder_mask se_mask = { 515 SE_COMMON_MASK_SH_LIST_DCN30(_MASK) 516 }; 517 518 519 #define aux_regs(id)\ 520 [id] = {\ 521 DCN2_AUX_REG_LIST(id)\ 522 } 523 524 static const struct dcn10_link_enc_aux_registers link_enc_aux_regs[] = { 525 aux_regs(0), 526 aux_regs(1), 527 aux_regs(2), 528 aux_regs(3), 529 aux_regs(4) 530 }; 531 532 #define hpd_regs(id)\ 533 [id] = {\ 534 HPD_REG_LIST(id)\ 535 } 536 537 static const struct dcn10_link_enc_hpd_registers link_enc_hpd_regs[] = { 538 hpd_regs(0), 539 hpd_regs(1), 540 hpd_regs(2), 541 hpd_regs(3), 542 hpd_regs(4) 543 }; 544 545 #define link_regs(id, phyid)\ 546 [id] = {\ 547 LE_DCN31_REG_LIST(id), \ 548 UNIPHY_DCN2_REG_LIST(phyid), \ 549 DPCS_DCN31_REG_LIST(id), \ 550 } 551 552 static const struct dce110_aux_registers_shift aux_shift = { 553 DCN_AUX_MASK_SH_LIST(__SHIFT) 554 }; 555 556 static const struct dce110_aux_registers_mask aux_mask = { 557 DCN_AUX_MASK_SH_LIST(_MASK) 558 }; 559 560 static const struct dcn10_link_enc_registers link_enc_regs[] = { 561 link_regs(0, A), 562 link_regs(1, B), 563 link_regs(2, C), 564 link_regs(3, D), 565 link_regs(4, E) 566 }; 567 568 static const struct dcn10_link_enc_shift le_shift = { 569 LINK_ENCODER_MASK_SH_LIST_DCN31(__SHIFT), \ 570 DPCS_DCN31_MASK_SH_LIST(__SHIFT) 571 }; 572 573 static const struct dcn10_link_enc_mask le_mask = { 574 LINK_ENCODER_MASK_SH_LIST_DCN31(_MASK), \ 575 DPCS_DCN31_MASK_SH_LIST(_MASK) 576 }; 577 578 #define hpo_dp_stream_encoder_reg_list(id)\ 579 [id] = {\ 580 DCN3_1_HPO_DP_STREAM_ENC_REG_LIST(id)\ 581 } 582 583 static const struct dcn31_hpo_dp_stream_encoder_registers hpo_dp_stream_enc_regs[] = { 584 hpo_dp_stream_encoder_reg_list(0), 585 hpo_dp_stream_encoder_reg_list(1), 586 hpo_dp_stream_encoder_reg_list(2), 587 hpo_dp_stream_encoder_reg_list(3), 588 }; 589 590 static const struct dcn31_hpo_dp_stream_encoder_shift hpo_dp_se_shift = { 591 DCN3_1_HPO_DP_STREAM_ENC_MASK_SH_LIST(__SHIFT) 592 }; 593 594 static const struct dcn31_hpo_dp_stream_encoder_mask hpo_dp_se_mask = { 595 DCN3_1_HPO_DP_STREAM_ENC_MASK_SH_LIST(_MASK) 596 }; 597 598 599 #define hpo_dp_link_encoder_reg_list(id)\ 600 [id] = {\ 601 DCN3_1_HPO_DP_LINK_ENC_REG_LIST(id),\ 602 DCN3_1_RDPCSTX_REG_LIST(0),\ 603 DCN3_1_RDPCSTX_REG_LIST(1),\ 604 DCN3_1_RDPCSTX_REG_LIST(2),\ 605 DCN3_1_RDPCSTX_REG_LIST(3),\ 606 DCN3_1_RDPCSTX_REG_LIST(4)\ 607 } 608 609 static const struct dcn31_hpo_dp_link_encoder_registers hpo_dp_link_enc_regs[] = { 610 hpo_dp_link_encoder_reg_list(0), 611 hpo_dp_link_encoder_reg_list(1), 612 }; 613 614 static const struct dcn31_hpo_dp_link_encoder_shift hpo_dp_le_shift = { 615 DCN3_1_HPO_DP_LINK_ENC_MASK_SH_LIST(__SHIFT) 616 }; 617 618 static const struct dcn31_hpo_dp_link_encoder_mask hpo_dp_le_mask = { 619 DCN3_1_HPO_DP_LINK_ENC_MASK_SH_LIST(_MASK) 620 }; 621 622 #define dpp_regs(id)\ 623 [id] = {\ 624 DPP_REG_LIST_DCN30(id),\ 625 } 626 627 static const struct dcn3_dpp_registers dpp_regs[] = { 628 dpp_regs(0), 629 dpp_regs(1), 630 dpp_regs(2), 631 dpp_regs(3) 632 }; 633 634 static const struct dcn3_dpp_shift tf_shift = { 635 DPP_REG_LIST_SH_MASK_DCN30(__SHIFT) 636 }; 637 638 static const struct dcn3_dpp_mask tf_mask = { 639 DPP_REG_LIST_SH_MASK_DCN30(_MASK) 640 }; 641 642 #define opp_regs(id)\ 643 [id] = {\ 644 OPP_REG_LIST_DCN30(id),\ 645 } 646 647 static const struct dcn20_opp_registers opp_regs[] = { 648 opp_regs(0), 649 opp_regs(1), 650 opp_regs(2), 651 opp_regs(3) 652 }; 653 654 static const struct dcn20_opp_shift opp_shift = { 655 OPP_MASK_SH_LIST_DCN20(__SHIFT) 656 }; 657 658 static const struct dcn20_opp_mask opp_mask = { 659 OPP_MASK_SH_LIST_DCN20(_MASK) 660 }; 661 662 #define aux_engine_regs(id)\ 663 [id] = {\ 664 AUX_COMMON_REG_LIST0(id), \ 665 .AUXN_IMPCAL = 0, \ 666 .AUXP_IMPCAL = 0, \ 667 .AUX_RESET_MASK = DP_AUX0_AUX_CONTROL__AUX_RESET_MASK, \ 668 } 669 670 static const struct dce110_aux_registers aux_engine_regs[] = { 671 aux_engine_regs(0), 672 aux_engine_regs(1), 673 aux_engine_regs(2), 674 aux_engine_regs(3), 675 aux_engine_regs(4) 676 }; 677 678 #define dwbc_regs_dcn3(id)\ 679 [id] = {\ 680 DWBC_COMMON_REG_LIST_DCN30(id),\ 681 } 682 683 static const struct dcn30_dwbc_registers dwbc30_regs[] = { 684 dwbc_regs_dcn3(0), 685 }; 686 687 static const struct dcn30_dwbc_shift dwbc30_shift = { 688 DWBC_COMMON_MASK_SH_LIST_DCN30(__SHIFT) 689 }; 690 691 static const struct dcn30_dwbc_mask dwbc30_mask = { 692 DWBC_COMMON_MASK_SH_LIST_DCN30(_MASK) 693 }; 694 695 #define mcif_wb_regs_dcn3(id)\ 696 [id] = {\ 697 MCIF_WB_COMMON_REG_LIST_DCN30(id),\ 698 } 699 700 static const struct dcn30_mmhubbub_registers mcif_wb30_regs[] = { 701 mcif_wb_regs_dcn3(0) 702 }; 703 704 static const struct dcn30_mmhubbub_shift mcif_wb30_shift = { 705 MCIF_WB_COMMON_MASK_SH_LIST_DCN30(__SHIFT) 706 }; 707 708 static const struct dcn30_mmhubbub_mask mcif_wb30_mask = { 709 MCIF_WB_COMMON_MASK_SH_LIST_DCN30(_MASK) 710 }; 711 712 #define dsc_regsDCN20(id)\ 713 [id] = {\ 714 DSC_REG_LIST_DCN20(id)\ 715 } 716 717 static const struct dcn20_dsc_registers dsc_regs[] = { 718 dsc_regsDCN20(0), 719 dsc_regsDCN20(1), 720 dsc_regsDCN20(2) 721 }; 722 723 static const struct dcn20_dsc_shift dsc_shift = { 724 DSC_REG_LIST_SH_MASK_DCN20(__SHIFT) 725 }; 726 727 static const struct dcn20_dsc_mask dsc_mask = { 728 DSC_REG_LIST_SH_MASK_DCN20(_MASK) 729 }; 730 731 static const struct dcn30_mpc_registers mpc_regs = { 732 MPC_REG_LIST_DCN3_0(0), 733 MPC_REG_LIST_DCN3_0(1), 734 MPC_REG_LIST_DCN3_0(2), 735 MPC_REG_LIST_DCN3_0(3), 736 MPC_OUT_MUX_REG_LIST_DCN3_0(0), 737 MPC_OUT_MUX_REG_LIST_DCN3_0(1), 738 MPC_OUT_MUX_REG_LIST_DCN3_0(2), 739 MPC_OUT_MUX_REG_LIST_DCN3_0(3), 740 MPC_DWB_MUX_REG_LIST_DCN3_0(0), 741 }; 742 743 static const struct dcn30_mpc_shift mpc_shift = { 744 MPC_COMMON_MASK_SH_LIST_DCN30(__SHIFT) 745 }; 746 747 static const struct dcn30_mpc_mask mpc_mask = { 748 MPC_COMMON_MASK_SH_LIST_DCN30(_MASK) 749 }; 750 751 #define optc_regs(id)\ 752 [id] = {OPTC_COMMON_REG_LIST_DCN3_1(id)} 753 754 static const struct dcn_optc_registers optc_regs[] = { 755 optc_regs(0), 756 optc_regs(1), 757 optc_regs(2), 758 optc_regs(3) 759 }; 760 761 static const struct dcn_optc_shift optc_shift = { 762 OPTC_COMMON_MASK_SH_LIST_DCN3_1(__SHIFT) 763 }; 764 765 static const struct dcn_optc_mask optc_mask = { 766 OPTC_COMMON_MASK_SH_LIST_DCN3_1(_MASK) 767 }; 768 769 #define hubp_regs(id)\ 770 [id] = {\ 771 HUBP_REG_LIST_DCN30(id)\ 772 } 773 774 static const struct dcn_hubp2_registers hubp_regs[] = { 775 hubp_regs(0), 776 hubp_regs(1), 777 hubp_regs(2), 778 hubp_regs(3) 779 }; 780 781 782 static const struct dcn_hubp2_shift hubp_shift = { 783 HUBP_MASK_SH_LIST_DCN31(__SHIFT) 784 }; 785 786 static const struct dcn_hubp2_mask hubp_mask = { 787 HUBP_MASK_SH_LIST_DCN31(_MASK) 788 }; 789 static const struct dcn_hubbub_registers hubbub_reg = { 790 HUBBUB_REG_LIST_DCN31(0) 791 }; 792 793 static const struct dcn_hubbub_shift hubbub_shift = { 794 HUBBUB_MASK_SH_LIST_DCN31(__SHIFT) 795 }; 796 797 static const struct dcn_hubbub_mask hubbub_mask = { 798 HUBBUB_MASK_SH_LIST_DCN31(_MASK) 799 }; 800 801 static const struct dccg_registers dccg_regs = { 802 DCCG_REG_LIST_DCN31() 803 }; 804 805 static const struct dccg_shift dccg_shift = { 806 DCCG_MASK_SH_LIST_DCN31(__SHIFT) 807 }; 808 809 static const struct dccg_mask dccg_mask = { 810 DCCG_MASK_SH_LIST_DCN31(_MASK) 811 }; 812 813 814 #define SRII2(reg_name_pre, reg_name_post, id)\ 815 .reg_name_pre ## _ ## reg_name_post[id] = BASE(reg ## reg_name_pre \ 816 ## id ## _ ## reg_name_post ## _BASE_IDX) + \ 817 reg ## reg_name_pre ## id ## _ ## reg_name_post 818 819 820 #define HWSEQ_DCN31_REG_LIST()\ 821 SR(DCHUBBUB_GLOBAL_TIMER_CNTL), \ 822 SR(DCHUBBUB_ARB_HOSTVM_CNTL), \ 823 SR(DIO_MEM_PWR_CTRL), \ 824 SR(ODM_MEM_PWR_CTRL3), \ 825 SR(DMU_MEM_PWR_CNTL), \ 826 SR(MMHUBBUB_MEM_PWR_CNTL), \ 827 SR(DCCG_GATE_DISABLE_CNTL), \ 828 SR(DCCG_GATE_DISABLE_CNTL2), \ 829 SR(DCFCLK_CNTL),\ 830 SR(DC_MEM_GLOBAL_PWR_REQ_CNTL), \ 831 SRII(PIXEL_RATE_CNTL, OTG, 0), \ 832 SRII(PIXEL_RATE_CNTL, OTG, 1),\ 833 SRII(PIXEL_RATE_CNTL, OTG, 2),\ 834 SRII(PIXEL_RATE_CNTL, OTG, 3),\ 835 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 0),\ 836 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 1),\ 837 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 2),\ 838 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 3),\ 839 SR(MICROSECOND_TIME_BASE_DIV), \ 840 SR(MILLISECOND_TIME_BASE_DIV), \ 841 SR(DISPCLK_FREQ_CHANGE_CNTL), \ 842 SR(RBBMIF_TIMEOUT_DIS), \ 843 SR(RBBMIF_TIMEOUT_DIS_2), \ 844 SR(DCHUBBUB_CRC_CTRL), \ 845 SR(DPP_TOP0_DPP_CRC_CTRL), \ 846 SR(DPP_TOP0_DPP_CRC_VAL_B_A), \ 847 SR(DPP_TOP0_DPP_CRC_VAL_R_G), \ 848 SR(MPC_CRC_CTRL), \ 849 SR(MPC_CRC_RESULT_GB), \ 850 SR(MPC_CRC_RESULT_C), \ 851 SR(MPC_CRC_RESULT_AR), \ 852 SR(DOMAIN0_PG_CONFIG), \ 853 SR(DOMAIN1_PG_CONFIG), \ 854 SR(DOMAIN2_PG_CONFIG), \ 855 SR(DOMAIN3_PG_CONFIG), \ 856 SR(DOMAIN16_PG_CONFIG), \ 857 SR(DOMAIN17_PG_CONFIG), \ 858 SR(DOMAIN18_PG_CONFIG), \ 859 SR(DOMAIN0_PG_STATUS), \ 860 SR(DOMAIN1_PG_STATUS), \ 861 SR(DOMAIN2_PG_STATUS), \ 862 SR(DOMAIN3_PG_STATUS), \ 863 SR(DOMAIN16_PG_STATUS), \ 864 SR(DOMAIN17_PG_STATUS), \ 865 SR(DOMAIN18_PG_STATUS), \ 866 SR(D1VGA_CONTROL), \ 867 SR(D2VGA_CONTROL), \ 868 SR(D3VGA_CONTROL), \ 869 SR(D4VGA_CONTROL), \ 870 SR(D5VGA_CONTROL), \ 871 SR(D6VGA_CONTROL), \ 872 SR(DC_IP_REQUEST_CNTL), \ 873 SR(AZALIA_AUDIO_DTO), \ 874 SR(AZALIA_CONTROLLER_CLOCK_GATING), \ 875 SR(HPO_TOP_HW_CONTROL) 876 877 static const struct dce_hwseq_registers hwseq_reg = { 878 HWSEQ_DCN31_REG_LIST() 879 }; 880 881 #define HWSEQ_DCN31_MASK_SH_LIST(mask_sh)\ 882 HWSEQ_DCN_MASK_SH_LIST(mask_sh), \ 883 HWS_SF(, DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_REFDIV, mask_sh), \ 884 HWS_SF(, DCHUBBUB_ARB_HOSTVM_CNTL, DISABLE_HOSTVM_FORCE_ALLOW_PSTATE, mask_sh), \ 885 HWS_SF(, DOMAIN0_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ 886 HWS_SF(, DOMAIN0_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ 887 HWS_SF(, DOMAIN1_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ 888 HWS_SF(, DOMAIN1_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ 889 HWS_SF(, DOMAIN2_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ 890 HWS_SF(, DOMAIN2_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ 891 HWS_SF(, DOMAIN3_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ 892 HWS_SF(, DOMAIN3_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ 893 HWS_SF(, DOMAIN16_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ 894 HWS_SF(, DOMAIN16_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ 895 HWS_SF(, DOMAIN17_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ 896 HWS_SF(, DOMAIN17_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ 897 HWS_SF(, DOMAIN18_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ 898 HWS_SF(, DOMAIN18_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ 899 HWS_SF(, DOMAIN0_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ 900 HWS_SF(, DOMAIN1_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ 901 HWS_SF(, DOMAIN2_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ 902 HWS_SF(, DOMAIN3_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ 903 HWS_SF(, DOMAIN16_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ 904 HWS_SF(, DOMAIN17_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ 905 HWS_SF(, DOMAIN18_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ 906 HWS_SF(, DC_IP_REQUEST_CNTL, IP_REQUEST_EN, mask_sh), \ 907 HWS_SF(, AZALIA_AUDIO_DTO, AZALIA_AUDIO_DTO_MODULE, mask_sh), \ 908 HWS_SF(, HPO_TOP_CLOCK_CONTROL, HPO_HDMISTREAMCLK_G_GATE_DIS, mask_sh), \ 909 HWS_SF(, DMU_MEM_PWR_CNTL, DMCU_ERAM_MEM_PWR_FORCE, mask_sh), \ 910 HWS_SF(, ODM_MEM_PWR_CTRL3, ODM_MEM_UNASSIGNED_PWR_MODE, mask_sh), \ 911 HWS_SF(, ODM_MEM_PWR_CTRL3, ODM_MEM_VBLANK_PWR_MODE, mask_sh), \ 912 HWS_SF(, MMHUBBUB_MEM_PWR_CNTL, VGA_MEM_PWR_FORCE, mask_sh), \ 913 HWS_SF(, DIO_MEM_PWR_CTRL, I2C_LIGHT_SLEEP_FORCE, mask_sh), \ 914 HWS_SF(, HPO_TOP_HW_CONTROL, HPO_IO_EN, mask_sh) 915 916 static const struct dce_hwseq_shift hwseq_shift = { 917 HWSEQ_DCN31_MASK_SH_LIST(__SHIFT) 918 }; 919 920 static const struct dce_hwseq_mask hwseq_mask = { 921 HWSEQ_DCN31_MASK_SH_LIST(_MASK) 922 }; 923 #define vmid_regs(id)\ 924 [id] = {\ 925 DCN20_VMID_REG_LIST(id)\ 926 } 927 928 static const struct dcn_vmid_registers vmid_regs[] = { 929 vmid_regs(0), 930 vmid_regs(1), 931 vmid_regs(2), 932 vmid_regs(3), 933 vmid_regs(4), 934 vmid_regs(5), 935 vmid_regs(6), 936 vmid_regs(7), 937 vmid_regs(8), 938 vmid_regs(9), 939 vmid_regs(10), 940 vmid_regs(11), 941 vmid_regs(12), 942 vmid_regs(13), 943 vmid_regs(14), 944 vmid_regs(15) 945 }; 946 947 static const struct dcn20_vmid_shift vmid_shifts = { 948 DCN20_VMID_MASK_SH_LIST(__SHIFT) 949 }; 950 951 static const struct dcn20_vmid_mask vmid_masks = { 952 DCN20_VMID_MASK_SH_LIST(_MASK) 953 }; 954 955 static const struct resource_caps res_cap_dcn31 = { 956 .num_timing_generator = 4, 957 .num_opp = 4, 958 .num_video_plane = 4, 959 .num_audio = 5, 960 .num_stream_encoder = 5, 961 .num_dig_link_enc = 5, 962 .num_hpo_dp_stream_encoder = 4, 963 .num_hpo_dp_link_encoder = 2, 964 .num_pll = 5, 965 .num_dwb = 1, 966 .num_ddc = 5, 967 .num_vmid = 16, 968 .num_mpc_3dlut = 2, 969 .num_dsc = 3, 970 }; 971 972 static const struct dc_plane_cap plane_cap = { 973 .type = DC_PLANE_TYPE_DCN_UNIVERSAL, 974 .blends_with_above = true, 975 .blends_with_below = true, 976 .per_pixel_alpha = true, 977 978 .pixel_format_support = { 979 .argb8888 = true, 980 .nv12 = true, 981 .fp16 = true, 982 .p010 = true, 983 .ayuv = false, 984 }, 985 986 .max_upscale_factor = { 987 .argb8888 = 16000, 988 .nv12 = 16000, 989 .fp16 = 16000 990 }, 991 992 // 6:1 downscaling ratio: 1000/6 = 166.666 993 .max_downscale_factor = { 994 .argb8888 = 167, 995 .nv12 = 167, 996 .fp16 = 167 997 }, 998 64, 999 64 1000 }; 1001 1002 static const struct dc_debug_options debug_defaults_drv = { 1003 .disable_z10 = true, /*hw not support it*/ 1004 .disable_dmcu = true, 1005 .force_abm_enable = false, 1006 .timing_trace = false, 1007 .clock_trace = true, 1008 .disable_pplib_clock_request = false, 1009 .pipe_split_policy = MPC_SPLIT_DYNAMIC, 1010 .force_single_disp_pipe_split = false, 1011 .disable_dcc = DCC_ENABLE, 1012 .vsr_support = true, 1013 .performance_trace = false, 1014 .max_downscale_src_width = 4096,/*upto true 4k*/ 1015 .disable_pplib_wm_range = false, 1016 .scl_reset_length10 = true, 1017 .sanity_checks = false, 1018 .underflow_assert_delay_us = 0xFFFFFFFF, 1019 .dwb_fi_phase = -1, // -1 = disable, 1020 .dmub_command_table = true, 1021 .pstate_enabled = true, 1022 .use_max_lb = true, 1023 .enable_mem_low_power = { 1024 .bits = { 1025 .vga = true, 1026 .i2c = true, 1027 .dmcu = false, // This is previously known to cause hang on S3 cycles if enabled 1028 .dscl = true, 1029 .cm = true, 1030 .mpc = true, 1031 .optc = true, 1032 .vpg = true, 1033 .afmt = true, 1034 } 1035 }, 1036 .optimize_edp_link_rate = true, 1037 .enable_sw_cntl_psr = true, 1038 .psr_power_use_phy_fsm = 0, 1039 }; 1040 1041 static const struct dc_debug_options debug_defaults_diags = { 1042 .disable_dmcu = true, 1043 .force_abm_enable = false, 1044 .timing_trace = true, 1045 .clock_trace = true, 1046 .disable_dpp_power_gate = true, 1047 .disable_hubp_power_gate = true, 1048 .disable_clock_gate = true, 1049 .disable_pplib_clock_request = true, 1050 .disable_pplib_wm_range = true, 1051 .disable_stutter = false, 1052 .scl_reset_length10 = true, 1053 .dwb_fi_phase = -1, // -1 = disable 1054 .dmub_command_table = true, 1055 .enable_tri_buf = true, 1056 .use_max_lb = true 1057 }; 1058 1059 static void dcn31_dpp_destroy(struct dpp **dpp) 1060 { 1061 kfree(TO_DCN20_DPP(*dpp)); 1062 *dpp = NULL; 1063 } 1064 1065 static struct dpp *dcn31_dpp_create( 1066 struct dc_context *ctx, 1067 uint32_t inst) 1068 { 1069 struct dcn3_dpp *dpp = 1070 kzalloc(sizeof(struct dcn3_dpp), GFP_KERNEL); 1071 1072 if (!dpp) 1073 return NULL; 1074 1075 if (dpp3_construct(dpp, ctx, inst, 1076 &dpp_regs[inst], &tf_shift, &tf_mask)) 1077 return &dpp->base; 1078 1079 BREAK_TO_DEBUGGER(); 1080 kfree(dpp); 1081 return NULL; 1082 } 1083 1084 static struct output_pixel_processor *dcn31_opp_create( 1085 struct dc_context *ctx, uint32_t inst) 1086 { 1087 struct dcn20_opp *opp = 1088 kzalloc(sizeof(struct dcn20_opp), GFP_KERNEL); 1089 1090 if (!opp) { 1091 BREAK_TO_DEBUGGER(); 1092 return NULL; 1093 } 1094 1095 dcn20_opp_construct(opp, ctx, inst, 1096 &opp_regs[inst], &opp_shift, &opp_mask); 1097 return &opp->base; 1098 } 1099 1100 static struct dce_aux *dcn31_aux_engine_create( 1101 struct dc_context *ctx, 1102 uint32_t inst) 1103 { 1104 struct aux_engine_dce110 *aux_engine = 1105 kzalloc(sizeof(struct aux_engine_dce110), GFP_KERNEL); 1106 1107 if (!aux_engine) 1108 return NULL; 1109 1110 dce110_aux_engine_construct(aux_engine, ctx, inst, 1111 SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD, 1112 &aux_engine_regs[inst], 1113 &aux_mask, 1114 &aux_shift, 1115 ctx->dc->caps.extended_aux_timeout_support); 1116 1117 return &aux_engine->base; 1118 } 1119 #define i2c_inst_regs(id) { I2C_HW_ENGINE_COMMON_REG_LIST_DCN30(id) } 1120 1121 static const struct dce_i2c_registers i2c_hw_regs[] = { 1122 i2c_inst_regs(1), 1123 i2c_inst_regs(2), 1124 i2c_inst_regs(3), 1125 i2c_inst_regs(4), 1126 i2c_inst_regs(5), 1127 }; 1128 1129 static const struct dce_i2c_shift i2c_shifts = { 1130 I2C_COMMON_MASK_SH_LIST_DCN30(__SHIFT) 1131 }; 1132 1133 static const struct dce_i2c_mask i2c_masks = { 1134 I2C_COMMON_MASK_SH_LIST_DCN30(_MASK) 1135 }; 1136 1137 static struct dce_i2c_hw *dcn31_i2c_hw_create( 1138 struct dc_context *ctx, 1139 uint32_t inst) 1140 { 1141 struct dce_i2c_hw *dce_i2c_hw = 1142 kzalloc(sizeof(struct dce_i2c_hw), GFP_KERNEL); 1143 1144 if (!dce_i2c_hw) 1145 return NULL; 1146 1147 dcn2_i2c_hw_construct(dce_i2c_hw, ctx, inst, 1148 &i2c_hw_regs[inst], &i2c_shifts, &i2c_masks); 1149 1150 return dce_i2c_hw; 1151 } 1152 static struct mpc *dcn31_mpc_create( 1153 struct dc_context *ctx, 1154 int num_mpcc, 1155 int num_rmu) 1156 { 1157 struct dcn30_mpc *mpc30 = kzalloc(sizeof(struct dcn30_mpc), 1158 GFP_KERNEL); 1159 1160 if (!mpc30) 1161 return NULL; 1162 1163 dcn30_mpc_construct(mpc30, ctx, 1164 &mpc_regs, 1165 &mpc_shift, 1166 &mpc_mask, 1167 num_mpcc, 1168 num_rmu); 1169 1170 return &mpc30->base; 1171 } 1172 1173 static struct hubbub *dcn31_hubbub_create(struct dc_context *ctx) 1174 { 1175 int i; 1176 1177 struct dcn20_hubbub *hubbub3 = kzalloc(sizeof(struct dcn20_hubbub), 1178 GFP_KERNEL); 1179 1180 if (!hubbub3) 1181 return NULL; 1182 1183 hubbub31_construct(hubbub3, ctx, 1184 &hubbub_reg, 1185 &hubbub_shift, 1186 &hubbub_mask, 1187 dcn3_15_ip.det_buffer_size_kbytes, 1188 dcn3_15_ip.pixel_chunk_size_kbytes, 1189 dcn3_15_ip.config_return_buffer_size_in_kbytes); 1190 1191 1192 for (i = 0; i < res_cap_dcn31.num_vmid; i++) { 1193 struct dcn20_vmid *vmid = &hubbub3->vmid[i]; 1194 1195 vmid->ctx = ctx; 1196 1197 vmid->regs = &vmid_regs[i]; 1198 vmid->shifts = &vmid_shifts; 1199 vmid->masks = &vmid_masks; 1200 } 1201 1202 return &hubbub3->base; 1203 } 1204 1205 static struct timing_generator *dcn31_timing_generator_create( 1206 struct dc_context *ctx, 1207 uint32_t instance) 1208 { 1209 struct optc *tgn10 = 1210 kzalloc(sizeof(struct optc), GFP_KERNEL); 1211 1212 if (!tgn10) 1213 return NULL; 1214 1215 tgn10->base.inst = instance; 1216 tgn10->base.ctx = ctx; 1217 1218 tgn10->tg_regs = &optc_regs[instance]; 1219 tgn10->tg_shift = &optc_shift; 1220 tgn10->tg_mask = &optc_mask; 1221 1222 dcn31_timing_generator_init(tgn10); 1223 1224 return &tgn10->base; 1225 } 1226 1227 static const struct encoder_feature_support link_enc_feature = { 1228 .max_hdmi_deep_color = COLOR_DEPTH_121212, 1229 .max_hdmi_pixel_clock = 600000, 1230 .hdmi_ycbcr420_supported = true, 1231 .dp_ycbcr420_supported = true, 1232 .fec_supported = true, 1233 .flags.bits.IS_HBR2_CAPABLE = true, 1234 .flags.bits.IS_HBR3_CAPABLE = true, 1235 .flags.bits.IS_TPS3_CAPABLE = true, 1236 .flags.bits.IS_TPS4_CAPABLE = true 1237 }; 1238 1239 static struct link_encoder *dcn31_link_encoder_create( 1240 const struct encoder_init_data *enc_init_data) 1241 { 1242 struct dcn20_link_encoder *enc20 = 1243 kzalloc(sizeof(struct dcn20_link_encoder), GFP_KERNEL); 1244 1245 if (!enc20) 1246 return NULL; 1247 1248 dcn31_link_encoder_construct(enc20, 1249 enc_init_data, 1250 &link_enc_feature, 1251 &link_enc_regs[enc_init_data->transmitter], 1252 &link_enc_aux_regs[enc_init_data->channel - 1], 1253 &link_enc_hpd_regs[enc_init_data->hpd_source], 1254 &le_shift, 1255 &le_mask); 1256 1257 return &enc20->enc10.base; 1258 } 1259 1260 /* Create a minimal link encoder object not associated with a particular 1261 * physical connector. 1262 * resource_funcs.link_enc_create_minimal 1263 */ 1264 static struct link_encoder *dcn31_link_enc_create_minimal( 1265 struct dc_context *ctx, enum engine_id eng_id) 1266 { 1267 struct dcn20_link_encoder *enc20; 1268 1269 if ((eng_id - ENGINE_ID_DIGA) > ctx->dc->res_pool->res_cap->num_dig_link_enc) 1270 return NULL; 1271 1272 enc20 = kzalloc(sizeof(struct dcn20_link_encoder), GFP_KERNEL); 1273 if (!enc20) 1274 return NULL; 1275 1276 dcn31_link_encoder_construct_minimal( 1277 enc20, 1278 ctx, 1279 &link_enc_feature, 1280 &link_enc_regs[eng_id - ENGINE_ID_DIGA], 1281 eng_id); 1282 1283 return &enc20->enc10.base; 1284 } 1285 1286 static struct panel_cntl *dcn31_panel_cntl_create(const struct panel_cntl_init_data *init_data) 1287 { 1288 struct dcn31_panel_cntl *panel_cntl = 1289 kzalloc(sizeof(struct dcn31_panel_cntl), GFP_KERNEL); 1290 1291 if (!panel_cntl) 1292 return NULL; 1293 1294 dcn31_panel_cntl_construct(panel_cntl, init_data); 1295 1296 return &panel_cntl->base; 1297 } 1298 1299 static void read_dce_straps( 1300 struct dc_context *ctx, 1301 struct resource_straps *straps) 1302 { 1303 generic_reg_get(ctx, regDC_PINSTRAPS + BASE(regDC_PINSTRAPS_BASE_IDX), 1304 FN(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO), &straps->dc_pinstraps_audio); 1305 1306 } 1307 1308 static struct audio *dcn31_create_audio( 1309 struct dc_context *ctx, unsigned int inst) 1310 { 1311 return dce_audio_create(ctx, inst, 1312 &audio_regs[inst], &audio_shift, &audio_mask); 1313 } 1314 1315 static struct vpg *dcn31_vpg_create( 1316 struct dc_context *ctx, 1317 uint32_t inst) 1318 { 1319 struct dcn31_vpg *vpg31 = kzalloc(sizeof(struct dcn31_vpg), GFP_KERNEL); 1320 1321 if (!vpg31) 1322 return NULL; 1323 1324 vpg31_construct(vpg31, ctx, inst, 1325 &vpg_regs[inst], 1326 &vpg_shift, 1327 &vpg_mask); 1328 1329 return &vpg31->base; 1330 } 1331 1332 static struct afmt *dcn31_afmt_create( 1333 struct dc_context *ctx, 1334 uint32_t inst) 1335 { 1336 struct dcn31_afmt *afmt31 = kzalloc(sizeof(struct dcn31_afmt), GFP_KERNEL); 1337 1338 if (!afmt31) 1339 return NULL; 1340 1341 afmt31_construct(afmt31, ctx, inst, 1342 &afmt_regs[inst], 1343 &afmt_shift, 1344 &afmt_mask); 1345 1346 // Light sleep by default, no need to power down here 1347 1348 return &afmt31->base; 1349 } 1350 1351 static struct apg *dcn31_apg_create( 1352 struct dc_context *ctx, 1353 uint32_t inst) 1354 { 1355 struct dcn31_apg *apg31 = kzalloc(sizeof(struct dcn31_apg), GFP_KERNEL); 1356 1357 if (!apg31) 1358 return NULL; 1359 1360 apg31_construct(apg31, ctx, inst, 1361 &apg_regs[inst], 1362 &apg_shift, 1363 &apg_mask); 1364 1365 return &apg31->base; 1366 } 1367 1368 static struct stream_encoder *dcn315_stream_encoder_create( 1369 enum engine_id eng_id, 1370 struct dc_context *ctx) 1371 { 1372 struct dcn10_stream_encoder *enc1; 1373 struct vpg *vpg; 1374 struct afmt *afmt; 1375 int vpg_inst; 1376 int afmt_inst; 1377 1378 /*PHYB is wired off in HW, allow front end to remapping, otherwise needs more changes*/ 1379 1380 /* Mapping of VPG, AFMT, DME register blocks to DIO block instance */ 1381 if (eng_id <= ENGINE_ID_DIGF) { 1382 vpg_inst = eng_id; 1383 afmt_inst = eng_id; 1384 } else 1385 return NULL; 1386 1387 enc1 = kzalloc(sizeof(struct dcn10_stream_encoder), GFP_KERNEL); 1388 vpg = dcn31_vpg_create(ctx, vpg_inst); 1389 afmt = dcn31_afmt_create(ctx, afmt_inst); 1390 1391 if (!enc1 || !vpg || !afmt) { 1392 kfree(enc1); 1393 kfree(vpg); 1394 kfree(afmt); 1395 return NULL; 1396 } 1397 1398 dcn30_dio_stream_encoder_construct(enc1, ctx, ctx->dc_bios, 1399 eng_id, vpg, afmt, 1400 &stream_enc_regs[eng_id], 1401 &se_shift, &se_mask); 1402 1403 return &enc1->base; 1404 } 1405 1406 static struct hpo_dp_stream_encoder *dcn31_hpo_dp_stream_encoder_create( 1407 enum engine_id eng_id, 1408 struct dc_context *ctx) 1409 { 1410 struct dcn31_hpo_dp_stream_encoder *hpo_dp_enc31; 1411 struct vpg *vpg; 1412 struct apg *apg; 1413 uint32_t hpo_dp_inst; 1414 uint32_t vpg_inst; 1415 uint32_t apg_inst; 1416 1417 ASSERT((eng_id >= ENGINE_ID_HPO_DP_0) && (eng_id <= ENGINE_ID_HPO_DP_3)); 1418 hpo_dp_inst = eng_id - ENGINE_ID_HPO_DP_0; 1419 1420 /* Mapping of VPG register blocks to HPO DP block instance: 1421 * VPG[6] -> HPO_DP[0] 1422 * VPG[7] -> HPO_DP[1] 1423 * VPG[8] -> HPO_DP[2] 1424 * VPG[9] -> HPO_DP[3] 1425 */ 1426 vpg_inst = hpo_dp_inst + 6; 1427 1428 /* Mapping of APG register blocks to HPO DP block instance: 1429 * APG[0] -> HPO_DP[0] 1430 * APG[1] -> HPO_DP[1] 1431 * APG[2] -> HPO_DP[2] 1432 * APG[3] -> HPO_DP[3] 1433 */ 1434 apg_inst = hpo_dp_inst; 1435 1436 /* allocate HPO stream encoder and create VPG sub-block */ 1437 hpo_dp_enc31 = kzalloc(sizeof(struct dcn31_hpo_dp_stream_encoder), GFP_KERNEL); 1438 vpg = dcn31_vpg_create(ctx, vpg_inst); 1439 apg = dcn31_apg_create(ctx, apg_inst); 1440 1441 if (!hpo_dp_enc31 || !vpg || !apg) { 1442 kfree(hpo_dp_enc31); 1443 kfree(vpg); 1444 kfree(apg); 1445 return NULL; 1446 } 1447 1448 dcn31_hpo_dp_stream_encoder_construct(hpo_dp_enc31, ctx, ctx->dc_bios, 1449 hpo_dp_inst, eng_id, vpg, apg, 1450 &hpo_dp_stream_enc_regs[hpo_dp_inst], 1451 &hpo_dp_se_shift, &hpo_dp_se_mask); 1452 1453 return &hpo_dp_enc31->base; 1454 } 1455 1456 static struct hpo_dp_link_encoder *dcn31_hpo_dp_link_encoder_create( 1457 uint8_t inst, 1458 struct dc_context *ctx) 1459 { 1460 struct dcn31_hpo_dp_link_encoder *hpo_dp_enc31; 1461 1462 /* allocate HPO link encoder */ 1463 hpo_dp_enc31 = kzalloc(sizeof(struct dcn31_hpo_dp_link_encoder), GFP_KERNEL); 1464 1465 hpo_dp_link_encoder31_construct(hpo_dp_enc31, ctx, inst, 1466 &hpo_dp_link_enc_regs[inst], 1467 &hpo_dp_le_shift, &hpo_dp_le_mask); 1468 1469 return &hpo_dp_enc31->base; 1470 } 1471 1472 static struct dce_hwseq *dcn31_hwseq_create( 1473 struct dc_context *ctx) 1474 { 1475 struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_KERNEL); 1476 1477 if (hws) { 1478 hws->ctx = ctx; 1479 hws->regs = &hwseq_reg; 1480 hws->shifts = &hwseq_shift; 1481 hws->masks = &hwseq_mask; 1482 /* DCN3.1 FPGA Workaround 1483 * Need to enable HPO DP Stream Encoder before setting OTG master enable. 1484 * To do so, move calling function enable_stream_timing to only be done AFTER calling 1485 * function core_link_enable_stream 1486 */ 1487 if (IS_FPGA_MAXIMUS_DC(ctx->dce_environment)) 1488 hws->wa.dp_hpo_and_otg_sequence = true; 1489 } 1490 return hws; 1491 } 1492 static const struct resource_create_funcs res_create_funcs = { 1493 .read_dce_straps = read_dce_straps, 1494 .create_audio = dcn31_create_audio, 1495 .create_stream_encoder = dcn315_stream_encoder_create, 1496 .create_hpo_dp_stream_encoder = dcn31_hpo_dp_stream_encoder_create, 1497 .create_hpo_dp_link_encoder = dcn31_hpo_dp_link_encoder_create, 1498 .create_hwseq = dcn31_hwseq_create, 1499 }; 1500 1501 static const struct resource_create_funcs res_create_maximus_funcs = { 1502 .read_dce_straps = NULL, 1503 .create_audio = NULL, 1504 .create_stream_encoder = NULL, 1505 .create_hpo_dp_stream_encoder = dcn31_hpo_dp_stream_encoder_create, 1506 .create_hpo_dp_link_encoder = dcn31_hpo_dp_link_encoder_create, 1507 .create_hwseq = dcn31_hwseq_create, 1508 }; 1509 1510 static void dcn315_resource_destruct(struct dcn315_resource_pool *pool) 1511 { 1512 unsigned int i; 1513 1514 for (i = 0; i < pool->base.stream_enc_count; i++) { 1515 if (pool->base.stream_enc[i] != NULL) { 1516 if (pool->base.stream_enc[i]->vpg != NULL) { 1517 kfree(DCN30_VPG_FROM_VPG(pool->base.stream_enc[i]->vpg)); 1518 pool->base.stream_enc[i]->vpg = NULL; 1519 } 1520 if (pool->base.stream_enc[i]->afmt != NULL) { 1521 kfree(DCN30_AFMT_FROM_AFMT(pool->base.stream_enc[i]->afmt)); 1522 pool->base.stream_enc[i]->afmt = NULL; 1523 } 1524 kfree(DCN10STRENC_FROM_STRENC(pool->base.stream_enc[i])); 1525 pool->base.stream_enc[i] = NULL; 1526 } 1527 } 1528 1529 for (i = 0; i < pool->base.hpo_dp_stream_enc_count; i++) { 1530 if (pool->base.hpo_dp_stream_enc[i] != NULL) { 1531 if (pool->base.hpo_dp_stream_enc[i]->vpg != NULL) { 1532 kfree(DCN30_VPG_FROM_VPG(pool->base.hpo_dp_stream_enc[i]->vpg)); 1533 pool->base.hpo_dp_stream_enc[i]->vpg = NULL; 1534 } 1535 if (pool->base.hpo_dp_stream_enc[i]->apg != NULL) { 1536 kfree(DCN31_APG_FROM_APG(pool->base.hpo_dp_stream_enc[i]->apg)); 1537 pool->base.hpo_dp_stream_enc[i]->apg = NULL; 1538 } 1539 kfree(DCN3_1_HPO_DP_STREAM_ENC_FROM_HPO_STREAM_ENC(pool->base.hpo_dp_stream_enc[i])); 1540 pool->base.hpo_dp_stream_enc[i] = NULL; 1541 } 1542 } 1543 1544 for (i = 0; i < pool->base.hpo_dp_link_enc_count; i++) { 1545 if (pool->base.hpo_dp_link_enc[i] != NULL) { 1546 kfree(DCN3_1_HPO_DP_LINK_ENC_FROM_HPO_LINK_ENC(pool->base.hpo_dp_link_enc[i])); 1547 pool->base.hpo_dp_link_enc[i] = NULL; 1548 } 1549 } 1550 1551 for (i = 0; i < pool->base.res_cap->num_dsc; i++) { 1552 if (pool->base.dscs[i] != NULL) 1553 dcn20_dsc_destroy(&pool->base.dscs[i]); 1554 } 1555 1556 if (pool->base.mpc != NULL) { 1557 kfree(TO_DCN20_MPC(pool->base.mpc)); 1558 pool->base.mpc = NULL; 1559 } 1560 if (pool->base.hubbub != NULL) { 1561 kfree(pool->base.hubbub); 1562 pool->base.hubbub = NULL; 1563 } 1564 for (i = 0; i < pool->base.pipe_count; i++) { 1565 if (pool->base.dpps[i] != NULL) 1566 dcn31_dpp_destroy(&pool->base.dpps[i]); 1567 1568 if (pool->base.ipps[i] != NULL) 1569 pool->base.ipps[i]->funcs->ipp_destroy(&pool->base.ipps[i]); 1570 1571 if (pool->base.hubps[i] != NULL) { 1572 kfree(TO_DCN20_HUBP(pool->base.hubps[i])); 1573 pool->base.hubps[i] = NULL; 1574 } 1575 1576 if (pool->base.irqs != NULL) { 1577 dal_irq_service_destroy(&pool->base.irqs); 1578 } 1579 } 1580 1581 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { 1582 if (pool->base.engines[i] != NULL) 1583 dce110_engine_destroy(&pool->base.engines[i]); 1584 if (pool->base.hw_i2cs[i] != NULL) { 1585 kfree(pool->base.hw_i2cs[i]); 1586 pool->base.hw_i2cs[i] = NULL; 1587 } 1588 if (pool->base.sw_i2cs[i] != NULL) { 1589 kfree(pool->base.sw_i2cs[i]); 1590 pool->base.sw_i2cs[i] = NULL; 1591 } 1592 } 1593 1594 for (i = 0; i < pool->base.res_cap->num_opp; i++) { 1595 if (pool->base.opps[i] != NULL) 1596 pool->base.opps[i]->funcs->opp_destroy(&pool->base.opps[i]); 1597 } 1598 1599 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { 1600 if (pool->base.timing_generators[i] != NULL) { 1601 kfree(DCN10TG_FROM_TG(pool->base.timing_generators[i])); 1602 pool->base.timing_generators[i] = NULL; 1603 } 1604 } 1605 1606 for (i = 0; i < pool->base.res_cap->num_dwb; i++) { 1607 if (pool->base.dwbc[i] != NULL) { 1608 kfree(TO_DCN30_DWBC(pool->base.dwbc[i])); 1609 pool->base.dwbc[i] = NULL; 1610 } 1611 if (pool->base.mcif_wb[i] != NULL) { 1612 kfree(TO_DCN30_MMHUBBUB(pool->base.mcif_wb[i])); 1613 pool->base.mcif_wb[i] = NULL; 1614 } 1615 } 1616 1617 for (i = 0; i < pool->base.audio_count; i++) { 1618 if (pool->base.audios[i]) 1619 dce_aud_destroy(&pool->base.audios[i]); 1620 } 1621 1622 for (i = 0; i < pool->base.clk_src_count; i++) { 1623 if (pool->base.clock_sources[i] != NULL) { 1624 dcn20_clock_source_destroy(&pool->base.clock_sources[i]); 1625 pool->base.clock_sources[i] = NULL; 1626 } 1627 } 1628 1629 for (i = 0; i < pool->base.res_cap->num_mpc_3dlut; i++) { 1630 if (pool->base.mpc_lut[i] != NULL) { 1631 dc_3dlut_func_release(pool->base.mpc_lut[i]); 1632 pool->base.mpc_lut[i] = NULL; 1633 } 1634 if (pool->base.mpc_shaper[i] != NULL) { 1635 dc_transfer_func_release(pool->base.mpc_shaper[i]); 1636 pool->base.mpc_shaper[i] = NULL; 1637 } 1638 } 1639 1640 if (pool->base.dp_clock_source != NULL) { 1641 dcn20_clock_source_destroy(&pool->base.dp_clock_source); 1642 pool->base.dp_clock_source = NULL; 1643 } 1644 1645 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { 1646 if (pool->base.multiple_abms[i] != NULL) 1647 dce_abm_destroy(&pool->base.multiple_abms[i]); 1648 } 1649 1650 if (pool->base.psr != NULL) 1651 dmub_psr_destroy(&pool->base.psr); 1652 1653 if (pool->base.dccg != NULL) 1654 dcn_dccg_destroy(&pool->base.dccg); 1655 } 1656 1657 static struct hubp *dcn31_hubp_create( 1658 struct dc_context *ctx, 1659 uint32_t inst) 1660 { 1661 struct dcn20_hubp *hubp2 = 1662 kzalloc(sizeof(struct dcn20_hubp), GFP_KERNEL); 1663 1664 if (!hubp2) 1665 return NULL; 1666 1667 if (hubp31_construct(hubp2, ctx, inst, 1668 &hubp_regs[inst], &hubp_shift, &hubp_mask)) 1669 return &hubp2->base; 1670 1671 BREAK_TO_DEBUGGER(); 1672 kfree(hubp2); 1673 return NULL; 1674 } 1675 1676 static bool dcn31_dwbc_create(struct dc_context *ctx, struct resource_pool *pool) 1677 { 1678 int i; 1679 uint32_t pipe_count = pool->res_cap->num_dwb; 1680 1681 for (i = 0; i < pipe_count; i++) { 1682 struct dcn30_dwbc *dwbc30 = kzalloc(sizeof(struct dcn30_dwbc), 1683 GFP_KERNEL); 1684 1685 if (!dwbc30) { 1686 dm_error("DC: failed to create dwbc30!\n"); 1687 return false; 1688 } 1689 1690 dcn30_dwbc_construct(dwbc30, ctx, 1691 &dwbc30_regs[i], 1692 &dwbc30_shift, 1693 &dwbc30_mask, 1694 i); 1695 1696 pool->dwbc[i] = &dwbc30->base; 1697 } 1698 return true; 1699 } 1700 1701 static bool dcn31_mmhubbub_create(struct dc_context *ctx, struct resource_pool *pool) 1702 { 1703 int i; 1704 uint32_t pipe_count = pool->res_cap->num_dwb; 1705 1706 for (i = 0; i < pipe_count; i++) { 1707 struct dcn30_mmhubbub *mcif_wb30 = kzalloc(sizeof(struct dcn30_mmhubbub), 1708 GFP_KERNEL); 1709 1710 if (!mcif_wb30) { 1711 dm_error("DC: failed to create mcif_wb30!\n"); 1712 return false; 1713 } 1714 1715 dcn30_mmhubbub_construct(mcif_wb30, ctx, 1716 &mcif_wb30_regs[i], 1717 &mcif_wb30_shift, 1718 &mcif_wb30_mask, 1719 i); 1720 1721 pool->mcif_wb[i] = &mcif_wb30->base; 1722 } 1723 return true; 1724 } 1725 1726 static struct display_stream_compressor *dcn31_dsc_create( 1727 struct dc_context *ctx, uint32_t inst) 1728 { 1729 struct dcn20_dsc *dsc = 1730 kzalloc(sizeof(struct dcn20_dsc), GFP_KERNEL); 1731 1732 if (!dsc) { 1733 BREAK_TO_DEBUGGER(); 1734 return NULL; 1735 } 1736 1737 dsc2_construct(dsc, ctx, inst, &dsc_regs[inst], &dsc_shift, &dsc_mask); 1738 return &dsc->base; 1739 } 1740 1741 static void dcn315_destroy_resource_pool(struct resource_pool **pool) 1742 { 1743 struct dcn315_resource_pool *dcn31_pool = TO_DCN315_RES_POOL(*pool); 1744 1745 dcn315_resource_destruct(dcn31_pool); 1746 kfree(dcn31_pool); 1747 *pool = NULL; 1748 } 1749 1750 static struct clock_source *dcn31_clock_source_create( 1751 struct dc_context *ctx, 1752 struct dc_bios *bios, 1753 enum clock_source_id id, 1754 const struct dce110_clk_src_regs *regs, 1755 bool dp_clk_src) 1756 { 1757 struct dce110_clk_src *clk_src = 1758 kzalloc(sizeof(struct dce110_clk_src), GFP_KERNEL); 1759 1760 if (!clk_src) 1761 return NULL; 1762 1763 if (dcn31_clk_src_construct(clk_src, ctx, bios, id, 1764 regs, &cs_shift, &cs_mask)) { 1765 clk_src->base.dp_clk_src = dp_clk_src; 1766 return &clk_src->base; 1767 } 1768 1769 BREAK_TO_DEBUGGER(); 1770 return NULL; 1771 } 1772 1773 static bool is_dual_plane(enum surface_pixel_format format) 1774 { 1775 return format >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN || format == SURFACE_PIXEL_FORMAT_GRPH_RGBE_ALPHA; 1776 } 1777 1778 static int dcn315_populate_dml_pipes_from_context( 1779 struct dc *dc, struct dc_state *context, 1780 display_e2e_pipe_params_st *pipes, 1781 bool fast_validate) 1782 { 1783 int i, pipe_cnt; 1784 struct resource_context *res_ctx = &context->res_ctx; 1785 struct pipe_ctx *pipe; 1786 const int max_usable_det = context->bw_ctx.dml.ip.config_return_buffer_size_in_kbytes - DCN3_15_MIN_COMPBUF_SIZE_KB; 1787 1788 DC_FP_START(); 1789 dcn20_populate_dml_pipes_from_context(dc, context, pipes, fast_validate); 1790 DC_FP_END(); 1791 1792 for (i = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) { 1793 struct dc_crtc_timing *timing; 1794 1795 if (!res_ctx->pipe_ctx[i].stream) 1796 continue; 1797 pipe = &res_ctx->pipe_ctx[i]; 1798 timing = &pipe->stream->timing; 1799 1800 /* 1801 * Immediate flip can be set dynamically after enabling the plane. 1802 * We need to require support for immediate flip or underflow can be 1803 * intermittently experienced depending on peak b/w requirements. 1804 */ 1805 pipes[pipe_cnt].pipe.src.immediate_flip = true; 1806 1807 pipes[pipe_cnt].pipe.src.unbounded_req_mode = false; 1808 pipes[pipe_cnt].pipe.src.gpuvm = true; 1809 pipes[pipe_cnt].pipe.src.dcc_fraction_of_zs_req_luma = 0; 1810 pipes[pipe_cnt].pipe.src.dcc_fraction_of_zs_req_chroma = 0; 1811 pipes[pipe_cnt].pipe.dest.vfront_porch = timing->v_front_porch; 1812 pipes[pipe_cnt].pipe.src.dcc_rate = 3; 1813 pipes[pipe_cnt].dout.dsc_input_bpc = 0; 1814 1815 if (pipes[pipe_cnt].dout.dsc_enable) { 1816 switch (timing->display_color_depth) { 1817 case COLOR_DEPTH_888: 1818 pipes[pipe_cnt].dout.dsc_input_bpc = 8; 1819 break; 1820 case COLOR_DEPTH_101010: 1821 pipes[pipe_cnt].dout.dsc_input_bpc = 10; 1822 break; 1823 case COLOR_DEPTH_121212: 1824 pipes[pipe_cnt].dout.dsc_input_bpc = 12; 1825 break; 1826 default: 1827 ASSERT(0); 1828 break; 1829 } 1830 } 1831 1832 pipe_cnt++; 1833 } 1834 1835 if (pipe_cnt) 1836 context->bw_ctx.dml.ip.det_buffer_size_kbytes = 1837 (max_usable_det / DCN3_15_CRB_SEGMENT_SIZE_KB / pipe_cnt) * DCN3_15_CRB_SEGMENT_SIZE_KB; 1838 if (context->bw_ctx.dml.ip.det_buffer_size_kbytes > DCN3_15_MAX_DET_SIZE) 1839 context->bw_ctx.dml.ip.det_buffer_size_kbytes = DCN3_15_MAX_DET_SIZE; 1840 ASSERT(context->bw_ctx.dml.ip.det_buffer_size_kbytes >= DCN3_15_DEFAULT_DET_SIZE); 1841 dc->config.enable_4to1MPC = false; 1842 if (pipe_cnt == 1 && pipe->plane_state && !dc->debug.disable_z9_mpc) { 1843 if (is_dual_plane(pipe->plane_state->format) 1844 && pipe->plane_state->src_rect.width <= 1920 && pipe->plane_state->src_rect.height <= 1080) { 1845 dc->config.enable_4to1MPC = true; 1846 context->bw_ctx.dml.ip.det_buffer_size_kbytes = 1847 (max_usable_det / DCN3_15_CRB_SEGMENT_SIZE_KB / 4) * DCN3_15_CRB_SEGMENT_SIZE_KB; 1848 } else if (!is_dual_plane(pipe->plane_state->format) && pipe->plane_state->src_rect.width <= 5120) { 1849 /* Limit to 5k max to avoid forced pipe split when there is not enough detile for swath */ 1850 context->bw_ctx.dml.ip.det_buffer_size_kbytes = 192; 1851 pipes[0].pipe.src.unbounded_req_mode = true; 1852 } 1853 } 1854 1855 return pipe_cnt; 1856 } 1857 1858 static struct dc_cap_funcs cap_funcs = { 1859 .get_dcc_compression_cap = dcn20_get_dcc_compression_cap 1860 }; 1861 1862 static void dcn315_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params) 1863 { 1864 struct clk_limit_table *clk_table = &bw_params->clk_table; 1865 struct _vcs_dpi_voltage_scaling_st clock_limits[DC__VOLTAGE_STATES]; 1866 unsigned int i, closest_clk_lvl; 1867 int max_dispclk_mhz = 0, max_dppclk_mhz = 0; 1868 int j; 1869 1870 // Default clock levels are used for diags, which may lead to overclocking. 1871 if (!IS_DIAG_DC(dc->ctx->dce_environment)) { 1872 1873 dcn3_15_ip.max_num_otg = dc->res_pool->res_cap->num_timing_generator; 1874 dcn3_15_ip.max_num_dpp = dc->res_pool->pipe_count; 1875 dcn3_15_soc.num_chans = bw_params->num_channels; 1876 1877 ASSERT(clk_table->num_entries); 1878 1879 /* Prepass to find max clocks independent of voltage level. */ 1880 for (i = 0; i < clk_table->num_entries; ++i) { 1881 if (clk_table->entries[i].dispclk_mhz > max_dispclk_mhz) 1882 max_dispclk_mhz = clk_table->entries[i].dispclk_mhz; 1883 if (clk_table->entries[i].dppclk_mhz > max_dppclk_mhz) 1884 max_dppclk_mhz = clk_table->entries[i].dppclk_mhz; 1885 } 1886 1887 for (i = 0; i < clk_table->num_entries; i++) { 1888 /* loop backwards*/ 1889 for (closest_clk_lvl = 0, j = dcn3_15_soc.num_states - 1; j >= 0; j--) { 1890 if ((unsigned int) dcn3_15_soc.clock_limits[j].dcfclk_mhz <= clk_table->entries[i].dcfclk_mhz) { 1891 closest_clk_lvl = j; 1892 break; 1893 } 1894 } 1895 if (clk_table->num_entries == 1) { 1896 /*smu gives one DPM level, let's take the highest one*/ 1897 closest_clk_lvl = dcn3_15_soc.num_states - 1; 1898 } 1899 1900 clock_limits[i].state = i; 1901 1902 /* Clocks dependent on voltage level. */ 1903 clock_limits[i].dcfclk_mhz = clk_table->entries[i].dcfclk_mhz; 1904 if (clk_table->num_entries == 1 && 1905 clock_limits[i].dcfclk_mhz < dcn3_15_soc.clock_limits[closest_clk_lvl].dcfclk_mhz) { 1906 /*SMU fix not released yet*/ 1907 clock_limits[i].dcfclk_mhz = dcn3_15_soc.clock_limits[closest_clk_lvl].dcfclk_mhz; 1908 } 1909 clock_limits[i].fabricclk_mhz = clk_table->entries[i].fclk_mhz; 1910 clock_limits[i].socclk_mhz = clk_table->entries[i].socclk_mhz; 1911 clock_limits[i].dram_speed_mts = clk_table->entries[i].memclk_mhz * 2 * clk_table->entries[i].wck_ratio; 1912 1913 /* Clocks independent of voltage level. */ 1914 clock_limits[i].dispclk_mhz = max_dispclk_mhz ? max_dispclk_mhz : 1915 dcn3_15_soc.clock_limits[closest_clk_lvl].dispclk_mhz; 1916 1917 clock_limits[i].dppclk_mhz = max_dppclk_mhz ? max_dppclk_mhz : 1918 dcn3_15_soc.clock_limits[closest_clk_lvl].dppclk_mhz; 1919 1920 clock_limits[i].dram_bw_per_chan_gbps = dcn3_15_soc.clock_limits[closest_clk_lvl].dram_bw_per_chan_gbps; 1921 clock_limits[i].dscclk_mhz = dcn3_15_soc.clock_limits[closest_clk_lvl].dscclk_mhz; 1922 clock_limits[i].dtbclk_mhz = dcn3_15_soc.clock_limits[closest_clk_lvl].dtbclk_mhz; 1923 clock_limits[i].phyclk_d18_mhz = dcn3_15_soc.clock_limits[closest_clk_lvl].phyclk_d18_mhz; 1924 clock_limits[i].phyclk_mhz = dcn3_15_soc.clock_limits[closest_clk_lvl].phyclk_mhz; 1925 } 1926 for (i = 0; i < clk_table->num_entries; i++) 1927 dcn3_15_soc.clock_limits[i] = clock_limits[i]; 1928 if (clk_table->num_entries) { 1929 dcn3_15_soc.num_states = clk_table->num_entries; 1930 } 1931 } 1932 1933 if (max_dispclk_mhz) { 1934 dcn3_15_soc.dispclk_dppclk_vco_speed_mhz = max_dispclk_mhz * 2; 1935 dc->dml.soc.dispclk_dppclk_vco_speed_mhz = max_dispclk_mhz * 2; 1936 } 1937 1938 if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) 1939 dml_init_instance(&dc->dml, &dcn3_15_soc, &dcn3_15_ip, DML_PROJECT_DCN31); 1940 else 1941 dml_init_instance(&dc->dml, &dcn3_15_soc, &dcn3_15_ip, DML_PROJECT_DCN31_FPGA); 1942 } 1943 1944 static struct resource_funcs dcn315_res_pool_funcs = { 1945 .destroy = dcn315_destroy_resource_pool, 1946 .link_enc_create = dcn31_link_encoder_create, 1947 .link_enc_create_minimal = dcn31_link_enc_create_minimal, 1948 .link_encs_assign = link_enc_cfg_link_encs_assign, 1949 .link_enc_unassign = link_enc_cfg_link_enc_unassign, 1950 .panel_cntl_create = dcn31_panel_cntl_create, 1951 .validate_bandwidth = dcn31_validate_bandwidth, 1952 .calculate_wm_and_dlg = dcn31_calculate_wm_and_dlg, 1953 .update_soc_for_wm_a = dcn31_update_soc_for_wm_a, 1954 .populate_dml_pipes = dcn315_populate_dml_pipes_from_context, 1955 .acquire_idle_pipe_for_layer = dcn20_acquire_idle_pipe_for_layer, 1956 .add_stream_to_ctx = dcn30_add_stream_to_ctx, 1957 .add_dsc_to_stream_resource = dcn20_add_dsc_to_stream_resource, 1958 .remove_stream_from_ctx = dcn20_remove_stream_from_ctx, 1959 .populate_dml_writeback_from_context = dcn30_populate_dml_writeback_from_context, 1960 .set_mcif_arb_params = dcn30_set_mcif_arb_params, 1961 .find_first_free_match_stream_enc_for_link = dcn10_find_first_free_match_stream_enc_for_link, 1962 .acquire_post_bldn_3dlut = dcn30_acquire_post_bldn_3dlut, 1963 .release_post_bldn_3dlut = dcn30_release_post_bldn_3dlut, 1964 .update_bw_bounding_box = dcn315_update_bw_bounding_box, 1965 .patch_unknown_plane_state = dcn20_patch_unknown_plane_state, 1966 }; 1967 1968 static bool dcn315_resource_construct( 1969 uint8_t num_virtual_links, 1970 struct dc *dc, 1971 struct dcn315_resource_pool *pool) 1972 { 1973 int i; 1974 struct dc_context *ctx = dc->ctx; 1975 struct irq_service_init_data init_data; 1976 1977 ctx->dc_bios->regs = &bios_regs; 1978 1979 pool->base.res_cap = &res_cap_dcn31; 1980 1981 pool->base.funcs = &dcn315_res_pool_funcs; 1982 1983 /************************************************* 1984 * Resource + asic cap harcoding * 1985 *************************************************/ 1986 pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE; 1987 pool->base.pipe_count = pool->base.res_cap->num_timing_generator; 1988 pool->base.mpcc_count = pool->base.res_cap->num_timing_generator; 1989 dc->caps.max_downscale_ratio = 600; 1990 dc->caps.i2c_speed_in_khz = 100; 1991 dc->caps.i2c_speed_in_khz_hdcp = 5; /*1.4 w/a applied by default*/ 1992 dc->caps.max_cursor_size = 256; 1993 dc->caps.min_horizontal_blanking_period = 80; 1994 dc->caps.dmdata_alloc_size = 2048; 1995 1996 dc->caps.max_slave_planes = 1; 1997 dc->caps.max_slave_yuv_planes = 1; 1998 dc->caps.max_slave_rgb_planes = 1; 1999 dc->caps.post_blend_color_processing = true; 2000 dc->caps.force_dp_tps4_for_cp2520 = true; 2001 dc->caps.dp_hpo = true; 2002 dc->caps.edp_dsc_support = true; 2003 dc->caps.extended_aux_timeout_support = true; 2004 dc->caps.dmcub_support = true; 2005 dc->caps.is_apu = true; 2006 2007 /* Color pipeline capabilities */ 2008 dc->caps.color.dpp.dcn_arch = 1; 2009 dc->caps.color.dpp.input_lut_shared = 0; 2010 dc->caps.color.dpp.icsc = 1; 2011 dc->caps.color.dpp.dgam_ram = 0; // must use gamma_corr 2012 dc->caps.color.dpp.dgam_rom_caps.srgb = 1; 2013 dc->caps.color.dpp.dgam_rom_caps.bt2020 = 1; 2014 dc->caps.color.dpp.dgam_rom_caps.gamma2_2 = 1; 2015 dc->caps.color.dpp.dgam_rom_caps.pq = 1; 2016 dc->caps.color.dpp.dgam_rom_caps.hlg = 1; 2017 dc->caps.color.dpp.post_csc = 1; 2018 dc->caps.color.dpp.gamma_corr = 1; 2019 dc->caps.color.dpp.dgam_rom_for_yuv = 0; 2020 2021 dc->caps.color.dpp.hw_3d_lut = 1; 2022 dc->caps.color.dpp.ogam_ram = 1; 2023 // no OGAM ROM on DCN301 2024 dc->caps.color.dpp.ogam_rom_caps.srgb = 0; 2025 dc->caps.color.dpp.ogam_rom_caps.bt2020 = 0; 2026 dc->caps.color.dpp.ogam_rom_caps.gamma2_2 = 0; 2027 dc->caps.color.dpp.ogam_rom_caps.pq = 0; 2028 dc->caps.color.dpp.ogam_rom_caps.hlg = 0; 2029 dc->caps.color.dpp.ocsc = 0; 2030 2031 dc->caps.color.mpc.gamut_remap = 1; 2032 dc->caps.color.mpc.num_3dluts = pool->base.res_cap->num_mpc_3dlut; //2 2033 dc->caps.color.mpc.ogam_ram = 1; 2034 dc->caps.color.mpc.ogam_rom_caps.srgb = 0; 2035 dc->caps.color.mpc.ogam_rom_caps.bt2020 = 0; 2036 dc->caps.color.mpc.ogam_rom_caps.gamma2_2 = 0; 2037 dc->caps.color.mpc.ogam_rom_caps.pq = 0; 2038 dc->caps.color.mpc.ogam_rom_caps.hlg = 0; 2039 dc->caps.color.mpc.ocsc = 1; 2040 2041 /* read VBIOS LTTPR caps */ 2042 { 2043 if (ctx->dc_bios->funcs->get_lttpr_caps) { 2044 enum bp_result bp_query_result; 2045 uint8_t is_vbios_lttpr_enable = 0; 2046 2047 bp_query_result = ctx->dc_bios->funcs->get_lttpr_caps(ctx->dc_bios, &is_vbios_lttpr_enable); 2048 dc->caps.vbios_lttpr_enable = (bp_query_result == BP_RESULT_OK) && !!is_vbios_lttpr_enable; 2049 } 2050 2051 /* interop bit is implicit */ 2052 { 2053 dc->caps.vbios_lttpr_aware = true; 2054 } 2055 } 2056 2057 if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV) 2058 dc->debug = debug_defaults_drv; 2059 else if (dc->ctx->dce_environment == DCE_ENV_FPGA_MAXIMUS) { 2060 dc->debug = debug_defaults_diags; 2061 } else 2062 dc->debug = debug_defaults_diags; 2063 // Init the vm_helper 2064 if (dc->vm_helper) 2065 vm_helper_init(dc->vm_helper, 16); 2066 2067 /************************************************* 2068 * Create resources * 2069 *************************************************/ 2070 2071 /* Clock Sources for Pixel Clock*/ 2072 pool->base.clock_sources[DCN31_CLK_SRC_PLL0] = 2073 dcn31_clock_source_create(ctx, ctx->dc_bios, 2074 CLOCK_SOURCE_COMBO_PHY_PLL0, 2075 &clk_src_regs[0], false); 2076 pool->base.clock_sources[DCN31_CLK_SRC_PLL1] = 2077 dcn31_clock_source_create(ctx, ctx->dc_bios, 2078 CLOCK_SOURCE_COMBO_PHY_PLL1, 2079 &clk_src_regs[1], false); 2080 pool->base.clock_sources[DCN31_CLK_SRC_PLL2] = 2081 dcn31_clock_source_create(ctx, ctx->dc_bios, 2082 CLOCK_SOURCE_COMBO_PHY_PLL2, 2083 &clk_src_regs[2], false); 2084 pool->base.clock_sources[DCN31_CLK_SRC_PLL3] = 2085 dcn31_clock_source_create(ctx, ctx->dc_bios, 2086 CLOCK_SOURCE_COMBO_PHY_PLL3, 2087 &clk_src_regs[3], false); 2088 pool->base.clock_sources[DCN31_CLK_SRC_PLL4] = 2089 dcn31_clock_source_create(ctx, ctx->dc_bios, 2090 CLOCK_SOURCE_COMBO_PHY_PLL4, 2091 &clk_src_regs[4], false); 2092 2093 pool->base.clk_src_count = DCN30_CLK_SRC_TOTAL; 2094 2095 /* todo: not reuse phy_pll registers */ 2096 pool->base.dp_clock_source = 2097 dcn31_clock_source_create(ctx, ctx->dc_bios, 2098 CLOCK_SOURCE_ID_DP_DTO, 2099 &clk_src_regs[0], true); 2100 2101 for (i = 0; i < pool->base.clk_src_count; i++) { 2102 if (pool->base.clock_sources[i] == NULL) { 2103 dm_error("DC: failed to create clock sources!\n"); 2104 BREAK_TO_DEBUGGER(); 2105 goto create_fail; 2106 } 2107 } 2108 2109 /* TODO: DCCG */ 2110 pool->base.dccg = dccg31_create(ctx, &dccg_regs, &dccg_shift, &dccg_mask); 2111 if (pool->base.dccg == NULL) { 2112 dm_error("DC: failed to create dccg!\n"); 2113 BREAK_TO_DEBUGGER(); 2114 goto create_fail; 2115 } 2116 2117 /* TODO: IRQ */ 2118 init_data.ctx = dc->ctx; 2119 pool->base.irqs = dal_irq_service_dcn315_create(&init_data); 2120 if (!pool->base.irqs) 2121 goto create_fail; 2122 2123 /* HUBBUB */ 2124 pool->base.hubbub = dcn31_hubbub_create(ctx); 2125 if (pool->base.hubbub == NULL) { 2126 BREAK_TO_DEBUGGER(); 2127 dm_error("DC: failed to create hubbub!\n"); 2128 goto create_fail; 2129 } 2130 2131 /* HUBPs, DPPs, OPPs and TGs */ 2132 for (i = 0; i < pool->base.pipe_count; i++) { 2133 pool->base.hubps[i] = dcn31_hubp_create(ctx, i); 2134 if (pool->base.hubps[i] == NULL) { 2135 BREAK_TO_DEBUGGER(); 2136 dm_error( 2137 "DC: failed to create hubps!\n"); 2138 goto create_fail; 2139 } 2140 2141 pool->base.dpps[i] = dcn31_dpp_create(ctx, i); 2142 if (pool->base.dpps[i] == NULL) { 2143 BREAK_TO_DEBUGGER(); 2144 dm_error( 2145 "DC: failed to create dpps!\n"); 2146 goto create_fail; 2147 } 2148 } 2149 2150 for (i = 0; i < pool->base.res_cap->num_opp; i++) { 2151 pool->base.opps[i] = dcn31_opp_create(ctx, i); 2152 if (pool->base.opps[i] == NULL) { 2153 BREAK_TO_DEBUGGER(); 2154 dm_error( 2155 "DC: failed to create output pixel processor!\n"); 2156 goto create_fail; 2157 } 2158 } 2159 2160 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { 2161 pool->base.timing_generators[i] = dcn31_timing_generator_create( 2162 ctx, i); 2163 if (pool->base.timing_generators[i] == NULL) { 2164 BREAK_TO_DEBUGGER(); 2165 dm_error("DC: failed to create tg!\n"); 2166 goto create_fail; 2167 } 2168 } 2169 pool->base.timing_generator_count = i; 2170 2171 /* PSR */ 2172 pool->base.psr = dmub_psr_create(ctx); 2173 if (pool->base.psr == NULL) { 2174 dm_error("DC: failed to create psr obj!\n"); 2175 BREAK_TO_DEBUGGER(); 2176 goto create_fail; 2177 } 2178 2179 /* ABM */ 2180 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { 2181 pool->base.multiple_abms[i] = dmub_abm_create(ctx, 2182 &abm_regs[i], 2183 &abm_shift, 2184 &abm_mask); 2185 if (pool->base.multiple_abms[i] == NULL) { 2186 dm_error("DC: failed to create abm for pipe %d!\n", i); 2187 BREAK_TO_DEBUGGER(); 2188 goto create_fail; 2189 } 2190 } 2191 2192 /* MPC and DSC */ 2193 pool->base.mpc = dcn31_mpc_create(ctx, pool->base.mpcc_count, pool->base.res_cap->num_mpc_3dlut); 2194 if (pool->base.mpc == NULL) { 2195 BREAK_TO_DEBUGGER(); 2196 dm_error("DC: failed to create mpc!\n"); 2197 goto create_fail; 2198 } 2199 2200 for (i = 0; i < pool->base.res_cap->num_dsc; i++) { 2201 pool->base.dscs[i] = dcn31_dsc_create(ctx, i); 2202 if (pool->base.dscs[i] == NULL) { 2203 BREAK_TO_DEBUGGER(); 2204 dm_error("DC: failed to create display stream compressor %d!\n", i); 2205 goto create_fail; 2206 } 2207 } 2208 2209 /* DWB and MMHUBBUB */ 2210 if (!dcn31_dwbc_create(ctx, &pool->base)) { 2211 BREAK_TO_DEBUGGER(); 2212 dm_error("DC: failed to create dwbc!\n"); 2213 goto create_fail; 2214 } 2215 2216 if (!dcn31_mmhubbub_create(ctx, &pool->base)) { 2217 BREAK_TO_DEBUGGER(); 2218 dm_error("DC: failed to create mcif_wb!\n"); 2219 goto create_fail; 2220 } 2221 2222 /* AUX and I2C */ 2223 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { 2224 pool->base.engines[i] = dcn31_aux_engine_create(ctx, i); 2225 if (pool->base.engines[i] == NULL) { 2226 BREAK_TO_DEBUGGER(); 2227 dm_error( 2228 "DC:failed to create aux engine!!\n"); 2229 goto create_fail; 2230 } 2231 pool->base.hw_i2cs[i] = dcn31_i2c_hw_create(ctx, i); 2232 if (pool->base.hw_i2cs[i] == NULL) { 2233 BREAK_TO_DEBUGGER(); 2234 dm_error( 2235 "DC:failed to create hw i2c!!\n"); 2236 goto create_fail; 2237 } 2238 pool->base.sw_i2cs[i] = NULL; 2239 } 2240 2241 /* Audio, Stream Encoders including HPO and virtual, MPC 3D LUTs */ 2242 if (!resource_construct(num_virtual_links, dc, &pool->base, 2243 (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment) ? 2244 &res_create_funcs : &res_create_maximus_funcs))) 2245 goto create_fail; 2246 2247 /* HW Sequencer and Plane caps */ 2248 dcn31_hw_sequencer_construct(dc); 2249 2250 dc->caps.max_planes = pool->base.pipe_count; 2251 2252 for (i = 0; i < dc->caps.max_planes; ++i) 2253 dc->caps.planes[i] = plane_cap; 2254 2255 dc->cap_funcs = cap_funcs; 2256 2257 dc->dcn_ip->max_num_dpp = dcn3_15_ip.max_num_dpp; 2258 2259 return true; 2260 2261 create_fail: 2262 2263 dcn315_resource_destruct(pool); 2264 2265 return false; 2266 } 2267 2268 struct resource_pool *dcn315_create_resource_pool( 2269 const struct dc_init_data *init_data, 2270 struct dc *dc) 2271 { 2272 struct dcn315_resource_pool *pool = 2273 kzalloc(sizeof(struct dcn315_resource_pool), GFP_KERNEL); 2274 2275 if (!pool) 2276 return NULL; 2277 2278 if (dcn315_resource_construct(init_data->num_virtual_links, dc, pool)) 2279 return &pool->base; 2280 2281 BREAK_TO_DEBUGGER(); 2282 kfree(pool); 2283 return NULL; 2284 } 2285