1 /* 2 * Copyright 2021 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 27 #include "dm_services.h" 28 #include "dc.h" 29 30 #include "dcn31/dcn31_init.h" 31 32 #include "resource.h" 33 #include "include/irq_service_interface.h" 34 #include "dcn315_resource.h" 35 36 #include "dcn20/dcn20_resource.h" 37 #include "dcn30/dcn30_resource.h" 38 #include "dcn31/dcn31_resource.h" 39 40 #include "dcn10/dcn10_ipp.h" 41 #include "dcn30/dcn30_hubbub.h" 42 #include "dcn31/dcn31_hubbub.h" 43 #include "dcn30/dcn30_mpc.h" 44 #include "dcn31/dcn31_hubp.h" 45 #include "irq/dcn315/irq_service_dcn315.h" 46 #include "dcn30/dcn30_dpp.h" 47 #include "dcn31/dcn31_optc.h" 48 #include "dcn20/dcn20_hwseq.h" 49 #include "dcn30/dcn30_hwseq.h" 50 #include "dce110/dce110_hw_sequencer.h" 51 #include "dcn30/dcn30_opp.h" 52 #include "dcn20/dcn20_dsc.h" 53 #include "dcn30/dcn30_vpg.h" 54 #include "dcn30/dcn30_afmt.h" 55 #include "dcn30/dcn30_dio_stream_encoder.h" 56 #include "dcn31/dcn31_hpo_dp_stream_encoder.h" 57 #include "dcn31/dcn31_hpo_dp_link_encoder.h" 58 #include "dcn31/dcn31_apg.h" 59 #include "dcn31/dcn31_dio_link_encoder.h" 60 #include "dcn31/dcn31_vpg.h" 61 #include "dcn31/dcn31_afmt.h" 62 #include "dce/dce_clock_source.h" 63 #include "dce/dce_audio.h" 64 #include "dce/dce_hwseq.h" 65 #include "clk_mgr.h" 66 #include "virtual/virtual_stream_encoder.h" 67 #include "dce110/dce110_resource.h" 68 #include "dml/display_mode_vba.h" 69 #include "dml/dcn31/dcn31_fpu.h" 70 #include "dcn31/dcn31_dccg.h" 71 #include "dcn10/dcn10_resource.h" 72 #include "dcn31/dcn31_panel_cntl.h" 73 74 #include "dcn30/dcn30_dwb.h" 75 #include "dcn30/dcn30_mmhubbub.h" 76 77 #include "dcn/dcn_3_1_5_offset.h" 78 #include "dcn/dcn_3_1_5_sh_mask.h" 79 #include "dpcs/dpcs_4_2_2_offset.h" 80 #include "dpcs/dpcs_4_2_2_sh_mask.h" 81 82 #define NBIO_BASE__INST0_SEG0 0x00000000 83 #define NBIO_BASE__INST0_SEG1 0x00000014 84 #define NBIO_BASE__INST0_SEG2 0x00000D20 85 #define NBIO_BASE__INST0_SEG3 0x00010400 86 #define NBIO_BASE__INST0_SEG4 0x0241B000 87 #define NBIO_BASE__INST0_SEG5 0x04040000 88 89 #define DPCS_BASE__INST0_SEG0 0x00000012 90 #define DPCS_BASE__INST0_SEG1 0x000000C0 91 #define DPCS_BASE__INST0_SEG2 0x000034C0 92 #define DPCS_BASE__INST0_SEG3 0x00009000 93 #define DPCS_BASE__INST0_SEG4 0x02403C00 94 #define DPCS_BASE__INST0_SEG5 0 95 96 #define DCN_BASE__INST0_SEG0 0x00000012 97 #define DCN_BASE__INST0_SEG1 0x000000C0 98 #define DCN_BASE__INST0_SEG2 0x000034C0 99 #define DCN_BASE__INST0_SEG3 0x00009000 100 #define DCN_BASE__INST0_SEG4 0x02403C00 101 #define DCN_BASE__INST0_SEG5 0 102 103 #define regBIF_BX_PF2_RSMU_INDEX 0x0000 104 #define regBIF_BX_PF2_RSMU_INDEX_BASE_IDX 1 105 #define regBIF_BX_PF2_RSMU_DATA 0x0001 106 #define regBIF_BX_PF2_RSMU_DATA_BASE_IDX 1 107 #define regBIF_BX2_BIOS_SCRATCH_6 0x003e 108 #define regBIF_BX2_BIOS_SCRATCH_6_BASE_IDX 1 109 #define BIF_BX2_BIOS_SCRATCH_6__BIOS_SCRATCH_6__SHIFT 0x0 110 #define BIF_BX2_BIOS_SCRATCH_6__BIOS_SCRATCH_6_MASK 0xFFFFFFFFL 111 #define regBIF_BX2_BIOS_SCRATCH_2 0x003a 112 #define regBIF_BX2_BIOS_SCRATCH_2_BASE_IDX 1 113 #define BIF_BX2_BIOS_SCRATCH_2__BIOS_SCRATCH_2__SHIFT 0x0 114 #define BIF_BX2_BIOS_SCRATCH_2__BIOS_SCRATCH_2_MASK 0xFFFFFFFFL 115 #define regBIF_BX2_BIOS_SCRATCH_3 0x003b 116 #define regBIF_BX2_BIOS_SCRATCH_3_BASE_IDX 1 117 #define BIF_BX2_BIOS_SCRATCH_3__BIOS_SCRATCH_3__SHIFT 0x0 118 #define BIF_BX2_BIOS_SCRATCH_3__BIOS_SCRATCH_3_MASK 0xFFFFFFFFL 119 120 #define regDCHUBBUB_DEBUG_CTRL_0 0x04d6 121 #define regDCHUBBUB_DEBUG_CTRL_0_BASE_IDX 2 122 #define DCHUBBUB_DEBUG_CTRL_0__DET_DEPTH__SHIFT 0x10 123 #define DCHUBBUB_DEBUG_CTRL_0__DET_DEPTH_MASK 0x01FF0000L 124 125 #include "reg_helper.h" 126 #include "dce/dmub_abm.h" 127 #include "dce/dmub_psr.h" 128 #include "dce/dce_aux.h" 129 #include "dce/dce_i2c.h" 130 131 #include "dml/dcn30/display_mode_vba_30.h" 132 #include "vm_helper.h" 133 #include "dcn20/dcn20_vmid.h" 134 135 #include "link_enc_cfg.h" 136 137 #define DCN3_15_MAX_DET_SIZE 384 138 #define DCN3_15_CRB_SEGMENT_SIZE_KB 64 139 140 enum dcn31_clk_src_array_id { 141 DCN31_CLK_SRC_PLL0, 142 DCN31_CLK_SRC_PLL1, 143 DCN31_CLK_SRC_PLL2, 144 DCN31_CLK_SRC_PLL3, 145 DCN31_CLK_SRC_PLL4, 146 DCN30_CLK_SRC_TOTAL 147 }; 148 149 /* begin ********************* 150 * macros to expend register list macro defined in HW object header file 151 */ 152 153 /* DCN */ 154 #define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg 155 156 #define BASE(seg) BASE_INNER(seg) 157 158 #define SR(reg_name)\ 159 .reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \ 160 reg ## reg_name 161 162 #define SRI(reg_name, block, id)\ 163 .reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 164 reg ## block ## id ## _ ## reg_name 165 166 #define SRI2(reg_name, block, id)\ 167 .reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \ 168 reg ## reg_name 169 170 #define SRIR(var_name, reg_name, block, id)\ 171 .var_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 172 reg ## block ## id ## _ ## reg_name 173 174 #define SRII(reg_name, block, id)\ 175 .reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 176 reg ## block ## id ## _ ## reg_name 177 178 #define SRII_MPC_RMU(reg_name, block, id)\ 179 .RMU##_##reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 180 reg ## block ## id ## _ ## reg_name 181 182 #define SRII_DWB(reg_name, temp_name, block, id)\ 183 .reg_name[id] = BASE(reg ## block ## id ## _ ## temp_name ## _BASE_IDX) + \ 184 reg ## block ## id ## _ ## temp_name 185 186 #define SF_DWB2(reg_name, block, id, field_name, post_fix) \ 187 .field_name = reg_name ## __ ## field_name ## post_fix 188 189 #define DCCG_SRII(reg_name, block, id)\ 190 .block ## _ ## reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 191 reg ## block ## id ## _ ## reg_name 192 193 #define VUPDATE_SRII(reg_name, block, id)\ 194 .reg_name[id] = BASE(reg ## reg_name ## _ ## block ## id ## _BASE_IDX) + \ 195 reg ## reg_name ## _ ## block ## id 196 197 /* NBIO */ 198 #define NBIO_BASE_INNER(seg) \ 199 NBIO_BASE__INST0_SEG ## seg 200 201 #define NBIO_BASE(seg) \ 202 NBIO_BASE_INNER(seg) 203 204 #define NBIO_SR(reg_name)\ 205 .reg_name = NBIO_BASE(regBIF_BX2_ ## reg_name ## _BASE_IDX) + \ 206 regBIF_BX2_ ## reg_name 207 208 static const struct bios_registers bios_regs = { 209 NBIO_SR(BIOS_SCRATCH_3), 210 NBIO_SR(BIOS_SCRATCH_6) 211 }; 212 213 #define clk_src_regs(index, pllid)\ 214 [index] = {\ 215 CS_COMMON_REG_LIST_DCN3_0(index, pllid),\ 216 } 217 218 static const struct dce110_clk_src_regs clk_src_regs[] = { 219 clk_src_regs(0, A), 220 clk_src_regs(1, B), 221 clk_src_regs(2, C), 222 clk_src_regs(3, D), 223 clk_src_regs(4, E) 224 }; 225 226 static const struct dce110_clk_src_shift cs_shift = { 227 CS_COMMON_MASK_SH_LIST_DCN2_0(__SHIFT) 228 }; 229 230 static const struct dce110_clk_src_mask cs_mask = { 231 CS_COMMON_MASK_SH_LIST_DCN2_0(_MASK) 232 }; 233 234 #define abm_regs(id)\ 235 [id] = {\ 236 ABM_DCN302_REG_LIST(id)\ 237 } 238 239 static const struct dce_abm_registers abm_regs[] = { 240 abm_regs(0), 241 abm_regs(1), 242 abm_regs(2), 243 abm_regs(3), 244 }; 245 246 static const struct dce_abm_shift abm_shift = { 247 ABM_MASK_SH_LIST_DCN30(__SHIFT) 248 }; 249 250 static const struct dce_abm_mask abm_mask = { 251 ABM_MASK_SH_LIST_DCN30(_MASK) 252 }; 253 254 #define audio_regs(id)\ 255 [id] = {\ 256 AUD_COMMON_REG_LIST(id)\ 257 } 258 259 static const struct dce_audio_registers audio_regs[] = { 260 audio_regs(0), 261 audio_regs(1), 262 audio_regs(2), 263 audio_regs(3), 264 audio_regs(4), 265 audio_regs(5), 266 audio_regs(6) 267 }; 268 269 #define DCE120_AUD_COMMON_MASK_SH_LIST(mask_sh)\ 270 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX, AZALIA_ENDPOINT_REG_INDEX, mask_sh),\ 271 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA, AZALIA_ENDPOINT_REG_DATA, mask_sh),\ 272 AUD_COMMON_MASK_SH_LIST_BASE(mask_sh) 273 274 static const struct dce_audio_shift audio_shift = { 275 DCE120_AUD_COMMON_MASK_SH_LIST(__SHIFT) 276 }; 277 278 static const struct dce_audio_mask audio_mask = { 279 DCE120_AUD_COMMON_MASK_SH_LIST(_MASK) 280 }; 281 282 #define vpg_regs(id)\ 283 [id] = {\ 284 VPG_DCN31_REG_LIST(id)\ 285 } 286 287 static const struct dcn31_vpg_registers vpg_regs[] = { 288 vpg_regs(0), 289 vpg_regs(1), 290 vpg_regs(2), 291 vpg_regs(3), 292 vpg_regs(4), 293 vpg_regs(5), 294 vpg_regs(6), 295 vpg_regs(7), 296 vpg_regs(8), 297 vpg_regs(9), 298 }; 299 300 static const struct dcn31_vpg_shift vpg_shift = { 301 DCN31_VPG_MASK_SH_LIST(__SHIFT) 302 }; 303 304 static const struct dcn31_vpg_mask vpg_mask = { 305 DCN31_VPG_MASK_SH_LIST(_MASK) 306 }; 307 308 #define afmt_regs(id)\ 309 [id] = {\ 310 AFMT_DCN31_REG_LIST(id)\ 311 } 312 313 static const struct dcn31_afmt_registers afmt_regs[] = { 314 afmt_regs(0), 315 afmt_regs(1), 316 afmt_regs(2), 317 afmt_regs(3), 318 afmt_regs(4), 319 afmt_regs(5) 320 }; 321 322 static const struct dcn31_afmt_shift afmt_shift = { 323 DCN31_AFMT_MASK_SH_LIST(__SHIFT) 324 }; 325 326 static const struct dcn31_afmt_mask afmt_mask = { 327 DCN31_AFMT_MASK_SH_LIST(_MASK) 328 }; 329 330 #define apg_regs(id)\ 331 [id] = {\ 332 APG_DCN31_REG_LIST(id)\ 333 } 334 335 static const struct dcn31_apg_registers apg_regs[] = { 336 apg_regs(0), 337 apg_regs(1), 338 apg_regs(2), 339 apg_regs(3) 340 }; 341 342 static const struct dcn31_apg_shift apg_shift = { 343 DCN31_APG_MASK_SH_LIST(__SHIFT) 344 }; 345 346 static const struct dcn31_apg_mask apg_mask = { 347 DCN31_APG_MASK_SH_LIST(_MASK) 348 }; 349 350 #define stream_enc_regs(id)\ 351 [id] = {\ 352 SE_DCN3_REG_LIST(id)\ 353 } 354 355 static const struct dcn10_stream_enc_registers stream_enc_regs[] = { 356 stream_enc_regs(0), 357 stream_enc_regs(1), 358 stream_enc_regs(2), 359 stream_enc_regs(3), 360 stream_enc_regs(4) 361 }; 362 363 static const struct dcn10_stream_encoder_shift se_shift = { 364 SE_COMMON_MASK_SH_LIST_DCN30(__SHIFT) 365 }; 366 367 static const struct dcn10_stream_encoder_mask se_mask = { 368 SE_COMMON_MASK_SH_LIST_DCN30(_MASK) 369 }; 370 371 372 #define aux_regs(id)\ 373 [id] = {\ 374 DCN2_AUX_REG_LIST(id)\ 375 } 376 377 static const struct dcn10_link_enc_aux_registers link_enc_aux_regs[] = { 378 aux_regs(0), 379 aux_regs(1), 380 aux_regs(2), 381 aux_regs(3), 382 aux_regs(4) 383 }; 384 385 #define hpd_regs(id)\ 386 [id] = {\ 387 HPD_REG_LIST(id)\ 388 } 389 390 static const struct dcn10_link_enc_hpd_registers link_enc_hpd_regs[] = { 391 hpd_regs(0), 392 hpd_regs(1), 393 hpd_regs(2), 394 hpd_regs(3), 395 hpd_regs(4) 396 }; 397 398 #define link_regs(id, phyid)\ 399 [id] = {\ 400 LE_DCN31_REG_LIST(id), \ 401 UNIPHY_DCN2_REG_LIST(phyid), \ 402 DPCS_DCN31_REG_LIST(id), \ 403 } 404 405 static const struct dce110_aux_registers_shift aux_shift = { 406 DCN_AUX_MASK_SH_LIST(__SHIFT) 407 }; 408 409 static const struct dce110_aux_registers_mask aux_mask = { 410 DCN_AUX_MASK_SH_LIST(_MASK) 411 }; 412 413 static const struct dcn10_link_enc_registers link_enc_regs[] = { 414 link_regs(0, A), 415 link_regs(1, B), 416 link_regs(2, C), 417 link_regs(3, D), 418 link_regs(4, E) 419 }; 420 421 static const struct dcn10_link_enc_shift le_shift = { 422 LINK_ENCODER_MASK_SH_LIST_DCN31(__SHIFT), \ 423 DPCS_DCN31_MASK_SH_LIST(__SHIFT) 424 }; 425 426 static const struct dcn10_link_enc_mask le_mask = { 427 LINK_ENCODER_MASK_SH_LIST_DCN31(_MASK), \ 428 DPCS_DCN31_MASK_SH_LIST(_MASK) 429 }; 430 431 #define hpo_dp_stream_encoder_reg_list(id)\ 432 [id] = {\ 433 DCN3_1_HPO_DP_STREAM_ENC_REG_LIST(id)\ 434 } 435 436 static const struct dcn31_hpo_dp_stream_encoder_registers hpo_dp_stream_enc_regs[] = { 437 hpo_dp_stream_encoder_reg_list(0), 438 hpo_dp_stream_encoder_reg_list(1), 439 hpo_dp_stream_encoder_reg_list(2), 440 hpo_dp_stream_encoder_reg_list(3), 441 }; 442 443 static const struct dcn31_hpo_dp_stream_encoder_shift hpo_dp_se_shift = { 444 DCN3_1_HPO_DP_STREAM_ENC_MASK_SH_LIST(__SHIFT) 445 }; 446 447 static const struct dcn31_hpo_dp_stream_encoder_mask hpo_dp_se_mask = { 448 DCN3_1_HPO_DP_STREAM_ENC_MASK_SH_LIST(_MASK) 449 }; 450 451 452 #define hpo_dp_link_encoder_reg_list(id)\ 453 [id] = {\ 454 DCN3_1_HPO_DP_LINK_ENC_REG_LIST(id),\ 455 DCN3_1_RDPCSTX_REG_LIST(0),\ 456 DCN3_1_RDPCSTX_REG_LIST(1),\ 457 DCN3_1_RDPCSTX_REG_LIST(2),\ 458 DCN3_1_RDPCSTX_REG_LIST(3),\ 459 DCN3_1_RDPCSTX_REG_LIST(4)\ 460 } 461 462 static const struct dcn31_hpo_dp_link_encoder_registers hpo_dp_link_enc_regs[] = { 463 hpo_dp_link_encoder_reg_list(0), 464 hpo_dp_link_encoder_reg_list(1), 465 }; 466 467 static const struct dcn31_hpo_dp_link_encoder_shift hpo_dp_le_shift = { 468 DCN3_1_HPO_DP_LINK_ENC_MASK_SH_LIST(__SHIFT) 469 }; 470 471 static const struct dcn31_hpo_dp_link_encoder_mask hpo_dp_le_mask = { 472 DCN3_1_HPO_DP_LINK_ENC_MASK_SH_LIST(_MASK) 473 }; 474 475 #define dpp_regs(id)\ 476 [id] = {\ 477 DPP_REG_LIST_DCN30(id),\ 478 } 479 480 static const struct dcn3_dpp_registers dpp_regs[] = { 481 dpp_regs(0), 482 dpp_regs(1), 483 dpp_regs(2), 484 dpp_regs(3) 485 }; 486 487 static const struct dcn3_dpp_shift tf_shift = { 488 DPP_REG_LIST_SH_MASK_DCN30(__SHIFT) 489 }; 490 491 static const struct dcn3_dpp_mask tf_mask = { 492 DPP_REG_LIST_SH_MASK_DCN30(_MASK) 493 }; 494 495 #define opp_regs(id)\ 496 [id] = {\ 497 OPP_REG_LIST_DCN30(id),\ 498 } 499 500 static const struct dcn20_opp_registers opp_regs[] = { 501 opp_regs(0), 502 opp_regs(1), 503 opp_regs(2), 504 opp_regs(3) 505 }; 506 507 static const struct dcn20_opp_shift opp_shift = { 508 OPP_MASK_SH_LIST_DCN20(__SHIFT) 509 }; 510 511 static const struct dcn20_opp_mask opp_mask = { 512 OPP_MASK_SH_LIST_DCN20(_MASK) 513 }; 514 515 #define aux_engine_regs(id)\ 516 [id] = {\ 517 AUX_COMMON_REG_LIST0(id), \ 518 .AUXN_IMPCAL = 0, \ 519 .AUXP_IMPCAL = 0, \ 520 .AUX_RESET_MASK = DP_AUX0_AUX_CONTROL__AUX_RESET_MASK, \ 521 } 522 523 static const struct dce110_aux_registers aux_engine_regs[] = { 524 aux_engine_regs(0), 525 aux_engine_regs(1), 526 aux_engine_regs(2), 527 aux_engine_regs(3), 528 aux_engine_regs(4) 529 }; 530 531 #define dwbc_regs_dcn3(id)\ 532 [id] = {\ 533 DWBC_COMMON_REG_LIST_DCN30(id),\ 534 } 535 536 static const struct dcn30_dwbc_registers dwbc30_regs[] = { 537 dwbc_regs_dcn3(0), 538 }; 539 540 static const struct dcn30_dwbc_shift dwbc30_shift = { 541 DWBC_COMMON_MASK_SH_LIST_DCN30(__SHIFT) 542 }; 543 544 static const struct dcn30_dwbc_mask dwbc30_mask = { 545 DWBC_COMMON_MASK_SH_LIST_DCN30(_MASK) 546 }; 547 548 #define mcif_wb_regs_dcn3(id)\ 549 [id] = {\ 550 MCIF_WB_COMMON_REG_LIST_DCN30(id),\ 551 } 552 553 static const struct dcn30_mmhubbub_registers mcif_wb30_regs[] = { 554 mcif_wb_regs_dcn3(0) 555 }; 556 557 static const struct dcn30_mmhubbub_shift mcif_wb30_shift = { 558 MCIF_WB_COMMON_MASK_SH_LIST_DCN30(__SHIFT) 559 }; 560 561 static const struct dcn30_mmhubbub_mask mcif_wb30_mask = { 562 MCIF_WB_COMMON_MASK_SH_LIST_DCN30(_MASK) 563 }; 564 565 #define dsc_regsDCN20(id)\ 566 [id] = {\ 567 DSC_REG_LIST_DCN20(id)\ 568 } 569 570 static const struct dcn20_dsc_registers dsc_regs[] = { 571 dsc_regsDCN20(0), 572 dsc_regsDCN20(1), 573 dsc_regsDCN20(2) 574 }; 575 576 static const struct dcn20_dsc_shift dsc_shift = { 577 DSC_REG_LIST_SH_MASK_DCN20(__SHIFT) 578 }; 579 580 static const struct dcn20_dsc_mask dsc_mask = { 581 DSC_REG_LIST_SH_MASK_DCN20(_MASK) 582 }; 583 584 static const struct dcn30_mpc_registers mpc_regs = { 585 MPC_REG_LIST_DCN3_0(0), 586 MPC_REG_LIST_DCN3_0(1), 587 MPC_REG_LIST_DCN3_0(2), 588 MPC_REG_LIST_DCN3_0(3), 589 MPC_OUT_MUX_REG_LIST_DCN3_0(0), 590 MPC_OUT_MUX_REG_LIST_DCN3_0(1), 591 MPC_OUT_MUX_REG_LIST_DCN3_0(2), 592 MPC_OUT_MUX_REG_LIST_DCN3_0(3), 593 MPC_DWB_MUX_REG_LIST_DCN3_0(0), 594 }; 595 596 static const struct dcn30_mpc_shift mpc_shift = { 597 MPC_COMMON_MASK_SH_LIST_DCN30(__SHIFT) 598 }; 599 600 static const struct dcn30_mpc_mask mpc_mask = { 601 MPC_COMMON_MASK_SH_LIST_DCN30(_MASK) 602 }; 603 604 #define optc_regs(id)\ 605 [id] = {OPTC_COMMON_REG_LIST_DCN3_1(id)} 606 607 static const struct dcn_optc_registers optc_regs[] = { 608 optc_regs(0), 609 optc_regs(1), 610 optc_regs(2), 611 optc_regs(3) 612 }; 613 614 static const struct dcn_optc_shift optc_shift = { 615 OPTC_COMMON_MASK_SH_LIST_DCN3_1(__SHIFT) 616 }; 617 618 static const struct dcn_optc_mask optc_mask = { 619 OPTC_COMMON_MASK_SH_LIST_DCN3_1(_MASK) 620 }; 621 622 #define hubp_regs(id)\ 623 [id] = {\ 624 HUBP_REG_LIST_DCN30(id)\ 625 } 626 627 static const struct dcn_hubp2_registers hubp_regs[] = { 628 hubp_regs(0), 629 hubp_regs(1), 630 hubp_regs(2), 631 hubp_regs(3) 632 }; 633 634 635 static const struct dcn_hubp2_shift hubp_shift = { 636 HUBP_MASK_SH_LIST_DCN31(__SHIFT) 637 }; 638 639 static const struct dcn_hubp2_mask hubp_mask = { 640 HUBP_MASK_SH_LIST_DCN31(_MASK) 641 }; 642 static const struct dcn_hubbub_registers hubbub_reg = { 643 HUBBUB_REG_LIST_DCN31(0) 644 }; 645 646 static const struct dcn_hubbub_shift hubbub_shift = { 647 HUBBUB_MASK_SH_LIST_DCN31(__SHIFT) 648 }; 649 650 static const struct dcn_hubbub_mask hubbub_mask = { 651 HUBBUB_MASK_SH_LIST_DCN31(_MASK) 652 }; 653 654 static const struct dccg_registers dccg_regs = { 655 DCCG_REG_LIST_DCN31() 656 }; 657 658 static const struct dccg_shift dccg_shift = { 659 DCCG_MASK_SH_LIST_DCN31(__SHIFT) 660 }; 661 662 static const struct dccg_mask dccg_mask = { 663 DCCG_MASK_SH_LIST_DCN31(_MASK) 664 }; 665 666 667 #define SRII2(reg_name_pre, reg_name_post, id)\ 668 .reg_name_pre ## _ ## reg_name_post[id] = BASE(reg ## reg_name_pre \ 669 ## id ## _ ## reg_name_post ## _BASE_IDX) + \ 670 reg ## reg_name_pre ## id ## _ ## reg_name_post 671 672 673 #define HWSEQ_DCN31_REG_LIST()\ 674 SR(DCHUBBUB_GLOBAL_TIMER_CNTL), \ 675 SR(DCHUBBUB_ARB_HOSTVM_CNTL), \ 676 SR(DIO_MEM_PWR_CTRL), \ 677 SR(ODM_MEM_PWR_CTRL3), \ 678 SR(DMU_MEM_PWR_CNTL), \ 679 SR(MMHUBBUB_MEM_PWR_CNTL), \ 680 SR(DCCG_GATE_DISABLE_CNTL), \ 681 SR(DCCG_GATE_DISABLE_CNTL2), \ 682 SR(DCFCLK_CNTL),\ 683 SR(DC_MEM_GLOBAL_PWR_REQ_CNTL), \ 684 SRII(PIXEL_RATE_CNTL, OTG, 0), \ 685 SRII(PIXEL_RATE_CNTL, OTG, 1),\ 686 SRII(PIXEL_RATE_CNTL, OTG, 2),\ 687 SRII(PIXEL_RATE_CNTL, OTG, 3),\ 688 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 0),\ 689 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 1),\ 690 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 2),\ 691 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 3),\ 692 SR(MICROSECOND_TIME_BASE_DIV), \ 693 SR(MILLISECOND_TIME_BASE_DIV), \ 694 SR(DISPCLK_FREQ_CHANGE_CNTL), \ 695 SR(RBBMIF_TIMEOUT_DIS), \ 696 SR(RBBMIF_TIMEOUT_DIS_2), \ 697 SR(DCHUBBUB_CRC_CTRL), \ 698 SR(DPP_TOP0_DPP_CRC_CTRL), \ 699 SR(DPP_TOP0_DPP_CRC_VAL_B_A), \ 700 SR(DPP_TOP0_DPP_CRC_VAL_R_G), \ 701 SR(MPC_CRC_CTRL), \ 702 SR(MPC_CRC_RESULT_GB), \ 703 SR(MPC_CRC_RESULT_C), \ 704 SR(MPC_CRC_RESULT_AR), \ 705 SR(DOMAIN0_PG_CONFIG), \ 706 SR(DOMAIN1_PG_CONFIG), \ 707 SR(DOMAIN2_PG_CONFIG), \ 708 SR(DOMAIN3_PG_CONFIG), \ 709 SR(DOMAIN16_PG_CONFIG), \ 710 SR(DOMAIN17_PG_CONFIG), \ 711 SR(DOMAIN18_PG_CONFIG), \ 712 SR(DOMAIN0_PG_STATUS), \ 713 SR(DOMAIN1_PG_STATUS), \ 714 SR(DOMAIN2_PG_STATUS), \ 715 SR(DOMAIN3_PG_STATUS), \ 716 SR(DOMAIN16_PG_STATUS), \ 717 SR(DOMAIN17_PG_STATUS), \ 718 SR(DOMAIN18_PG_STATUS), \ 719 SR(D1VGA_CONTROL), \ 720 SR(D2VGA_CONTROL), \ 721 SR(D3VGA_CONTROL), \ 722 SR(D4VGA_CONTROL), \ 723 SR(D5VGA_CONTROL), \ 724 SR(D6VGA_CONTROL), \ 725 SR(DC_IP_REQUEST_CNTL), \ 726 SR(AZALIA_AUDIO_DTO), \ 727 SR(AZALIA_CONTROLLER_CLOCK_GATING), \ 728 SR(HPO_TOP_HW_CONTROL) 729 730 static const struct dce_hwseq_registers hwseq_reg = { 731 HWSEQ_DCN31_REG_LIST() 732 }; 733 734 #define HWSEQ_DCN31_MASK_SH_LIST(mask_sh)\ 735 HWSEQ_DCN_MASK_SH_LIST(mask_sh), \ 736 HWS_SF(, DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_REFDIV, mask_sh), \ 737 HWS_SF(, DCHUBBUB_ARB_HOSTVM_CNTL, DISABLE_HOSTVM_FORCE_ALLOW_PSTATE, mask_sh), \ 738 HWS_SF(, DOMAIN0_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ 739 HWS_SF(, DOMAIN0_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ 740 HWS_SF(, DOMAIN1_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ 741 HWS_SF(, DOMAIN1_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ 742 HWS_SF(, DOMAIN2_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ 743 HWS_SF(, DOMAIN2_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ 744 HWS_SF(, DOMAIN3_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ 745 HWS_SF(, DOMAIN3_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ 746 HWS_SF(, DOMAIN16_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ 747 HWS_SF(, DOMAIN16_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ 748 HWS_SF(, DOMAIN17_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ 749 HWS_SF(, DOMAIN17_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ 750 HWS_SF(, DOMAIN18_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ 751 HWS_SF(, DOMAIN18_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ 752 HWS_SF(, DOMAIN0_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ 753 HWS_SF(, DOMAIN1_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ 754 HWS_SF(, DOMAIN2_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ 755 HWS_SF(, DOMAIN3_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ 756 HWS_SF(, DOMAIN16_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ 757 HWS_SF(, DOMAIN17_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ 758 HWS_SF(, DOMAIN18_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ 759 HWS_SF(, DC_IP_REQUEST_CNTL, IP_REQUEST_EN, mask_sh), \ 760 HWS_SF(, AZALIA_AUDIO_DTO, AZALIA_AUDIO_DTO_MODULE, mask_sh), \ 761 HWS_SF(, HPO_TOP_CLOCK_CONTROL, HPO_HDMISTREAMCLK_G_GATE_DIS, mask_sh), \ 762 HWS_SF(, DMU_MEM_PWR_CNTL, DMCU_ERAM_MEM_PWR_FORCE, mask_sh), \ 763 HWS_SF(, ODM_MEM_PWR_CTRL3, ODM_MEM_UNASSIGNED_PWR_MODE, mask_sh), \ 764 HWS_SF(, ODM_MEM_PWR_CTRL3, ODM_MEM_VBLANK_PWR_MODE, mask_sh), \ 765 HWS_SF(, MMHUBBUB_MEM_PWR_CNTL, VGA_MEM_PWR_FORCE, mask_sh), \ 766 HWS_SF(, DIO_MEM_PWR_CTRL, I2C_LIGHT_SLEEP_FORCE, mask_sh), \ 767 HWS_SF(, HPO_TOP_HW_CONTROL, HPO_IO_EN, mask_sh) 768 769 static const struct dce_hwseq_shift hwseq_shift = { 770 HWSEQ_DCN31_MASK_SH_LIST(__SHIFT) 771 }; 772 773 static const struct dce_hwseq_mask hwseq_mask = { 774 HWSEQ_DCN31_MASK_SH_LIST(_MASK) 775 }; 776 #define vmid_regs(id)\ 777 [id] = {\ 778 DCN20_VMID_REG_LIST(id)\ 779 } 780 781 static const struct dcn_vmid_registers vmid_regs[] = { 782 vmid_regs(0), 783 vmid_regs(1), 784 vmid_regs(2), 785 vmid_regs(3), 786 vmid_regs(4), 787 vmid_regs(5), 788 vmid_regs(6), 789 vmid_regs(7), 790 vmid_regs(8), 791 vmid_regs(9), 792 vmid_regs(10), 793 vmid_regs(11), 794 vmid_regs(12), 795 vmid_regs(13), 796 vmid_regs(14), 797 vmid_regs(15) 798 }; 799 800 static const struct dcn20_vmid_shift vmid_shifts = { 801 DCN20_VMID_MASK_SH_LIST(__SHIFT) 802 }; 803 804 static const struct dcn20_vmid_mask vmid_masks = { 805 DCN20_VMID_MASK_SH_LIST(_MASK) 806 }; 807 808 static const struct resource_caps res_cap_dcn31 = { 809 .num_timing_generator = 4, 810 .num_opp = 4, 811 .num_video_plane = 4, 812 .num_audio = 5, 813 .num_stream_encoder = 5, 814 .num_dig_link_enc = 5, 815 .num_hpo_dp_stream_encoder = 4, 816 .num_hpo_dp_link_encoder = 2, 817 .num_pll = 5, 818 .num_dwb = 1, 819 .num_ddc = 5, 820 .num_vmid = 16, 821 .num_mpc_3dlut = 2, 822 .num_dsc = 3, 823 }; 824 825 static const struct dc_plane_cap plane_cap = { 826 .type = DC_PLANE_TYPE_DCN_UNIVERSAL, 827 .per_pixel_alpha = true, 828 829 .pixel_format_support = { 830 .argb8888 = true, 831 .nv12 = true, 832 .fp16 = true, 833 .p010 = true, 834 .ayuv = false, 835 }, 836 837 .max_upscale_factor = { 838 .argb8888 = 16000, 839 .nv12 = 16000, 840 .fp16 = 16000 841 }, 842 843 // 6:1 downscaling ratio: 1000/6 = 166.666 844 .max_downscale_factor = { 845 .argb8888 = 167, 846 .nv12 = 167, 847 .fp16 = 167 848 }, 849 64, 850 64 851 }; 852 853 static const struct dc_debug_options debug_defaults_drv = { 854 .disable_z10 = true, /*hw not support it*/ 855 .disable_dmcu = true, 856 .force_abm_enable = false, 857 .timing_trace = false, 858 .clock_trace = true, 859 .disable_pplib_clock_request = false, 860 .pipe_split_policy = MPC_SPLIT_DYNAMIC, 861 .force_single_disp_pipe_split = false, 862 .disable_dcc = DCC_ENABLE, 863 .vsr_support = true, 864 .performance_trace = false, 865 .max_downscale_src_width = 4096,/*upto true 4k*/ 866 .disable_pplib_wm_range = false, 867 .scl_reset_length10 = true, 868 .sanity_checks = false, 869 .underflow_assert_delay_us = 0xFFFFFFFF, 870 .dwb_fi_phase = -1, // -1 = disable, 871 .dmub_command_table = true, 872 .pstate_enabled = true, 873 .use_max_lb = true, 874 .enable_mem_low_power = { 875 .bits = { 876 .vga = true, 877 .i2c = true, 878 .dmcu = false, // This is previously known to cause hang on S3 cycles if enabled 879 .dscl = true, 880 .cm = true, 881 .mpc = true, 882 .optc = true, 883 .vpg = true, 884 .afmt = true, 885 } 886 }, 887 .psr_power_use_phy_fsm = 0, 888 }; 889 890 static const struct dc_debug_options debug_defaults_diags = { 891 .disable_dmcu = true, 892 .force_abm_enable = false, 893 .timing_trace = true, 894 .clock_trace = true, 895 .disable_dpp_power_gate = true, 896 .disable_hubp_power_gate = true, 897 .disable_clock_gate = true, 898 .disable_pplib_clock_request = true, 899 .disable_pplib_wm_range = true, 900 .disable_stutter = false, 901 .scl_reset_length10 = true, 902 .dwb_fi_phase = -1, // -1 = disable 903 .dmub_command_table = true, 904 .enable_tri_buf = true, 905 .use_max_lb = true 906 }; 907 908 static const struct dc_panel_config panel_config_defaults = { 909 .psr = { 910 .disable_psr = false, 911 .disallow_psrsu = false, 912 }, 913 .ilr = { 914 .optimize_edp_link_rate = true, 915 }, 916 }; 917 918 static void dcn31_dpp_destroy(struct dpp **dpp) 919 { 920 kfree(TO_DCN20_DPP(*dpp)); 921 *dpp = NULL; 922 } 923 924 static struct dpp *dcn31_dpp_create( 925 struct dc_context *ctx, 926 uint32_t inst) 927 { 928 struct dcn3_dpp *dpp = 929 kzalloc(sizeof(struct dcn3_dpp), GFP_KERNEL); 930 931 if (!dpp) 932 return NULL; 933 934 if (dpp3_construct(dpp, ctx, inst, 935 &dpp_regs[inst], &tf_shift, &tf_mask)) 936 return &dpp->base; 937 938 BREAK_TO_DEBUGGER(); 939 kfree(dpp); 940 return NULL; 941 } 942 943 static struct output_pixel_processor *dcn31_opp_create( 944 struct dc_context *ctx, uint32_t inst) 945 { 946 struct dcn20_opp *opp = 947 kzalloc(sizeof(struct dcn20_opp), GFP_KERNEL); 948 949 if (!opp) { 950 BREAK_TO_DEBUGGER(); 951 return NULL; 952 } 953 954 dcn20_opp_construct(opp, ctx, inst, 955 &opp_regs[inst], &opp_shift, &opp_mask); 956 return &opp->base; 957 } 958 959 static struct dce_aux *dcn31_aux_engine_create( 960 struct dc_context *ctx, 961 uint32_t inst) 962 { 963 struct aux_engine_dce110 *aux_engine = 964 kzalloc(sizeof(struct aux_engine_dce110), GFP_KERNEL); 965 966 if (!aux_engine) 967 return NULL; 968 969 dce110_aux_engine_construct(aux_engine, ctx, inst, 970 SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD, 971 &aux_engine_regs[inst], 972 &aux_mask, 973 &aux_shift, 974 ctx->dc->caps.extended_aux_timeout_support); 975 976 return &aux_engine->base; 977 } 978 #define i2c_inst_regs(id) { I2C_HW_ENGINE_COMMON_REG_LIST_DCN30(id) } 979 980 static const struct dce_i2c_registers i2c_hw_regs[] = { 981 i2c_inst_regs(1), 982 i2c_inst_regs(2), 983 i2c_inst_regs(3), 984 i2c_inst_regs(4), 985 i2c_inst_regs(5), 986 }; 987 988 static const struct dce_i2c_shift i2c_shifts = { 989 I2C_COMMON_MASK_SH_LIST_DCN30(__SHIFT) 990 }; 991 992 static const struct dce_i2c_mask i2c_masks = { 993 I2C_COMMON_MASK_SH_LIST_DCN30(_MASK) 994 }; 995 996 static struct dce_i2c_hw *dcn31_i2c_hw_create( 997 struct dc_context *ctx, 998 uint32_t inst) 999 { 1000 struct dce_i2c_hw *dce_i2c_hw = 1001 kzalloc(sizeof(struct dce_i2c_hw), GFP_KERNEL); 1002 1003 if (!dce_i2c_hw) 1004 return NULL; 1005 1006 dcn2_i2c_hw_construct(dce_i2c_hw, ctx, inst, 1007 &i2c_hw_regs[inst], &i2c_shifts, &i2c_masks); 1008 1009 return dce_i2c_hw; 1010 } 1011 static struct mpc *dcn31_mpc_create( 1012 struct dc_context *ctx, 1013 int num_mpcc, 1014 int num_rmu) 1015 { 1016 struct dcn30_mpc *mpc30 = kzalloc(sizeof(struct dcn30_mpc), 1017 GFP_KERNEL); 1018 1019 if (!mpc30) 1020 return NULL; 1021 1022 dcn30_mpc_construct(mpc30, ctx, 1023 &mpc_regs, 1024 &mpc_shift, 1025 &mpc_mask, 1026 num_mpcc, 1027 num_rmu); 1028 1029 return &mpc30->base; 1030 } 1031 1032 static struct hubbub *dcn31_hubbub_create(struct dc_context *ctx) 1033 { 1034 int i; 1035 1036 struct dcn20_hubbub *hubbub3 = kzalloc(sizeof(struct dcn20_hubbub), 1037 GFP_KERNEL); 1038 1039 if (!hubbub3) 1040 return NULL; 1041 1042 hubbub31_construct(hubbub3, ctx, 1043 &hubbub_reg, 1044 &hubbub_shift, 1045 &hubbub_mask, 1046 dcn3_15_ip.det_buffer_size_kbytes, 1047 dcn3_15_ip.pixel_chunk_size_kbytes, 1048 dcn3_15_ip.config_return_buffer_size_in_kbytes); 1049 1050 1051 for (i = 0; i < res_cap_dcn31.num_vmid; i++) { 1052 struct dcn20_vmid *vmid = &hubbub3->vmid[i]; 1053 1054 vmid->ctx = ctx; 1055 1056 vmid->regs = &vmid_regs[i]; 1057 vmid->shifts = &vmid_shifts; 1058 vmid->masks = &vmid_masks; 1059 } 1060 1061 return &hubbub3->base; 1062 } 1063 1064 static struct timing_generator *dcn31_timing_generator_create( 1065 struct dc_context *ctx, 1066 uint32_t instance) 1067 { 1068 struct optc *tgn10 = 1069 kzalloc(sizeof(struct optc), GFP_KERNEL); 1070 1071 if (!tgn10) 1072 return NULL; 1073 1074 tgn10->base.inst = instance; 1075 tgn10->base.ctx = ctx; 1076 1077 tgn10->tg_regs = &optc_regs[instance]; 1078 tgn10->tg_shift = &optc_shift; 1079 tgn10->tg_mask = &optc_mask; 1080 1081 dcn31_timing_generator_init(tgn10); 1082 1083 return &tgn10->base; 1084 } 1085 1086 static const struct encoder_feature_support link_enc_feature = { 1087 .max_hdmi_deep_color = COLOR_DEPTH_121212, 1088 .max_hdmi_pixel_clock = 600000, 1089 .hdmi_ycbcr420_supported = true, 1090 .dp_ycbcr420_supported = true, 1091 .fec_supported = true, 1092 .flags.bits.IS_HBR2_CAPABLE = true, 1093 .flags.bits.IS_HBR3_CAPABLE = true, 1094 .flags.bits.IS_TPS3_CAPABLE = true, 1095 .flags.bits.IS_TPS4_CAPABLE = true 1096 }; 1097 1098 static struct link_encoder *dcn31_link_encoder_create( 1099 struct dc_context *ctx, 1100 const struct encoder_init_data *enc_init_data) 1101 { 1102 struct dcn20_link_encoder *enc20 = 1103 kzalloc(sizeof(struct dcn20_link_encoder), GFP_KERNEL); 1104 1105 if (!enc20) 1106 return NULL; 1107 1108 dcn31_link_encoder_construct(enc20, 1109 enc_init_data, 1110 &link_enc_feature, 1111 &link_enc_regs[enc_init_data->transmitter], 1112 &link_enc_aux_regs[enc_init_data->channel - 1], 1113 &link_enc_hpd_regs[enc_init_data->hpd_source], 1114 &le_shift, 1115 &le_mask); 1116 1117 return &enc20->enc10.base; 1118 } 1119 1120 /* Create a minimal link encoder object not associated with a particular 1121 * physical connector. 1122 * resource_funcs.link_enc_create_minimal 1123 */ 1124 static struct link_encoder *dcn31_link_enc_create_minimal( 1125 struct dc_context *ctx, enum engine_id eng_id) 1126 { 1127 struct dcn20_link_encoder *enc20; 1128 1129 if ((eng_id - ENGINE_ID_DIGA) > ctx->dc->res_pool->res_cap->num_dig_link_enc) 1130 return NULL; 1131 1132 enc20 = kzalloc(sizeof(struct dcn20_link_encoder), GFP_KERNEL); 1133 if (!enc20) 1134 return NULL; 1135 1136 dcn31_link_encoder_construct_minimal( 1137 enc20, 1138 ctx, 1139 &link_enc_feature, 1140 &link_enc_regs[eng_id - ENGINE_ID_DIGA], 1141 eng_id); 1142 1143 return &enc20->enc10.base; 1144 } 1145 1146 static struct panel_cntl *dcn31_panel_cntl_create(const struct panel_cntl_init_data *init_data) 1147 { 1148 struct dcn31_panel_cntl *panel_cntl = 1149 kzalloc(sizeof(struct dcn31_panel_cntl), GFP_KERNEL); 1150 1151 if (!panel_cntl) 1152 return NULL; 1153 1154 dcn31_panel_cntl_construct(panel_cntl, init_data); 1155 1156 return &panel_cntl->base; 1157 } 1158 1159 static void read_dce_straps( 1160 struct dc_context *ctx, 1161 struct resource_straps *straps) 1162 { 1163 generic_reg_get(ctx, regDC_PINSTRAPS + BASE(regDC_PINSTRAPS_BASE_IDX), 1164 FN(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO), &straps->dc_pinstraps_audio); 1165 1166 } 1167 1168 static struct audio *dcn31_create_audio( 1169 struct dc_context *ctx, unsigned int inst) 1170 { 1171 return dce_audio_create(ctx, inst, 1172 &audio_regs[inst], &audio_shift, &audio_mask); 1173 } 1174 1175 static struct vpg *dcn31_vpg_create( 1176 struct dc_context *ctx, 1177 uint32_t inst) 1178 { 1179 struct dcn31_vpg *vpg31 = kzalloc(sizeof(struct dcn31_vpg), GFP_KERNEL); 1180 1181 if (!vpg31) 1182 return NULL; 1183 1184 vpg31_construct(vpg31, ctx, inst, 1185 &vpg_regs[inst], 1186 &vpg_shift, 1187 &vpg_mask); 1188 1189 return &vpg31->base; 1190 } 1191 1192 static struct afmt *dcn31_afmt_create( 1193 struct dc_context *ctx, 1194 uint32_t inst) 1195 { 1196 struct dcn31_afmt *afmt31 = kzalloc(sizeof(struct dcn31_afmt), GFP_KERNEL); 1197 1198 if (!afmt31) 1199 return NULL; 1200 1201 afmt31_construct(afmt31, ctx, inst, 1202 &afmt_regs[inst], 1203 &afmt_shift, 1204 &afmt_mask); 1205 1206 // Light sleep by default, no need to power down here 1207 1208 return &afmt31->base; 1209 } 1210 1211 static struct apg *dcn31_apg_create( 1212 struct dc_context *ctx, 1213 uint32_t inst) 1214 { 1215 struct dcn31_apg *apg31 = kzalloc(sizeof(struct dcn31_apg), GFP_KERNEL); 1216 1217 if (!apg31) 1218 return NULL; 1219 1220 apg31_construct(apg31, ctx, inst, 1221 &apg_regs[inst], 1222 &apg_shift, 1223 &apg_mask); 1224 1225 return &apg31->base; 1226 } 1227 1228 static struct stream_encoder *dcn315_stream_encoder_create( 1229 enum engine_id eng_id, 1230 struct dc_context *ctx) 1231 { 1232 struct dcn10_stream_encoder *enc1; 1233 struct vpg *vpg; 1234 struct afmt *afmt; 1235 int vpg_inst; 1236 int afmt_inst; 1237 1238 /*PHYB is wired off in HW, allow front end to remapping, otherwise needs more changes*/ 1239 1240 /* Mapping of VPG, AFMT, DME register blocks to DIO block instance */ 1241 if (eng_id <= ENGINE_ID_DIGF) { 1242 vpg_inst = eng_id; 1243 afmt_inst = eng_id; 1244 } else 1245 return NULL; 1246 1247 enc1 = kzalloc(sizeof(struct dcn10_stream_encoder), GFP_KERNEL); 1248 vpg = dcn31_vpg_create(ctx, vpg_inst); 1249 afmt = dcn31_afmt_create(ctx, afmt_inst); 1250 1251 if (!enc1 || !vpg || !afmt) { 1252 kfree(enc1); 1253 kfree(vpg); 1254 kfree(afmt); 1255 return NULL; 1256 } 1257 1258 dcn30_dio_stream_encoder_construct(enc1, ctx, ctx->dc_bios, 1259 eng_id, vpg, afmt, 1260 &stream_enc_regs[eng_id], 1261 &se_shift, &se_mask); 1262 1263 return &enc1->base; 1264 } 1265 1266 static struct hpo_dp_stream_encoder *dcn31_hpo_dp_stream_encoder_create( 1267 enum engine_id eng_id, 1268 struct dc_context *ctx) 1269 { 1270 struct dcn31_hpo_dp_stream_encoder *hpo_dp_enc31; 1271 struct vpg *vpg; 1272 struct apg *apg; 1273 uint32_t hpo_dp_inst; 1274 uint32_t vpg_inst; 1275 uint32_t apg_inst; 1276 1277 ASSERT((eng_id >= ENGINE_ID_HPO_DP_0) && (eng_id <= ENGINE_ID_HPO_DP_3)); 1278 hpo_dp_inst = eng_id - ENGINE_ID_HPO_DP_0; 1279 1280 /* Mapping of VPG register blocks to HPO DP block instance: 1281 * VPG[6] -> HPO_DP[0] 1282 * VPG[7] -> HPO_DP[1] 1283 * VPG[8] -> HPO_DP[2] 1284 * VPG[9] -> HPO_DP[3] 1285 */ 1286 vpg_inst = hpo_dp_inst + 6; 1287 1288 /* Mapping of APG register blocks to HPO DP block instance: 1289 * APG[0] -> HPO_DP[0] 1290 * APG[1] -> HPO_DP[1] 1291 * APG[2] -> HPO_DP[2] 1292 * APG[3] -> HPO_DP[3] 1293 */ 1294 apg_inst = hpo_dp_inst; 1295 1296 /* allocate HPO stream encoder and create VPG sub-block */ 1297 hpo_dp_enc31 = kzalloc(sizeof(struct dcn31_hpo_dp_stream_encoder), GFP_KERNEL); 1298 vpg = dcn31_vpg_create(ctx, vpg_inst); 1299 apg = dcn31_apg_create(ctx, apg_inst); 1300 1301 if (!hpo_dp_enc31 || !vpg || !apg) { 1302 kfree(hpo_dp_enc31); 1303 kfree(vpg); 1304 kfree(apg); 1305 return NULL; 1306 } 1307 1308 dcn31_hpo_dp_stream_encoder_construct(hpo_dp_enc31, ctx, ctx->dc_bios, 1309 hpo_dp_inst, eng_id, vpg, apg, 1310 &hpo_dp_stream_enc_regs[hpo_dp_inst], 1311 &hpo_dp_se_shift, &hpo_dp_se_mask); 1312 1313 return &hpo_dp_enc31->base; 1314 } 1315 1316 static struct hpo_dp_link_encoder *dcn31_hpo_dp_link_encoder_create( 1317 uint8_t inst, 1318 struct dc_context *ctx) 1319 { 1320 struct dcn31_hpo_dp_link_encoder *hpo_dp_enc31; 1321 1322 /* allocate HPO link encoder */ 1323 hpo_dp_enc31 = kzalloc(sizeof(struct dcn31_hpo_dp_link_encoder), GFP_KERNEL); 1324 1325 hpo_dp_link_encoder31_construct(hpo_dp_enc31, ctx, inst, 1326 &hpo_dp_link_enc_regs[inst], 1327 &hpo_dp_le_shift, &hpo_dp_le_mask); 1328 1329 return &hpo_dp_enc31->base; 1330 } 1331 1332 static struct dce_hwseq *dcn31_hwseq_create( 1333 struct dc_context *ctx) 1334 { 1335 struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_KERNEL); 1336 1337 if (hws) { 1338 hws->ctx = ctx; 1339 hws->regs = &hwseq_reg; 1340 hws->shifts = &hwseq_shift; 1341 hws->masks = &hwseq_mask; 1342 /* DCN3.1 FPGA Workaround 1343 * Need to enable HPO DP Stream Encoder before setting OTG master enable. 1344 * To do so, move calling function enable_stream_timing to only be done AFTER calling 1345 * function core_link_enable_stream 1346 */ 1347 if (IS_FPGA_MAXIMUS_DC(ctx->dce_environment)) 1348 hws->wa.dp_hpo_and_otg_sequence = true; 1349 } 1350 return hws; 1351 } 1352 static const struct resource_create_funcs res_create_funcs = { 1353 .read_dce_straps = read_dce_straps, 1354 .create_audio = dcn31_create_audio, 1355 .create_stream_encoder = dcn315_stream_encoder_create, 1356 .create_hpo_dp_stream_encoder = dcn31_hpo_dp_stream_encoder_create, 1357 .create_hpo_dp_link_encoder = dcn31_hpo_dp_link_encoder_create, 1358 .create_hwseq = dcn31_hwseq_create, 1359 }; 1360 1361 static const struct resource_create_funcs res_create_maximus_funcs = { 1362 .read_dce_straps = NULL, 1363 .create_audio = NULL, 1364 .create_stream_encoder = NULL, 1365 .create_hpo_dp_stream_encoder = dcn31_hpo_dp_stream_encoder_create, 1366 .create_hpo_dp_link_encoder = dcn31_hpo_dp_link_encoder_create, 1367 .create_hwseq = dcn31_hwseq_create, 1368 }; 1369 1370 static void dcn315_resource_destruct(struct dcn315_resource_pool *pool) 1371 { 1372 unsigned int i; 1373 1374 for (i = 0; i < pool->base.stream_enc_count; i++) { 1375 if (pool->base.stream_enc[i] != NULL) { 1376 if (pool->base.stream_enc[i]->vpg != NULL) { 1377 kfree(DCN30_VPG_FROM_VPG(pool->base.stream_enc[i]->vpg)); 1378 pool->base.stream_enc[i]->vpg = NULL; 1379 } 1380 if (pool->base.stream_enc[i]->afmt != NULL) { 1381 kfree(DCN30_AFMT_FROM_AFMT(pool->base.stream_enc[i]->afmt)); 1382 pool->base.stream_enc[i]->afmt = NULL; 1383 } 1384 kfree(DCN10STRENC_FROM_STRENC(pool->base.stream_enc[i])); 1385 pool->base.stream_enc[i] = NULL; 1386 } 1387 } 1388 1389 for (i = 0; i < pool->base.hpo_dp_stream_enc_count; i++) { 1390 if (pool->base.hpo_dp_stream_enc[i] != NULL) { 1391 if (pool->base.hpo_dp_stream_enc[i]->vpg != NULL) { 1392 kfree(DCN30_VPG_FROM_VPG(pool->base.hpo_dp_stream_enc[i]->vpg)); 1393 pool->base.hpo_dp_stream_enc[i]->vpg = NULL; 1394 } 1395 if (pool->base.hpo_dp_stream_enc[i]->apg != NULL) { 1396 kfree(DCN31_APG_FROM_APG(pool->base.hpo_dp_stream_enc[i]->apg)); 1397 pool->base.hpo_dp_stream_enc[i]->apg = NULL; 1398 } 1399 kfree(DCN3_1_HPO_DP_STREAM_ENC_FROM_HPO_STREAM_ENC(pool->base.hpo_dp_stream_enc[i])); 1400 pool->base.hpo_dp_stream_enc[i] = NULL; 1401 } 1402 } 1403 1404 for (i = 0; i < pool->base.hpo_dp_link_enc_count; i++) { 1405 if (pool->base.hpo_dp_link_enc[i] != NULL) { 1406 kfree(DCN3_1_HPO_DP_LINK_ENC_FROM_HPO_LINK_ENC(pool->base.hpo_dp_link_enc[i])); 1407 pool->base.hpo_dp_link_enc[i] = NULL; 1408 } 1409 } 1410 1411 for (i = 0; i < pool->base.res_cap->num_dsc; i++) { 1412 if (pool->base.dscs[i] != NULL) 1413 dcn20_dsc_destroy(&pool->base.dscs[i]); 1414 } 1415 1416 if (pool->base.mpc != NULL) { 1417 kfree(TO_DCN20_MPC(pool->base.mpc)); 1418 pool->base.mpc = NULL; 1419 } 1420 if (pool->base.hubbub != NULL) { 1421 kfree(pool->base.hubbub); 1422 pool->base.hubbub = NULL; 1423 } 1424 for (i = 0; i < pool->base.pipe_count; i++) { 1425 if (pool->base.dpps[i] != NULL) 1426 dcn31_dpp_destroy(&pool->base.dpps[i]); 1427 1428 if (pool->base.ipps[i] != NULL) 1429 pool->base.ipps[i]->funcs->ipp_destroy(&pool->base.ipps[i]); 1430 1431 if (pool->base.hubps[i] != NULL) { 1432 kfree(TO_DCN20_HUBP(pool->base.hubps[i])); 1433 pool->base.hubps[i] = NULL; 1434 } 1435 1436 if (pool->base.irqs != NULL) { 1437 dal_irq_service_destroy(&pool->base.irqs); 1438 } 1439 } 1440 1441 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { 1442 if (pool->base.engines[i] != NULL) 1443 dce110_engine_destroy(&pool->base.engines[i]); 1444 if (pool->base.hw_i2cs[i] != NULL) { 1445 kfree(pool->base.hw_i2cs[i]); 1446 pool->base.hw_i2cs[i] = NULL; 1447 } 1448 if (pool->base.sw_i2cs[i] != NULL) { 1449 kfree(pool->base.sw_i2cs[i]); 1450 pool->base.sw_i2cs[i] = NULL; 1451 } 1452 } 1453 1454 for (i = 0; i < pool->base.res_cap->num_opp; i++) { 1455 if (pool->base.opps[i] != NULL) 1456 pool->base.opps[i]->funcs->opp_destroy(&pool->base.opps[i]); 1457 } 1458 1459 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { 1460 if (pool->base.timing_generators[i] != NULL) { 1461 kfree(DCN10TG_FROM_TG(pool->base.timing_generators[i])); 1462 pool->base.timing_generators[i] = NULL; 1463 } 1464 } 1465 1466 for (i = 0; i < pool->base.res_cap->num_dwb; i++) { 1467 if (pool->base.dwbc[i] != NULL) { 1468 kfree(TO_DCN30_DWBC(pool->base.dwbc[i])); 1469 pool->base.dwbc[i] = NULL; 1470 } 1471 if (pool->base.mcif_wb[i] != NULL) { 1472 kfree(TO_DCN30_MMHUBBUB(pool->base.mcif_wb[i])); 1473 pool->base.mcif_wb[i] = NULL; 1474 } 1475 } 1476 1477 for (i = 0; i < pool->base.audio_count; i++) { 1478 if (pool->base.audios[i]) 1479 dce_aud_destroy(&pool->base.audios[i]); 1480 } 1481 1482 for (i = 0; i < pool->base.clk_src_count; i++) { 1483 if (pool->base.clock_sources[i] != NULL) { 1484 dcn20_clock_source_destroy(&pool->base.clock_sources[i]); 1485 pool->base.clock_sources[i] = NULL; 1486 } 1487 } 1488 1489 for (i = 0; i < pool->base.res_cap->num_mpc_3dlut; i++) { 1490 if (pool->base.mpc_lut[i] != NULL) { 1491 dc_3dlut_func_release(pool->base.mpc_lut[i]); 1492 pool->base.mpc_lut[i] = NULL; 1493 } 1494 if (pool->base.mpc_shaper[i] != NULL) { 1495 dc_transfer_func_release(pool->base.mpc_shaper[i]); 1496 pool->base.mpc_shaper[i] = NULL; 1497 } 1498 } 1499 1500 if (pool->base.dp_clock_source != NULL) { 1501 dcn20_clock_source_destroy(&pool->base.dp_clock_source); 1502 pool->base.dp_clock_source = NULL; 1503 } 1504 1505 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { 1506 if (pool->base.multiple_abms[i] != NULL) 1507 dce_abm_destroy(&pool->base.multiple_abms[i]); 1508 } 1509 1510 if (pool->base.psr != NULL) 1511 dmub_psr_destroy(&pool->base.psr); 1512 1513 if (pool->base.dccg != NULL) 1514 dcn_dccg_destroy(&pool->base.dccg); 1515 } 1516 1517 static struct hubp *dcn31_hubp_create( 1518 struct dc_context *ctx, 1519 uint32_t inst) 1520 { 1521 struct dcn20_hubp *hubp2 = 1522 kzalloc(sizeof(struct dcn20_hubp), GFP_KERNEL); 1523 1524 if (!hubp2) 1525 return NULL; 1526 1527 if (hubp31_construct(hubp2, ctx, inst, 1528 &hubp_regs[inst], &hubp_shift, &hubp_mask)) 1529 return &hubp2->base; 1530 1531 BREAK_TO_DEBUGGER(); 1532 kfree(hubp2); 1533 return NULL; 1534 } 1535 1536 static bool dcn31_dwbc_create(struct dc_context *ctx, struct resource_pool *pool) 1537 { 1538 int i; 1539 uint32_t pipe_count = pool->res_cap->num_dwb; 1540 1541 for (i = 0; i < pipe_count; i++) { 1542 struct dcn30_dwbc *dwbc30 = kzalloc(sizeof(struct dcn30_dwbc), 1543 GFP_KERNEL); 1544 1545 if (!dwbc30) { 1546 dm_error("DC: failed to create dwbc30!\n"); 1547 return false; 1548 } 1549 1550 dcn30_dwbc_construct(dwbc30, ctx, 1551 &dwbc30_regs[i], 1552 &dwbc30_shift, 1553 &dwbc30_mask, 1554 i); 1555 1556 pool->dwbc[i] = &dwbc30->base; 1557 } 1558 return true; 1559 } 1560 1561 static bool dcn31_mmhubbub_create(struct dc_context *ctx, struct resource_pool *pool) 1562 { 1563 int i; 1564 uint32_t pipe_count = pool->res_cap->num_dwb; 1565 1566 for (i = 0; i < pipe_count; i++) { 1567 struct dcn30_mmhubbub *mcif_wb30 = kzalloc(sizeof(struct dcn30_mmhubbub), 1568 GFP_KERNEL); 1569 1570 if (!mcif_wb30) { 1571 dm_error("DC: failed to create mcif_wb30!\n"); 1572 return false; 1573 } 1574 1575 dcn30_mmhubbub_construct(mcif_wb30, ctx, 1576 &mcif_wb30_regs[i], 1577 &mcif_wb30_shift, 1578 &mcif_wb30_mask, 1579 i); 1580 1581 pool->mcif_wb[i] = &mcif_wb30->base; 1582 } 1583 return true; 1584 } 1585 1586 static struct display_stream_compressor *dcn31_dsc_create( 1587 struct dc_context *ctx, uint32_t inst) 1588 { 1589 struct dcn20_dsc *dsc = 1590 kzalloc(sizeof(struct dcn20_dsc), GFP_KERNEL); 1591 1592 if (!dsc) { 1593 BREAK_TO_DEBUGGER(); 1594 return NULL; 1595 } 1596 1597 dsc2_construct(dsc, ctx, inst, &dsc_regs[inst], &dsc_shift, &dsc_mask); 1598 return &dsc->base; 1599 } 1600 1601 static void dcn315_destroy_resource_pool(struct resource_pool **pool) 1602 { 1603 struct dcn315_resource_pool *dcn31_pool = TO_DCN315_RES_POOL(*pool); 1604 1605 dcn315_resource_destruct(dcn31_pool); 1606 kfree(dcn31_pool); 1607 *pool = NULL; 1608 } 1609 1610 static struct clock_source *dcn31_clock_source_create( 1611 struct dc_context *ctx, 1612 struct dc_bios *bios, 1613 enum clock_source_id id, 1614 const struct dce110_clk_src_regs *regs, 1615 bool dp_clk_src) 1616 { 1617 struct dce110_clk_src *clk_src = 1618 kzalloc(sizeof(struct dce110_clk_src), GFP_KERNEL); 1619 1620 if (!clk_src) 1621 return NULL; 1622 1623 if (dcn31_clk_src_construct(clk_src, ctx, bios, id, 1624 regs, &cs_shift, &cs_mask)) { 1625 clk_src->base.dp_clk_src = dp_clk_src; 1626 return &clk_src->base; 1627 } 1628 1629 kfree(clk_src); 1630 BREAK_TO_DEBUGGER(); 1631 return NULL; 1632 } 1633 1634 static bool is_dual_plane(enum surface_pixel_format format) 1635 { 1636 return format >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN || format == SURFACE_PIXEL_FORMAT_GRPH_RGBE_ALPHA; 1637 } 1638 1639 static int dcn315_populate_dml_pipes_from_context( 1640 struct dc *dc, struct dc_state *context, 1641 display_e2e_pipe_params_st *pipes, 1642 bool fast_validate) 1643 { 1644 int i, pipe_cnt; 1645 struct resource_context *res_ctx = &context->res_ctx; 1646 struct pipe_ctx *pipe; 1647 const int max_usable_det = context->bw_ctx.dml.ip.config_return_buffer_size_in_kbytes - DCN3_15_MIN_COMPBUF_SIZE_KB; 1648 1649 DC_FP_START(); 1650 dcn31x_populate_dml_pipes_from_context(dc, context, pipes, fast_validate); 1651 DC_FP_END(); 1652 1653 for (i = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) { 1654 struct dc_crtc_timing *timing; 1655 1656 if (!res_ctx->pipe_ctx[i].stream) 1657 continue; 1658 pipe = &res_ctx->pipe_ctx[i]; 1659 timing = &pipe->stream->timing; 1660 1661 /* 1662 * Immediate flip can be set dynamically after enabling the plane. 1663 * We need to require support for immediate flip or underflow can be 1664 * intermittently experienced depending on peak b/w requirements. 1665 */ 1666 pipes[pipe_cnt].pipe.src.immediate_flip = true; 1667 1668 pipes[pipe_cnt].pipe.src.unbounded_req_mode = false; 1669 pipes[pipe_cnt].pipe.dest.vfront_porch = timing->v_front_porch; 1670 pipes[pipe_cnt].pipe.src.dcc_rate = 3; 1671 pipes[pipe_cnt].dout.dsc_input_bpc = 0; 1672 DC_FP_START(); 1673 dcn31_zero_pipe_dcc_fraction(pipes, pipe_cnt); 1674 DC_FP_END(); 1675 1676 if (pipes[pipe_cnt].dout.dsc_enable) { 1677 switch (timing->display_color_depth) { 1678 case COLOR_DEPTH_888: 1679 pipes[pipe_cnt].dout.dsc_input_bpc = 8; 1680 break; 1681 case COLOR_DEPTH_101010: 1682 pipes[pipe_cnt].dout.dsc_input_bpc = 10; 1683 break; 1684 case COLOR_DEPTH_121212: 1685 pipes[pipe_cnt].dout.dsc_input_bpc = 12; 1686 break; 1687 default: 1688 ASSERT(0); 1689 break; 1690 } 1691 } 1692 1693 pipe_cnt++; 1694 } 1695 1696 if (pipe_cnt) 1697 context->bw_ctx.dml.ip.det_buffer_size_kbytes = 1698 (max_usable_det / DCN3_15_CRB_SEGMENT_SIZE_KB / pipe_cnt) * DCN3_15_CRB_SEGMENT_SIZE_KB; 1699 if (context->bw_ctx.dml.ip.det_buffer_size_kbytes > DCN3_15_MAX_DET_SIZE) 1700 context->bw_ctx.dml.ip.det_buffer_size_kbytes = DCN3_15_MAX_DET_SIZE; 1701 ASSERT(context->bw_ctx.dml.ip.det_buffer_size_kbytes >= DCN3_15_DEFAULT_DET_SIZE); 1702 dc->config.enable_4to1MPC = false; 1703 if (pipe_cnt == 1 && pipe->plane_state && !dc->debug.disable_z9_mpc) { 1704 if (is_dual_plane(pipe->plane_state->format) 1705 && pipe->plane_state->src_rect.width <= 1920 && pipe->plane_state->src_rect.height <= 1080) { 1706 dc->config.enable_4to1MPC = true; 1707 context->bw_ctx.dml.ip.det_buffer_size_kbytes = 1708 (max_usable_det / DCN3_15_CRB_SEGMENT_SIZE_KB / 4) * DCN3_15_CRB_SEGMENT_SIZE_KB; 1709 } else if (!is_dual_plane(pipe->plane_state->format) 1710 && pipe->plane_state->src_rect.width <= 5120 1711 && pipe->stream->timing.pix_clk_100hz < dcn_get_max_non_odm_pix_rate_100hz(&dc->dml.soc)) { 1712 /* Limit to 5k max to avoid forced pipe split when there is not enough detile for swath */ 1713 context->bw_ctx.dml.ip.det_buffer_size_kbytes = 192; 1714 pipes[0].pipe.src.unbounded_req_mode = true; 1715 } 1716 } 1717 1718 return pipe_cnt; 1719 } 1720 1721 static void dcn315_get_panel_config_defaults(struct dc_panel_config *panel_config) 1722 { 1723 *panel_config = panel_config_defaults; 1724 } 1725 1726 static struct dc_cap_funcs cap_funcs = { 1727 .get_dcc_compression_cap = dcn20_get_dcc_compression_cap 1728 }; 1729 1730 static struct resource_funcs dcn315_res_pool_funcs = { 1731 .destroy = dcn315_destroy_resource_pool, 1732 .link_enc_create = dcn31_link_encoder_create, 1733 .link_enc_create_minimal = dcn31_link_enc_create_minimal, 1734 .link_encs_assign = link_enc_cfg_link_encs_assign, 1735 .link_enc_unassign = link_enc_cfg_link_enc_unassign, 1736 .panel_cntl_create = dcn31_panel_cntl_create, 1737 .validate_bandwidth = dcn31_validate_bandwidth, 1738 .calculate_wm_and_dlg = dcn31_calculate_wm_and_dlg, 1739 .update_soc_for_wm_a = dcn315_update_soc_for_wm_a, 1740 .populate_dml_pipes = dcn315_populate_dml_pipes_from_context, 1741 .acquire_idle_pipe_for_layer = dcn20_acquire_idle_pipe_for_layer, 1742 .add_stream_to_ctx = dcn30_add_stream_to_ctx, 1743 .add_dsc_to_stream_resource = dcn20_add_dsc_to_stream_resource, 1744 .remove_stream_from_ctx = dcn20_remove_stream_from_ctx, 1745 .populate_dml_writeback_from_context = dcn31_populate_dml_writeback_from_context, 1746 .set_mcif_arb_params = dcn31_set_mcif_arb_params, 1747 .find_first_free_match_stream_enc_for_link = dcn10_find_first_free_match_stream_enc_for_link, 1748 .acquire_post_bldn_3dlut = dcn30_acquire_post_bldn_3dlut, 1749 .release_post_bldn_3dlut = dcn30_release_post_bldn_3dlut, 1750 .update_bw_bounding_box = dcn315_update_bw_bounding_box, 1751 .patch_unknown_plane_state = dcn20_patch_unknown_plane_state, 1752 .get_panel_config_defaults = dcn315_get_panel_config_defaults, 1753 }; 1754 1755 static bool dcn315_resource_construct( 1756 uint8_t num_virtual_links, 1757 struct dc *dc, 1758 struct dcn315_resource_pool *pool) 1759 { 1760 int i; 1761 struct dc_context *ctx = dc->ctx; 1762 struct irq_service_init_data init_data; 1763 1764 ctx->dc_bios->regs = &bios_regs; 1765 1766 pool->base.res_cap = &res_cap_dcn31; 1767 1768 pool->base.funcs = &dcn315_res_pool_funcs; 1769 1770 /************************************************* 1771 * Resource + asic cap harcoding * 1772 *************************************************/ 1773 pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE; 1774 pool->base.pipe_count = pool->base.res_cap->num_timing_generator; 1775 pool->base.mpcc_count = pool->base.res_cap->num_timing_generator; 1776 dc->caps.max_downscale_ratio = 600; 1777 dc->caps.i2c_speed_in_khz = 100; 1778 dc->caps.i2c_speed_in_khz_hdcp = 100; 1779 dc->caps.max_cursor_size = 256; 1780 dc->caps.min_horizontal_blanking_period = 80; 1781 dc->caps.dmdata_alloc_size = 2048; 1782 dc->caps.max_slave_planes = 2; 1783 dc->caps.max_slave_yuv_planes = 2; 1784 dc->caps.max_slave_rgb_planes = 2; 1785 dc->caps.post_blend_color_processing = true; 1786 dc->caps.force_dp_tps4_for_cp2520 = true; 1787 if (dc->config.forceHBR2CP2520) 1788 dc->caps.force_dp_tps4_for_cp2520 = false; 1789 dc->caps.dp_hpo = true; 1790 dc->caps.dp_hdmi21_pcon_support = true; 1791 dc->caps.edp_dsc_support = true; 1792 dc->caps.extended_aux_timeout_support = true; 1793 dc->caps.dmcub_support = true; 1794 dc->caps.is_apu = true; 1795 1796 /* Color pipeline capabilities */ 1797 dc->caps.color.dpp.dcn_arch = 1; 1798 dc->caps.color.dpp.input_lut_shared = 0; 1799 dc->caps.color.dpp.icsc = 1; 1800 dc->caps.color.dpp.dgam_ram = 0; // must use gamma_corr 1801 dc->caps.color.dpp.dgam_rom_caps.srgb = 1; 1802 dc->caps.color.dpp.dgam_rom_caps.bt2020 = 1; 1803 dc->caps.color.dpp.dgam_rom_caps.gamma2_2 = 1; 1804 dc->caps.color.dpp.dgam_rom_caps.pq = 1; 1805 dc->caps.color.dpp.dgam_rom_caps.hlg = 1; 1806 dc->caps.color.dpp.post_csc = 1; 1807 dc->caps.color.dpp.gamma_corr = 1; 1808 dc->caps.color.dpp.dgam_rom_for_yuv = 0; 1809 1810 dc->caps.color.dpp.hw_3d_lut = 1; 1811 dc->caps.color.dpp.ogam_ram = 1; 1812 // no OGAM ROM on DCN301 1813 dc->caps.color.dpp.ogam_rom_caps.srgb = 0; 1814 dc->caps.color.dpp.ogam_rom_caps.bt2020 = 0; 1815 dc->caps.color.dpp.ogam_rom_caps.gamma2_2 = 0; 1816 dc->caps.color.dpp.ogam_rom_caps.pq = 0; 1817 dc->caps.color.dpp.ogam_rom_caps.hlg = 0; 1818 dc->caps.color.dpp.ocsc = 0; 1819 1820 dc->caps.color.mpc.gamut_remap = 1; 1821 dc->caps.color.mpc.num_3dluts = pool->base.res_cap->num_mpc_3dlut; //2 1822 dc->caps.color.mpc.ogam_ram = 1; 1823 dc->caps.color.mpc.ogam_rom_caps.srgb = 0; 1824 dc->caps.color.mpc.ogam_rom_caps.bt2020 = 0; 1825 dc->caps.color.mpc.ogam_rom_caps.gamma2_2 = 0; 1826 dc->caps.color.mpc.ogam_rom_caps.pq = 0; 1827 dc->caps.color.mpc.ogam_rom_caps.hlg = 0; 1828 dc->caps.color.mpc.ocsc = 1; 1829 1830 /* read VBIOS LTTPR caps */ 1831 { 1832 if (ctx->dc_bios->funcs->get_lttpr_caps) { 1833 enum bp_result bp_query_result; 1834 uint8_t is_vbios_lttpr_enable = 0; 1835 1836 bp_query_result = ctx->dc_bios->funcs->get_lttpr_caps(ctx->dc_bios, &is_vbios_lttpr_enable); 1837 dc->caps.vbios_lttpr_enable = (bp_query_result == BP_RESULT_OK) && !!is_vbios_lttpr_enable; 1838 } 1839 1840 /* interop bit is implicit */ 1841 { 1842 dc->caps.vbios_lttpr_aware = true; 1843 } 1844 } 1845 1846 if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV) 1847 dc->debug = debug_defaults_drv; 1848 else if (dc->ctx->dce_environment == DCE_ENV_FPGA_MAXIMUS) { 1849 dc->debug = debug_defaults_diags; 1850 } else 1851 dc->debug = debug_defaults_diags; 1852 // Init the vm_helper 1853 if (dc->vm_helper) 1854 vm_helper_init(dc->vm_helper, 16); 1855 1856 /************************************************* 1857 * Create resources * 1858 *************************************************/ 1859 1860 /* Clock Sources for Pixel Clock*/ 1861 pool->base.clock_sources[DCN31_CLK_SRC_PLL0] = 1862 dcn31_clock_source_create(ctx, ctx->dc_bios, 1863 CLOCK_SOURCE_COMBO_PHY_PLL0, 1864 &clk_src_regs[0], false); 1865 pool->base.clock_sources[DCN31_CLK_SRC_PLL1] = 1866 dcn31_clock_source_create(ctx, ctx->dc_bios, 1867 CLOCK_SOURCE_COMBO_PHY_PLL1, 1868 &clk_src_regs[1], false); 1869 pool->base.clock_sources[DCN31_CLK_SRC_PLL2] = 1870 dcn31_clock_source_create(ctx, ctx->dc_bios, 1871 CLOCK_SOURCE_COMBO_PHY_PLL2, 1872 &clk_src_regs[2], false); 1873 pool->base.clock_sources[DCN31_CLK_SRC_PLL3] = 1874 dcn31_clock_source_create(ctx, ctx->dc_bios, 1875 CLOCK_SOURCE_COMBO_PHY_PLL3, 1876 &clk_src_regs[3], false); 1877 pool->base.clock_sources[DCN31_CLK_SRC_PLL4] = 1878 dcn31_clock_source_create(ctx, ctx->dc_bios, 1879 CLOCK_SOURCE_COMBO_PHY_PLL4, 1880 &clk_src_regs[4], false); 1881 1882 pool->base.clk_src_count = DCN30_CLK_SRC_TOTAL; 1883 1884 /* todo: not reuse phy_pll registers */ 1885 pool->base.dp_clock_source = 1886 dcn31_clock_source_create(ctx, ctx->dc_bios, 1887 CLOCK_SOURCE_ID_DP_DTO, 1888 &clk_src_regs[0], true); 1889 1890 for (i = 0; i < pool->base.clk_src_count; i++) { 1891 if (pool->base.clock_sources[i] == NULL) { 1892 dm_error("DC: failed to create clock sources!\n"); 1893 BREAK_TO_DEBUGGER(); 1894 goto create_fail; 1895 } 1896 } 1897 1898 /* TODO: DCCG */ 1899 pool->base.dccg = dccg31_create(ctx, &dccg_regs, &dccg_shift, &dccg_mask); 1900 if (pool->base.dccg == NULL) { 1901 dm_error("DC: failed to create dccg!\n"); 1902 BREAK_TO_DEBUGGER(); 1903 goto create_fail; 1904 } 1905 1906 /* TODO: IRQ */ 1907 init_data.ctx = dc->ctx; 1908 pool->base.irqs = dal_irq_service_dcn315_create(&init_data); 1909 if (!pool->base.irqs) 1910 goto create_fail; 1911 1912 /* HUBBUB */ 1913 pool->base.hubbub = dcn31_hubbub_create(ctx); 1914 if (pool->base.hubbub == NULL) { 1915 BREAK_TO_DEBUGGER(); 1916 dm_error("DC: failed to create hubbub!\n"); 1917 goto create_fail; 1918 } 1919 1920 /* HUBPs, DPPs, OPPs and TGs */ 1921 for (i = 0; i < pool->base.pipe_count; i++) { 1922 pool->base.hubps[i] = dcn31_hubp_create(ctx, i); 1923 if (pool->base.hubps[i] == NULL) { 1924 BREAK_TO_DEBUGGER(); 1925 dm_error( 1926 "DC: failed to create hubps!\n"); 1927 goto create_fail; 1928 } 1929 1930 pool->base.dpps[i] = dcn31_dpp_create(ctx, i); 1931 if (pool->base.dpps[i] == NULL) { 1932 BREAK_TO_DEBUGGER(); 1933 dm_error( 1934 "DC: failed to create dpps!\n"); 1935 goto create_fail; 1936 } 1937 } 1938 1939 for (i = 0; i < pool->base.res_cap->num_opp; i++) { 1940 pool->base.opps[i] = dcn31_opp_create(ctx, i); 1941 if (pool->base.opps[i] == NULL) { 1942 BREAK_TO_DEBUGGER(); 1943 dm_error( 1944 "DC: failed to create output pixel processor!\n"); 1945 goto create_fail; 1946 } 1947 } 1948 1949 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { 1950 pool->base.timing_generators[i] = dcn31_timing_generator_create( 1951 ctx, i); 1952 if (pool->base.timing_generators[i] == NULL) { 1953 BREAK_TO_DEBUGGER(); 1954 dm_error("DC: failed to create tg!\n"); 1955 goto create_fail; 1956 } 1957 } 1958 pool->base.timing_generator_count = i; 1959 1960 /* PSR */ 1961 pool->base.psr = dmub_psr_create(ctx); 1962 if (pool->base.psr == NULL) { 1963 dm_error("DC: failed to create psr obj!\n"); 1964 BREAK_TO_DEBUGGER(); 1965 goto create_fail; 1966 } 1967 1968 /* ABM */ 1969 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { 1970 pool->base.multiple_abms[i] = dmub_abm_create(ctx, 1971 &abm_regs[i], 1972 &abm_shift, 1973 &abm_mask); 1974 if (pool->base.multiple_abms[i] == NULL) { 1975 dm_error("DC: failed to create abm for pipe %d!\n", i); 1976 BREAK_TO_DEBUGGER(); 1977 goto create_fail; 1978 } 1979 } 1980 1981 /* MPC and DSC */ 1982 pool->base.mpc = dcn31_mpc_create(ctx, pool->base.mpcc_count, pool->base.res_cap->num_mpc_3dlut); 1983 if (pool->base.mpc == NULL) { 1984 BREAK_TO_DEBUGGER(); 1985 dm_error("DC: failed to create mpc!\n"); 1986 goto create_fail; 1987 } 1988 1989 for (i = 0; i < pool->base.res_cap->num_dsc; i++) { 1990 pool->base.dscs[i] = dcn31_dsc_create(ctx, i); 1991 if (pool->base.dscs[i] == NULL) { 1992 BREAK_TO_DEBUGGER(); 1993 dm_error("DC: failed to create display stream compressor %d!\n", i); 1994 goto create_fail; 1995 } 1996 } 1997 1998 /* DWB and MMHUBBUB */ 1999 if (!dcn31_dwbc_create(ctx, &pool->base)) { 2000 BREAK_TO_DEBUGGER(); 2001 dm_error("DC: failed to create dwbc!\n"); 2002 goto create_fail; 2003 } 2004 2005 if (!dcn31_mmhubbub_create(ctx, &pool->base)) { 2006 BREAK_TO_DEBUGGER(); 2007 dm_error("DC: failed to create mcif_wb!\n"); 2008 goto create_fail; 2009 } 2010 2011 /* AUX and I2C */ 2012 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { 2013 pool->base.engines[i] = dcn31_aux_engine_create(ctx, i); 2014 if (pool->base.engines[i] == NULL) { 2015 BREAK_TO_DEBUGGER(); 2016 dm_error( 2017 "DC:failed to create aux engine!!\n"); 2018 goto create_fail; 2019 } 2020 pool->base.hw_i2cs[i] = dcn31_i2c_hw_create(ctx, i); 2021 if (pool->base.hw_i2cs[i] == NULL) { 2022 BREAK_TO_DEBUGGER(); 2023 dm_error( 2024 "DC:failed to create hw i2c!!\n"); 2025 goto create_fail; 2026 } 2027 pool->base.sw_i2cs[i] = NULL; 2028 } 2029 2030 /* Audio, Stream Encoders including HPO and virtual, MPC 3D LUTs */ 2031 if (!resource_construct(num_virtual_links, dc, &pool->base, 2032 (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment) ? 2033 &res_create_funcs : &res_create_maximus_funcs))) 2034 goto create_fail; 2035 2036 /* HW Sequencer and Plane caps */ 2037 dcn31_hw_sequencer_construct(dc); 2038 2039 dc->caps.max_planes = pool->base.pipe_count; 2040 2041 for (i = 0; i < dc->caps.max_planes; ++i) 2042 dc->caps.planes[i] = plane_cap; 2043 2044 dc->cap_funcs = cap_funcs; 2045 2046 dc->dcn_ip->max_num_dpp = dcn3_15_ip.max_num_dpp; 2047 2048 return true; 2049 2050 create_fail: 2051 2052 dcn315_resource_destruct(pool); 2053 2054 return false; 2055 } 2056 2057 struct resource_pool *dcn315_create_resource_pool( 2058 const struct dc_init_data *init_data, 2059 struct dc *dc) 2060 { 2061 struct dcn315_resource_pool *pool = 2062 kzalloc(sizeof(struct dcn315_resource_pool), GFP_KERNEL); 2063 2064 if (!pool) 2065 return NULL; 2066 2067 if (dcn315_resource_construct(init_data->num_virtual_links, dc, pool)) 2068 return &pool->base; 2069 2070 BREAK_TO_DEBUGGER(); 2071 kfree(pool); 2072 return NULL; 2073 } 2074