1 /* 2 * Copyright 2021 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 27 #include "dm_services.h" 28 #include "dc.h" 29 30 #include "dcn31/dcn31_init.h" 31 32 #include "resource.h" 33 #include "include/irq_service_interface.h" 34 #include "dcn315_resource.h" 35 36 #include "dcn20/dcn20_resource.h" 37 #include "dcn30/dcn30_resource.h" 38 #include "dcn31/dcn31_resource.h" 39 40 #include "dcn10/dcn10_ipp.h" 41 #include "dcn30/dcn30_hubbub.h" 42 #include "dcn31/dcn31_hubbub.h" 43 #include "dcn30/dcn30_mpc.h" 44 #include "dcn31/dcn31_hubp.h" 45 #include "irq/dcn315/irq_service_dcn315.h" 46 #include "dcn30/dcn30_dpp.h" 47 #include "dcn31/dcn31_optc.h" 48 #include "dcn20/dcn20_hwseq.h" 49 #include "dcn30/dcn30_hwseq.h" 50 #include "dce110/dce110_hw_sequencer.h" 51 #include "dcn30/dcn30_opp.h" 52 #include "dcn20/dcn20_dsc.h" 53 #include "dcn30/dcn30_vpg.h" 54 #include "dcn30/dcn30_afmt.h" 55 #include "dcn30/dcn30_dio_stream_encoder.h" 56 #include "dcn31/dcn31_hpo_dp_stream_encoder.h" 57 #include "dcn31/dcn31_hpo_dp_link_encoder.h" 58 #include "dcn31/dcn31_apg.h" 59 #include "dcn31/dcn31_dio_link_encoder.h" 60 #include "dcn31/dcn31_vpg.h" 61 #include "dcn31/dcn31_afmt.h" 62 #include "dce/dce_clock_source.h" 63 #include "dce/dce_audio.h" 64 #include "dce/dce_hwseq.h" 65 #include "clk_mgr.h" 66 #include "virtual/virtual_stream_encoder.h" 67 #include "dce110/dce110_resource.h" 68 #include "dml/display_mode_vba.h" 69 #include "dml/dcn31/dcn31_fpu.h" 70 #include "dcn31/dcn31_dccg.h" 71 #include "dcn10/dcn10_resource.h" 72 #include "dcn31/dcn31_panel_cntl.h" 73 74 #include "dcn30/dcn30_dwb.h" 75 #include "dcn30/dcn30_mmhubbub.h" 76 77 #include "dcn/dcn_3_1_5_offset.h" 78 #include "dcn/dcn_3_1_5_sh_mask.h" 79 #include "dpcs/dpcs_4_2_2_offset.h" 80 #include "dpcs/dpcs_4_2_2_sh_mask.h" 81 82 #define NBIO_BASE__INST0_SEG0 0x00000000 83 #define NBIO_BASE__INST0_SEG1 0x00000014 84 #define NBIO_BASE__INST0_SEG2 0x00000D20 85 #define NBIO_BASE__INST0_SEG3 0x00010400 86 #define NBIO_BASE__INST0_SEG4 0x0241B000 87 #define NBIO_BASE__INST0_SEG5 0x04040000 88 89 #define DPCS_BASE__INST0_SEG0 0x00000012 90 #define DPCS_BASE__INST0_SEG1 0x000000C0 91 #define DPCS_BASE__INST0_SEG2 0x000034C0 92 #define DPCS_BASE__INST0_SEG3 0x00009000 93 #define DPCS_BASE__INST0_SEG4 0x02403C00 94 #define DPCS_BASE__INST0_SEG5 0 95 96 #define DCN_BASE__INST0_SEG0 0x00000012 97 #define DCN_BASE__INST0_SEG1 0x000000C0 98 #define DCN_BASE__INST0_SEG2 0x000034C0 99 #define DCN_BASE__INST0_SEG3 0x00009000 100 #define DCN_BASE__INST0_SEG4 0x02403C00 101 #define DCN_BASE__INST0_SEG5 0 102 103 #define regBIF_BX_PF2_RSMU_INDEX 0x0000 104 #define regBIF_BX_PF2_RSMU_INDEX_BASE_IDX 1 105 #define regBIF_BX_PF2_RSMU_DATA 0x0001 106 #define regBIF_BX_PF2_RSMU_DATA_BASE_IDX 1 107 #define regBIF_BX2_BIOS_SCRATCH_6 0x003e 108 #define regBIF_BX2_BIOS_SCRATCH_6_BASE_IDX 1 109 #define BIF_BX2_BIOS_SCRATCH_6__BIOS_SCRATCH_6__SHIFT 0x0 110 #define BIF_BX2_BIOS_SCRATCH_6__BIOS_SCRATCH_6_MASK 0xFFFFFFFFL 111 #define regBIF_BX2_BIOS_SCRATCH_2 0x003a 112 #define regBIF_BX2_BIOS_SCRATCH_2_BASE_IDX 1 113 #define BIF_BX2_BIOS_SCRATCH_2__BIOS_SCRATCH_2__SHIFT 0x0 114 #define BIF_BX2_BIOS_SCRATCH_2__BIOS_SCRATCH_2_MASK 0xFFFFFFFFL 115 #define regBIF_BX2_BIOS_SCRATCH_3 0x003b 116 #define regBIF_BX2_BIOS_SCRATCH_3_BASE_IDX 1 117 #define BIF_BX2_BIOS_SCRATCH_3__BIOS_SCRATCH_3__SHIFT 0x0 118 #define BIF_BX2_BIOS_SCRATCH_3__BIOS_SCRATCH_3_MASK 0xFFFFFFFFL 119 120 #define regDCHUBBUB_DEBUG_CTRL_0 0x04d6 121 #define regDCHUBBUB_DEBUG_CTRL_0_BASE_IDX 2 122 #define DCHUBBUB_DEBUG_CTRL_0__DET_DEPTH__SHIFT 0x10 123 #define DCHUBBUB_DEBUG_CTRL_0__DET_DEPTH_MASK 0x01FF0000L 124 125 #include "reg_helper.h" 126 #include "dce/dmub_abm.h" 127 #include "dce/dmub_psr.h" 128 #include "dce/dce_aux.h" 129 #include "dce/dce_i2c.h" 130 131 #include "dml/dcn30/display_mode_vba_30.h" 132 #include "vm_helper.h" 133 #include "dcn20/dcn20_vmid.h" 134 135 #include "link_enc_cfg.h" 136 137 #define DCN3_15_MAX_DET_SIZE 384 138 #define DCN3_15_CRB_SEGMENT_SIZE_KB 64 139 140 enum dcn31_clk_src_array_id { 141 DCN31_CLK_SRC_PLL0, 142 DCN31_CLK_SRC_PLL1, 143 DCN31_CLK_SRC_PLL2, 144 DCN31_CLK_SRC_PLL3, 145 DCN31_CLK_SRC_PLL4, 146 DCN30_CLK_SRC_TOTAL 147 }; 148 149 /* begin ********************* 150 * macros to expend register list macro defined in HW object header file 151 */ 152 153 /* DCN */ 154 #define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg 155 156 #define BASE(seg) BASE_INNER(seg) 157 158 #define SR(reg_name)\ 159 .reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \ 160 reg ## reg_name 161 162 #define SRI(reg_name, block, id)\ 163 .reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 164 reg ## block ## id ## _ ## reg_name 165 166 #define SRI2(reg_name, block, id)\ 167 .reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \ 168 reg ## reg_name 169 170 #define SRIR(var_name, reg_name, block, id)\ 171 .var_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 172 reg ## block ## id ## _ ## reg_name 173 174 #define SRII(reg_name, block, id)\ 175 .reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 176 reg ## block ## id ## _ ## reg_name 177 178 #define SRII_MPC_RMU(reg_name, block, id)\ 179 .RMU##_##reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 180 reg ## block ## id ## _ ## reg_name 181 182 #define SRII_DWB(reg_name, temp_name, block, id)\ 183 .reg_name[id] = BASE(reg ## block ## id ## _ ## temp_name ## _BASE_IDX) + \ 184 reg ## block ## id ## _ ## temp_name 185 186 #define SF_DWB2(reg_name, block, id, field_name, post_fix) \ 187 .field_name = reg_name ## __ ## field_name ## post_fix 188 189 #define DCCG_SRII(reg_name, block, id)\ 190 .block ## _ ## reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 191 reg ## block ## id ## _ ## reg_name 192 193 #define VUPDATE_SRII(reg_name, block, id)\ 194 .reg_name[id] = BASE(reg ## reg_name ## _ ## block ## id ## _BASE_IDX) + \ 195 reg ## reg_name ## _ ## block ## id 196 197 /* NBIO */ 198 #define NBIO_BASE_INNER(seg) \ 199 NBIO_BASE__INST0_SEG ## seg 200 201 #define NBIO_BASE(seg) \ 202 NBIO_BASE_INNER(seg) 203 204 #define NBIO_SR(reg_name)\ 205 .reg_name = NBIO_BASE(regBIF_BX2_ ## reg_name ## _BASE_IDX) + \ 206 regBIF_BX2_ ## reg_name 207 208 static const struct bios_registers bios_regs = { 209 NBIO_SR(BIOS_SCRATCH_3), 210 NBIO_SR(BIOS_SCRATCH_6) 211 }; 212 213 #define clk_src_regs(index, pllid)\ 214 [index] = {\ 215 CS_COMMON_REG_LIST_DCN3_0(index, pllid),\ 216 } 217 218 static const struct dce110_clk_src_regs clk_src_regs[] = { 219 clk_src_regs(0, A), 220 clk_src_regs(1, B), 221 clk_src_regs(2, C), 222 clk_src_regs(3, D), 223 clk_src_regs(4, E) 224 }; 225 226 static const struct dce110_clk_src_shift cs_shift = { 227 CS_COMMON_MASK_SH_LIST_DCN2_0(__SHIFT) 228 }; 229 230 static const struct dce110_clk_src_mask cs_mask = { 231 CS_COMMON_MASK_SH_LIST_DCN2_0(_MASK) 232 }; 233 234 #define abm_regs(id)\ 235 [id] = {\ 236 ABM_DCN302_REG_LIST(id)\ 237 } 238 239 static const struct dce_abm_registers abm_regs[] = { 240 abm_regs(0), 241 abm_regs(1), 242 abm_regs(2), 243 abm_regs(3), 244 }; 245 246 static const struct dce_abm_shift abm_shift = { 247 ABM_MASK_SH_LIST_DCN30(__SHIFT) 248 }; 249 250 static const struct dce_abm_mask abm_mask = { 251 ABM_MASK_SH_LIST_DCN30(_MASK) 252 }; 253 254 #define audio_regs(id)\ 255 [id] = {\ 256 AUD_COMMON_REG_LIST(id)\ 257 } 258 259 static const struct dce_audio_registers audio_regs[] = { 260 audio_regs(0), 261 audio_regs(1), 262 audio_regs(2), 263 audio_regs(3), 264 audio_regs(4), 265 audio_regs(5), 266 audio_regs(6) 267 }; 268 269 #define DCE120_AUD_COMMON_MASK_SH_LIST(mask_sh)\ 270 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX, AZALIA_ENDPOINT_REG_INDEX, mask_sh),\ 271 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA, AZALIA_ENDPOINT_REG_DATA, mask_sh),\ 272 AUD_COMMON_MASK_SH_LIST_BASE(mask_sh) 273 274 static const struct dce_audio_shift audio_shift = { 275 DCE120_AUD_COMMON_MASK_SH_LIST(__SHIFT) 276 }; 277 278 static const struct dce_audio_mask audio_mask = { 279 DCE120_AUD_COMMON_MASK_SH_LIST(_MASK) 280 }; 281 282 #define vpg_regs(id)\ 283 [id] = {\ 284 VPG_DCN31_REG_LIST(id)\ 285 } 286 287 static const struct dcn31_vpg_registers vpg_regs[] = { 288 vpg_regs(0), 289 vpg_regs(1), 290 vpg_regs(2), 291 vpg_regs(3), 292 vpg_regs(4), 293 vpg_regs(5), 294 vpg_regs(6), 295 vpg_regs(7), 296 vpg_regs(8), 297 vpg_regs(9), 298 }; 299 300 static const struct dcn31_vpg_shift vpg_shift = { 301 DCN31_VPG_MASK_SH_LIST(__SHIFT) 302 }; 303 304 static const struct dcn31_vpg_mask vpg_mask = { 305 DCN31_VPG_MASK_SH_LIST(_MASK) 306 }; 307 308 #define afmt_regs(id)\ 309 [id] = {\ 310 AFMT_DCN31_REG_LIST(id)\ 311 } 312 313 static const struct dcn31_afmt_registers afmt_regs[] = { 314 afmt_regs(0), 315 afmt_regs(1), 316 afmt_regs(2), 317 afmt_regs(3), 318 afmt_regs(4), 319 afmt_regs(5) 320 }; 321 322 static const struct dcn31_afmt_shift afmt_shift = { 323 DCN31_AFMT_MASK_SH_LIST(__SHIFT) 324 }; 325 326 static const struct dcn31_afmt_mask afmt_mask = { 327 DCN31_AFMT_MASK_SH_LIST(_MASK) 328 }; 329 330 #define apg_regs(id)\ 331 [id] = {\ 332 APG_DCN31_REG_LIST(id)\ 333 } 334 335 static const struct dcn31_apg_registers apg_regs[] = { 336 apg_regs(0), 337 apg_regs(1), 338 apg_regs(2), 339 apg_regs(3) 340 }; 341 342 static const struct dcn31_apg_shift apg_shift = { 343 DCN31_APG_MASK_SH_LIST(__SHIFT) 344 }; 345 346 static const struct dcn31_apg_mask apg_mask = { 347 DCN31_APG_MASK_SH_LIST(_MASK) 348 }; 349 350 #define stream_enc_regs(id)\ 351 [id] = {\ 352 SE_DCN3_REG_LIST(id)\ 353 } 354 355 static const struct dcn10_stream_enc_registers stream_enc_regs[] = { 356 stream_enc_regs(0), 357 stream_enc_regs(1), 358 stream_enc_regs(2), 359 stream_enc_regs(3), 360 stream_enc_regs(4) 361 }; 362 363 static const struct dcn10_stream_encoder_shift se_shift = { 364 SE_COMMON_MASK_SH_LIST_DCN30(__SHIFT) 365 }; 366 367 static const struct dcn10_stream_encoder_mask se_mask = { 368 SE_COMMON_MASK_SH_LIST_DCN30(_MASK) 369 }; 370 371 372 #define aux_regs(id)\ 373 [id] = {\ 374 DCN2_AUX_REG_LIST(id)\ 375 } 376 377 static const struct dcn10_link_enc_aux_registers link_enc_aux_regs[] = { 378 aux_regs(0), 379 aux_regs(1), 380 aux_regs(2), 381 aux_regs(3), 382 aux_regs(4) 383 }; 384 385 #define hpd_regs(id)\ 386 [id] = {\ 387 HPD_REG_LIST(id)\ 388 } 389 390 static const struct dcn10_link_enc_hpd_registers link_enc_hpd_regs[] = { 391 hpd_regs(0), 392 hpd_regs(1), 393 hpd_regs(2), 394 hpd_regs(3), 395 hpd_regs(4) 396 }; 397 398 #define link_regs(id, phyid)\ 399 [id] = {\ 400 LE_DCN31_REG_LIST(id), \ 401 UNIPHY_DCN2_REG_LIST(phyid), \ 402 DPCS_DCN31_REG_LIST(id), \ 403 } 404 405 static const struct dce110_aux_registers_shift aux_shift = { 406 DCN_AUX_MASK_SH_LIST(__SHIFT) 407 }; 408 409 static const struct dce110_aux_registers_mask aux_mask = { 410 DCN_AUX_MASK_SH_LIST(_MASK) 411 }; 412 413 static const struct dcn10_link_enc_registers link_enc_regs[] = { 414 link_regs(0, A), 415 link_regs(1, B), 416 link_regs(2, C), 417 link_regs(3, D), 418 link_regs(4, E) 419 }; 420 421 static const struct dcn10_link_enc_shift le_shift = { 422 LINK_ENCODER_MASK_SH_LIST_DCN31(__SHIFT), \ 423 DPCS_DCN31_MASK_SH_LIST(__SHIFT) 424 }; 425 426 static const struct dcn10_link_enc_mask le_mask = { 427 LINK_ENCODER_MASK_SH_LIST_DCN31(_MASK), \ 428 DPCS_DCN31_MASK_SH_LIST(_MASK) 429 }; 430 431 #define hpo_dp_stream_encoder_reg_list(id)\ 432 [id] = {\ 433 DCN3_1_HPO_DP_STREAM_ENC_REG_LIST(id)\ 434 } 435 436 static const struct dcn31_hpo_dp_stream_encoder_registers hpo_dp_stream_enc_regs[] = { 437 hpo_dp_stream_encoder_reg_list(0), 438 hpo_dp_stream_encoder_reg_list(1), 439 hpo_dp_stream_encoder_reg_list(2), 440 hpo_dp_stream_encoder_reg_list(3), 441 }; 442 443 static const struct dcn31_hpo_dp_stream_encoder_shift hpo_dp_se_shift = { 444 DCN3_1_HPO_DP_STREAM_ENC_MASK_SH_LIST(__SHIFT) 445 }; 446 447 static const struct dcn31_hpo_dp_stream_encoder_mask hpo_dp_se_mask = { 448 DCN3_1_HPO_DP_STREAM_ENC_MASK_SH_LIST(_MASK) 449 }; 450 451 452 #define hpo_dp_link_encoder_reg_list(id)\ 453 [id] = {\ 454 DCN3_1_HPO_DP_LINK_ENC_REG_LIST(id),\ 455 DCN3_1_RDPCSTX_REG_LIST(0),\ 456 DCN3_1_RDPCSTX_REG_LIST(1),\ 457 DCN3_1_RDPCSTX_REG_LIST(2),\ 458 DCN3_1_RDPCSTX_REG_LIST(3),\ 459 DCN3_1_RDPCSTX_REG_LIST(4)\ 460 } 461 462 static const struct dcn31_hpo_dp_link_encoder_registers hpo_dp_link_enc_regs[] = { 463 hpo_dp_link_encoder_reg_list(0), 464 hpo_dp_link_encoder_reg_list(1), 465 }; 466 467 static const struct dcn31_hpo_dp_link_encoder_shift hpo_dp_le_shift = { 468 DCN3_1_HPO_DP_LINK_ENC_MASK_SH_LIST(__SHIFT) 469 }; 470 471 static const struct dcn31_hpo_dp_link_encoder_mask hpo_dp_le_mask = { 472 DCN3_1_HPO_DP_LINK_ENC_MASK_SH_LIST(_MASK) 473 }; 474 475 #define dpp_regs(id)\ 476 [id] = {\ 477 DPP_REG_LIST_DCN30(id),\ 478 } 479 480 static const struct dcn3_dpp_registers dpp_regs[] = { 481 dpp_regs(0), 482 dpp_regs(1), 483 dpp_regs(2), 484 dpp_regs(3) 485 }; 486 487 static const struct dcn3_dpp_shift tf_shift = { 488 DPP_REG_LIST_SH_MASK_DCN30(__SHIFT) 489 }; 490 491 static const struct dcn3_dpp_mask tf_mask = { 492 DPP_REG_LIST_SH_MASK_DCN30(_MASK) 493 }; 494 495 #define opp_regs(id)\ 496 [id] = {\ 497 OPP_REG_LIST_DCN30(id),\ 498 } 499 500 static const struct dcn20_opp_registers opp_regs[] = { 501 opp_regs(0), 502 opp_regs(1), 503 opp_regs(2), 504 opp_regs(3) 505 }; 506 507 static const struct dcn20_opp_shift opp_shift = { 508 OPP_MASK_SH_LIST_DCN20(__SHIFT) 509 }; 510 511 static const struct dcn20_opp_mask opp_mask = { 512 OPP_MASK_SH_LIST_DCN20(_MASK) 513 }; 514 515 #define aux_engine_regs(id)\ 516 [id] = {\ 517 AUX_COMMON_REG_LIST0(id), \ 518 .AUXN_IMPCAL = 0, \ 519 .AUXP_IMPCAL = 0, \ 520 .AUX_RESET_MASK = DP_AUX0_AUX_CONTROL__AUX_RESET_MASK, \ 521 } 522 523 static const struct dce110_aux_registers aux_engine_regs[] = { 524 aux_engine_regs(0), 525 aux_engine_regs(1), 526 aux_engine_regs(2), 527 aux_engine_regs(3), 528 aux_engine_regs(4) 529 }; 530 531 #define dwbc_regs_dcn3(id)\ 532 [id] = {\ 533 DWBC_COMMON_REG_LIST_DCN30(id),\ 534 } 535 536 static const struct dcn30_dwbc_registers dwbc30_regs[] = { 537 dwbc_regs_dcn3(0), 538 }; 539 540 static const struct dcn30_dwbc_shift dwbc30_shift = { 541 DWBC_COMMON_MASK_SH_LIST_DCN30(__SHIFT) 542 }; 543 544 static const struct dcn30_dwbc_mask dwbc30_mask = { 545 DWBC_COMMON_MASK_SH_LIST_DCN30(_MASK) 546 }; 547 548 #define mcif_wb_regs_dcn3(id)\ 549 [id] = {\ 550 MCIF_WB_COMMON_REG_LIST_DCN30(id),\ 551 } 552 553 static const struct dcn30_mmhubbub_registers mcif_wb30_regs[] = { 554 mcif_wb_regs_dcn3(0) 555 }; 556 557 static const struct dcn30_mmhubbub_shift mcif_wb30_shift = { 558 MCIF_WB_COMMON_MASK_SH_LIST_DCN30(__SHIFT) 559 }; 560 561 static const struct dcn30_mmhubbub_mask mcif_wb30_mask = { 562 MCIF_WB_COMMON_MASK_SH_LIST_DCN30(_MASK) 563 }; 564 565 #define dsc_regsDCN20(id)\ 566 [id] = {\ 567 DSC_REG_LIST_DCN20(id)\ 568 } 569 570 static const struct dcn20_dsc_registers dsc_regs[] = { 571 dsc_regsDCN20(0), 572 dsc_regsDCN20(1), 573 dsc_regsDCN20(2) 574 }; 575 576 static const struct dcn20_dsc_shift dsc_shift = { 577 DSC_REG_LIST_SH_MASK_DCN20(__SHIFT) 578 }; 579 580 static const struct dcn20_dsc_mask dsc_mask = { 581 DSC_REG_LIST_SH_MASK_DCN20(_MASK) 582 }; 583 584 static const struct dcn30_mpc_registers mpc_regs = { 585 MPC_REG_LIST_DCN3_0(0), 586 MPC_REG_LIST_DCN3_0(1), 587 MPC_REG_LIST_DCN3_0(2), 588 MPC_REG_LIST_DCN3_0(3), 589 MPC_OUT_MUX_REG_LIST_DCN3_0(0), 590 MPC_OUT_MUX_REG_LIST_DCN3_0(1), 591 MPC_OUT_MUX_REG_LIST_DCN3_0(2), 592 MPC_OUT_MUX_REG_LIST_DCN3_0(3), 593 MPC_DWB_MUX_REG_LIST_DCN3_0(0), 594 }; 595 596 static const struct dcn30_mpc_shift mpc_shift = { 597 MPC_COMMON_MASK_SH_LIST_DCN30(__SHIFT) 598 }; 599 600 static const struct dcn30_mpc_mask mpc_mask = { 601 MPC_COMMON_MASK_SH_LIST_DCN30(_MASK) 602 }; 603 604 #define optc_regs(id)\ 605 [id] = {OPTC_COMMON_REG_LIST_DCN3_1(id)} 606 607 static const struct dcn_optc_registers optc_regs[] = { 608 optc_regs(0), 609 optc_regs(1), 610 optc_regs(2), 611 optc_regs(3) 612 }; 613 614 static const struct dcn_optc_shift optc_shift = { 615 OPTC_COMMON_MASK_SH_LIST_DCN3_1(__SHIFT) 616 }; 617 618 static const struct dcn_optc_mask optc_mask = { 619 OPTC_COMMON_MASK_SH_LIST_DCN3_1(_MASK) 620 }; 621 622 #define hubp_regs(id)\ 623 [id] = {\ 624 HUBP_REG_LIST_DCN30(id)\ 625 } 626 627 static const struct dcn_hubp2_registers hubp_regs[] = { 628 hubp_regs(0), 629 hubp_regs(1), 630 hubp_regs(2), 631 hubp_regs(3) 632 }; 633 634 635 static const struct dcn_hubp2_shift hubp_shift = { 636 HUBP_MASK_SH_LIST_DCN31(__SHIFT) 637 }; 638 639 static const struct dcn_hubp2_mask hubp_mask = { 640 HUBP_MASK_SH_LIST_DCN31(_MASK) 641 }; 642 static const struct dcn_hubbub_registers hubbub_reg = { 643 HUBBUB_REG_LIST_DCN31(0) 644 }; 645 646 static const struct dcn_hubbub_shift hubbub_shift = { 647 HUBBUB_MASK_SH_LIST_DCN31(__SHIFT) 648 }; 649 650 static const struct dcn_hubbub_mask hubbub_mask = { 651 HUBBUB_MASK_SH_LIST_DCN31(_MASK) 652 }; 653 654 static const struct dccg_registers dccg_regs = { 655 DCCG_REG_LIST_DCN31() 656 }; 657 658 static const struct dccg_shift dccg_shift = { 659 DCCG_MASK_SH_LIST_DCN31(__SHIFT) 660 }; 661 662 static const struct dccg_mask dccg_mask = { 663 DCCG_MASK_SH_LIST_DCN31(_MASK) 664 }; 665 666 667 #define SRII2(reg_name_pre, reg_name_post, id)\ 668 .reg_name_pre ## _ ## reg_name_post[id] = BASE(reg ## reg_name_pre \ 669 ## id ## _ ## reg_name_post ## _BASE_IDX) + \ 670 reg ## reg_name_pre ## id ## _ ## reg_name_post 671 672 673 #define HWSEQ_DCN31_REG_LIST()\ 674 SR(DCHUBBUB_GLOBAL_TIMER_CNTL), \ 675 SR(DCHUBBUB_ARB_HOSTVM_CNTL), \ 676 SR(DIO_MEM_PWR_CTRL), \ 677 SR(ODM_MEM_PWR_CTRL3), \ 678 SR(DMU_MEM_PWR_CNTL), \ 679 SR(MMHUBBUB_MEM_PWR_CNTL), \ 680 SR(DCCG_GATE_DISABLE_CNTL), \ 681 SR(DCCG_GATE_DISABLE_CNTL2), \ 682 SR(DCFCLK_CNTL),\ 683 SR(DC_MEM_GLOBAL_PWR_REQ_CNTL), \ 684 SRII(PIXEL_RATE_CNTL, OTG, 0), \ 685 SRII(PIXEL_RATE_CNTL, OTG, 1),\ 686 SRII(PIXEL_RATE_CNTL, OTG, 2),\ 687 SRII(PIXEL_RATE_CNTL, OTG, 3),\ 688 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 0),\ 689 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 1),\ 690 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 2),\ 691 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 3),\ 692 SR(MICROSECOND_TIME_BASE_DIV), \ 693 SR(MILLISECOND_TIME_BASE_DIV), \ 694 SR(DISPCLK_FREQ_CHANGE_CNTL), \ 695 SR(RBBMIF_TIMEOUT_DIS), \ 696 SR(RBBMIF_TIMEOUT_DIS_2), \ 697 SR(DCHUBBUB_CRC_CTRL), \ 698 SR(DPP_TOP0_DPP_CRC_CTRL), \ 699 SR(DPP_TOP0_DPP_CRC_VAL_B_A), \ 700 SR(DPP_TOP0_DPP_CRC_VAL_R_G), \ 701 SR(MPC_CRC_CTRL), \ 702 SR(MPC_CRC_RESULT_GB), \ 703 SR(MPC_CRC_RESULT_C), \ 704 SR(MPC_CRC_RESULT_AR), \ 705 SR(DOMAIN0_PG_CONFIG), \ 706 SR(DOMAIN1_PG_CONFIG), \ 707 SR(DOMAIN2_PG_CONFIG), \ 708 SR(DOMAIN3_PG_CONFIG), \ 709 SR(DOMAIN16_PG_CONFIG), \ 710 SR(DOMAIN17_PG_CONFIG), \ 711 SR(DOMAIN18_PG_CONFIG), \ 712 SR(DOMAIN0_PG_STATUS), \ 713 SR(DOMAIN1_PG_STATUS), \ 714 SR(DOMAIN2_PG_STATUS), \ 715 SR(DOMAIN3_PG_STATUS), \ 716 SR(DOMAIN16_PG_STATUS), \ 717 SR(DOMAIN17_PG_STATUS), \ 718 SR(DOMAIN18_PG_STATUS), \ 719 SR(D1VGA_CONTROL), \ 720 SR(D2VGA_CONTROL), \ 721 SR(D3VGA_CONTROL), \ 722 SR(D4VGA_CONTROL), \ 723 SR(D5VGA_CONTROL), \ 724 SR(D6VGA_CONTROL), \ 725 SR(DC_IP_REQUEST_CNTL), \ 726 SR(AZALIA_AUDIO_DTO), \ 727 SR(AZALIA_CONTROLLER_CLOCK_GATING), \ 728 SR(HPO_TOP_HW_CONTROL) 729 730 static const struct dce_hwseq_registers hwseq_reg = { 731 HWSEQ_DCN31_REG_LIST() 732 }; 733 734 #define HWSEQ_DCN31_MASK_SH_LIST(mask_sh)\ 735 HWSEQ_DCN_MASK_SH_LIST(mask_sh), \ 736 HWS_SF(, DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_REFDIV, mask_sh), \ 737 HWS_SF(, DCHUBBUB_ARB_HOSTVM_CNTL, DISABLE_HOSTVM_FORCE_ALLOW_PSTATE, mask_sh), \ 738 HWS_SF(, DOMAIN0_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ 739 HWS_SF(, DOMAIN0_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ 740 HWS_SF(, DOMAIN1_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ 741 HWS_SF(, DOMAIN1_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ 742 HWS_SF(, DOMAIN2_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ 743 HWS_SF(, DOMAIN2_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ 744 HWS_SF(, DOMAIN3_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ 745 HWS_SF(, DOMAIN3_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ 746 HWS_SF(, DOMAIN16_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ 747 HWS_SF(, DOMAIN16_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ 748 HWS_SF(, DOMAIN17_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ 749 HWS_SF(, DOMAIN17_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ 750 HWS_SF(, DOMAIN18_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ 751 HWS_SF(, DOMAIN18_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ 752 HWS_SF(, DOMAIN0_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ 753 HWS_SF(, DOMAIN1_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ 754 HWS_SF(, DOMAIN2_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ 755 HWS_SF(, DOMAIN3_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ 756 HWS_SF(, DOMAIN16_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ 757 HWS_SF(, DOMAIN17_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ 758 HWS_SF(, DOMAIN18_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ 759 HWS_SF(, DC_IP_REQUEST_CNTL, IP_REQUEST_EN, mask_sh), \ 760 HWS_SF(, AZALIA_AUDIO_DTO, AZALIA_AUDIO_DTO_MODULE, mask_sh), \ 761 HWS_SF(, HPO_TOP_CLOCK_CONTROL, HPO_HDMISTREAMCLK_G_GATE_DIS, mask_sh), \ 762 HWS_SF(, DMU_MEM_PWR_CNTL, DMCU_ERAM_MEM_PWR_FORCE, mask_sh), \ 763 HWS_SF(, ODM_MEM_PWR_CTRL3, ODM_MEM_UNASSIGNED_PWR_MODE, mask_sh), \ 764 HWS_SF(, ODM_MEM_PWR_CTRL3, ODM_MEM_VBLANK_PWR_MODE, mask_sh), \ 765 HWS_SF(, MMHUBBUB_MEM_PWR_CNTL, VGA_MEM_PWR_FORCE, mask_sh), \ 766 HWS_SF(, DIO_MEM_PWR_CTRL, I2C_LIGHT_SLEEP_FORCE, mask_sh), \ 767 HWS_SF(, HPO_TOP_HW_CONTROL, HPO_IO_EN, mask_sh) 768 769 static const struct dce_hwseq_shift hwseq_shift = { 770 HWSEQ_DCN31_MASK_SH_LIST(__SHIFT) 771 }; 772 773 static const struct dce_hwseq_mask hwseq_mask = { 774 HWSEQ_DCN31_MASK_SH_LIST(_MASK) 775 }; 776 #define vmid_regs(id)\ 777 [id] = {\ 778 DCN20_VMID_REG_LIST(id)\ 779 } 780 781 static const struct dcn_vmid_registers vmid_regs[] = { 782 vmid_regs(0), 783 vmid_regs(1), 784 vmid_regs(2), 785 vmid_regs(3), 786 vmid_regs(4), 787 vmid_regs(5), 788 vmid_regs(6), 789 vmid_regs(7), 790 vmid_regs(8), 791 vmid_regs(9), 792 vmid_regs(10), 793 vmid_regs(11), 794 vmid_regs(12), 795 vmid_regs(13), 796 vmid_regs(14), 797 vmid_regs(15) 798 }; 799 800 static const struct dcn20_vmid_shift vmid_shifts = { 801 DCN20_VMID_MASK_SH_LIST(__SHIFT) 802 }; 803 804 static const struct dcn20_vmid_mask vmid_masks = { 805 DCN20_VMID_MASK_SH_LIST(_MASK) 806 }; 807 808 static const struct resource_caps res_cap_dcn31 = { 809 .num_timing_generator = 4, 810 .num_opp = 4, 811 .num_video_plane = 4, 812 .num_audio = 5, 813 .num_stream_encoder = 5, 814 .num_dig_link_enc = 5, 815 .num_hpo_dp_stream_encoder = 4, 816 .num_hpo_dp_link_encoder = 2, 817 .num_pll = 5, 818 .num_dwb = 1, 819 .num_ddc = 5, 820 .num_vmid = 16, 821 .num_mpc_3dlut = 2, 822 .num_dsc = 3, 823 }; 824 825 static const struct dc_plane_cap plane_cap = { 826 .type = DC_PLANE_TYPE_DCN_UNIVERSAL, 827 .blends_with_above = true, 828 .blends_with_below = true, 829 .per_pixel_alpha = true, 830 831 .pixel_format_support = { 832 .argb8888 = true, 833 .nv12 = true, 834 .fp16 = true, 835 .p010 = true, 836 .ayuv = false, 837 }, 838 839 .max_upscale_factor = { 840 .argb8888 = 16000, 841 .nv12 = 16000, 842 .fp16 = 16000 843 }, 844 845 // 6:1 downscaling ratio: 1000/6 = 166.666 846 .max_downscale_factor = { 847 .argb8888 = 167, 848 .nv12 = 167, 849 .fp16 = 167 850 }, 851 64, 852 64 853 }; 854 855 static const struct dc_debug_options debug_defaults_drv = { 856 .disable_z10 = true, /*hw not support it*/ 857 .disable_dmcu = true, 858 .force_abm_enable = false, 859 .timing_trace = false, 860 .clock_trace = true, 861 .disable_pplib_clock_request = false, 862 .pipe_split_policy = MPC_SPLIT_DYNAMIC, 863 .force_single_disp_pipe_split = false, 864 .disable_dcc = DCC_ENABLE, 865 .vsr_support = true, 866 .performance_trace = false, 867 .max_downscale_src_width = 4096,/*upto true 4k*/ 868 .disable_pplib_wm_range = false, 869 .scl_reset_length10 = true, 870 .sanity_checks = false, 871 .underflow_assert_delay_us = 0xFFFFFFFF, 872 .dwb_fi_phase = -1, // -1 = disable, 873 .dmub_command_table = true, 874 .pstate_enabled = true, 875 .use_max_lb = true, 876 .enable_mem_low_power = { 877 .bits = { 878 .vga = true, 879 .i2c = true, 880 .dmcu = false, // This is previously known to cause hang on S3 cycles if enabled 881 .dscl = true, 882 .cm = true, 883 .mpc = true, 884 .optc = true, 885 .vpg = true, 886 .afmt = true, 887 } 888 }, 889 .psr_power_use_phy_fsm = 0, 890 }; 891 892 static const struct dc_debug_options debug_defaults_diags = { 893 .disable_dmcu = true, 894 .force_abm_enable = false, 895 .timing_trace = true, 896 .clock_trace = true, 897 .disable_dpp_power_gate = true, 898 .disable_hubp_power_gate = true, 899 .disable_clock_gate = true, 900 .disable_pplib_clock_request = true, 901 .disable_pplib_wm_range = true, 902 .disable_stutter = false, 903 .scl_reset_length10 = true, 904 .dwb_fi_phase = -1, // -1 = disable 905 .dmub_command_table = true, 906 .enable_tri_buf = true, 907 .use_max_lb = true 908 }; 909 910 static const struct dc_panel_config panel_config_defaults = { 911 .psr = { 912 .disable_psr = false, 913 .disallow_psrsu = false, 914 }, 915 .ilr = { 916 .optimize_edp_link_rate = true, 917 }, 918 }; 919 920 static void dcn31_dpp_destroy(struct dpp **dpp) 921 { 922 kfree(TO_DCN20_DPP(*dpp)); 923 *dpp = NULL; 924 } 925 926 static struct dpp *dcn31_dpp_create( 927 struct dc_context *ctx, 928 uint32_t inst) 929 { 930 struct dcn3_dpp *dpp = 931 kzalloc(sizeof(struct dcn3_dpp), GFP_KERNEL); 932 933 if (!dpp) 934 return NULL; 935 936 if (dpp3_construct(dpp, ctx, inst, 937 &dpp_regs[inst], &tf_shift, &tf_mask)) 938 return &dpp->base; 939 940 BREAK_TO_DEBUGGER(); 941 kfree(dpp); 942 return NULL; 943 } 944 945 static struct output_pixel_processor *dcn31_opp_create( 946 struct dc_context *ctx, uint32_t inst) 947 { 948 struct dcn20_opp *opp = 949 kzalloc(sizeof(struct dcn20_opp), GFP_KERNEL); 950 951 if (!opp) { 952 BREAK_TO_DEBUGGER(); 953 return NULL; 954 } 955 956 dcn20_opp_construct(opp, ctx, inst, 957 &opp_regs[inst], &opp_shift, &opp_mask); 958 return &opp->base; 959 } 960 961 static struct dce_aux *dcn31_aux_engine_create( 962 struct dc_context *ctx, 963 uint32_t inst) 964 { 965 struct aux_engine_dce110 *aux_engine = 966 kzalloc(sizeof(struct aux_engine_dce110), GFP_KERNEL); 967 968 if (!aux_engine) 969 return NULL; 970 971 dce110_aux_engine_construct(aux_engine, ctx, inst, 972 SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD, 973 &aux_engine_regs[inst], 974 &aux_mask, 975 &aux_shift, 976 ctx->dc->caps.extended_aux_timeout_support); 977 978 return &aux_engine->base; 979 } 980 #define i2c_inst_regs(id) { I2C_HW_ENGINE_COMMON_REG_LIST_DCN30(id) } 981 982 static const struct dce_i2c_registers i2c_hw_regs[] = { 983 i2c_inst_regs(1), 984 i2c_inst_regs(2), 985 i2c_inst_regs(3), 986 i2c_inst_regs(4), 987 i2c_inst_regs(5), 988 }; 989 990 static const struct dce_i2c_shift i2c_shifts = { 991 I2C_COMMON_MASK_SH_LIST_DCN30(__SHIFT) 992 }; 993 994 static const struct dce_i2c_mask i2c_masks = { 995 I2C_COMMON_MASK_SH_LIST_DCN30(_MASK) 996 }; 997 998 static struct dce_i2c_hw *dcn31_i2c_hw_create( 999 struct dc_context *ctx, 1000 uint32_t inst) 1001 { 1002 struct dce_i2c_hw *dce_i2c_hw = 1003 kzalloc(sizeof(struct dce_i2c_hw), GFP_KERNEL); 1004 1005 if (!dce_i2c_hw) 1006 return NULL; 1007 1008 dcn2_i2c_hw_construct(dce_i2c_hw, ctx, inst, 1009 &i2c_hw_regs[inst], &i2c_shifts, &i2c_masks); 1010 1011 return dce_i2c_hw; 1012 } 1013 static struct mpc *dcn31_mpc_create( 1014 struct dc_context *ctx, 1015 int num_mpcc, 1016 int num_rmu) 1017 { 1018 struct dcn30_mpc *mpc30 = kzalloc(sizeof(struct dcn30_mpc), 1019 GFP_KERNEL); 1020 1021 if (!mpc30) 1022 return NULL; 1023 1024 dcn30_mpc_construct(mpc30, ctx, 1025 &mpc_regs, 1026 &mpc_shift, 1027 &mpc_mask, 1028 num_mpcc, 1029 num_rmu); 1030 1031 return &mpc30->base; 1032 } 1033 1034 static struct hubbub *dcn31_hubbub_create(struct dc_context *ctx) 1035 { 1036 int i; 1037 1038 struct dcn20_hubbub *hubbub3 = kzalloc(sizeof(struct dcn20_hubbub), 1039 GFP_KERNEL); 1040 1041 if (!hubbub3) 1042 return NULL; 1043 1044 hubbub31_construct(hubbub3, ctx, 1045 &hubbub_reg, 1046 &hubbub_shift, 1047 &hubbub_mask, 1048 dcn3_15_ip.det_buffer_size_kbytes, 1049 dcn3_15_ip.pixel_chunk_size_kbytes, 1050 dcn3_15_ip.config_return_buffer_size_in_kbytes); 1051 1052 1053 for (i = 0; i < res_cap_dcn31.num_vmid; i++) { 1054 struct dcn20_vmid *vmid = &hubbub3->vmid[i]; 1055 1056 vmid->ctx = ctx; 1057 1058 vmid->regs = &vmid_regs[i]; 1059 vmid->shifts = &vmid_shifts; 1060 vmid->masks = &vmid_masks; 1061 } 1062 1063 return &hubbub3->base; 1064 } 1065 1066 static struct timing_generator *dcn31_timing_generator_create( 1067 struct dc_context *ctx, 1068 uint32_t instance) 1069 { 1070 struct optc *tgn10 = 1071 kzalloc(sizeof(struct optc), GFP_KERNEL); 1072 1073 if (!tgn10) 1074 return NULL; 1075 1076 tgn10->base.inst = instance; 1077 tgn10->base.ctx = ctx; 1078 1079 tgn10->tg_regs = &optc_regs[instance]; 1080 tgn10->tg_shift = &optc_shift; 1081 tgn10->tg_mask = &optc_mask; 1082 1083 dcn31_timing_generator_init(tgn10); 1084 1085 return &tgn10->base; 1086 } 1087 1088 static const struct encoder_feature_support link_enc_feature = { 1089 .max_hdmi_deep_color = COLOR_DEPTH_121212, 1090 .max_hdmi_pixel_clock = 600000, 1091 .hdmi_ycbcr420_supported = true, 1092 .dp_ycbcr420_supported = true, 1093 .fec_supported = true, 1094 .flags.bits.IS_HBR2_CAPABLE = true, 1095 .flags.bits.IS_HBR3_CAPABLE = true, 1096 .flags.bits.IS_TPS3_CAPABLE = true, 1097 .flags.bits.IS_TPS4_CAPABLE = true 1098 }; 1099 1100 static struct link_encoder *dcn31_link_encoder_create( 1101 struct dc_context *ctx, 1102 const struct encoder_init_data *enc_init_data) 1103 { 1104 struct dcn20_link_encoder *enc20 = 1105 kzalloc(sizeof(struct dcn20_link_encoder), GFP_KERNEL); 1106 1107 if (!enc20) 1108 return NULL; 1109 1110 dcn31_link_encoder_construct(enc20, 1111 enc_init_data, 1112 &link_enc_feature, 1113 &link_enc_regs[enc_init_data->transmitter], 1114 &link_enc_aux_regs[enc_init_data->channel - 1], 1115 &link_enc_hpd_regs[enc_init_data->hpd_source], 1116 &le_shift, 1117 &le_mask); 1118 1119 return &enc20->enc10.base; 1120 } 1121 1122 /* Create a minimal link encoder object not associated with a particular 1123 * physical connector. 1124 * resource_funcs.link_enc_create_minimal 1125 */ 1126 static struct link_encoder *dcn31_link_enc_create_minimal( 1127 struct dc_context *ctx, enum engine_id eng_id) 1128 { 1129 struct dcn20_link_encoder *enc20; 1130 1131 if ((eng_id - ENGINE_ID_DIGA) > ctx->dc->res_pool->res_cap->num_dig_link_enc) 1132 return NULL; 1133 1134 enc20 = kzalloc(sizeof(struct dcn20_link_encoder), GFP_KERNEL); 1135 if (!enc20) 1136 return NULL; 1137 1138 dcn31_link_encoder_construct_minimal( 1139 enc20, 1140 ctx, 1141 &link_enc_feature, 1142 &link_enc_regs[eng_id - ENGINE_ID_DIGA], 1143 eng_id); 1144 1145 return &enc20->enc10.base; 1146 } 1147 1148 static struct panel_cntl *dcn31_panel_cntl_create(const struct panel_cntl_init_data *init_data) 1149 { 1150 struct dcn31_panel_cntl *panel_cntl = 1151 kzalloc(sizeof(struct dcn31_panel_cntl), GFP_KERNEL); 1152 1153 if (!panel_cntl) 1154 return NULL; 1155 1156 dcn31_panel_cntl_construct(panel_cntl, init_data); 1157 1158 return &panel_cntl->base; 1159 } 1160 1161 static void read_dce_straps( 1162 struct dc_context *ctx, 1163 struct resource_straps *straps) 1164 { 1165 generic_reg_get(ctx, regDC_PINSTRAPS + BASE(regDC_PINSTRAPS_BASE_IDX), 1166 FN(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO), &straps->dc_pinstraps_audio); 1167 1168 } 1169 1170 static struct audio *dcn31_create_audio( 1171 struct dc_context *ctx, unsigned int inst) 1172 { 1173 return dce_audio_create(ctx, inst, 1174 &audio_regs[inst], &audio_shift, &audio_mask); 1175 } 1176 1177 static struct vpg *dcn31_vpg_create( 1178 struct dc_context *ctx, 1179 uint32_t inst) 1180 { 1181 struct dcn31_vpg *vpg31 = kzalloc(sizeof(struct dcn31_vpg), GFP_KERNEL); 1182 1183 if (!vpg31) 1184 return NULL; 1185 1186 vpg31_construct(vpg31, ctx, inst, 1187 &vpg_regs[inst], 1188 &vpg_shift, 1189 &vpg_mask); 1190 1191 return &vpg31->base; 1192 } 1193 1194 static struct afmt *dcn31_afmt_create( 1195 struct dc_context *ctx, 1196 uint32_t inst) 1197 { 1198 struct dcn31_afmt *afmt31 = kzalloc(sizeof(struct dcn31_afmt), GFP_KERNEL); 1199 1200 if (!afmt31) 1201 return NULL; 1202 1203 afmt31_construct(afmt31, ctx, inst, 1204 &afmt_regs[inst], 1205 &afmt_shift, 1206 &afmt_mask); 1207 1208 // Light sleep by default, no need to power down here 1209 1210 return &afmt31->base; 1211 } 1212 1213 static struct apg *dcn31_apg_create( 1214 struct dc_context *ctx, 1215 uint32_t inst) 1216 { 1217 struct dcn31_apg *apg31 = kzalloc(sizeof(struct dcn31_apg), GFP_KERNEL); 1218 1219 if (!apg31) 1220 return NULL; 1221 1222 apg31_construct(apg31, ctx, inst, 1223 &apg_regs[inst], 1224 &apg_shift, 1225 &apg_mask); 1226 1227 return &apg31->base; 1228 } 1229 1230 static struct stream_encoder *dcn315_stream_encoder_create( 1231 enum engine_id eng_id, 1232 struct dc_context *ctx) 1233 { 1234 struct dcn10_stream_encoder *enc1; 1235 struct vpg *vpg; 1236 struct afmt *afmt; 1237 int vpg_inst; 1238 int afmt_inst; 1239 1240 /*PHYB is wired off in HW, allow front end to remapping, otherwise needs more changes*/ 1241 1242 /* Mapping of VPG, AFMT, DME register blocks to DIO block instance */ 1243 if (eng_id <= ENGINE_ID_DIGF) { 1244 vpg_inst = eng_id; 1245 afmt_inst = eng_id; 1246 } else 1247 return NULL; 1248 1249 enc1 = kzalloc(sizeof(struct dcn10_stream_encoder), GFP_KERNEL); 1250 vpg = dcn31_vpg_create(ctx, vpg_inst); 1251 afmt = dcn31_afmt_create(ctx, afmt_inst); 1252 1253 if (!enc1 || !vpg || !afmt) { 1254 kfree(enc1); 1255 kfree(vpg); 1256 kfree(afmt); 1257 return NULL; 1258 } 1259 1260 dcn30_dio_stream_encoder_construct(enc1, ctx, ctx->dc_bios, 1261 eng_id, vpg, afmt, 1262 &stream_enc_regs[eng_id], 1263 &se_shift, &se_mask); 1264 1265 return &enc1->base; 1266 } 1267 1268 static struct hpo_dp_stream_encoder *dcn31_hpo_dp_stream_encoder_create( 1269 enum engine_id eng_id, 1270 struct dc_context *ctx) 1271 { 1272 struct dcn31_hpo_dp_stream_encoder *hpo_dp_enc31; 1273 struct vpg *vpg; 1274 struct apg *apg; 1275 uint32_t hpo_dp_inst; 1276 uint32_t vpg_inst; 1277 uint32_t apg_inst; 1278 1279 ASSERT((eng_id >= ENGINE_ID_HPO_DP_0) && (eng_id <= ENGINE_ID_HPO_DP_3)); 1280 hpo_dp_inst = eng_id - ENGINE_ID_HPO_DP_0; 1281 1282 /* Mapping of VPG register blocks to HPO DP block instance: 1283 * VPG[6] -> HPO_DP[0] 1284 * VPG[7] -> HPO_DP[1] 1285 * VPG[8] -> HPO_DP[2] 1286 * VPG[9] -> HPO_DP[3] 1287 */ 1288 vpg_inst = hpo_dp_inst + 6; 1289 1290 /* Mapping of APG register blocks to HPO DP block instance: 1291 * APG[0] -> HPO_DP[0] 1292 * APG[1] -> HPO_DP[1] 1293 * APG[2] -> HPO_DP[2] 1294 * APG[3] -> HPO_DP[3] 1295 */ 1296 apg_inst = hpo_dp_inst; 1297 1298 /* allocate HPO stream encoder and create VPG sub-block */ 1299 hpo_dp_enc31 = kzalloc(sizeof(struct dcn31_hpo_dp_stream_encoder), GFP_KERNEL); 1300 vpg = dcn31_vpg_create(ctx, vpg_inst); 1301 apg = dcn31_apg_create(ctx, apg_inst); 1302 1303 if (!hpo_dp_enc31 || !vpg || !apg) { 1304 kfree(hpo_dp_enc31); 1305 kfree(vpg); 1306 kfree(apg); 1307 return NULL; 1308 } 1309 1310 dcn31_hpo_dp_stream_encoder_construct(hpo_dp_enc31, ctx, ctx->dc_bios, 1311 hpo_dp_inst, eng_id, vpg, apg, 1312 &hpo_dp_stream_enc_regs[hpo_dp_inst], 1313 &hpo_dp_se_shift, &hpo_dp_se_mask); 1314 1315 return &hpo_dp_enc31->base; 1316 } 1317 1318 static struct hpo_dp_link_encoder *dcn31_hpo_dp_link_encoder_create( 1319 uint8_t inst, 1320 struct dc_context *ctx) 1321 { 1322 struct dcn31_hpo_dp_link_encoder *hpo_dp_enc31; 1323 1324 /* allocate HPO link encoder */ 1325 hpo_dp_enc31 = kzalloc(sizeof(struct dcn31_hpo_dp_link_encoder), GFP_KERNEL); 1326 1327 hpo_dp_link_encoder31_construct(hpo_dp_enc31, ctx, inst, 1328 &hpo_dp_link_enc_regs[inst], 1329 &hpo_dp_le_shift, &hpo_dp_le_mask); 1330 1331 return &hpo_dp_enc31->base; 1332 } 1333 1334 static struct dce_hwseq *dcn31_hwseq_create( 1335 struct dc_context *ctx) 1336 { 1337 struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_KERNEL); 1338 1339 if (hws) { 1340 hws->ctx = ctx; 1341 hws->regs = &hwseq_reg; 1342 hws->shifts = &hwseq_shift; 1343 hws->masks = &hwseq_mask; 1344 /* DCN3.1 FPGA Workaround 1345 * Need to enable HPO DP Stream Encoder before setting OTG master enable. 1346 * To do so, move calling function enable_stream_timing to only be done AFTER calling 1347 * function core_link_enable_stream 1348 */ 1349 if (IS_FPGA_MAXIMUS_DC(ctx->dce_environment)) 1350 hws->wa.dp_hpo_and_otg_sequence = true; 1351 } 1352 return hws; 1353 } 1354 static const struct resource_create_funcs res_create_funcs = { 1355 .read_dce_straps = read_dce_straps, 1356 .create_audio = dcn31_create_audio, 1357 .create_stream_encoder = dcn315_stream_encoder_create, 1358 .create_hpo_dp_stream_encoder = dcn31_hpo_dp_stream_encoder_create, 1359 .create_hpo_dp_link_encoder = dcn31_hpo_dp_link_encoder_create, 1360 .create_hwseq = dcn31_hwseq_create, 1361 }; 1362 1363 static const struct resource_create_funcs res_create_maximus_funcs = { 1364 .read_dce_straps = NULL, 1365 .create_audio = NULL, 1366 .create_stream_encoder = NULL, 1367 .create_hpo_dp_stream_encoder = dcn31_hpo_dp_stream_encoder_create, 1368 .create_hpo_dp_link_encoder = dcn31_hpo_dp_link_encoder_create, 1369 .create_hwseq = dcn31_hwseq_create, 1370 }; 1371 1372 static void dcn315_resource_destruct(struct dcn315_resource_pool *pool) 1373 { 1374 unsigned int i; 1375 1376 for (i = 0; i < pool->base.stream_enc_count; i++) { 1377 if (pool->base.stream_enc[i] != NULL) { 1378 if (pool->base.stream_enc[i]->vpg != NULL) { 1379 kfree(DCN30_VPG_FROM_VPG(pool->base.stream_enc[i]->vpg)); 1380 pool->base.stream_enc[i]->vpg = NULL; 1381 } 1382 if (pool->base.stream_enc[i]->afmt != NULL) { 1383 kfree(DCN30_AFMT_FROM_AFMT(pool->base.stream_enc[i]->afmt)); 1384 pool->base.stream_enc[i]->afmt = NULL; 1385 } 1386 kfree(DCN10STRENC_FROM_STRENC(pool->base.stream_enc[i])); 1387 pool->base.stream_enc[i] = NULL; 1388 } 1389 } 1390 1391 for (i = 0; i < pool->base.hpo_dp_stream_enc_count; i++) { 1392 if (pool->base.hpo_dp_stream_enc[i] != NULL) { 1393 if (pool->base.hpo_dp_stream_enc[i]->vpg != NULL) { 1394 kfree(DCN30_VPG_FROM_VPG(pool->base.hpo_dp_stream_enc[i]->vpg)); 1395 pool->base.hpo_dp_stream_enc[i]->vpg = NULL; 1396 } 1397 if (pool->base.hpo_dp_stream_enc[i]->apg != NULL) { 1398 kfree(DCN31_APG_FROM_APG(pool->base.hpo_dp_stream_enc[i]->apg)); 1399 pool->base.hpo_dp_stream_enc[i]->apg = NULL; 1400 } 1401 kfree(DCN3_1_HPO_DP_STREAM_ENC_FROM_HPO_STREAM_ENC(pool->base.hpo_dp_stream_enc[i])); 1402 pool->base.hpo_dp_stream_enc[i] = NULL; 1403 } 1404 } 1405 1406 for (i = 0; i < pool->base.hpo_dp_link_enc_count; i++) { 1407 if (pool->base.hpo_dp_link_enc[i] != NULL) { 1408 kfree(DCN3_1_HPO_DP_LINK_ENC_FROM_HPO_LINK_ENC(pool->base.hpo_dp_link_enc[i])); 1409 pool->base.hpo_dp_link_enc[i] = NULL; 1410 } 1411 } 1412 1413 for (i = 0; i < pool->base.res_cap->num_dsc; i++) { 1414 if (pool->base.dscs[i] != NULL) 1415 dcn20_dsc_destroy(&pool->base.dscs[i]); 1416 } 1417 1418 if (pool->base.mpc != NULL) { 1419 kfree(TO_DCN20_MPC(pool->base.mpc)); 1420 pool->base.mpc = NULL; 1421 } 1422 if (pool->base.hubbub != NULL) { 1423 kfree(pool->base.hubbub); 1424 pool->base.hubbub = NULL; 1425 } 1426 for (i = 0; i < pool->base.pipe_count; i++) { 1427 if (pool->base.dpps[i] != NULL) 1428 dcn31_dpp_destroy(&pool->base.dpps[i]); 1429 1430 if (pool->base.ipps[i] != NULL) 1431 pool->base.ipps[i]->funcs->ipp_destroy(&pool->base.ipps[i]); 1432 1433 if (pool->base.hubps[i] != NULL) { 1434 kfree(TO_DCN20_HUBP(pool->base.hubps[i])); 1435 pool->base.hubps[i] = NULL; 1436 } 1437 1438 if (pool->base.irqs != NULL) { 1439 dal_irq_service_destroy(&pool->base.irqs); 1440 } 1441 } 1442 1443 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { 1444 if (pool->base.engines[i] != NULL) 1445 dce110_engine_destroy(&pool->base.engines[i]); 1446 if (pool->base.hw_i2cs[i] != NULL) { 1447 kfree(pool->base.hw_i2cs[i]); 1448 pool->base.hw_i2cs[i] = NULL; 1449 } 1450 if (pool->base.sw_i2cs[i] != NULL) { 1451 kfree(pool->base.sw_i2cs[i]); 1452 pool->base.sw_i2cs[i] = NULL; 1453 } 1454 } 1455 1456 for (i = 0; i < pool->base.res_cap->num_opp; i++) { 1457 if (pool->base.opps[i] != NULL) 1458 pool->base.opps[i]->funcs->opp_destroy(&pool->base.opps[i]); 1459 } 1460 1461 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { 1462 if (pool->base.timing_generators[i] != NULL) { 1463 kfree(DCN10TG_FROM_TG(pool->base.timing_generators[i])); 1464 pool->base.timing_generators[i] = NULL; 1465 } 1466 } 1467 1468 for (i = 0; i < pool->base.res_cap->num_dwb; i++) { 1469 if (pool->base.dwbc[i] != NULL) { 1470 kfree(TO_DCN30_DWBC(pool->base.dwbc[i])); 1471 pool->base.dwbc[i] = NULL; 1472 } 1473 if (pool->base.mcif_wb[i] != NULL) { 1474 kfree(TO_DCN30_MMHUBBUB(pool->base.mcif_wb[i])); 1475 pool->base.mcif_wb[i] = NULL; 1476 } 1477 } 1478 1479 for (i = 0; i < pool->base.audio_count; i++) { 1480 if (pool->base.audios[i]) 1481 dce_aud_destroy(&pool->base.audios[i]); 1482 } 1483 1484 for (i = 0; i < pool->base.clk_src_count; i++) { 1485 if (pool->base.clock_sources[i] != NULL) { 1486 dcn20_clock_source_destroy(&pool->base.clock_sources[i]); 1487 pool->base.clock_sources[i] = NULL; 1488 } 1489 } 1490 1491 for (i = 0; i < pool->base.res_cap->num_mpc_3dlut; i++) { 1492 if (pool->base.mpc_lut[i] != NULL) { 1493 dc_3dlut_func_release(pool->base.mpc_lut[i]); 1494 pool->base.mpc_lut[i] = NULL; 1495 } 1496 if (pool->base.mpc_shaper[i] != NULL) { 1497 dc_transfer_func_release(pool->base.mpc_shaper[i]); 1498 pool->base.mpc_shaper[i] = NULL; 1499 } 1500 } 1501 1502 if (pool->base.dp_clock_source != NULL) { 1503 dcn20_clock_source_destroy(&pool->base.dp_clock_source); 1504 pool->base.dp_clock_source = NULL; 1505 } 1506 1507 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { 1508 if (pool->base.multiple_abms[i] != NULL) 1509 dce_abm_destroy(&pool->base.multiple_abms[i]); 1510 } 1511 1512 if (pool->base.psr != NULL) 1513 dmub_psr_destroy(&pool->base.psr); 1514 1515 if (pool->base.dccg != NULL) 1516 dcn_dccg_destroy(&pool->base.dccg); 1517 } 1518 1519 static struct hubp *dcn31_hubp_create( 1520 struct dc_context *ctx, 1521 uint32_t inst) 1522 { 1523 struct dcn20_hubp *hubp2 = 1524 kzalloc(sizeof(struct dcn20_hubp), GFP_KERNEL); 1525 1526 if (!hubp2) 1527 return NULL; 1528 1529 if (hubp31_construct(hubp2, ctx, inst, 1530 &hubp_regs[inst], &hubp_shift, &hubp_mask)) 1531 return &hubp2->base; 1532 1533 BREAK_TO_DEBUGGER(); 1534 kfree(hubp2); 1535 return NULL; 1536 } 1537 1538 static bool dcn31_dwbc_create(struct dc_context *ctx, struct resource_pool *pool) 1539 { 1540 int i; 1541 uint32_t pipe_count = pool->res_cap->num_dwb; 1542 1543 for (i = 0; i < pipe_count; i++) { 1544 struct dcn30_dwbc *dwbc30 = kzalloc(sizeof(struct dcn30_dwbc), 1545 GFP_KERNEL); 1546 1547 if (!dwbc30) { 1548 dm_error("DC: failed to create dwbc30!\n"); 1549 return false; 1550 } 1551 1552 dcn30_dwbc_construct(dwbc30, ctx, 1553 &dwbc30_regs[i], 1554 &dwbc30_shift, 1555 &dwbc30_mask, 1556 i); 1557 1558 pool->dwbc[i] = &dwbc30->base; 1559 } 1560 return true; 1561 } 1562 1563 static bool dcn31_mmhubbub_create(struct dc_context *ctx, struct resource_pool *pool) 1564 { 1565 int i; 1566 uint32_t pipe_count = pool->res_cap->num_dwb; 1567 1568 for (i = 0; i < pipe_count; i++) { 1569 struct dcn30_mmhubbub *mcif_wb30 = kzalloc(sizeof(struct dcn30_mmhubbub), 1570 GFP_KERNEL); 1571 1572 if (!mcif_wb30) { 1573 dm_error("DC: failed to create mcif_wb30!\n"); 1574 return false; 1575 } 1576 1577 dcn30_mmhubbub_construct(mcif_wb30, ctx, 1578 &mcif_wb30_regs[i], 1579 &mcif_wb30_shift, 1580 &mcif_wb30_mask, 1581 i); 1582 1583 pool->mcif_wb[i] = &mcif_wb30->base; 1584 } 1585 return true; 1586 } 1587 1588 static struct display_stream_compressor *dcn31_dsc_create( 1589 struct dc_context *ctx, uint32_t inst) 1590 { 1591 struct dcn20_dsc *dsc = 1592 kzalloc(sizeof(struct dcn20_dsc), GFP_KERNEL); 1593 1594 if (!dsc) { 1595 BREAK_TO_DEBUGGER(); 1596 return NULL; 1597 } 1598 1599 dsc2_construct(dsc, ctx, inst, &dsc_regs[inst], &dsc_shift, &dsc_mask); 1600 return &dsc->base; 1601 } 1602 1603 static void dcn315_destroy_resource_pool(struct resource_pool **pool) 1604 { 1605 struct dcn315_resource_pool *dcn31_pool = TO_DCN315_RES_POOL(*pool); 1606 1607 dcn315_resource_destruct(dcn31_pool); 1608 kfree(dcn31_pool); 1609 *pool = NULL; 1610 } 1611 1612 static struct clock_source *dcn31_clock_source_create( 1613 struct dc_context *ctx, 1614 struct dc_bios *bios, 1615 enum clock_source_id id, 1616 const struct dce110_clk_src_regs *regs, 1617 bool dp_clk_src) 1618 { 1619 struct dce110_clk_src *clk_src = 1620 kzalloc(sizeof(struct dce110_clk_src), GFP_KERNEL); 1621 1622 if (!clk_src) 1623 return NULL; 1624 1625 if (dcn31_clk_src_construct(clk_src, ctx, bios, id, 1626 regs, &cs_shift, &cs_mask)) { 1627 clk_src->base.dp_clk_src = dp_clk_src; 1628 return &clk_src->base; 1629 } 1630 1631 kfree(clk_src); 1632 BREAK_TO_DEBUGGER(); 1633 return NULL; 1634 } 1635 1636 static bool is_dual_plane(enum surface_pixel_format format) 1637 { 1638 return format >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN || format == SURFACE_PIXEL_FORMAT_GRPH_RGBE_ALPHA; 1639 } 1640 1641 static int dcn315_populate_dml_pipes_from_context( 1642 struct dc *dc, struct dc_state *context, 1643 display_e2e_pipe_params_st *pipes, 1644 bool fast_validate) 1645 { 1646 int i, pipe_cnt; 1647 struct resource_context *res_ctx = &context->res_ctx; 1648 struct pipe_ctx *pipe; 1649 const int max_usable_det = context->bw_ctx.dml.ip.config_return_buffer_size_in_kbytes - DCN3_15_MIN_COMPBUF_SIZE_KB; 1650 1651 DC_FP_START(); 1652 dcn31x_populate_dml_pipes_from_context(dc, context, pipes, fast_validate); 1653 DC_FP_END(); 1654 1655 for (i = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) { 1656 struct dc_crtc_timing *timing; 1657 1658 if (!res_ctx->pipe_ctx[i].stream) 1659 continue; 1660 pipe = &res_ctx->pipe_ctx[i]; 1661 timing = &pipe->stream->timing; 1662 1663 /* 1664 * Immediate flip can be set dynamically after enabling the plane. 1665 * We need to require support for immediate flip or underflow can be 1666 * intermittently experienced depending on peak b/w requirements. 1667 */ 1668 pipes[pipe_cnt].pipe.src.immediate_flip = true; 1669 1670 pipes[pipe_cnt].pipe.src.unbounded_req_mode = false; 1671 pipes[pipe_cnt].pipe.dest.vfront_porch = timing->v_front_porch; 1672 pipes[pipe_cnt].pipe.src.dcc_rate = 3; 1673 pipes[pipe_cnt].dout.dsc_input_bpc = 0; 1674 DC_FP_START(); 1675 dcn31_zero_pipe_dcc_fraction(pipes, pipe_cnt); 1676 DC_FP_END(); 1677 1678 if (pipes[pipe_cnt].dout.dsc_enable) { 1679 switch (timing->display_color_depth) { 1680 case COLOR_DEPTH_888: 1681 pipes[pipe_cnt].dout.dsc_input_bpc = 8; 1682 break; 1683 case COLOR_DEPTH_101010: 1684 pipes[pipe_cnt].dout.dsc_input_bpc = 10; 1685 break; 1686 case COLOR_DEPTH_121212: 1687 pipes[pipe_cnt].dout.dsc_input_bpc = 12; 1688 break; 1689 default: 1690 ASSERT(0); 1691 break; 1692 } 1693 } 1694 1695 pipe_cnt++; 1696 } 1697 1698 if (pipe_cnt) 1699 context->bw_ctx.dml.ip.det_buffer_size_kbytes = 1700 (max_usable_det / DCN3_15_CRB_SEGMENT_SIZE_KB / pipe_cnt) * DCN3_15_CRB_SEGMENT_SIZE_KB; 1701 if (context->bw_ctx.dml.ip.det_buffer_size_kbytes > DCN3_15_MAX_DET_SIZE) 1702 context->bw_ctx.dml.ip.det_buffer_size_kbytes = DCN3_15_MAX_DET_SIZE; 1703 ASSERT(context->bw_ctx.dml.ip.det_buffer_size_kbytes >= DCN3_15_DEFAULT_DET_SIZE); 1704 dc->config.enable_4to1MPC = false; 1705 if (pipe_cnt == 1 && pipe->plane_state && !dc->debug.disable_z9_mpc) { 1706 if (is_dual_plane(pipe->plane_state->format) 1707 && pipe->plane_state->src_rect.width <= 1920 && pipe->plane_state->src_rect.height <= 1080) { 1708 dc->config.enable_4to1MPC = true; 1709 context->bw_ctx.dml.ip.det_buffer_size_kbytes = 1710 (max_usable_det / DCN3_15_CRB_SEGMENT_SIZE_KB / 4) * DCN3_15_CRB_SEGMENT_SIZE_KB; 1711 } else if (!is_dual_plane(pipe->plane_state->format) 1712 && pipe->plane_state->src_rect.width <= 5120 1713 && pipe->stream->timing.pix_clk_100hz < dcn_get_max_non_odm_pix_rate_100hz(&dc->dml.soc)) { 1714 /* Limit to 5k max to avoid forced pipe split when there is not enough detile for swath */ 1715 context->bw_ctx.dml.ip.det_buffer_size_kbytes = 192; 1716 pipes[0].pipe.src.unbounded_req_mode = true; 1717 } 1718 } 1719 1720 return pipe_cnt; 1721 } 1722 1723 static void dcn315_get_panel_config_defaults(struct dc_panel_config *panel_config) 1724 { 1725 *panel_config = panel_config_defaults; 1726 } 1727 1728 static struct dc_cap_funcs cap_funcs = { 1729 .get_dcc_compression_cap = dcn20_get_dcc_compression_cap 1730 }; 1731 1732 static struct resource_funcs dcn315_res_pool_funcs = { 1733 .destroy = dcn315_destroy_resource_pool, 1734 .link_enc_create = dcn31_link_encoder_create, 1735 .link_enc_create_minimal = dcn31_link_enc_create_minimal, 1736 .link_encs_assign = link_enc_cfg_link_encs_assign, 1737 .link_enc_unassign = link_enc_cfg_link_enc_unassign, 1738 .panel_cntl_create = dcn31_panel_cntl_create, 1739 .validate_bandwidth = dcn31_validate_bandwidth, 1740 .calculate_wm_and_dlg = dcn31_calculate_wm_and_dlg, 1741 .update_soc_for_wm_a = dcn315_update_soc_for_wm_a, 1742 .populate_dml_pipes = dcn315_populate_dml_pipes_from_context, 1743 .acquire_idle_pipe_for_layer = dcn20_acquire_idle_pipe_for_layer, 1744 .add_stream_to_ctx = dcn30_add_stream_to_ctx, 1745 .add_dsc_to_stream_resource = dcn20_add_dsc_to_stream_resource, 1746 .remove_stream_from_ctx = dcn20_remove_stream_from_ctx, 1747 .populate_dml_writeback_from_context = dcn31_populate_dml_writeback_from_context, 1748 .set_mcif_arb_params = dcn31_set_mcif_arb_params, 1749 .find_first_free_match_stream_enc_for_link = dcn10_find_first_free_match_stream_enc_for_link, 1750 .acquire_post_bldn_3dlut = dcn30_acquire_post_bldn_3dlut, 1751 .release_post_bldn_3dlut = dcn30_release_post_bldn_3dlut, 1752 .update_bw_bounding_box = dcn315_update_bw_bounding_box, 1753 .patch_unknown_plane_state = dcn20_patch_unknown_plane_state, 1754 .get_panel_config_defaults = dcn315_get_panel_config_defaults, 1755 }; 1756 1757 static bool dcn315_resource_construct( 1758 uint8_t num_virtual_links, 1759 struct dc *dc, 1760 struct dcn315_resource_pool *pool) 1761 { 1762 int i; 1763 struct dc_context *ctx = dc->ctx; 1764 struct irq_service_init_data init_data; 1765 1766 ctx->dc_bios->regs = &bios_regs; 1767 1768 pool->base.res_cap = &res_cap_dcn31; 1769 1770 pool->base.funcs = &dcn315_res_pool_funcs; 1771 1772 /************************************************* 1773 * Resource + asic cap harcoding * 1774 *************************************************/ 1775 pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE; 1776 pool->base.pipe_count = pool->base.res_cap->num_timing_generator; 1777 pool->base.mpcc_count = pool->base.res_cap->num_timing_generator; 1778 dc->caps.max_downscale_ratio = 600; 1779 dc->caps.i2c_speed_in_khz = 100; 1780 dc->caps.i2c_speed_in_khz_hdcp = 100; 1781 dc->caps.max_cursor_size = 256; 1782 dc->caps.min_horizontal_blanking_period = 80; 1783 dc->caps.dmdata_alloc_size = 2048; 1784 dc->caps.max_slave_planes = 2; 1785 dc->caps.max_slave_yuv_planes = 2; 1786 dc->caps.max_slave_rgb_planes = 2; 1787 dc->caps.post_blend_color_processing = true; 1788 dc->caps.force_dp_tps4_for_cp2520 = true; 1789 if (dc->config.forceHBR2CP2520) 1790 dc->caps.force_dp_tps4_for_cp2520 = false; 1791 dc->caps.dp_hpo = true; 1792 dc->caps.dp_hdmi21_pcon_support = true; 1793 dc->caps.edp_dsc_support = true; 1794 dc->caps.extended_aux_timeout_support = true; 1795 dc->caps.dmcub_support = true; 1796 dc->caps.is_apu = true; 1797 1798 /* Color pipeline capabilities */ 1799 dc->caps.color.dpp.dcn_arch = 1; 1800 dc->caps.color.dpp.input_lut_shared = 0; 1801 dc->caps.color.dpp.icsc = 1; 1802 dc->caps.color.dpp.dgam_ram = 0; // must use gamma_corr 1803 dc->caps.color.dpp.dgam_rom_caps.srgb = 1; 1804 dc->caps.color.dpp.dgam_rom_caps.bt2020 = 1; 1805 dc->caps.color.dpp.dgam_rom_caps.gamma2_2 = 1; 1806 dc->caps.color.dpp.dgam_rom_caps.pq = 1; 1807 dc->caps.color.dpp.dgam_rom_caps.hlg = 1; 1808 dc->caps.color.dpp.post_csc = 1; 1809 dc->caps.color.dpp.gamma_corr = 1; 1810 dc->caps.color.dpp.dgam_rom_for_yuv = 0; 1811 1812 dc->caps.color.dpp.hw_3d_lut = 1; 1813 dc->caps.color.dpp.ogam_ram = 1; 1814 // no OGAM ROM on DCN301 1815 dc->caps.color.dpp.ogam_rom_caps.srgb = 0; 1816 dc->caps.color.dpp.ogam_rom_caps.bt2020 = 0; 1817 dc->caps.color.dpp.ogam_rom_caps.gamma2_2 = 0; 1818 dc->caps.color.dpp.ogam_rom_caps.pq = 0; 1819 dc->caps.color.dpp.ogam_rom_caps.hlg = 0; 1820 dc->caps.color.dpp.ocsc = 0; 1821 1822 dc->caps.color.mpc.gamut_remap = 1; 1823 dc->caps.color.mpc.num_3dluts = pool->base.res_cap->num_mpc_3dlut; //2 1824 dc->caps.color.mpc.ogam_ram = 1; 1825 dc->caps.color.mpc.ogam_rom_caps.srgb = 0; 1826 dc->caps.color.mpc.ogam_rom_caps.bt2020 = 0; 1827 dc->caps.color.mpc.ogam_rom_caps.gamma2_2 = 0; 1828 dc->caps.color.mpc.ogam_rom_caps.pq = 0; 1829 dc->caps.color.mpc.ogam_rom_caps.hlg = 0; 1830 dc->caps.color.mpc.ocsc = 1; 1831 1832 /* read VBIOS LTTPR caps */ 1833 { 1834 if (ctx->dc_bios->funcs->get_lttpr_caps) { 1835 enum bp_result bp_query_result; 1836 uint8_t is_vbios_lttpr_enable = 0; 1837 1838 bp_query_result = ctx->dc_bios->funcs->get_lttpr_caps(ctx->dc_bios, &is_vbios_lttpr_enable); 1839 dc->caps.vbios_lttpr_enable = (bp_query_result == BP_RESULT_OK) && !!is_vbios_lttpr_enable; 1840 } 1841 1842 /* interop bit is implicit */ 1843 { 1844 dc->caps.vbios_lttpr_aware = true; 1845 } 1846 } 1847 1848 if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV) 1849 dc->debug = debug_defaults_drv; 1850 else if (dc->ctx->dce_environment == DCE_ENV_FPGA_MAXIMUS) { 1851 dc->debug = debug_defaults_diags; 1852 } else 1853 dc->debug = debug_defaults_diags; 1854 // Init the vm_helper 1855 if (dc->vm_helper) 1856 vm_helper_init(dc->vm_helper, 16); 1857 1858 /************************************************* 1859 * Create resources * 1860 *************************************************/ 1861 1862 /* Clock Sources for Pixel Clock*/ 1863 pool->base.clock_sources[DCN31_CLK_SRC_PLL0] = 1864 dcn31_clock_source_create(ctx, ctx->dc_bios, 1865 CLOCK_SOURCE_COMBO_PHY_PLL0, 1866 &clk_src_regs[0], false); 1867 pool->base.clock_sources[DCN31_CLK_SRC_PLL1] = 1868 dcn31_clock_source_create(ctx, ctx->dc_bios, 1869 CLOCK_SOURCE_COMBO_PHY_PLL1, 1870 &clk_src_regs[1], false); 1871 pool->base.clock_sources[DCN31_CLK_SRC_PLL2] = 1872 dcn31_clock_source_create(ctx, ctx->dc_bios, 1873 CLOCK_SOURCE_COMBO_PHY_PLL2, 1874 &clk_src_regs[2], false); 1875 pool->base.clock_sources[DCN31_CLK_SRC_PLL3] = 1876 dcn31_clock_source_create(ctx, ctx->dc_bios, 1877 CLOCK_SOURCE_COMBO_PHY_PLL3, 1878 &clk_src_regs[3], false); 1879 pool->base.clock_sources[DCN31_CLK_SRC_PLL4] = 1880 dcn31_clock_source_create(ctx, ctx->dc_bios, 1881 CLOCK_SOURCE_COMBO_PHY_PLL4, 1882 &clk_src_regs[4], false); 1883 1884 pool->base.clk_src_count = DCN30_CLK_SRC_TOTAL; 1885 1886 /* todo: not reuse phy_pll registers */ 1887 pool->base.dp_clock_source = 1888 dcn31_clock_source_create(ctx, ctx->dc_bios, 1889 CLOCK_SOURCE_ID_DP_DTO, 1890 &clk_src_regs[0], true); 1891 1892 for (i = 0; i < pool->base.clk_src_count; i++) { 1893 if (pool->base.clock_sources[i] == NULL) { 1894 dm_error("DC: failed to create clock sources!\n"); 1895 BREAK_TO_DEBUGGER(); 1896 goto create_fail; 1897 } 1898 } 1899 1900 /* TODO: DCCG */ 1901 pool->base.dccg = dccg31_create(ctx, &dccg_regs, &dccg_shift, &dccg_mask); 1902 if (pool->base.dccg == NULL) { 1903 dm_error("DC: failed to create dccg!\n"); 1904 BREAK_TO_DEBUGGER(); 1905 goto create_fail; 1906 } 1907 1908 /* TODO: IRQ */ 1909 init_data.ctx = dc->ctx; 1910 pool->base.irqs = dal_irq_service_dcn315_create(&init_data); 1911 if (!pool->base.irqs) 1912 goto create_fail; 1913 1914 /* HUBBUB */ 1915 pool->base.hubbub = dcn31_hubbub_create(ctx); 1916 if (pool->base.hubbub == NULL) { 1917 BREAK_TO_DEBUGGER(); 1918 dm_error("DC: failed to create hubbub!\n"); 1919 goto create_fail; 1920 } 1921 1922 /* HUBPs, DPPs, OPPs and TGs */ 1923 for (i = 0; i < pool->base.pipe_count; i++) { 1924 pool->base.hubps[i] = dcn31_hubp_create(ctx, i); 1925 if (pool->base.hubps[i] == NULL) { 1926 BREAK_TO_DEBUGGER(); 1927 dm_error( 1928 "DC: failed to create hubps!\n"); 1929 goto create_fail; 1930 } 1931 1932 pool->base.dpps[i] = dcn31_dpp_create(ctx, i); 1933 if (pool->base.dpps[i] == NULL) { 1934 BREAK_TO_DEBUGGER(); 1935 dm_error( 1936 "DC: failed to create dpps!\n"); 1937 goto create_fail; 1938 } 1939 } 1940 1941 for (i = 0; i < pool->base.res_cap->num_opp; i++) { 1942 pool->base.opps[i] = dcn31_opp_create(ctx, i); 1943 if (pool->base.opps[i] == NULL) { 1944 BREAK_TO_DEBUGGER(); 1945 dm_error( 1946 "DC: failed to create output pixel processor!\n"); 1947 goto create_fail; 1948 } 1949 } 1950 1951 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { 1952 pool->base.timing_generators[i] = dcn31_timing_generator_create( 1953 ctx, i); 1954 if (pool->base.timing_generators[i] == NULL) { 1955 BREAK_TO_DEBUGGER(); 1956 dm_error("DC: failed to create tg!\n"); 1957 goto create_fail; 1958 } 1959 } 1960 pool->base.timing_generator_count = i; 1961 1962 /* PSR */ 1963 pool->base.psr = dmub_psr_create(ctx); 1964 if (pool->base.psr == NULL) { 1965 dm_error("DC: failed to create psr obj!\n"); 1966 BREAK_TO_DEBUGGER(); 1967 goto create_fail; 1968 } 1969 1970 /* ABM */ 1971 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { 1972 pool->base.multiple_abms[i] = dmub_abm_create(ctx, 1973 &abm_regs[i], 1974 &abm_shift, 1975 &abm_mask); 1976 if (pool->base.multiple_abms[i] == NULL) { 1977 dm_error("DC: failed to create abm for pipe %d!\n", i); 1978 BREAK_TO_DEBUGGER(); 1979 goto create_fail; 1980 } 1981 } 1982 1983 /* MPC and DSC */ 1984 pool->base.mpc = dcn31_mpc_create(ctx, pool->base.mpcc_count, pool->base.res_cap->num_mpc_3dlut); 1985 if (pool->base.mpc == NULL) { 1986 BREAK_TO_DEBUGGER(); 1987 dm_error("DC: failed to create mpc!\n"); 1988 goto create_fail; 1989 } 1990 1991 for (i = 0; i < pool->base.res_cap->num_dsc; i++) { 1992 pool->base.dscs[i] = dcn31_dsc_create(ctx, i); 1993 if (pool->base.dscs[i] == NULL) { 1994 BREAK_TO_DEBUGGER(); 1995 dm_error("DC: failed to create display stream compressor %d!\n", i); 1996 goto create_fail; 1997 } 1998 } 1999 2000 /* DWB and MMHUBBUB */ 2001 if (!dcn31_dwbc_create(ctx, &pool->base)) { 2002 BREAK_TO_DEBUGGER(); 2003 dm_error("DC: failed to create dwbc!\n"); 2004 goto create_fail; 2005 } 2006 2007 if (!dcn31_mmhubbub_create(ctx, &pool->base)) { 2008 BREAK_TO_DEBUGGER(); 2009 dm_error("DC: failed to create mcif_wb!\n"); 2010 goto create_fail; 2011 } 2012 2013 /* AUX and I2C */ 2014 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { 2015 pool->base.engines[i] = dcn31_aux_engine_create(ctx, i); 2016 if (pool->base.engines[i] == NULL) { 2017 BREAK_TO_DEBUGGER(); 2018 dm_error( 2019 "DC:failed to create aux engine!!\n"); 2020 goto create_fail; 2021 } 2022 pool->base.hw_i2cs[i] = dcn31_i2c_hw_create(ctx, i); 2023 if (pool->base.hw_i2cs[i] == NULL) { 2024 BREAK_TO_DEBUGGER(); 2025 dm_error( 2026 "DC:failed to create hw i2c!!\n"); 2027 goto create_fail; 2028 } 2029 pool->base.sw_i2cs[i] = NULL; 2030 } 2031 2032 /* Audio, Stream Encoders including HPO and virtual, MPC 3D LUTs */ 2033 if (!resource_construct(num_virtual_links, dc, &pool->base, 2034 (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment) ? 2035 &res_create_funcs : &res_create_maximus_funcs))) 2036 goto create_fail; 2037 2038 /* HW Sequencer and Plane caps */ 2039 dcn31_hw_sequencer_construct(dc); 2040 2041 dc->caps.max_planes = pool->base.pipe_count; 2042 2043 for (i = 0; i < dc->caps.max_planes; ++i) 2044 dc->caps.planes[i] = plane_cap; 2045 2046 dc->cap_funcs = cap_funcs; 2047 2048 dc->dcn_ip->max_num_dpp = dcn3_15_ip.max_num_dpp; 2049 2050 return true; 2051 2052 create_fail: 2053 2054 dcn315_resource_destruct(pool); 2055 2056 return false; 2057 } 2058 2059 struct resource_pool *dcn315_create_resource_pool( 2060 const struct dc_init_data *init_data, 2061 struct dc *dc) 2062 { 2063 struct dcn315_resource_pool *pool = 2064 kzalloc(sizeof(struct dcn315_resource_pool), GFP_KERNEL); 2065 2066 if (!pool) 2067 return NULL; 2068 2069 if (dcn315_resource_construct(init_data->num_virtual_links, dc, pool)) 2070 return &pool->base; 2071 2072 BREAK_TO_DEBUGGER(); 2073 kfree(pool); 2074 return NULL; 2075 } 2076