1 /* 2 * Copyright 2021 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 27 #include "dm_services.h" 28 #include "dc.h" 29 30 #include "dcn31/dcn31_init.h" 31 32 #include "resource.h" 33 #include "include/irq_service_interface.h" 34 #include "dcn315_resource.h" 35 36 #include "dcn20/dcn20_resource.h" 37 #include "dcn30/dcn30_resource.h" 38 #include "dcn31/dcn31_resource.h" 39 40 #include "dcn10/dcn10_ipp.h" 41 #include "dcn30/dcn30_hubbub.h" 42 #include "dcn31/dcn31_hubbub.h" 43 #include "dcn30/dcn30_mpc.h" 44 #include "dcn31/dcn31_hubp.h" 45 #include "irq/dcn315/irq_service_dcn315.h" 46 #include "dcn30/dcn30_dpp.h" 47 #include "dcn31/dcn31_optc.h" 48 #include "dcn20/dcn20_hwseq.h" 49 #include "dcn30/dcn30_hwseq.h" 50 #include "dce110/dce110_hw_sequencer.h" 51 #include "dcn30/dcn30_opp.h" 52 #include "dcn20/dcn20_dsc.h" 53 #include "dcn30/dcn30_vpg.h" 54 #include "dcn30/dcn30_afmt.h" 55 #include "dcn30/dcn30_dio_stream_encoder.h" 56 #include "dcn31/dcn31_hpo_dp_stream_encoder.h" 57 #include "dcn31/dcn31_hpo_dp_link_encoder.h" 58 #include "dcn31/dcn31_apg.h" 59 #include "dcn31/dcn31_dio_link_encoder.h" 60 #include "dcn31/dcn31_vpg.h" 61 #include "dcn31/dcn31_afmt.h" 62 #include "dce/dce_clock_source.h" 63 #include "dce/dce_audio.h" 64 #include "dce/dce_hwseq.h" 65 #include "clk_mgr.h" 66 #include "virtual/virtual_stream_encoder.h" 67 #include "dce110/dce110_resource.h" 68 #include "dml/display_mode_vba.h" 69 #include "dcn31/dcn31_dccg.h" 70 #include "dcn10/dcn10_resource.h" 71 #include "dcn31/dcn31_panel_cntl.h" 72 73 #include "dcn30/dcn30_dwb.h" 74 #include "dcn30/dcn30_mmhubbub.h" 75 76 #include "dcn/dcn_3_1_5_offset.h" 77 #include "dcn/dcn_3_1_5_sh_mask.h" 78 #include "dpcs/dpcs_4_2_2_offset.h" 79 #include "dpcs/dpcs_4_2_2_sh_mask.h" 80 81 #define NBIO_BASE__INST0_SEG0 0x00000000 82 #define NBIO_BASE__INST0_SEG1 0x00000014 83 #define NBIO_BASE__INST0_SEG2 0x00000D20 84 #define NBIO_BASE__INST0_SEG3 0x00010400 85 #define NBIO_BASE__INST0_SEG4 0x0241B000 86 #define NBIO_BASE__INST0_SEG5 0x04040000 87 88 #define DPCS_BASE__INST0_SEG0 0x00000012 89 #define DPCS_BASE__INST0_SEG1 0x000000C0 90 #define DPCS_BASE__INST0_SEG2 0x000034C0 91 #define DPCS_BASE__INST0_SEG3 0x00009000 92 #define DPCS_BASE__INST0_SEG4 0x02403C00 93 #define DPCS_BASE__INST0_SEG5 0 94 95 #define DCN_BASE__INST0_SEG0 0x00000012 96 #define DCN_BASE__INST0_SEG1 0x000000C0 97 #define DCN_BASE__INST0_SEG2 0x000034C0 98 #define DCN_BASE__INST0_SEG3 0x00009000 99 #define DCN_BASE__INST0_SEG4 0x02403C00 100 #define DCN_BASE__INST0_SEG5 0 101 102 #define regBIF_BX_PF2_RSMU_INDEX 0x0000 103 #define regBIF_BX_PF2_RSMU_INDEX_BASE_IDX 1 104 #define regBIF_BX_PF2_RSMU_DATA 0x0001 105 #define regBIF_BX_PF2_RSMU_DATA_BASE_IDX 1 106 #define regBIF_BX2_BIOS_SCRATCH_6 0x003e 107 #define regBIF_BX2_BIOS_SCRATCH_6_BASE_IDX 1 108 #define BIF_BX2_BIOS_SCRATCH_6__BIOS_SCRATCH_6__SHIFT 0x0 109 #define BIF_BX2_BIOS_SCRATCH_6__BIOS_SCRATCH_6_MASK 0xFFFFFFFFL 110 #define regBIF_BX2_BIOS_SCRATCH_2 0x003a 111 #define regBIF_BX2_BIOS_SCRATCH_2_BASE_IDX 1 112 #define BIF_BX2_BIOS_SCRATCH_2__BIOS_SCRATCH_2__SHIFT 0x0 113 #define BIF_BX2_BIOS_SCRATCH_2__BIOS_SCRATCH_2_MASK 0xFFFFFFFFL 114 #define regBIF_BX2_BIOS_SCRATCH_3 0x003b 115 #define regBIF_BX2_BIOS_SCRATCH_3_BASE_IDX 1 116 #define BIF_BX2_BIOS_SCRATCH_3__BIOS_SCRATCH_3__SHIFT 0x0 117 #define BIF_BX2_BIOS_SCRATCH_3__BIOS_SCRATCH_3_MASK 0xFFFFFFFFL 118 119 #define regDCHUBBUB_DEBUG_CTRL_0 0x04d6 120 #define regDCHUBBUB_DEBUG_CTRL_0_BASE_IDX 2 121 #define DCHUBBUB_DEBUG_CTRL_0__DET_DEPTH__SHIFT 0x10 122 #define DCHUBBUB_DEBUG_CTRL_0__DET_DEPTH_MASK 0x01FF0000L 123 124 #include "reg_helper.h" 125 #include "dce/dmub_abm.h" 126 #include "dce/dmub_psr.h" 127 #include "dce/dce_aux.h" 128 #include "dce/dce_i2c.h" 129 130 #include "dml/dcn30/display_mode_vba_30.h" 131 #include "vm_helper.h" 132 #include "dcn20/dcn20_vmid.h" 133 134 #include "link_enc_cfg.h" 135 136 #define DC_LOGGER_INIT(logger) 137 138 #define DCN3_15_DEFAULT_DET_SIZE 192 139 #define DCN3_15_MAX_DET_SIZE 384 140 #define DCN3_15_MIN_COMPBUF_SIZE_KB 128 141 #define DCN3_15_CRB_SEGMENT_SIZE_KB 64 142 143 struct _vcs_dpi_ip_params_st dcn3_15_ip = { 144 .gpuvm_enable = 1, 145 .gpuvm_max_page_table_levels = 1, 146 .hostvm_enable = 1, 147 .hostvm_max_page_table_levels = 2, 148 .rob_buffer_size_kbytes = 64, 149 .det_buffer_size_kbytes = DCN3_15_DEFAULT_DET_SIZE, 150 .config_return_buffer_size_in_kbytes = 1024, 151 .compressed_buffer_segment_size_in_kbytes = 64, 152 .meta_fifo_size_in_kentries = 32, 153 .zero_size_buffer_entries = 512, 154 .compbuf_reserved_space_64b = 256, 155 .compbuf_reserved_space_zs = 64, 156 .dpp_output_buffer_pixels = 2560, 157 .opp_output_buffer_lines = 1, 158 .pixel_chunk_size_kbytes = 8, 159 .meta_chunk_size_kbytes = 2, 160 .min_meta_chunk_size_bytes = 256, 161 .writeback_chunk_size_kbytes = 8, 162 .ptoi_supported = false, 163 .num_dsc = 3, 164 .maximum_dsc_bits_per_component = 10, 165 .dsc422_native_support = false, 166 .is_line_buffer_bpp_fixed = true, 167 .line_buffer_fixed_bpp = 49, 168 .line_buffer_size_bits = 789504, 169 .max_line_buffer_lines = 12, 170 .writeback_interface_buffer_size_kbytes = 90, 171 .max_num_dpp = 4, 172 .max_num_otg = 4, 173 .max_num_hdmi_frl_outputs = 1, 174 .max_num_wb = 1, 175 .max_dchub_pscl_bw_pix_per_clk = 4, 176 .max_pscl_lb_bw_pix_per_clk = 2, 177 .max_lb_vscl_bw_pix_per_clk = 4, 178 .max_vscl_hscl_bw_pix_per_clk = 4, 179 .max_hscl_ratio = 6, 180 .max_vscl_ratio = 6, 181 .max_hscl_taps = 8, 182 .max_vscl_taps = 8, 183 .dpte_buffer_size_in_pte_reqs_luma = 64, 184 .dpte_buffer_size_in_pte_reqs_chroma = 34, 185 .dispclk_ramp_margin_percent = 1, 186 .max_inter_dcn_tile_repeaters = 9, 187 .cursor_buffer_size = 16, 188 .cursor_chunk_size = 2, 189 .writeback_line_buffer_buffer_size = 0, 190 .writeback_min_hscl_ratio = 1, 191 .writeback_min_vscl_ratio = 1, 192 .writeback_max_hscl_ratio = 1, 193 .writeback_max_vscl_ratio = 1, 194 .writeback_max_hscl_taps = 1, 195 .writeback_max_vscl_taps = 1, 196 .dppclk_delay_subtotal = 46, 197 .dppclk_delay_scl = 50, 198 .dppclk_delay_scl_lb_only = 16, 199 .dppclk_delay_cnvc_formatter = 27, 200 .dppclk_delay_cnvc_cursor = 6, 201 .dispclk_delay_subtotal = 119, 202 .dynamic_metadata_vm_enabled = false, 203 .odm_combine_4to1_supported = false, 204 .dcc_supported = true, 205 }; 206 207 struct _vcs_dpi_soc_bounding_box_st dcn3_15_soc = { 208 /*TODO: correct dispclk/dppclk voltage level determination*/ 209 .clock_limits = { 210 { 211 .state = 0, 212 .dispclk_mhz = 1372.0, 213 .dppclk_mhz = 1372.0, 214 .phyclk_mhz = 810.0, 215 .phyclk_d18_mhz = 667.0, 216 .dscclk_mhz = 417.0, 217 .dtbclk_mhz = 600.0, 218 }, 219 { 220 .state = 1, 221 .dispclk_mhz = 1372.0, 222 .dppclk_mhz = 1372.0, 223 .phyclk_mhz = 810.0, 224 .phyclk_d18_mhz = 667.0, 225 .dscclk_mhz = 417.0, 226 .dtbclk_mhz = 600.0, 227 }, 228 { 229 .state = 2, 230 .dispclk_mhz = 1372.0, 231 .dppclk_mhz = 1372.0, 232 .phyclk_mhz = 810.0, 233 .phyclk_d18_mhz = 667.0, 234 .dscclk_mhz = 417.0, 235 .dtbclk_mhz = 600.0, 236 }, 237 { 238 .state = 3, 239 .dispclk_mhz = 1372.0, 240 .dppclk_mhz = 1372.0, 241 .phyclk_mhz = 810.0, 242 .phyclk_d18_mhz = 667.0, 243 .dscclk_mhz = 417.0, 244 .dtbclk_mhz = 600.0, 245 }, 246 { 247 .state = 4, 248 .dispclk_mhz = 1372.0, 249 .dppclk_mhz = 1372.0, 250 .phyclk_mhz = 810.0, 251 .phyclk_d18_mhz = 667.0, 252 .dscclk_mhz = 417.0, 253 .dtbclk_mhz = 600.0, 254 }, 255 }, 256 .num_states = 5, 257 .sr_exit_time_us = 9.0, 258 .sr_enter_plus_exit_time_us = 11.0, 259 .sr_exit_z8_time_us = 50.0, 260 .sr_enter_plus_exit_z8_time_us = 50.0, 261 .writeback_latency_us = 12.0, 262 .dram_channel_width_bytes = 4, 263 .round_trip_ping_latency_dcfclk_cycles = 106, 264 .urgent_latency_pixel_data_only_us = 4.0, 265 .urgent_latency_pixel_mixed_with_vm_data_us = 4.0, 266 .urgent_latency_vm_data_only_us = 4.0, 267 .urgent_out_of_order_return_per_channel_pixel_only_bytes = 4096, 268 .urgent_out_of_order_return_per_channel_pixel_and_vm_bytes = 4096, 269 .urgent_out_of_order_return_per_channel_vm_only_bytes = 4096, 270 .pct_ideal_sdp_bw_after_urgent = 80.0, 271 .pct_ideal_dram_sdp_bw_after_urgent_pixel_only = 65.0, 272 .pct_ideal_dram_sdp_bw_after_urgent_pixel_and_vm = 60.0, 273 .pct_ideal_dram_sdp_bw_after_urgent_vm_only = 30.0, 274 .max_avg_sdp_bw_use_normal_percent = 60.0, 275 .max_avg_dram_bw_use_normal_percent = 30.0, 276 .fabric_datapath_to_dcn_data_return_bytes = 32, 277 .return_bus_width_bytes = 64, 278 .downspread_percent = 0.38, 279 .dcn_downspread_percent = 0.38, 280 .gpuvm_min_page_size_bytes = 4096, 281 .hostvm_min_page_size_bytes = 4096, 282 .do_urgent_latency_adjustment = false, 283 .urgent_latency_adjustment_fabric_clock_component_us = 0, 284 .urgent_latency_adjustment_fabric_clock_reference_mhz = 0, 285 }; 286 287 enum dcn31_clk_src_array_id { 288 DCN31_CLK_SRC_PLL0, 289 DCN31_CLK_SRC_PLL1, 290 DCN31_CLK_SRC_PLL2, 291 DCN31_CLK_SRC_PLL3, 292 DCN31_CLK_SRC_PLL4, 293 DCN30_CLK_SRC_TOTAL 294 }; 295 296 /* begin ********************* 297 * macros to expend register list macro defined in HW object header file 298 */ 299 300 /* DCN */ 301 /* TODO awful hack. fixup dcn20_dwb.h */ 302 #undef BASE_INNER 303 #define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg 304 305 #define BASE(seg) BASE_INNER(seg) 306 307 #define SR(reg_name)\ 308 .reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \ 309 reg ## reg_name 310 311 #define SRI(reg_name, block, id)\ 312 .reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 313 reg ## block ## id ## _ ## reg_name 314 315 #define SRI2(reg_name, block, id)\ 316 .reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \ 317 reg ## reg_name 318 319 #define SRIR(var_name, reg_name, block, id)\ 320 .var_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 321 reg ## block ## id ## _ ## reg_name 322 323 #define SRII(reg_name, block, id)\ 324 .reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 325 reg ## block ## id ## _ ## reg_name 326 327 #define SRII_MPC_RMU(reg_name, block, id)\ 328 .RMU##_##reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 329 reg ## block ## id ## _ ## reg_name 330 331 #define SRII_DWB(reg_name, temp_name, block, id)\ 332 .reg_name[id] = BASE(reg ## block ## id ## _ ## temp_name ## _BASE_IDX) + \ 333 reg ## block ## id ## _ ## temp_name 334 335 #define DCCG_SRII(reg_name, block, id)\ 336 .block ## _ ## reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 337 reg ## block ## id ## _ ## reg_name 338 339 #define VUPDATE_SRII(reg_name, block, id)\ 340 .reg_name[id] = BASE(reg ## reg_name ## _ ## block ## id ## _BASE_IDX) + \ 341 reg ## reg_name ## _ ## block ## id 342 343 /* NBIO */ 344 #define NBIO_BASE_INNER(seg) \ 345 NBIO_BASE__INST0_SEG ## seg 346 347 #define NBIO_BASE(seg) \ 348 NBIO_BASE_INNER(seg) 349 350 #define NBIO_SR(reg_name)\ 351 .reg_name = NBIO_BASE(regBIF_BX2_ ## reg_name ## _BASE_IDX) + \ 352 regBIF_BX2_ ## reg_name 353 354 static const struct bios_registers bios_regs = { 355 NBIO_SR(BIOS_SCRATCH_3), 356 NBIO_SR(BIOS_SCRATCH_6) 357 }; 358 359 #define clk_src_regs(index, pllid)\ 360 [index] = {\ 361 CS_COMMON_REG_LIST_DCN3_0(index, pllid),\ 362 } 363 364 static const struct dce110_clk_src_regs clk_src_regs[] = { 365 clk_src_regs(0, A), 366 clk_src_regs(1, B), 367 clk_src_regs(2, C), 368 clk_src_regs(3, D), 369 clk_src_regs(4, E) 370 }; 371 372 static const struct dce110_clk_src_shift cs_shift = { 373 CS_COMMON_MASK_SH_LIST_DCN2_0(__SHIFT) 374 }; 375 376 static const struct dce110_clk_src_mask cs_mask = { 377 CS_COMMON_MASK_SH_LIST_DCN2_0(_MASK) 378 }; 379 380 #define abm_regs(id)\ 381 [id] = {\ 382 ABM_DCN302_REG_LIST(id)\ 383 } 384 385 static const struct dce_abm_registers abm_regs[] = { 386 abm_regs(0), 387 abm_regs(1), 388 abm_regs(2), 389 abm_regs(3), 390 }; 391 392 static const struct dce_abm_shift abm_shift = { 393 ABM_MASK_SH_LIST_DCN30(__SHIFT) 394 }; 395 396 static const struct dce_abm_mask abm_mask = { 397 ABM_MASK_SH_LIST_DCN30(_MASK) 398 }; 399 400 #define audio_regs(id)\ 401 [id] = {\ 402 AUD_COMMON_REG_LIST(id)\ 403 } 404 405 static const struct dce_audio_registers audio_regs[] = { 406 audio_regs(0), 407 audio_regs(1), 408 audio_regs(2), 409 audio_regs(3), 410 audio_regs(4), 411 audio_regs(5), 412 audio_regs(6) 413 }; 414 415 #define DCE120_AUD_COMMON_MASK_SH_LIST(mask_sh)\ 416 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX, AZALIA_ENDPOINT_REG_INDEX, mask_sh),\ 417 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA, AZALIA_ENDPOINT_REG_DATA, mask_sh),\ 418 AUD_COMMON_MASK_SH_LIST_BASE(mask_sh) 419 420 static const struct dce_audio_shift audio_shift = { 421 DCE120_AUD_COMMON_MASK_SH_LIST(__SHIFT) 422 }; 423 424 static const struct dce_audio_mask audio_mask = { 425 DCE120_AUD_COMMON_MASK_SH_LIST(_MASK) 426 }; 427 428 #define vpg_regs(id)\ 429 [id] = {\ 430 VPG_DCN31_REG_LIST(id)\ 431 } 432 433 static const struct dcn31_vpg_registers vpg_regs[] = { 434 vpg_regs(0), 435 vpg_regs(1), 436 vpg_regs(2), 437 vpg_regs(3), 438 vpg_regs(4), 439 vpg_regs(5), 440 vpg_regs(6), 441 vpg_regs(7), 442 vpg_regs(8), 443 vpg_regs(9), 444 }; 445 446 static const struct dcn31_vpg_shift vpg_shift = { 447 DCN31_VPG_MASK_SH_LIST(__SHIFT) 448 }; 449 450 static const struct dcn31_vpg_mask vpg_mask = { 451 DCN31_VPG_MASK_SH_LIST(_MASK) 452 }; 453 454 #define afmt_regs(id)\ 455 [id] = {\ 456 AFMT_DCN31_REG_LIST(id)\ 457 } 458 459 static const struct dcn31_afmt_registers afmt_regs[] = { 460 afmt_regs(0), 461 afmt_regs(1), 462 afmt_regs(2), 463 afmt_regs(3), 464 afmt_regs(4), 465 afmt_regs(5) 466 }; 467 468 static const struct dcn31_afmt_shift afmt_shift = { 469 DCN31_AFMT_MASK_SH_LIST(__SHIFT) 470 }; 471 472 static const struct dcn31_afmt_mask afmt_mask = { 473 DCN31_AFMT_MASK_SH_LIST(_MASK) 474 }; 475 476 #define apg_regs(id)\ 477 [id] = {\ 478 APG_DCN31_REG_LIST(id)\ 479 } 480 481 static const struct dcn31_apg_registers apg_regs[] = { 482 apg_regs(0), 483 apg_regs(1), 484 apg_regs(2), 485 apg_regs(3) 486 }; 487 488 static const struct dcn31_apg_shift apg_shift = { 489 DCN31_APG_MASK_SH_LIST(__SHIFT) 490 }; 491 492 static const struct dcn31_apg_mask apg_mask = { 493 DCN31_APG_MASK_SH_LIST(_MASK) 494 }; 495 496 #define stream_enc_regs(id)\ 497 [id] = {\ 498 SE_DCN3_REG_LIST(id)\ 499 } 500 501 static const struct dcn10_stream_enc_registers stream_enc_regs[] = { 502 stream_enc_regs(0), 503 stream_enc_regs(1), 504 stream_enc_regs(2), 505 stream_enc_regs(3), 506 stream_enc_regs(4) 507 }; 508 509 static const struct dcn10_stream_encoder_shift se_shift = { 510 SE_COMMON_MASK_SH_LIST_DCN30(__SHIFT) 511 }; 512 513 static const struct dcn10_stream_encoder_mask se_mask = { 514 SE_COMMON_MASK_SH_LIST_DCN30(_MASK) 515 }; 516 517 518 #define aux_regs(id)\ 519 [id] = {\ 520 DCN2_AUX_REG_LIST(id)\ 521 } 522 523 static const struct dcn10_link_enc_aux_registers link_enc_aux_regs[] = { 524 aux_regs(0), 525 aux_regs(1), 526 aux_regs(2), 527 aux_regs(3), 528 aux_regs(4) 529 }; 530 531 #define hpd_regs(id)\ 532 [id] = {\ 533 HPD_REG_LIST(id)\ 534 } 535 536 static const struct dcn10_link_enc_hpd_registers link_enc_hpd_regs[] = { 537 hpd_regs(0), 538 hpd_regs(1), 539 hpd_regs(2), 540 hpd_regs(3), 541 hpd_regs(4) 542 }; 543 544 #define link_regs(id, phyid)\ 545 [id] = {\ 546 LE_DCN31_REG_LIST(id), \ 547 UNIPHY_DCN2_REG_LIST(phyid), \ 548 DPCS_DCN31_REG_LIST(id), \ 549 } 550 551 static const struct dce110_aux_registers_shift aux_shift = { 552 DCN_AUX_MASK_SH_LIST(__SHIFT) 553 }; 554 555 static const struct dce110_aux_registers_mask aux_mask = { 556 DCN_AUX_MASK_SH_LIST(_MASK) 557 }; 558 559 static const struct dcn10_link_enc_registers link_enc_regs[] = { 560 link_regs(0, A), 561 link_regs(1, B), 562 link_regs(2, C), 563 link_regs(3, D), 564 link_regs(4, E) 565 }; 566 567 static const struct dcn10_link_enc_shift le_shift = { 568 LINK_ENCODER_MASK_SH_LIST_DCN31(__SHIFT), \ 569 DPCS_DCN31_MASK_SH_LIST(__SHIFT) 570 }; 571 572 static const struct dcn10_link_enc_mask le_mask = { 573 LINK_ENCODER_MASK_SH_LIST_DCN31(_MASK), \ 574 DPCS_DCN31_MASK_SH_LIST(_MASK) 575 }; 576 577 #define hpo_dp_stream_encoder_reg_list(id)\ 578 [id] = {\ 579 DCN3_1_HPO_DP_STREAM_ENC_REG_LIST(id)\ 580 } 581 582 static const struct dcn31_hpo_dp_stream_encoder_registers hpo_dp_stream_enc_regs[] = { 583 hpo_dp_stream_encoder_reg_list(0), 584 hpo_dp_stream_encoder_reg_list(1), 585 hpo_dp_stream_encoder_reg_list(2), 586 hpo_dp_stream_encoder_reg_list(3), 587 }; 588 589 static const struct dcn31_hpo_dp_stream_encoder_shift hpo_dp_se_shift = { 590 DCN3_1_HPO_DP_STREAM_ENC_MASK_SH_LIST(__SHIFT) 591 }; 592 593 static const struct dcn31_hpo_dp_stream_encoder_mask hpo_dp_se_mask = { 594 DCN3_1_HPO_DP_STREAM_ENC_MASK_SH_LIST(_MASK) 595 }; 596 597 598 #define hpo_dp_link_encoder_reg_list(id)\ 599 [id] = {\ 600 DCN3_1_HPO_DP_LINK_ENC_REG_LIST(id),\ 601 DCN3_1_RDPCSTX_REG_LIST(0),\ 602 DCN3_1_RDPCSTX_REG_LIST(1),\ 603 DCN3_1_RDPCSTX_REG_LIST(2),\ 604 DCN3_1_RDPCSTX_REG_LIST(3),\ 605 DCN3_1_RDPCSTX_REG_LIST(4)\ 606 } 607 608 static const struct dcn31_hpo_dp_link_encoder_registers hpo_dp_link_enc_regs[] = { 609 hpo_dp_link_encoder_reg_list(0), 610 hpo_dp_link_encoder_reg_list(1), 611 }; 612 613 static const struct dcn31_hpo_dp_link_encoder_shift hpo_dp_le_shift = { 614 DCN3_1_HPO_DP_LINK_ENC_MASK_SH_LIST(__SHIFT) 615 }; 616 617 static const struct dcn31_hpo_dp_link_encoder_mask hpo_dp_le_mask = { 618 DCN3_1_HPO_DP_LINK_ENC_MASK_SH_LIST(_MASK) 619 }; 620 621 #define dpp_regs(id)\ 622 [id] = {\ 623 DPP_REG_LIST_DCN30(id),\ 624 } 625 626 static const struct dcn3_dpp_registers dpp_regs[] = { 627 dpp_regs(0), 628 dpp_regs(1), 629 dpp_regs(2), 630 dpp_regs(3) 631 }; 632 633 static const struct dcn3_dpp_shift tf_shift = { 634 DPP_REG_LIST_SH_MASK_DCN30(__SHIFT) 635 }; 636 637 static const struct dcn3_dpp_mask tf_mask = { 638 DPP_REG_LIST_SH_MASK_DCN30(_MASK) 639 }; 640 641 #define opp_regs(id)\ 642 [id] = {\ 643 OPP_REG_LIST_DCN30(id),\ 644 } 645 646 static const struct dcn20_opp_registers opp_regs[] = { 647 opp_regs(0), 648 opp_regs(1), 649 opp_regs(2), 650 opp_regs(3) 651 }; 652 653 static const struct dcn20_opp_shift opp_shift = { 654 OPP_MASK_SH_LIST_DCN20(__SHIFT) 655 }; 656 657 static const struct dcn20_opp_mask opp_mask = { 658 OPP_MASK_SH_LIST_DCN20(_MASK) 659 }; 660 661 #define aux_engine_regs(id)\ 662 [id] = {\ 663 AUX_COMMON_REG_LIST0(id), \ 664 .AUXN_IMPCAL = 0, \ 665 .AUXP_IMPCAL = 0, \ 666 .AUX_RESET_MASK = DP_AUX0_AUX_CONTROL__AUX_RESET_MASK, \ 667 } 668 669 static const struct dce110_aux_registers aux_engine_regs[] = { 670 aux_engine_regs(0), 671 aux_engine_regs(1), 672 aux_engine_regs(2), 673 aux_engine_regs(3), 674 aux_engine_regs(4) 675 }; 676 677 #define dwbc_regs_dcn3(id)\ 678 [id] = {\ 679 DWBC_COMMON_REG_LIST_DCN30(id),\ 680 } 681 682 static const struct dcn30_dwbc_registers dwbc30_regs[] = { 683 dwbc_regs_dcn3(0), 684 }; 685 686 static const struct dcn30_dwbc_shift dwbc30_shift = { 687 DWBC_COMMON_MASK_SH_LIST_DCN30(__SHIFT) 688 }; 689 690 static const struct dcn30_dwbc_mask dwbc30_mask = { 691 DWBC_COMMON_MASK_SH_LIST_DCN30(_MASK) 692 }; 693 694 #define mcif_wb_regs_dcn3(id)\ 695 [id] = {\ 696 MCIF_WB_COMMON_REG_LIST_DCN30(id),\ 697 } 698 699 static const struct dcn30_mmhubbub_registers mcif_wb30_regs[] = { 700 mcif_wb_regs_dcn3(0) 701 }; 702 703 static const struct dcn30_mmhubbub_shift mcif_wb30_shift = { 704 MCIF_WB_COMMON_MASK_SH_LIST_DCN30(__SHIFT) 705 }; 706 707 static const struct dcn30_mmhubbub_mask mcif_wb30_mask = { 708 MCIF_WB_COMMON_MASK_SH_LIST_DCN30(_MASK) 709 }; 710 711 #define dsc_regsDCN20(id)\ 712 [id] = {\ 713 DSC_REG_LIST_DCN20(id)\ 714 } 715 716 static const struct dcn20_dsc_registers dsc_regs[] = { 717 dsc_regsDCN20(0), 718 dsc_regsDCN20(1), 719 dsc_regsDCN20(2) 720 }; 721 722 static const struct dcn20_dsc_shift dsc_shift = { 723 DSC_REG_LIST_SH_MASK_DCN20(__SHIFT) 724 }; 725 726 static const struct dcn20_dsc_mask dsc_mask = { 727 DSC_REG_LIST_SH_MASK_DCN20(_MASK) 728 }; 729 730 static const struct dcn30_mpc_registers mpc_regs = { 731 MPC_REG_LIST_DCN3_0(0), 732 MPC_REG_LIST_DCN3_0(1), 733 MPC_REG_LIST_DCN3_0(2), 734 MPC_REG_LIST_DCN3_0(3), 735 MPC_OUT_MUX_REG_LIST_DCN3_0(0), 736 MPC_OUT_MUX_REG_LIST_DCN3_0(1), 737 MPC_OUT_MUX_REG_LIST_DCN3_0(2), 738 MPC_OUT_MUX_REG_LIST_DCN3_0(3), 739 MPC_DWB_MUX_REG_LIST_DCN3_0(0), 740 }; 741 742 static const struct dcn30_mpc_shift mpc_shift = { 743 MPC_COMMON_MASK_SH_LIST_DCN30(__SHIFT) 744 }; 745 746 static const struct dcn30_mpc_mask mpc_mask = { 747 MPC_COMMON_MASK_SH_LIST_DCN30(_MASK) 748 }; 749 750 #define optc_regs(id)\ 751 [id] = {OPTC_COMMON_REG_LIST_DCN3_1(id)} 752 753 static const struct dcn_optc_registers optc_regs[] = { 754 optc_regs(0), 755 optc_regs(1), 756 optc_regs(2), 757 optc_regs(3) 758 }; 759 760 static const struct dcn_optc_shift optc_shift = { 761 OPTC_COMMON_MASK_SH_LIST_DCN3_1(__SHIFT) 762 }; 763 764 static const struct dcn_optc_mask optc_mask = { 765 OPTC_COMMON_MASK_SH_LIST_DCN3_1(_MASK) 766 }; 767 768 #define hubp_regs(id)\ 769 [id] = {\ 770 HUBP_REG_LIST_DCN30(id)\ 771 } 772 773 static const struct dcn_hubp2_registers hubp_regs[] = { 774 hubp_regs(0), 775 hubp_regs(1), 776 hubp_regs(2), 777 hubp_regs(3) 778 }; 779 780 781 static const struct dcn_hubp2_shift hubp_shift = { 782 HUBP_MASK_SH_LIST_DCN31(__SHIFT) 783 }; 784 785 static const struct dcn_hubp2_mask hubp_mask = { 786 HUBP_MASK_SH_LIST_DCN31(_MASK) 787 }; 788 static const struct dcn_hubbub_registers hubbub_reg = { 789 HUBBUB_REG_LIST_DCN31(0) 790 }; 791 792 static const struct dcn_hubbub_shift hubbub_shift = { 793 HUBBUB_MASK_SH_LIST_DCN31(__SHIFT) 794 }; 795 796 static const struct dcn_hubbub_mask hubbub_mask = { 797 HUBBUB_MASK_SH_LIST_DCN31(_MASK) 798 }; 799 800 static const struct dccg_registers dccg_regs = { 801 DCCG_REG_LIST_DCN31() 802 }; 803 804 static const struct dccg_shift dccg_shift = { 805 DCCG_MASK_SH_LIST_DCN31(__SHIFT) 806 }; 807 808 static const struct dccg_mask dccg_mask = { 809 DCCG_MASK_SH_LIST_DCN31(_MASK) 810 }; 811 812 813 #define SRII2(reg_name_pre, reg_name_post, id)\ 814 .reg_name_pre ## _ ## reg_name_post[id] = BASE(reg ## reg_name_pre \ 815 ## id ## _ ## reg_name_post ## _BASE_IDX) + \ 816 reg ## reg_name_pre ## id ## _ ## reg_name_post 817 818 819 #define HWSEQ_DCN31_REG_LIST()\ 820 SR(DCHUBBUB_GLOBAL_TIMER_CNTL), \ 821 SR(DCHUBBUB_ARB_HOSTVM_CNTL), \ 822 SR(DIO_MEM_PWR_CTRL), \ 823 SR(ODM_MEM_PWR_CTRL3), \ 824 SR(DMU_MEM_PWR_CNTL), \ 825 SR(MMHUBBUB_MEM_PWR_CNTL), \ 826 SR(DCCG_GATE_DISABLE_CNTL), \ 827 SR(DCCG_GATE_DISABLE_CNTL2), \ 828 SR(DCFCLK_CNTL),\ 829 SR(DC_MEM_GLOBAL_PWR_REQ_CNTL), \ 830 SRII(PIXEL_RATE_CNTL, OTG, 0), \ 831 SRII(PIXEL_RATE_CNTL, OTG, 1),\ 832 SRII(PIXEL_RATE_CNTL, OTG, 2),\ 833 SRII(PIXEL_RATE_CNTL, OTG, 3),\ 834 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 0),\ 835 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 1),\ 836 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 2),\ 837 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 3),\ 838 SR(MICROSECOND_TIME_BASE_DIV), \ 839 SR(MILLISECOND_TIME_BASE_DIV), \ 840 SR(DISPCLK_FREQ_CHANGE_CNTL), \ 841 SR(RBBMIF_TIMEOUT_DIS), \ 842 SR(RBBMIF_TIMEOUT_DIS_2), \ 843 SR(DCHUBBUB_CRC_CTRL), \ 844 SR(DPP_TOP0_DPP_CRC_CTRL), \ 845 SR(DPP_TOP0_DPP_CRC_VAL_B_A), \ 846 SR(DPP_TOP0_DPP_CRC_VAL_R_G), \ 847 SR(MPC_CRC_CTRL), \ 848 SR(MPC_CRC_RESULT_GB), \ 849 SR(MPC_CRC_RESULT_C), \ 850 SR(MPC_CRC_RESULT_AR), \ 851 SR(DOMAIN0_PG_CONFIG), \ 852 SR(DOMAIN1_PG_CONFIG), \ 853 SR(DOMAIN2_PG_CONFIG), \ 854 SR(DOMAIN3_PG_CONFIG), \ 855 SR(DOMAIN16_PG_CONFIG), \ 856 SR(DOMAIN17_PG_CONFIG), \ 857 SR(DOMAIN18_PG_CONFIG), \ 858 SR(DOMAIN0_PG_STATUS), \ 859 SR(DOMAIN1_PG_STATUS), \ 860 SR(DOMAIN2_PG_STATUS), \ 861 SR(DOMAIN3_PG_STATUS), \ 862 SR(DOMAIN16_PG_STATUS), \ 863 SR(DOMAIN17_PG_STATUS), \ 864 SR(DOMAIN18_PG_STATUS), \ 865 SR(D1VGA_CONTROL), \ 866 SR(D2VGA_CONTROL), \ 867 SR(D3VGA_CONTROL), \ 868 SR(D4VGA_CONTROL), \ 869 SR(D5VGA_CONTROL), \ 870 SR(D6VGA_CONTROL), \ 871 SR(DC_IP_REQUEST_CNTL), \ 872 SR(AZALIA_AUDIO_DTO), \ 873 SR(AZALIA_CONTROLLER_CLOCK_GATING), \ 874 SR(HPO_TOP_HW_CONTROL) 875 876 static const struct dce_hwseq_registers hwseq_reg = { 877 HWSEQ_DCN31_REG_LIST() 878 }; 879 880 #define HWSEQ_DCN31_MASK_SH_LIST(mask_sh)\ 881 HWSEQ_DCN_MASK_SH_LIST(mask_sh), \ 882 HWS_SF(, DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_REFDIV, mask_sh), \ 883 HWS_SF(, DCHUBBUB_ARB_HOSTVM_CNTL, DISABLE_HOSTVM_FORCE_ALLOW_PSTATE, mask_sh), \ 884 HWS_SF(, DOMAIN0_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ 885 HWS_SF(, DOMAIN0_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ 886 HWS_SF(, DOMAIN1_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ 887 HWS_SF(, DOMAIN1_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ 888 HWS_SF(, DOMAIN2_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ 889 HWS_SF(, DOMAIN2_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ 890 HWS_SF(, DOMAIN3_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ 891 HWS_SF(, DOMAIN3_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ 892 HWS_SF(, DOMAIN16_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ 893 HWS_SF(, DOMAIN16_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ 894 HWS_SF(, DOMAIN17_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ 895 HWS_SF(, DOMAIN17_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ 896 HWS_SF(, DOMAIN18_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ 897 HWS_SF(, DOMAIN18_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ 898 HWS_SF(, DOMAIN0_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ 899 HWS_SF(, DOMAIN1_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ 900 HWS_SF(, DOMAIN2_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ 901 HWS_SF(, DOMAIN3_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ 902 HWS_SF(, DOMAIN16_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ 903 HWS_SF(, DOMAIN17_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ 904 HWS_SF(, DOMAIN18_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ 905 HWS_SF(, DC_IP_REQUEST_CNTL, IP_REQUEST_EN, mask_sh), \ 906 HWS_SF(, AZALIA_AUDIO_DTO, AZALIA_AUDIO_DTO_MODULE, mask_sh), \ 907 HWS_SF(, HPO_TOP_CLOCK_CONTROL, HPO_HDMISTREAMCLK_G_GATE_DIS, mask_sh), \ 908 HWS_SF(, DMU_MEM_PWR_CNTL, DMCU_ERAM_MEM_PWR_FORCE, mask_sh), \ 909 HWS_SF(, ODM_MEM_PWR_CTRL3, ODM_MEM_UNASSIGNED_PWR_MODE, mask_sh), \ 910 HWS_SF(, ODM_MEM_PWR_CTRL3, ODM_MEM_VBLANK_PWR_MODE, mask_sh), \ 911 HWS_SF(, MMHUBBUB_MEM_PWR_CNTL, VGA_MEM_PWR_FORCE, mask_sh), \ 912 HWS_SF(, DIO_MEM_PWR_CTRL, I2C_LIGHT_SLEEP_FORCE, mask_sh), \ 913 HWS_SF(, HPO_TOP_HW_CONTROL, HPO_IO_EN, mask_sh) 914 915 static const struct dce_hwseq_shift hwseq_shift = { 916 HWSEQ_DCN31_MASK_SH_LIST(__SHIFT) 917 }; 918 919 static const struct dce_hwseq_mask hwseq_mask = { 920 HWSEQ_DCN31_MASK_SH_LIST(_MASK) 921 }; 922 #define vmid_regs(id)\ 923 [id] = {\ 924 DCN20_VMID_REG_LIST(id)\ 925 } 926 927 static const struct dcn_vmid_registers vmid_regs[] = { 928 vmid_regs(0), 929 vmid_regs(1), 930 vmid_regs(2), 931 vmid_regs(3), 932 vmid_regs(4), 933 vmid_regs(5), 934 vmid_regs(6), 935 vmid_regs(7), 936 vmid_regs(8), 937 vmid_regs(9), 938 vmid_regs(10), 939 vmid_regs(11), 940 vmid_regs(12), 941 vmid_regs(13), 942 vmid_regs(14), 943 vmid_regs(15) 944 }; 945 946 static const struct dcn20_vmid_shift vmid_shifts = { 947 DCN20_VMID_MASK_SH_LIST(__SHIFT) 948 }; 949 950 static const struct dcn20_vmid_mask vmid_masks = { 951 DCN20_VMID_MASK_SH_LIST(_MASK) 952 }; 953 954 static const struct resource_caps res_cap_dcn31 = { 955 .num_timing_generator = 4, 956 .num_opp = 4, 957 .num_video_plane = 4, 958 .num_audio = 5, 959 .num_stream_encoder = 5, 960 .num_dig_link_enc = 5, 961 .num_hpo_dp_stream_encoder = 4, 962 .num_hpo_dp_link_encoder = 2, 963 .num_pll = 5, 964 .num_dwb = 1, 965 .num_ddc = 5, 966 .num_vmid = 16, 967 .num_mpc_3dlut = 2, 968 .num_dsc = 3, 969 }; 970 971 static const struct dc_plane_cap plane_cap = { 972 .type = DC_PLANE_TYPE_DCN_UNIVERSAL, 973 .blends_with_above = true, 974 .blends_with_below = true, 975 .per_pixel_alpha = true, 976 977 .pixel_format_support = { 978 .argb8888 = true, 979 .nv12 = true, 980 .fp16 = true, 981 .p010 = true, 982 .ayuv = false, 983 }, 984 985 .max_upscale_factor = { 986 .argb8888 = 16000, 987 .nv12 = 16000, 988 .fp16 = 16000 989 }, 990 991 // 6:1 downscaling ratio: 1000/6 = 166.666 992 .max_downscale_factor = { 993 .argb8888 = 167, 994 .nv12 = 167, 995 .fp16 = 167 996 }, 997 64, 998 64 999 }; 1000 1001 static const struct dc_debug_options debug_defaults_drv = { 1002 .disable_z10 = true, /*hw not support it*/ 1003 .disable_dmcu = true, 1004 .force_abm_enable = false, 1005 .timing_trace = false, 1006 .clock_trace = true, 1007 .disable_pplib_clock_request = false, 1008 .pipe_split_policy = MPC_SPLIT_DYNAMIC, 1009 .force_single_disp_pipe_split = false, 1010 .disable_dcc = DCC_ENABLE, 1011 .vsr_support = true, 1012 .performance_trace = false, 1013 .max_downscale_src_width = 4096,/*upto true 4k*/ 1014 .disable_pplib_wm_range = false, 1015 .scl_reset_length10 = true, 1016 .sanity_checks = false, 1017 .underflow_assert_delay_us = 0xFFFFFFFF, 1018 .dwb_fi_phase = -1, // -1 = disable, 1019 .dmub_command_table = true, 1020 .pstate_enabled = true, 1021 .use_max_lb = true, 1022 .enable_mem_low_power = { 1023 .bits = { 1024 .vga = true, 1025 .i2c = true, 1026 .dmcu = false, // This is previously known to cause hang on S3 cycles if enabled 1027 .dscl = true, 1028 .cm = true, 1029 .mpc = true, 1030 .optc = true, 1031 .vpg = true, 1032 .afmt = true, 1033 } 1034 }, 1035 .optimize_edp_link_rate = true, 1036 .enable_sw_cntl_psr = true, 1037 }; 1038 1039 static const struct dc_debug_options debug_defaults_diags = { 1040 .disable_dmcu = true, 1041 .force_abm_enable = false, 1042 .timing_trace = true, 1043 .clock_trace = true, 1044 .disable_dpp_power_gate = true, 1045 .disable_hubp_power_gate = true, 1046 .disable_clock_gate = true, 1047 .disable_pplib_clock_request = true, 1048 .disable_pplib_wm_range = true, 1049 .disable_stutter = false, 1050 .scl_reset_length10 = true, 1051 .dwb_fi_phase = -1, // -1 = disable 1052 .dmub_command_table = true, 1053 .enable_tri_buf = true, 1054 .use_max_lb = true 1055 }; 1056 1057 static void dcn31_dpp_destroy(struct dpp **dpp) 1058 { 1059 kfree(TO_DCN20_DPP(*dpp)); 1060 *dpp = NULL; 1061 } 1062 1063 static struct dpp *dcn31_dpp_create( 1064 struct dc_context *ctx, 1065 uint32_t inst) 1066 { 1067 struct dcn3_dpp *dpp = 1068 kzalloc(sizeof(struct dcn3_dpp), GFP_KERNEL); 1069 1070 if (!dpp) 1071 return NULL; 1072 1073 if (dpp3_construct(dpp, ctx, inst, 1074 &dpp_regs[inst], &tf_shift, &tf_mask)) 1075 return &dpp->base; 1076 1077 BREAK_TO_DEBUGGER(); 1078 kfree(dpp); 1079 return NULL; 1080 } 1081 1082 static struct output_pixel_processor *dcn31_opp_create( 1083 struct dc_context *ctx, uint32_t inst) 1084 { 1085 struct dcn20_opp *opp = 1086 kzalloc(sizeof(struct dcn20_opp), GFP_KERNEL); 1087 1088 if (!opp) { 1089 BREAK_TO_DEBUGGER(); 1090 return NULL; 1091 } 1092 1093 dcn20_opp_construct(opp, ctx, inst, 1094 &opp_regs[inst], &opp_shift, &opp_mask); 1095 return &opp->base; 1096 } 1097 1098 static struct dce_aux *dcn31_aux_engine_create( 1099 struct dc_context *ctx, 1100 uint32_t inst) 1101 { 1102 struct aux_engine_dce110 *aux_engine = 1103 kzalloc(sizeof(struct aux_engine_dce110), GFP_KERNEL); 1104 1105 if (!aux_engine) 1106 return NULL; 1107 1108 dce110_aux_engine_construct(aux_engine, ctx, inst, 1109 SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD, 1110 &aux_engine_regs[inst], 1111 &aux_mask, 1112 &aux_shift, 1113 ctx->dc->caps.extended_aux_timeout_support); 1114 1115 return &aux_engine->base; 1116 } 1117 #define i2c_inst_regs(id) { I2C_HW_ENGINE_COMMON_REG_LIST_DCN30(id) } 1118 1119 static const struct dce_i2c_registers i2c_hw_regs[] = { 1120 i2c_inst_regs(1), 1121 i2c_inst_regs(2), 1122 i2c_inst_regs(3), 1123 i2c_inst_regs(4), 1124 i2c_inst_regs(5), 1125 }; 1126 1127 static const struct dce_i2c_shift i2c_shifts = { 1128 I2C_COMMON_MASK_SH_LIST_DCN30(__SHIFT) 1129 }; 1130 1131 static const struct dce_i2c_mask i2c_masks = { 1132 I2C_COMMON_MASK_SH_LIST_DCN30(_MASK) 1133 }; 1134 1135 static struct dce_i2c_hw *dcn31_i2c_hw_create( 1136 struct dc_context *ctx, 1137 uint32_t inst) 1138 { 1139 struct dce_i2c_hw *dce_i2c_hw = 1140 kzalloc(sizeof(struct dce_i2c_hw), GFP_KERNEL); 1141 1142 if (!dce_i2c_hw) 1143 return NULL; 1144 1145 dcn2_i2c_hw_construct(dce_i2c_hw, ctx, inst, 1146 &i2c_hw_regs[inst], &i2c_shifts, &i2c_masks); 1147 1148 return dce_i2c_hw; 1149 } 1150 static struct mpc *dcn31_mpc_create( 1151 struct dc_context *ctx, 1152 int num_mpcc, 1153 int num_rmu) 1154 { 1155 struct dcn30_mpc *mpc30 = kzalloc(sizeof(struct dcn30_mpc), 1156 GFP_KERNEL); 1157 1158 if (!mpc30) 1159 return NULL; 1160 1161 dcn30_mpc_construct(mpc30, ctx, 1162 &mpc_regs, 1163 &mpc_shift, 1164 &mpc_mask, 1165 num_mpcc, 1166 num_rmu); 1167 1168 return &mpc30->base; 1169 } 1170 1171 static struct hubbub *dcn31_hubbub_create(struct dc_context *ctx) 1172 { 1173 int i; 1174 1175 struct dcn20_hubbub *hubbub3 = kzalloc(sizeof(struct dcn20_hubbub), 1176 GFP_KERNEL); 1177 1178 if (!hubbub3) 1179 return NULL; 1180 1181 hubbub31_construct(hubbub3, ctx, 1182 &hubbub_reg, 1183 &hubbub_shift, 1184 &hubbub_mask, 1185 dcn3_15_ip.det_buffer_size_kbytes, 1186 dcn3_15_ip.pixel_chunk_size_kbytes, 1187 dcn3_15_ip.config_return_buffer_size_in_kbytes); 1188 1189 1190 for (i = 0; i < res_cap_dcn31.num_vmid; i++) { 1191 struct dcn20_vmid *vmid = &hubbub3->vmid[i]; 1192 1193 vmid->ctx = ctx; 1194 1195 vmid->regs = &vmid_regs[i]; 1196 vmid->shifts = &vmid_shifts; 1197 vmid->masks = &vmid_masks; 1198 } 1199 1200 return &hubbub3->base; 1201 } 1202 1203 static struct timing_generator *dcn31_timing_generator_create( 1204 struct dc_context *ctx, 1205 uint32_t instance) 1206 { 1207 struct optc *tgn10 = 1208 kzalloc(sizeof(struct optc), GFP_KERNEL); 1209 1210 if (!tgn10) 1211 return NULL; 1212 1213 tgn10->base.inst = instance; 1214 tgn10->base.ctx = ctx; 1215 1216 tgn10->tg_regs = &optc_regs[instance]; 1217 tgn10->tg_shift = &optc_shift; 1218 tgn10->tg_mask = &optc_mask; 1219 1220 dcn31_timing_generator_init(tgn10); 1221 1222 return &tgn10->base; 1223 } 1224 1225 static const struct encoder_feature_support link_enc_feature = { 1226 .max_hdmi_deep_color = COLOR_DEPTH_121212, 1227 .max_hdmi_pixel_clock = 600000, 1228 .hdmi_ycbcr420_supported = true, 1229 .dp_ycbcr420_supported = true, 1230 .fec_supported = true, 1231 .flags.bits.IS_HBR2_CAPABLE = true, 1232 .flags.bits.IS_HBR3_CAPABLE = true, 1233 .flags.bits.IS_TPS3_CAPABLE = true, 1234 .flags.bits.IS_TPS4_CAPABLE = true 1235 }; 1236 1237 static struct link_encoder *dcn31_link_encoder_create( 1238 const struct encoder_init_data *enc_init_data) 1239 { 1240 struct dcn20_link_encoder *enc20 = 1241 kzalloc(sizeof(struct dcn20_link_encoder), GFP_KERNEL); 1242 1243 if (!enc20) 1244 return NULL; 1245 1246 dcn31_link_encoder_construct(enc20, 1247 enc_init_data, 1248 &link_enc_feature, 1249 &link_enc_regs[enc_init_data->transmitter], 1250 &link_enc_aux_regs[enc_init_data->channel - 1], 1251 &link_enc_hpd_regs[enc_init_data->hpd_source], 1252 &le_shift, 1253 &le_mask); 1254 1255 return &enc20->enc10.base; 1256 } 1257 1258 /* Create a minimal link encoder object not associated with a particular 1259 * physical connector. 1260 * resource_funcs.link_enc_create_minimal 1261 */ 1262 static struct link_encoder *dcn31_link_enc_create_minimal( 1263 struct dc_context *ctx, enum engine_id eng_id) 1264 { 1265 struct dcn20_link_encoder *enc20; 1266 1267 if ((eng_id - ENGINE_ID_DIGA) > ctx->dc->res_pool->res_cap->num_dig_link_enc) 1268 return NULL; 1269 1270 enc20 = kzalloc(sizeof(struct dcn20_link_encoder), GFP_KERNEL); 1271 if (!enc20) 1272 return NULL; 1273 1274 dcn31_link_encoder_construct_minimal( 1275 enc20, 1276 ctx, 1277 &link_enc_feature, 1278 &link_enc_regs[eng_id - ENGINE_ID_DIGA], 1279 eng_id); 1280 1281 return &enc20->enc10.base; 1282 } 1283 1284 static struct panel_cntl *dcn31_panel_cntl_create(const struct panel_cntl_init_data *init_data) 1285 { 1286 struct dcn31_panel_cntl *panel_cntl = 1287 kzalloc(sizeof(struct dcn31_panel_cntl), GFP_KERNEL); 1288 1289 if (!panel_cntl) 1290 return NULL; 1291 1292 dcn31_panel_cntl_construct(panel_cntl, init_data); 1293 1294 return &panel_cntl->base; 1295 } 1296 1297 static void read_dce_straps( 1298 struct dc_context *ctx, 1299 struct resource_straps *straps) 1300 { 1301 generic_reg_get(ctx, regDC_PINSTRAPS + BASE(regDC_PINSTRAPS_BASE_IDX), 1302 FN(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO), &straps->dc_pinstraps_audio); 1303 1304 } 1305 1306 static struct audio *dcn31_create_audio( 1307 struct dc_context *ctx, unsigned int inst) 1308 { 1309 return dce_audio_create(ctx, inst, 1310 &audio_regs[inst], &audio_shift, &audio_mask); 1311 } 1312 1313 static struct vpg *dcn31_vpg_create( 1314 struct dc_context *ctx, 1315 uint32_t inst) 1316 { 1317 struct dcn31_vpg *vpg31 = kzalloc(sizeof(struct dcn31_vpg), GFP_KERNEL); 1318 1319 if (!vpg31) 1320 return NULL; 1321 1322 vpg31_construct(vpg31, ctx, inst, 1323 &vpg_regs[inst], 1324 &vpg_shift, 1325 &vpg_mask); 1326 1327 return &vpg31->base; 1328 } 1329 1330 static struct afmt *dcn31_afmt_create( 1331 struct dc_context *ctx, 1332 uint32_t inst) 1333 { 1334 struct dcn31_afmt *afmt31 = kzalloc(sizeof(struct dcn31_afmt), GFP_KERNEL); 1335 1336 if (!afmt31) 1337 return NULL; 1338 1339 afmt31_construct(afmt31, ctx, inst, 1340 &afmt_regs[inst], 1341 &afmt_shift, 1342 &afmt_mask); 1343 1344 // Light sleep by default, no need to power down here 1345 1346 return &afmt31->base; 1347 } 1348 1349 static struct apg *dcn31_apg_create( 1350 struct dc_context *ctx, 1351 uint32_t inst) 1352 { 1353 struct dcn31_apg *apg31 = kzalloc(sizeof(struct dcn31_apg), GFP_KERNEL); 1354 1355 if (!apg31) 1356 return NULL; 1357 1358 apg31_construct(apg31, ctx, inst, 1359 &apg_regs[inst], 1360 &apg_shift, 1361 &apg_mask); 1362 1363 return &apg31->base; 1364 } 1365 1366 static struct stream_encoder *dcn315_stream_encoder_create( 1367 enum engine_id eng_id, 1368 struct dc_context *ctx) 1369 { 1370 struct dcn10_stream_encoder *enc1; 1371 struct vpg *vpg; 1372 struct afmt *afmt; 1373 int vpg_inst; 1374 int afmt_inst; 1375 1376 /*PHYB is wired off in HW, allow front end to remapping, otherwise needs more changes*/ 1377 1378 /* Mapping of VPG, AFMT, DME register blocks to DIO block instance */ 1379 if (eng_id <= ENGINE_ID_DIGF) { 1380 vpg_inst = eng_id; 1381 afmt_inst = eng_id; 1382 } else 1383 return NULL; 1384 1385 enc1 = kzalloc(sizeof(struct dcn10_stream_encoder), GFP_KERNEL); 1386 vpg = dcn31_vpg_create(ctx, vpg_inst); 1387 afmt = dcn31_afmt_create(ctx, afmt_inst); 1388 1389 if (!enc1 || !vpg || !afmt) { 1390 kfree(enc1); 1391 kfree(vpg); 1392 kfree(afmt); 1393 return NULL; 1394 } 1395 1396 dcn30_dio_stream_encoder_construct(enc1, ctx, ctx->dc_bios, 1397 eng_id, vpg, afmt, 1398 &stream_enc_regs[eng_id], 1399 &se_shift, &se_mask); 1400 1401 return &enc1->base; 1402 } 1403 1404 static struct hpo_dp_stream_encoder *dcn31_hpo_dp_stream_encoder_create( 1405 enum engine_id eng_id, 1406 struct dc_context *ctx) 1407 { 1408 struct dcn31_hpo_dp_stream_encoder *hpo_dp_enc31; 1409 struct vpg *vpg; 1410 struct apg *apg; 1411 uint32_t hpo_dp_inst; 1412 uint32_t vpg_inst; 1413 uint32_t apg_inst; 1414 1415 ASSERT((eng_id >= ENGINE_ID_HPO_DP_0) && (eng_id <= ENGINE_ID_HPO_DP_3)); 1416 hpo_dp_inst = eng_id - ENGINE_ID_HPO_DP_0; 1417 1418 /* Mapping of VPG register blocks to HPO DP block instance: 1419 * VPG[6] -> HPO_DP[0] 1420 * VPG[7] -> HPO_DP[1] 1421 * VPG[8] -> HPO_DP[2] 1422 * VPG[9] -> HPO_DP[3] 1423 */ 1424 vpg_inst = hpo_dp_inst + 6; 1425 1426 /* Mapping of APG register blocks to HPO DP block instance: 1427 * APG[0] -> HPO_DP[0] 1428 * APG[1] -> HPO_DP[1] 1429 * APG[2] -> HPO_DP[2] 1430 * APG[3] -> HPO_DP[3] 1431 */ 1432 apg_inst = hpo_dp_inst; 1433 1434 /* allocate HPO stream encoder and create VPG sub-block */ 1435 hpo_dp_enc31 = kzalloc(sizeof(struct dcn31_hpo_dp_stream_encoder), GFP_KERNEL); 1436 vpg = dcn31_vpg_create(ctx, vpg_inst); 1437 apg = dcn31_apg_create(ctx, apg_inst); 1438 1439 if (!hpo_dp_enc31 || !vpg || !apg) { 1440 kfree(hpo_dp_enc31); 1441 kfree(vpg); 1442 kfree(apg); 1443 return NULL; 1444 } 1445 1446 dcn31_hpo_dp_stream_encoder_construct(hpo_dp_enc31, ctx, ctx->dc_bios, 1447 hpo_dp_inst, eng_id, vpg, apg, 1448 &hpo_dp_stream_enc_regs[hpo_dp_inst], 1449 &hpo_dp_se_shift, &hpo_dp_se_mask); 1450 1451 return &hpo_dp_enc31->base; 1452 } 1453 1454 static struct hpo_dp_link_encoder *dcn31_hpo_dp_link_encoder_create( 1455 uint8_t inst, 1456 struct dc_context *ctx) 1457 { 1458 struct dcn31_hpo_dp_link_encoder *hpo_dp_enc31; 1459 1460 /* allocate HPO link encoder */ 1461 hpo_dp_enc31 = kzalloc(sizeof(struct dcn31_hpo_dp_link_encoder), GFP_KERNEL); 1462 1463 hpo_dp_link_encoder31_construct(hpo_dp_enc31, ctx, inst, 1464 &hpo_dp_link_enc_regs[inst], 1465 &hpo_dp_le_shift, &hpo_dp_le_mask); 1466 1467 return &hpo_dp_enc31->base; 1468 } 1469 1470 static struct dce_hwseq *dcn31_hwseq_create( 1471 struct dc_context *ctx) 1472 { 1473 struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_KERNEL); 1474 1475 if (hws) { 1476 hws->ctx = ctx; 1477 hws->regs = &hwseq_reg; 1478 hws->shifts = &hwseq_shift; 1479 hws->masks = &hwseq_mask; 1480 /* DCN3.1 FPGA Workaround 1481 * Need to enable HPO DP Stream Encoder before setting OTG master enable. 1482 * To do so, move calling function enable_stream_timing to only be done AFTER calling 1483 * function core_link_enable_stream 1484 */ 1485 if (IS_FPGA_MAXIMUS_DC(ctx->dce_environment)) 1486 hws->wa.dp_hpo_and_otg_sequence = true; 1487 } 1488 return hws; 1489 } 1490 static const struct resource_create_funcs res_create_funcs = { 1491 .read_dce_straps = read_dce_straps, 1492 .create_audio = dcn31_create_audio, 1493 .create_stream_encoder = dcn315_stream_encoder_create, 1494 .create_hpo_dp_stream_encoder = dcn31_hpo_dp_stream_encoder_create, 1495 .create_hpo_dp_link_encoder = dcn31_hpo_dp_link_encoder_create, 1496 .create_hwseq = dcn31_hwseq_create, 1497 }; 1498 1499 static const struct resource_create_funcs res_create_maximus_funcs = { 1500 .read_dce_straps = NULL, 1501 .create_audio = NULL, 1502 .create_stream_encoder = NULL, 1503 .create_hpo_dp_stream_encoder = dcn31_hpo_dp_stream_encoder_create, 1504 .create_hpo_dp_link_encoder = dcn31_hpo_dp_link_encoder_create, 1505 .create_hwseq = dcn31_hwseq_create, 1506 }; 1507 1508 static void dcn315_resource_destruct(struct dcn315_resource_pool *pool) 1509 { 1510 unsigned int i; 1511 1512 for (i = 0; i < pool->base.stream_enc_count; i++) { 1513 if (pool->base.stream_enc[i] != NULL) { 1514 if (pool->base.stream_enc[i]->vpg != NULL) { 1515 kfree(DCN30_VPG_FROM_VPG(pool->base.stream_enc[i]->vpg)); 1516 pool->base.stream_enc[i]->vpg = NULL; 1517 } 1518 if (pool->base.stream_enc[i]->afmt != NULL) { 1519 kfree(DCN30_AFMT_FROM_AFMT(pool->base.stream_enc[i]->afmt)); 1520 pool->base.stream_enc[i]->afmt = NULL; 1521 } 1522 kfree(DCN10STRENC_FROM_STRENC(pool->base.stream_enc[i])); 1523 pool->base.stream_enc[i] = NULL; 1524 } 1525 } 1526 1527 for (i = 0; i < pool->base.hpo_dp_stream_enc_count; i++) { 1528 if (pool->base.hpo_dp_stream_enc[i] != NULL) { 1529 if (pool->base.hpo_dp_stream_enc[i]->vpg != NULL) { 1530 kfree(DCN30_VPG_FROM_VPG(pool->base.hpo_dp_stream_enc[i]->vpg)); 1531 pool->base.hpo_dp_stream_enc[i]->vpg = NULL; 1532 } 1533 if (pool->base.hpo_dp_stream_enc[i]->apg != NULL) { 1534 kfree(DCN31_APG_FROM_APG(pool->base.hpo_dp_stream_enc[i]->apg)); 1535 pool->base.hpo_dp_stream_enc[i]->apg = NULL; 1536 } 1537 kfree(DCN3_1_HPO_DP_STREAM_ENC_FROM_HPO_STREAM_ENC(pool->base.hpo_dp_stream_enc[i])); 1538 pool->base.hpo_dp_stream_enc[i] = NULL; 1539 } 1540 } 1541 1542 for (i = 0; i < pool->base.hpo_dp_link_enc_count; i++) { 1543 if (pool->base.hpo_dp_link_enc[i] != NULL) { 1544 kfree(DCN3_1_HPO_DP_LINK_ENC_FROM_HPO_LINK_ENC(pool->base.hpo_dp_link_enc[i])); 1545 pool->base.hpo_dp_link_enc[i] = NULL; 1546 } 1547 } 1548 1549 for (i = 0; i < pool->base.res_cap->num_dsc; i++) { 1550 if (pool->base.dscs[i] != NULL) 1551 dcn20_dsc_destroy(&pool->base.dscs[i]); 1552 } 1553 1554 if (pool->base.mpc != NULL) { 1555 kfree(TO_DCN20_MPC(pool->base.mpc)); 1556 pool->base.mpc = NULL; 1557 } 1558 if (pool->base.hubbub != NULL) { 1559 kfree(pool->base.hubbub); 1560 pool->base.hubbub = NULL; 1561 } 1562 for (i = 0; i < pool->base.pipe_count; i++) { 1563 if (pool->base.dpps[i] != NULL) 1564 dcn31_dpp_destroy(&pool->base.dpps[i]); 1565 1566 if (pool->base.ipps[i] != NULL) 1567 pool->base.ipps[i]->funcs->ipp_destroy(&pool->base.ipps[i]); 1568 1569 if (pool->base.hubps[i] != NULL) { 1570 kfree(TO_DCN20_HUBP(pool->base.hubps[i])); 1571 pool->base.hubps[i] = NULL; 1572 } 1573 1574 if (pool->base.irqs != NULL) { 1575 dal_irq_service_destroy(&pool->base.irqs); 1576 } 1577 } 1578 1579 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { 1580 if (pool->base.engines[i] != NULL) 1581 dce110_engine_destroy(&pool->base.engines[i]); 1582 if (pool->base.hw_i2cs[i] != NULL) { 1583 kfree(pool->base.hw_i2cs[i]); 1584 pool->base.hw_i2cs[i] = NULL; 1585 } 1586 if (pool->base.sw_i2cs[i] != NULL) { 1587 kfree(pool->base.sw_i2cs[i]); 1588 pool->base.sw_i2cs[i] = NULL; 1589 } 1590 } 1591 1592 for (i = 0; i < pool->base.res_cap->num_opp; i++) { 1593 if (pool->base.opps[i] != NULL) 1594 pool->base.opps[i]->funcs->opp_destroy(&pool->base.opps[i]); 1595 } 1596 1597 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { 1598 if (pool->base.timing_generators[i] != NULL) { 1599 kfree(DCN10TG_FROM_TG(pool->base.timing_generators[i])); 1600 pool->base.timing_generators[i] = NULL; 1601 } 1602 } 1603 1604 for (i = 0; i < pool->base.res_cap->num_dwb; i++) { 1605 if (pool->base.dwbc[i] != NULL) { 1606 kfree(TO_DCN30_DWBC(pool->base.dwbc[i])); 1607 pool->base.dwbc[i] = NULL; 1608 } 1609 if (pool->base.mcif_wb[i] != NULL) { 1610 kfree(TO_DCN30_MMHUBBUB(pool->base.mcif_wb[i])); 1611 pool->base.mcif_wb[i] = NULL; 1612 } 1613 } 1614 1615 for (i = 0; i < pool->base.audio_count; i++) { 1616 if (pool->base.audios[i]) 1617 dce_aud_destroy(&pool->base.audios[i]); 1618 } 1619 1620 for (i = 0; i < pool->base.clk_src_count; i++) { 1621 if (pool->base.clock_sources[i] != NULL) { 1622 dcn20_clock_source_destroy(&pool->base.clock_sources[i]); 1623 pool->base.clock_sources[i] = NULL; 1624 } 1625 } 1626 1627 for (i = 0; i < pool->base.res_cap->num_mpc_3dlut; i++) { 1628 if (pool->base.mpc_lut[i] != NULL) { 1629 dc_3dlut_func_release(pool->base.mpc_lut[i]); 1630 pool->base.mpc_lut[i] = NULL; 1631 } 1632 if (pool->base.mpc_shaper[i] != NULL) { 1633 dc_transfer_func_release(pool->base.mpc_shaper[i]); 1634 pool->base.mpc_shaper[i] = NULL; 1635 } 1636 } 1637 1638 if (pool->base.dp_clock_source != NULL) { 1639 dcn20_clock_source_destroy(&pool->base.dp_clock_source); 1640 pool->base.dp_clock_source = NULL; 1641 } 1642 1643 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { 1644 if (pool->base.multiple_abms[i] != NULL) 1645 dce_abm_destroy(&pool->base.multiple_abms[i]); 1646 } 1647 1648 if (pool->base.psr != NULL) 1649 dmub_psr_destroy(&pool->base.psr); 1650 1651 if (pool->base.dccg != NULL) 1652 dcn_dccg_destroy(&pool->base.dccg); 1653 } 1654 1655 static struct hubp *dcn31_hubp_create( 1656 struct dc_context *ctx, 1657 uint32_t inst) 1658 { 1659 struct dcn20_hubp *hubp2 = 1660 kzalloc(sizeof(struct dcn20_hubp), GFP_KERNEL); 1661 1662 if (!hubp2) 1663 return NULL; 1664 1665 if (hubp31_construct(hubp2, ctx, inst, 1666 &hubp_regs[inst], &hubp_shift, &hubp_mask)) 1667 return &hubp2->base; 1668 1669 BREAK_TO_DEBUGGER(); 1670 kfree(hubp2); 1671 return NULL; 1672 } 1673 1674 static bool dcn31_dwbc_create(struct dc_context *ctx, struct resource_pool *pool) 1675 { 1676 int i; 1677 uint32_t pipe_count = pool->res_cap->num_dwb; 1678 1679 for (i = 0; i < pipe_count; i++) { 1680 struct dcn30_dwbc *dwbc30 = kzalloc(sizeof(struct dcn30_dwbc), 1681 GFP_KERNEL); 1682 1683 if (!dwbc30) { 1684 dm_error("DC: failed to create dwbc30!\n"); 1685 return false; 1686 } 1687 1688 dcn30_dwbc_construct(dwbc30, ctx, 1689 &dwbc30_regs[i], 1690 &dwbc30_shift, 1691 &dwbc30_mask, 1692 i); 1693 1694 pool->dwbc[i] = &dwbc30->base; 1695 } 1696 return true; 1697 } 1698 1699 static bool dcn31_mmhubbub_create(struct dc_context *ctx, struct resource_pool *pool) 1700 { 1701 int i; 1702 uint32_t pipe_count = pool->res_cap->num_dwb; 1703 1704 for (i = 0; i < pipe_count; i++) { 1705 struct dcn30_mmhubbub *mcif_wb30 = kzalloc(sizeof(struct dcn30_mmhubbub), 1706 GFP_KERNEL); 1707 1708 if (!mcif_wb30) { 1709 dm_error("DC: failed to create mcif_wb30!\n"); 1710 return false; 1711 } 1712 1713 dcn30_mmhubbub_construct(mcif_wb30, ctx, 1714 &mcif_wb30_regs[i], 1715 &mcif_wb30_shift, 1716 &mcif_wb30_mask, 1717 i); 1718 1719 pool->mcif_wb[i] = &mcif_wb30->base; 1720 } 1721 return true; 1722 } 1723 1724 static struct display_stream_compressor *dcn31_dsc_create( 1725 struct dc_context *ctx, uint32_t inst) 1726 { 1727 struct dcn20_dsc *dsc = 1728 kzalloc(sizeof(struct dcn20_dsc), GFP_KERNEL); 1729 1730 if (!dsc) { 1731 BREAK_TO_DEBUGGER(); 1732 return NULL; 1733 } 1734 1735 dsc2_construct(dsc, ctx, inst, &dsc_regs[inst], &dsc_shift, &dsc_mask); 1736 return &dsc->base; 1737 } 1738 1739 static void dcn315_destroy_resource_pool(struct resource_pool **pool) 1740 { 1741 struct dcn315_resource_pool *dcn31_pool = TO_DCN315_RES_POOL(*pool); 1742 1743 dcn315_resource_destruct(dcn31_pool); 1744 kfree(dcn31_pool); 1745 *pool = NULL; 1746 } 1747 1748 static struct clock_source *dcn31_clock_source_create( 1749 struct dc_context *ctx, 1750 struct dc_bios *bios, 1751 enum clock_source_id id, 1752 const struct dce110_clk_src_regs *regs, 1753 bool dp_clk_src) 1754 { 1755 struct dce110_clk_src *clk_src = 1756 kzalloc(sizeof(struct dce110_clk_src), GFP_KERNEL); 1757 1758 if (!clk_src) 1759 return NULL; 1760 1761 if (dcn3_clk_src_construct(clk_src, ctx, bios, id, 1762 regs, &cs_shift, &cs_mask)) { 1763 clk_src->base.dp_clk_src = dp_clk_src; 1764 return &clk_src->base; 1765 } 1766 1767 BREAK_TO_DEBUGGER(); 1768 return NULL; 1769 } 1770 1771 static bool is_dual_plane(enum surface_pixel_format format) 1772 { 1773 return format >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN || format == SURFACE_PIXEL_FORMAT_GRPH_RGBE_ALPHA; 1774 } 1775 1776 static int dcn315_populate_dml_pipes_from_context( 1777 struct dc *dc, struct dc_state *context, 1778 display_e2e_pipe_params_st *pipes, 1779 bool fast_validate) 1780 { 1781 int i, pipe_cnt; 1782 struct resource_context *res_ctx = &context->res_ctx; 1783 struct pipe_ctx *pipe; 1784 const int max_usable_det = context->bw_ctx.dml.ip.config_return_buffer_size_in_kbytes - DCN3_15_MIN_COMPBUF_SIZE_KB; 1785 1786 dcn20_populate_dml_pipes_from_context(dc, context, pipes, fast_validate); 1787 1788 for (i = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) { 1789 struct dc_crtc_timing *timing; 1790 1791 if (!res_ctx->pipe_ctx[i].stream) 1792 continue; 1793 pipe = &res_ctx->pipe_ctx[i]; 1794 timing = &pipe->stream->timing; 1795 1796 /* 1797 * Immediate flip can be set dynamically after enabling the plane. 1798 * We need to require support for immediate flip or underflow can be 1799 * intermittently experienced depending on peak b/w requirements. 1800 */ 1801 pipes[pipe_cnt].pipe.src.immediate_flip = true; 1802 1803 pipes[pipe_cnt].pipe.src.unbounded_req_mode = false; 1804 pipes[pipe_cnt].pipe.src.gpuvm = true; 1805 pipes[pipe_cnt].pipe.src.dcc_fraction_of_zs_req_luma = 0; 1806 pipes[pipe_cnt].pipe.src.dcc_fraction_of_zs_req_chroma = 0; 1807 pipes[pipe_cnt].pipe.dest.vfront_porch = timing->v_front_porch; 1808 pipes[pipe_cnt].pipe.src.dcc_rate = 3; 1809 pipes[pipe_cnt].dout.dsc_input_bpc = 0; 1810 1811 if (pipes[pipe_cnt].dout.dsc_enable) { 1812 switch (timing->display_color_depth) { 1813 case COLOR_DEPTH_888: 1814 pipes[pipe_cnt].dout.dsc_input_bpc = 8; 1815 break; 1816 case COLOR_DEPTH_101010: 1817 pipes[pipe_cnt].dout.dsc_input_bpc = 10; 1818 break; 1819 case COLOR_DEPTH_121212: 1820 pipes[pipe_cnt].dout.dsc_input_bpc = 12; 1821 break; 1822 default: 1823 ASSERT(0); 1824 break; 1825 } 1826 } 1827 1828 pipe_cnt++; 1829 } 1830 1831 if (pipe_cnt) 1832 context->bw_ctx.dml.ip.det_buffer_size_kbytes = 1833 (max_usable_det / DCN3_15_CRB_SEGMENT_SIZE_KB / pipe_cnt) * DCN3_15_CRB_SEGMENT_SIZE_KB; 1834 if (context->bw_ctx.dml.ip.det_buffer_size_kbytes > DCN3_15_MAX_DET_SIZE) 1835 context->bw_ctx.dml.ip.det_buffer_size_kbytes = DCN3_15_MAX_DET_SIZE; 1836 ASSERT(context->bw_ctx.dml.ip.det_buffer_size_kbytes >= DCN3_15_DEFAULT_DET_SIZE); 1837 dc->config.enable_4to1MPC = false; 1838 if (pipe_cnt == 1 && pipe->plane_state && !dc->debug.disable_z9_mpc) { 1839 if (is_dual_plane(pipe->plane_state->format) 1840 && pipe->plane_state->src_rect.width <= 1920 && pipe->plane_state->src_rect.height <= 1080) { 1841 dc->config.enable_4to1MPC = true; 1842 context->bw_ctx.dml.ip.det_buffer_size_kbytes = 1843 (max_usable_det / DCN3_15_CRB_SEGMENT_SIZE_KB / 4) * DCN3_15_CRB_SEGMENT_SIZE_KB; 1844 } else if (!is_dual_plane(pipe->plane_state->format)) { 1845 context->bw_ctx.dml.ip.det_buffer_size_kbytes = 192; 1846 pipes[0].pipe.src.unbounded_req_mode = true; 1847 } 1848 } 1849 1850 return pipe_cnt; 1851 } 1852 1853 static struct dc_cap_funcs cap_funcs = { 1854 .get_dcc_compression_cap = dcn20_get_dcc_compression_cap 1855 }; 1856 1857 static void dcn315_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params) 1858 { 1859 struct clk_limit_table *clk_table = &bw_params->clk_table; 1860 struct _vcs_dpi_voltage_scaling_st clock_limits[DC__VOLTAGE_STATES]; 1861 unsigned int i, closest_clk_lvl; 1862 int max_dispclk_mhz = 0, max_dppclk_mhz = 0; 1863 int j; 1864 1865 // Default clock levels are used for diags, which may lead to overclocking. 1866 if (!IS_DIAG_DC(dc->ctx->dce_environment)) { 1867 1868 dcn3_15_ip.max_num_otg = dc->res_pool->res_cap->num_timing_generator; 1869 dcn3_15_ip.max_num_dpp = dc->res_pool->pipe_count; 1870 dcn3_15_soc.num_chans = bw_params->num_channels; 1871 1872 ASSERT(clk_table->num_entries); 1873 1874 /* Prepass to find max clocks independent of voltage level. */ 1875 for (i = 0; i < clk_table->num_entries; ++i) { 1876 if (clk_table->entries[i].dispclk_mhz > max_dispclk_mhz) 1877 max_dispclk_mhz = clk_table->entries[i].dispclk_mhz; 1878 if (clk_table->entries[i].dppclk_mhz > max_dppclk_mhz) 1879 max_dppclk_mhz = clk_table->entries[i].dppclk_mhz; 1880 } 1881 1882 for (i = 0; i < clk_table->num_entries; i++) { 1883 /* loop backwards*/ 1884 for (closest_clk_lvl = 0, j = dcn3_15_soc.num_states - 1; j >= 0; j--) { 1885 if ((unsigned int) dcn3_15_soc.clock_limits[j].dcfclk_mhz <= clk_table->entries[i].dcfclk_mhz) { 1886 closest_clk_lvl = j; 1887 break; 1888 } 1889 } 1890 if (clk_table->num_entries == 1) { 1891 /*smu gives one DPM level, let's take the highest one*/ 1892 closest_clk_lvl = dcn3_15_soc.num_states - 1; 1893 } 1894 1895 clock_limits[i].state = i; 1896 1897 /* Clocks dependent on voltage level. */ 1898 clock_limits[i].dcfclk_mhz = clk_table->entries[i].dcfclk_mhz; 1899 if (clk_table->num_entries == 1 && 1900 clock_limits[i].dcfclk_mhz < dcn3_15_soc.clock_limits[closest_clk_lvl].dcfclk_mhz) { 1901 /*SMU fix not released yet*/ 1902 clock_limits[i].dcfclk_mhz = dcn3_15_soc.clock_limits[closest_clk_lvl].dcfclk_mhz; 1903 } 1904 clock_limits[i].fabricclk_mhz = clk_table->entries[i].fclk_mhz; 1905 clock_limits[i].socclk_mhz = clk_table->entries[i].socclk_mhz; 1906 clock_limits[i].dram_speed_mts = clk_table->entries[i].memclk_mhz * 2 * clk_table->entries[i].wck_ratio; 1907 1908 /* Clocks independent of voltage level. */ 1909 clock_limits[i].dispclk_mhz = max_dispclk_mhz ? max_dispclk_mhz : 1910 dcn3_15_soc.clock_limits[closest_clk_lvl].dispclk_mhz; 1911 1912 clock_limits[i].dppclk_mhz = max_dppclk_mhz ? max_dppclk_mhz : 1913 dcn3_15_soc.clock_limits[closest_clk_lvl].dppclk_mhz; 1914 1915 clock_limits[i].dram_bw_per_chan_gbps = dcn3_15_soc.clock_limits[closest_clk_lvl].dram_bw_per_chan_gbps; 1916 clock_limits[i].dscclk_mhz = dcn3_15_soc.clock_limits[closest_clk_lvl].dscclk_mhz; 1917 clock_limits[i].dtbclk_mhz = dcn3_15_soc.clock_limits[closest_clk_lvl].dtbclk_mhz; 1918 clock_limits[i].phyclk_d18_mhz = dcn3_15_soc.clock_limits[closest_clk_lvl].phyclk_d18_mhz; 1919 clock_limits[i].phyclk_mhz = dcn3_15_soc.clock_limits[closest_clk_lvl].phyclk_mhz; 1920 } 1921 for (i = 0; i < clk_table->num_entries; i++) 1922 dcn3_15_soc.clock_limits[i] = clock_limits[i]; 1923 if (clk_table->num_entries) { 1924 dcn3_15_soc.num_states = clk_table->num_entries; 1925 } 1926 } 1927 1928 if (max_dispclk_mhz) { 1929 dcn3_15_soc.dispclk_dppclk_vco_speed_mhz = max_dispclk_mhz * 2; 1930 dc->dml.soc.dispclk_dppclk_vco_speed_mhz = max_dispclk_mhz * 2; 1931 } 1932 1933 if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) 1934 dml_init_instance(&dc->dml, &dcn3_15_soc, &dcn3_15_ip, DML_PROJECT_DCN31); 1935 else 1936 dml_init_instance(&dc->dml, &dcn3_15_soc, &dcn3_15_ip, DML_PROJECT_DCN31_FPGA); 1937 } 1938 1939 static struct resource_funcs dcn315_res_pool_funcs = { 1940 .destroy = dcn315_destroy_resource_pool, 1941 .link_enc_create = dcn31_link_encoder_create, 1942 .link_enc_create_minimal = dcn31_link_enc_create_minimal, 1943 .link_encs_assign = link_enc_cfg_link_encs_assign, 1944 .link_enc_unassign = link_enc_cfg_link_enc_unassign, 1945 .panel_cntl_create = dcn31_panel_cntl_create, 1946 .validate_bandwidth = dcn31_validate_bandwidth, 1947 .calculate_wm_and_dlg = dcn31_calculate_wm_and_dlg, 1948 .update_soc_for_wm_a = dcn31_update_soc_for_wm_a, 1949 .populate_dml_pipes = dcn315_populate_dml_pipes_from_context, 1950 .acquire_idle_pipe_for_layer = dcn20_acquire_idle_pipe_for_layer, 1951 .add_stream_to_ctx = dcn30_add_stream_to_ctx, 1952 .add_dsc_to_stream_resource = dcn20_add_dsc_to_stream_resource, 1953 .remove_stream_from_ctx = dcn20_remove_stream_from_ctx, 1954 .populate_dml_writeback_from_context = dcn30_populate_dml_writeback_from_context, 1955 .set_mcif_arb_params = dcn30_set_mcif_arb_params, 1956 .find_first_free_match_stream_enc_for_link = dcn10_find_first_free_match_stream_enc_for_link, 1957 .acquire_post_bldn_3dlut = dcn30_acquire_post_bldn_3dlut, 1958 .release_post_bldn_3dlut = dcn30_release_post_bldn_3dlut, 1959 .update_bw_bounding_box = dcn315_update_bw_bounding_box, 1960 .patch_unknown_plane_state = dcn20_patch_unknown_plane_state, 1961 }; 1962 1963 static struct clock_source *dcn30_clock_source_create( 1964 struct dc_context *ctx, 1965 struct dc_bios *bios, 1966 enum clock_source_id id, 1967 const struct dce110_clk_src_regs *regs, 1968 bool dp_clk_src) 1969 { 1970 struct dce110_clk_src *clk_src = 1971 kzalloc(sizeof(struct dce110_clk_src), GFP_KERNEL); 1972 1973 if (!clk_src) 1974 return NULL; 1975 1976 if (dcn3_clk_src_construct(clk_src, ctx, bios, id, 1977 regs, &cs_shift, &cs_mask)) { 1978 clk_src->base.dp_clk_src = dp_clk_src; 1979 return &clk_src->base; 1980 } 1981 1982 BREAK_TO_DEBUGGER(); 1983 return NULL; 1984 } 1985 1986 static bool dcn315_resource_construct( 1987 uint8_t num_virtual_links, 1988 struct dc *dc, 1989 struct dcn315_resource_pool *pool) 1990 { 1991 int i; 1992 struct dc_context *ctx = dc->ctx; 1993 struct irq_service_init_data init_data; 1994 1995 ctx->dc_bios->regs = &bios_regs; 1996 1997 pool->base.res_cap = &res_cap_dcn31; 1998 1999 pool->base.funcs = &dcn315_res_pool_funcs; 2000 2001 /************************************************* 2002 * Resource + asic cap harcoding * 2003 *************************************************/ 2004 pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE; 2005 pool->base.pipe_count = pool->base.res_cap->num_timing_generator; 2006 pool->base.mpcc_count = pool->base.res_cap->num_timing_generator; 2007 dc->caps.max_downscale_ratio = 600; 2008 dc->caps.i2c_speed_in_khz = 100; 2009 dc->caps.i2c_speed_in_khz_hdcp = 5; /*1.4 w/a applied by default*/ 2010 dc->caps.max_cursor_size = 256; 2011 dc->caps.min_horizontal_blanking_period = 80; 2012 dc->caps.dmdata_alloc_size = 2048; 2013 2014 dc->caps.max_slave_planes = 1; 2015 dc->caps.max_slave_yuv_planes = 1; 2016 dc->caps.max_slave_rgb_planes = 1; 2017 dc->caps.post_blend_color_processing = true; 2018 dc->caps.force_dp_tps4_for_cp2520 = true; 2019 dc->caps.dp_hpo = true; 2020 dc->caps.edp_dsc_support = true; 2021 dc->caps.extended_aux_timeout_support = true; 2022 dc->caps.dmcub_support = true; 2023 dc->caps.is_apu = true; 2024 2025 /* Color pipeline capabilities */ 2026 dc->caps.color.dpp.dcn_arch = 1; 2027 dc->caps.color.dpp.input_lut_shared = 0; 2028 dc->caps.color.dpp.icsc = 1; 2029 dc->caps.color.dpp.dgam_ram = 0; // must use gamma_corr 2030 dc->caps.color.dpp.dgam_rom_caps.srgb = 1; 2031 dc->caps.color.dpp.dgam_rom_caps.bt2020 = 1; 2032 dc->caps.color.dpp.dgam_rom_caps.gamma2_2 = 1; 2033 dc->caps.color.dpp.dgam_rom_caps.pq = 1; 2034 dc->caps.color.dpp.dgam_rom_caps.hlg = 1; 2035 dc->caps.color.dpp.post_csc = 1; 2036 dc->caps.color.dpp.gamma_corr = 1; 2037 dc->caps.color.dpp.dgam_rom_for_yuv = 0; 2038 2039 dc->caps.color.dpp.hw_3d_lut = 1; 2040 dc->caps.color.dpp.ogam_ram = 1; 2041 // no OGAM ROM on DCN301 2042 dc->caps.color.dpp.ogam_rom_caps.srgb = 0; 2043 dc->caps.color.dpp.ogam_rom_caps.bt2020 = 0; 2044 dc->caps.color.dpp.ogam_rom_caps.gamma2_2 = 0; 2045 dc->caps.color.dpp.ogam_rom_caps.pq = 0; 2046 dc->caps.color.dpp.ogam_rom_caps.hlg = 0; 2047 dc->caps.color.dpp.ocsc = 0; 2048 2049 dc->caps.color.mpc.gamut_remap = 1; 2050 dc->caps.color.mpc.num_3dluts = pool->base.res_cap->num_mpc_3dlut; //2 2051 dc->caps.color.mpc.ogam_ram = 1; 2052 dc->caps.color.mpc.ogam_rom_caps.srgb = 0; 2053 dc->caps.color.mpc.ogam_rom_caps.bt2020 = 0; 2054 dc->caps.color.mpc.ogam_rom_caps.gamma2_2 = 0; 2055 dc->caps.color.mpc.ogam_rom_caps.pq = 0; 2056 dc->caps.color.mpc.ogam_rom_caps.hlg = 0; 2057 dc->caps.color.mpc.ocsc = 1; 2058 2059 /* read VBIOS LTTPR caps */ 2060 { 2061 if (ctx->dc_bios->funcs->get_lttpr_caps) { 2062 enum bp_result bp_query_result; 2063 uint8_t is_vbios_lttpr_enable = 0; 2064 2065 bp_query_result = ctx->dc_bios->funcs->get_lttpr_caps(ctx->dc_bios, &is_vbios_lttpr_enable); 2066 dc->caps.vbios_lttpr_enable = (bp_query_result == BP_RESULT_OK) && !!is_vbios_lttpr_enable; 2067 } 2068 2069 /* interop bit is implicit */ 2070 { 2071 dc->caps.vbios_lttpr_aware = true; 2072 } 2073 } 2074 2075 if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV) 2076 dc->debug = debug_defaults_drv; 2077 else if (dc->ctx->dce_environment == DCE_ENV_FPGA_MAXIMUS) { 2078 dc->debug = debug_defaults_diags; 2079 } else 2080 dc->debug = debug_defaults_diags; 2081 // Init the vm_helper 2082 if (dc->vm_helper) 2083 vm_helper_init(dc->vm_helper, 16); 2084 2085 /************************************************* 2086 * Create resources * 2087 *************************************************/ 2088 2089 /* Clock Sources for Pixel Clock*/ 2090 pool->base.clock_sources[DCN31_CLK_SRC_PLL0] = 2091 dcn30_clock_source_create(ctx, ctx->dc_bios, 2092 CLOCK_SOURCE_COMBO_PHY_PLL0, 2093 &clk_src_regs[0], false); 2094 pool->base.clock_sources[DCN31_CLK_SRC_PLL1] = 2095 dcn30_clock_source_create(ctx, ctx->dc_bios, 2096 CLOCK_SOURCE_COMBO_PHY_PLL1, 2097 &clk_src_regs[1], false); 2098 pool->base.clock_sources[DCN31_CLK_SRC_PLL2] = 2099 dcn30_clock_source_create(ctx, ctx->dc_bios, 2100 CLOCK_SOURCE_COMBO_PHY_PLL2, 2101 &clk_src_regs[2], false); 2102 pool->base.clock_sources[DCN31_CLK_SRC_PLL3] = 2103 dcn30_clock_source_create(ctx, ctx->dc_bios, 2104 CLOCK_SOURCE_COMBO_PHY_PLL3, 2105 &clk_src_regs[3], false); 2106 pool->base.clock_sources[DCN31_CLK_SRC_PLL4] = 2107 dcn30_clock_source_create(ctx, ctx->dc_bios, 2108 CLOCK_SOURCE_COMBO_PHY_PLL4, 2109 &clk_src_regs[4], false); 2110 2111 pool->base.clk_src_count = DCN30_CLK_SRC_TOTAL; 2112 2113 /* todo: not reuse phy_pll registers */ 2114 pool->base.dp_clock_source = 2115 dcn31_clock_source_create(ctx, ctx->dc_bios, 2116 CLOCK_SOURCE_ID_DP_DTO, 2117 &clk_src_regs[0], true); 2118 2119 for (i = 0; i < pool->base.clk_src_count; i++) { 2120 if (pool->base.clock_sources[i] == NULL) { 2121 dm_error("DC: failed to create clock sources!\n"); 2122 BREAK_TO_DEBUGGER(); 2123 goto create_fail; 2124 } 2125 } 2126 2127 /* TODO: DCCG */ 2128 pool->base.dccg = dccg31_create(ctx, &dccg_regs, &dccg_shift, &dccg_mask); 2129 if (pool->base.dccg == NULL) { 2130 dm_error("DC: failed to create dccg!\n"); 2131 BREAK_TO_DEBUGGER(); 2132 goto create_fail; 2133 } 2134 2135 /* TODO: IRQ */ 2136 init_data.ctx = dc->ctx; 2137 pool->base.irqs = dal_irq_service_dcn315_create(&init_data); 2138 if (!pool->base.irqs) 2139 goto create_fail; 2140 2141 /* HUBBUB */ 2142 pool->base.hubbub = dcn31_hubbub_create(ctx); 2143 if (pool->base.hubbub == NULL) { 2144 BREAK_TO_DEBUGGER(); 2145 dm_error("DC: failed to create hubbub!\n"); 2146 goto create_fail; 2147 } 2148 2149 /* HUBPs, DPPs, OPPs and TGs */ 2150 for (i = 0; i < pool->base.pipe_count; i++) { 2151 pool->base.hubps[i] = dcn31_hubp_create(ctx, i); 2152 if (pool->base.hubps[i] == NULL) { 2153 BREAK_TO_DEBUGGER(); 2154 dm_error( 2155 "DC: failed to create hubps!\n"); 2156 goto create_fail; 2157 } 2158 2159 pool->base.dpps[i] = dcn31_dpp_create(ctx, i); 2160 if (pool->base.dpps[i] == NULL) { 2161 BREAK_TO_DEBUGGER(); 2162 dm_error( 2163 "DC: failed to create dpps!\n"); 2164 goto create_fail; 2165 } 2166 } 2167 2168 for (i = 0; i < pool->base.res_cap->num_opp; i++) { 2169 pool->base.opps[i] = dcn31_opp_create(ctx, i); 2170 if (pool->base.opps[i] == NULL) { 2171 BREAK_TO_DEBUGGER(); 2172 dm_error( 2173 "DC: failed to create output pixel processor!\n"); 2174 goto create_fail; 2175 } 2176 } 2177 2178 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { 2179 pool->base.timing_generators[i] = dcn31_timing_generator_create( 2180 ctx, i); 2181 if (pool->base.timing_generators[i] == NULL) { 2182 BREAK_TO_DEBUGGER(); 2183 dm_error("DC: failed to create tg!\n"); 2184 goto create_fail; 2185 } 2186 } 2187 pool->base.timing_generator_count = i; 2188 2189 /* PSR */ 2190 pool->base.psr = dmub_psr_create(ctx); 2191 if (pool->base.psr == NULL) { 2192 dm_error("DC: failed to create psr obj!\n"); 2193 BREAK_TO_DEBUGGER(); 2194 goto create_fail; 2195 } 2196 2197 /* ABM */ 2198 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { 2199 pool->base.multiple_abms[i] = dmub_abm_create(ctx, 2200 &abm_regs[i], 2201 &abm_shift, 2202 &abm_mask); 2203 if (pool->base.multiple_abms[i] == NULL) { 2204 dm_error("DC: failed to create abm for pipe %d!\n", i); 2205 BREAK_TO_DEBUGGER(); 2206 goto create_fail; 2207 } 2208 } 2209 2210 /* MPC and DSC */ 2211 pool->base.mpc = dcn31_mpc_create(ctx, pool->base.mpcc_count, pool->base.res_cap->num_mpc_3dlut); 2212 if (pool->base.mpc == NULL) { 2213 BREAK_TO_DEBUGGER(); 2214 dm_error("DC: failed to create mpc!\n"); 2215 goto create_fail; 2216 } 2217 2218 for (i = 0; i < pool->base.res_cap->num_dsc; i++) { 2219 pool->base.dscs[i] = dcn31_dsc_create(ctx, i); 2220 if (pool->base.dscs[i] == NULL) { 2221 BREAK_TO_DEBUGGER(); 2222 dm_error("DC: failed to create display stream compressor %d!\n", i); 2223 goto create_fail; 2224 } 2225 } 2226 2227 /* DWB and MMHUBBUB */ 2228 if (!dcn31_dwbc_create(ctx, &pool->base)) { 2229 BREAK_TO_DEBUGGER(); 2230 dm_error("DC: failed to create dwbc!\n"); 2231 goto create_fail; 2232 } 2233 2234 if (!dcn31_mmhubbub_create(ctx, &pool->base)) { 2235 BREAK_TO_DEBUGGER(); 2236 dm_error("DC: failed to create mcif_wb!\n"); 2237 goto create_fail; 2238 } 2239 2240 /* AUX and I2C */ 2241 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { 2242 pool->base.engines[i] = dcn31_aux_engine_create(ctx, i); 2243 if (pool->base.engines[i] == NULL) { 2244 BREAK_TO_DEBUGGER(); 2245 dm_error( 2246 "DC:failed to create aux engine!!\n"); 2247 goto create_fail; 2248 } 2249 pool->base.hw_i2cs[i] = dcn31_i2c_hw_create(ctx, i); 2250 if (pool->base.hw_i2cs[i] == NULL) { 2251 BREAK_TO_DEBUGGER(); 2252 dm_error( 2253 "DC:failed to create hw i2c!!\n"); 2254 goto create_fail; 2255 } 2256 pool->base.sw_i2cs[i] = NULL; 2257 } 2258 2259 /* Audio, Stream Encoders including HPO and virtual, MPC 3D LUTs */ 2260 if (!resource_construct(num_virtual_links, dc, &pool->base, 2261 (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment) ? 2262 &res_create_funcs : &res_create_maximus_funcs))) 2263 goto create_fail; 2264 2265 /* HW Sequencer and Plane caps */ 2266 dcn31_hw_sequencer_construct(dc); 2267 2268 dc->caps.max_planes = pool->base.pipe_count; 2269 2270 for (i = 0; i < dc->caps.max_planes; ++i) 2271 dc->caps.planes[i] = plane_cap; 2272 2273 dc->cap_funcs = cap_funcs; 2274 2275 dc->dcn_ip->max_num_dpp = dcn3_15_ip.max_num_dpp; 2276 2277 return true; 2278 2279 create_fail: 2280 2281 dcn315_resource_destruct(pool); 2282 2283 return false; 2284 } 2285 2286 struct resource_pool *dcn315_create_resource_pool( 2287 const struct dc_init_data *init_data, 2288 struct dc *dc) 2289 { 2290 struct dcn315_resource_pool *pool = 2291 kzalloc(sizeof(struct dcn315_resource_pool), GFP_KERNEL); 2292 2293 if (!pool) 2294 return NULL; 2295 2296 if (dcn315_resource_construct(init_data->num_virtual_links, dc, pool)) 2297 return &pool->base; 2298 2299 BREAK_TO_DEBUGGER(); 2300 kfree(pool); 2301 return NULL; 2302 } 2303