1 /* 2 * Copyright 2021 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 27 #include "dm_services.h" 28 #include "dc.h" 29 30 #include "dcn31/dcn31_init.h" 31 32 #include "resource.h" 33 #include "include/irq_service_interface.h" 34 #include "dcn315_resource.h" 35 36 #include "dcn20/dcn20_resource.h" 37 #include "dcn30/dcn30_resource.h" 38 #include "dcn31/dcn31_resource.h" 39 40 #include "dcn10/dcn10_ipp.h" 41 #include "dcn30/dcn30_hubbub.h" 42 #include "dcn31/dcn31_hubbub.h" 43 #include "dcn30/dcn30_mpc.h" 44 #include "dcn31/dcn31_hubp.h" 45 #include "irq/dcn315/irq_service_dcn315.h" 46 #include "dcn30/dcn30_dpp.h" 47 #include "dcn31/dcn31_optc.h" 48 #include "dcn20/dcn20_hwseq.h" 49 #include "dcn30/dcn30_hwseq.h" 50 #include "dce110/dce110_hw_sequencer.h" 51 #include "dcn30/dcn30_opp.h" 52 #include "dcn20/dcn20_dsc.h" 53 #include "dcn30/dcn30_vpg.h" 54 #include "dcn30/dcn30_afmt.h" 55 #include "dcn30/dcn30_dio_stream_encoder.h" 56 #include "dcn31/dcn31_hpo_dp_stream_encoder.h" 57 #include "dcn31/dcn31_hpo_dp_link_encoder.h" 58 #include "dcn31/dcn31_apg.h" 59 #include "dcn31/dcn31_dio_link_encoder.h" 60 #include "dcn31/dcn31_vpg.h" 61 #include "dcn31/dcn31_afmt.h" 62 #include "dce/dce_clock_source.h" 63 #include "dce/dce_audio.h" 64 #include "dce/dce_hwseq.h" 65 #include "clk_mgr.h" 66 #include "virtual/virtual_stream_encoder.h" 67 #include "dce110/dce110_resource.h" 68 #include "dml/display_mode_vba.h" 69 #include "dml/dcn31/dcn31_fpu.h" 70 #include "dcn31/dcn31_dccg.h" 71 #include "dcn10/dcn10_resource.h" 72 #include "dcn31/dcn31_panel_cntl.h" 73 74 #include "dcn30/dcn30_dwb.h" 75 #include "dcn30/dcn30_mmhubbub.h" 76 77 #include "dcn/dcn_3_1_5_offset.h" 78 #include "dcn/dcn_3_1_5_sh_mask.h" 79 #include "dpcs/dpcs_4_2_2_offset.h" 80 #include "dpcs/dpcs_4_2_2_sh_mask.h" 81 82 #define NBIO_BASE__INST0_SEG0 0x00000000 83 #define NBIO_BASE__INST0_SEG1 0x00000014 84 #define NBIO_BASE__INST0_SEG2 0x00000D20 85 #define NBIO_BASE__INST0_SEG3 0x00010400 86 #define NBIO_BASE__INST0_SEG4 0x0241B000 87 #define NBIO_BASE__INST0_SEG5 0x04040000 88 89 #define DPCS_BASE__INST0_SEG0 0x00000012 90 #define DPCS_BASE__INST0_SEG1 0x000000C0 91 #define DPCS_BASE__INST0_SEG2 0x000034C0 92 #define DPCS_BASE__INST0_SEG3 0x00009000 93 #define DPCS_BASE__INST0_SEG4 0x02403C00 94 #define DPCS_BASE__INST0_SEG5 0 95 96 #define DCN_BASE__INST0_SEG0 0x00000012 97 #define DCN_BASE__INST0_SEG1 0x000000C0 98 #define DCN_BASE__INST0_SEG2 0x000034C0 99 #define DCN_BASE__INST0_SEG3 0x00009000 100 #define DCN_BASE__INST0_SEG4 0x02403C00 101 #define DCN_BASE__INST0_SEG5 0 102 103 #define regBIF_BX_PF2_RSMU_INDEX 0x0000 104 #define regBIF_BX_PF2_RSMU_INDEX_BASE_IDX 1 105 #define regBIF_BX_PF2_RSMU_DATA 0x0001 106 #define regBIF_BX_PF2_RSMU_DATA_BASE_IDX 1 107 #define regBIF_BX2_BIOS_SCRATCH_6 0x003e 108 #define regBIF_BX2_BIOS_SCRATCH_6_BASE_IDX 1 109 #define BIF_BX2_BIOS_SCRATCH_6__BIOS_SCRATCH_6__SHIFT 0x0 110 #define BIF_BX2_BIOS_SCRATCH_6__BIOS_SCRATCH_6_MASK 0xFFFFFFFFL 111 #define regBIF_BX2_BIOS_SCRATCH_2 0x003a 112 #define regBIF_BX2_BIOS_SCRATCH_2_BASE_IDX 1 113 #define BIF_BX2_BIOS_SCRATCH_2__BIOS_SCRATCH_2__SHIFT 0x0 114 #define BIF_BX2_BIOS_SCRATCH_2__BIOS_SCRATCH_2_MASK 0xFFFFFFFFL 115 #define regBIF_BX2_BIOS_SCRATCH_3 0x003b 116 #define regBIF_BX2_BIOS_SCRATCH_3_BASE_IDX 1 117 #define BIF_BX2_BIOS_SCRATCH_3__BIOS_SCRATCH_3__SHIFT 0x0 118 #define BIF_BX2_BIOS_SCRATCH_3__BIOS_SCRATCH_3_MASK 0xFFFFFFFFL 119 120 #define regDCHUBBUB_DEBUG_CTRL_0 0x04d6 121 #define regDCHUBBUB_DEBUG_CTRL_0_BASE_IDX 2 122 #define DCHUBBUB_DEBUG_CTRL_0__DET_DEPTH__SHIFT 0x10 123 #define DCHUBBUB_DEBUG_CTRL_0__DET_DEPTH_MASK 0x01FF0000L 124 125 #include "reg_helper.h" 126 #include "dce/dmub_abm.h" 127 #include "dce/dmub_psr.h" 128 #include "dce/dce_aux.h" 129 #include "dce/dce_i2c.h" 130 131 #include "dml/dcn30/display_mode_vba_30.h" 132 #include "vm_helper.h" 133 #include "dcn20/dcn20_vmid.h" 134 135 #include "link_enc_cfg.h" 136 137 #define DCN3_15_MAX_DET_SIZE 384 138 #define DCN3_15_CRB_SEGMENT_SIZE_KB 64 139 140 enum dcn31_clk_src_array_id { 141 DCN31_CLK_SRC_PLL0, 142 DCN31_CLK_SRC_PLL1, 143 DCN31_CLK_SRC_PLL2, 144 DCN31_CLK_SRC_PLL3, 145 DCN31_CLK_SRC_PLL4, 146 DCN30_CLK_SRC_TOTAL 147 }; 148 149 /* begin ********************* 150 * macros to expend register list macro defined in HW object header file 151 */ 152 153 /* DCN */ 154 /* TODO awful hack. fixup dcn20_dwb.h */ 155 #undef BASE_INNER 156 #define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg 157 158 #define BASE(seg) BASE_INNER(seg) 159 160 #define SR(reg_name)\ 161 .reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \ 162 reg ## reg_name 163 164 #define SRI(reg_name, block, id)\ 165 .reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 166 reg ## block ## id ## _ ## reg_name 167 168 #define SRI2(reg_name, block, id)\ 169 .reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \ 170 reg ## reg_name 171 172 #define SRIR(var_name, reg_name, block, id)\ 173 .var_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 174 reg ## block ## id ## _ ## reg_name 175 176 #define SRII(reg_name, block, id)\ 177 .reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 178 reg ## block ## id ## _ ## reg_name 179 180 #define SRII_MPC_RMU(reg_name, block, id)\ 181 .RMU##_##reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 182 reg ## block ## id ## _ ## reg_name 183 184 #define SRII_DWB(reg_name, temp_name, block, id)\ 185 .reg_name[id] = BASE(reg ## block ## id ## _ ## temp_name ## _BASE_IDX) + \ 186 reg ## block ## id ## _ ## temp_name 187 188 #define DCCG_SRII(reg_name, block, id)\ 189 .block ## _ ## reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 190 reg ## block ## id ## _ ## reg_name 191 192 #define VUPDATE_SRII(reg_name, block, id)\ 193 .reg_name[id] = BASE(reg ## reg_name ## _ ## block ## id ## _BASE_IDX) + \ 194 reg ## reg_name ## _ ## block ## id 195 196 /* NBIO */ 197 #define NBIO_BASE_INNER(seg) \ 198 NBIO_BASE__INST0_SEG ## seg 199 200 #define NBIO_BASE(seg) \ 201 NBIO_BASE_INNER(seg) 202 203 #define NBIO_SR(reg_name)\ 204 .reg_name = NBIO_BASE(regBIF_BX2_ ## reg_name ## _BASE_IDX) + \ 205 regBIF_BX2_ ## reg_name 206 207 static const struct bios_registers bios_regs = { 208 NBIO_SR(BIOS_SCRATCH_3), 209 NBIO_SR(BIOS_SCRATCH_6) 210 }; 211 212 #define clk_src_regs(index, pllid)\ 213 [index] = {\ 214 CS_COMMON_REG_LIST_DCN3_0(index, pllid),\ 215 } 216 217 static const struct dce110_clk_src_regs clk_src_regs[] = { 218 clk_src_regs(0, A), 219 clk_src_regs(1, B), 220 clk_src_regs(2, C), 221 clk_src_regs(3, D), 222 clk_src_regs(4, E) 223 }; 224 225 static const struct dce110_clk_src_shift cs_shift = { 226 CS_COMMON_MASK_SH_LIST_DCN2_0(__SHIFT) 227 }; 228 229 static const struct dce110_clk_src_mask cs_mask = { 230 CS_COMMON_MASK_SH_LIST_DCN2_0(_MASK) 231 }; 232 233 #define abm_regs(id)\ 234 [id] = {\ 235 ABM_DCN302_REG_LIST(id)\ 236 } 237 238 static const struct dce_abm_registers abm_regs[] = { 239 abm_regs(0), 240 abm_regs(1), 241 abm_regs(2), 242 abm_regs(3), 243 }; 244 245 static const struct dce_abm_shift abm_shift = { 246 ABM_MASK_SH_LIST_DCN30(__SHIFT) 247 }; 248 249 static const struct dce_abm_mask abm_mask = { 250 ABM_MASK_SH_LIST_DCN30(_MASK) 251 }; 252 253 #define audio_regs(id)\ 254 [id] = {\ 255 AUD_COMMON_REG_LIST(id)\ 256 } 257 258 static const struct dce_audio_registers audio_regs[] = { 259 audio_regs(0), 260 audio_regs(1), 261 audio_regs(2), 262 audio_regs(3), 263 audio_regs(4), 264 audio_regs(5), 265 audio_regs(6) 266 }; 267 268 #define DCE120_AUD_COMMON_MASK_SH_LIST(mask_sh)\ 269 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX, AZALIA_ENDPOINT_REG_INDEX, mask_sh),\ 270 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA, AZALIA_ENDPOINT_REG_DATA, mask_sh),\ 271 AUD_COMMON_MASK_SH_LIST_BASE(mask_sh) 272 273 static const struct dce_audio_shift audio_shift = { 274 DCE120_AUD_COMMON_MASK_SH_LIST(__SHIFT) 275 }; 276 277 static const struct dce_audio_mask audio_mask = { 278 DCE120_AUD_COMMON_MASK_SH_LIST(_MASK) 279 }; 280 281 #define vpg_regs(id)\ 282 [id] = {\ 283 VPG_DCN31_REG_LIST(id)\ 284 } 285 286 static const struct dcn31_vpg_registers vpg_regs[] = { 287 vpg_regs(0), 288 vpg_regs(1), 289 vpg_regs(2), 290 vpg_regs(3), 291 vpg_regs(4), 292 vpg_regs(5), 293 vpg_regs(6), 294 vpg_regs(7), 295 vpg_regs(8), 296 vpg_regs(9), 297 }; 298 299 static const struct dcn31_vpg_shift vpg_shift = { 300 DCN31_VPG_MASK_SH_LIST(__SHIFT) 301 }; 302 303 static const struct dcn31_vpg_mask vpg_mask = { 304 DCN31_VPG_MASK_SH_LIST(_MASK) 305 }; 306 307 #define afmt_regs(id)\ 308 [id] = {\ 309 AFMT_DCN31_REG_LIST(id)\ 310 } 311 312 static const struct dcn31_afmt_registers afmt_regs[] = { 313 afmt_regs(0), 314 afmt_regs(1), 315 afmt_regs(2), 316 afmt_regs(3), 317 afmt_regs(4), 318 afmt_regs(5) 319 }; 320 321 static const struct dcn31_afmt_shift afmt_shift = { 322 DCN31_AFMT_MASK_SH_LIST(__SHIFT) 323 }; 324 325 static const struct dcn31_afmt_mask afmt_mask = { 326 DCN31_AFMT_MASK_SH_LIST(_MASK) 327 }; 328 329 #define apg_regs(id)\ 330 [id] = {\ 331 APG_DCN31_REG_LIST(id)\ 332 } 333 334 static const struct dcn31_apg_registers apg_regs[] = { 335 apg_regs(0), 336 apg_regs(1), 337 apg_regs(2), 338 apg_regs(3) 339 }; 340 341 static const struct dcn31_apg_shift apg_shift = { 342 DCN31_APG_MASK_SH_LIST(__SHIFT) 343 }; 344 345 static const struct dcn31_apg_mask apg_mask = { 346 DCN31_APG_MASK_SH_LIST(_MASK) 347 }; 348 349 #define stream_enc_regs(id)\ 350 [id] = {\ 351 SE_DCN3_REG_LIST(id)\ 352 } 353 354 static const struct dcn10_stream_enc_registers stream_enc_regs[] = { 355 stream_enc_regs(0), 356 stream_enc_regs(1), 357 stream_enc_regs(2), 358 stream_enc_regs(3), 359 stream_enc_regs(4) 360 }; 361 362 static const struct dcn10_stream_encoder_shift se_shift = { 363 SE_COMMON_MASK_SH_LIST_DCN30(__SHIFT) 364 }; 365 366 static const struct dcn10_stream_encoder_mask se_mask = { 367 SE_COMMON_MASK_SH_LIST_DCN30(_MASK) 368 }; 369 370 371 #define aux_regs(id)\ 372 [id] = {\ 373 DCN2_AUX_REG_LIST(id)\ 374 } 375 376 static const struct dcn10_link_enc_aux_registers link_enc_aux_regs[] = { 377 aux_regs(0), 378 aux_regs(1), 379 aux_regs(2), 380 aux_regs(3), 381 aux_regs(4) 382 }; 383 384 #define hpd_regs(id)\ 385 [id] = {\ 386 HPD_REG_LIST(id)\ 387 } 388 389 static const struct dcn10_link_enc_hpd_registers link_enc_hpd_regs[] = { 390 hpd_regs(0), 391 hpd_regs(1), 392 hpd_regs(2), 393 hpd_regs(3), 394 hpd_regs(4) 395 }; 396 397 #define link_regs(id, phyid)\ 398 [id] = {\ 399 LE_DCN31_REG_LIST(id), \ 400 UNIPHY_DCN2_REG_LIST(phyid), \ 401 DPCS_DCN31_REG_LIST(id), \ 402 } 403 404 static const struct dce110_aux_registers_shift aux_shift = { 405 DCN_AUX_MASK_SH_LIST(__SHIFT) 406 }; 407 408 static const struct dce110_aux_registers_mask aux_mask = { 409 DCN_AUX_MASK_SH_LIST(_MASK) 410 }; 411 412 static const struct dcn10_link_enc_registers link_enc_regs[] = { 413 link_regs(0, A), 414 link_regs(1, B), 415 link_regs(2, C), 416 link_regs(3, D), 417 link_regs(4, E) 418 }; 419 420 static const struct dcn10_link_enc_shift le_shift = { 421 LINK_ENCODER_MASK_SH_LIST_DCN31(__SHIFT), \ 422 DPCS_DCN31_MASK_SH_LIST(__SHIFT) 423 }; 424 425 static const struct dcn10_link_enc_mask le_mask = { 426 LINK_ENCODER_MASK_SH_LIST_DCN31(_MASK), \ 427 DPCS_DCN31_MASK_SH_LIST(_MASK) 428 }; 429 430 #define hpo_dp_stream_encoder_reg_list(id)\ 431 [id] = {\ 432 DCN3_1_HPO_DP_STREAM_ENC_REG_LIST(id)\ 433 } 434 435 static const struct dcn31_hpo_dp_stream_encoder_registers hpo_dp_stream_enc_regs[] = { 436 hpo_dp_stream_encoder_reg_list(0), 437 hpo_dp_stream_encoder_reg_list(1), 438 hpo_dp_stream_encoder_reg_list(2), 439 hpo_dp_stream_encoder_reg_list(3), 440 }; 441 442 static const struct dcn31_hpo_dp_stream_encoder_shift hpo_dp_se_shift = { 443 DCN3_1_HPO_DP_STREAM_ENC_MASK_SH_LIST(__SHIFT) 444 }; 445 446 static const struct dcn31_hpo_dp_stream_encoder_mask hpo_dp_se_mask = { 447 DCN3_1_HPO_DP_STREAM_ENC_MASK_SH_LIST(_MASK) 448 }; 449 450 451 #define hpo_dp_link_encoder_reg_list(id)\ 452 [id] = {\ 453 DCN3_1_HPO_DP_LINK_ENC_REG_LIST(id),\ 454 DCN3_1_RDPCSTX_REG_LIST(0),\ 455 DCN3_1_RDPCSTX_REG_LIST(1),\ 456 DCN3_1_RDPCSTX_REG_LIST(2),\ 457 DCN3_1_RDPCSTX_REG_LIST(3),\ 458 DCN3_1_RDPCSTX_REG_LIST(4)\ 459 } 460 461 static const struct dcn31_hpo_dp_link_encoder_registers hpo_dp_link_enc_regs[] = { 462 hpo_dp_link_encoder_reg_list(0), 463 hpo_dp_link_encoder_reg_list(1), 464 }; 465 466 static const struct dcn31_hpo_dp_link_encoder_shift hpo_dp_le_shift = { 467 DCN3_1_HPO_DP_LINK_ENC_MASK_SH_LIST(__SHIFT) 468 }; 469 470 static const struct dcn31_hpo_dp_link_encoder_mask hpo_dp_le_mask = { 471 DCN3_1_HPO_DP_LINK_ENC_MASK_SH_LIST(_MASK) 472 }; 473 474 #define dpp_regs(id)\ 475 [id] = {\ 476 DPP_REG_LIST_DCN30(id),\ 477 } 478 479 static const struct dcn3_dpp_registers dpp_regs[] = { 480 dpp_regs(0), 481 dpp_regs(1), 482 dpp_regs(2), 483 dpp_regs(3) 484 }; 485 486 static const struct dcn3_dpp_shift tf_shift = { 487 DPP_REG_LIST_SH_MASK_DCN30(__SHIFT) 488 }; 489 490 static const struct dcn3_dpp_mask tf_mask = { 491 DPP_REG_LIST_SH_MASK_DCN30(_MASK) 492 }; 493 494 #define opp_regs(id)\ 495 [id] = {\ 496 OPP_REG_LIST_DCN30(id),\ 497 } 498 499 static const struct dcn20_opp_registers opp_regs[] = { 500 opp_regs(0), 501 opp_regs(1), 502 opp_regs(2), 503 opp_regs(3) 504 }; 505 506 static const struct dcn20_opp_shift opp_shift = { 507 OPP_MASK_SH_LIST_DCN20(__SHIFT) 508 }; 509 510 static const struct dcn20_opp_mask opp_mask = { 511 OPP_MASK_SH_LIST_DCN20(_MASK) 512 }; 513 514 #define aux_engine_regs(id)\ 515 [id] = {\ 516 AUX_COMMON_REG_LIST0(id), \ 517 .AUXN_IMPCAL = 0, \ 518 .AUXP_IMPCAL = 0, \ 519 .AUX_RESET_MASK = DP_AUX0_AUX_CONTROL__AUX_RESET_MASK, \ 520 } 521 522 static const struct dce110_aux_registers aux_engine_regs[] = { 523 aux_engine_regs(0), 524 aux_engine_regs(1), 525 aux_engine_regs(2), 526 aux_engine_regs(3), 527 aux_engine_regs(4) 528 }; 529 530 #define dwbc_regs_dcn3(id)\ 531 [id] = {\ 532 DWBC_COMMON_REG_LIST_DCN30(id),\ 533 } 534 535 static const struct dcn30_dwbc_registers dwbc30_regs[] = { 536 dwbc_regs_dcn3(0), 537 }; 538 539 static const struct dcn30_dwbc_shift dwbc30_shift = { 540 DWBC_COMMON_MASK_SH_LIST_DCN30(__SHIFT) 541 }; 542 543 static const struct dcn30_dwbc_mask dwbc30_mask = { 544 DWBC_COMMON_MASK_SH_LIST_DCN30(_MASK) 545 }; 546 547 #define mcif_wb_regs_dcn3(id)\ 548 [id] = {\ 549 MCIF_WB_COMMON_REG_LIST_DCN30(id),\ 550 } 551 552 static const struct dcn30_mmhubbub_registers mcif_wb30_regs[] = { 553 mcif_wb_regs_dcn3(0) 554 }; 555 556 static const struct dcn30_mmhubbub_shift mcif_wb30_shift = { 557 MCIF_WB_COMMON_MASK_SH_LIST_DCN30(__SHIFT) 558 }; 559 560 static const struct dcn30_mmhubbub_mask mcif_wb30_mask = { 561 MCIF_WB_COMMON_MASK_SH_LIST_DCN30(_MASK) 562 }; 563 564 #define dsc_regsDCN20(id)\ 565 [id] = {\ 566 DSC_REG_LIST_DCN20(id)\ 567 } 568 569 static const struct dcn20_dsc_registers dsc_regs[] = { 570 dsc_regsDCN20(0), 571 dsc_regsDCN20(1), 572 dsc_regsDCN20(2) 573 }; 574 575 static const struct dcn20_dsc_shift dsc_shift = { 576 DSC_REG_LIST_SH_MASK_DCN20(__SHIFT) 577 }; 578 579 static const struct dcn20_dsc_mask dsc_mask = { 580 DSC_REG_LIST_SH_MASK_DCN20(_MASK) 581 }; 582 583 static const struct dcn30_mpc_registers mpc_regs = { 584 MPC_REG_LIST_DCN3_0(0), 585 MPC_REG_LIST_DCN3_0(1), 586 MPC_REG_LIST_DCN3_0(2), 587 MPC_REG_LIST_DCN3_0(3), 588 MPC_OUT_MUX_REG_LIST_DCN3_0(0), 589 MPC_OUT_MUX_REG_LIST_DCN3_0(1), 590 MPC_OUT_MUX_REG_LIST_DCN3_0(2), 591 MPC_OUT_MUX_REG_LIST_DCN3_0(3), 592 MPC_DWB_MUX_REG_LIST_DCN3_0(0), 593 }; 594 595 static const struct dcn30_mpc_shift mpc_shift = { 596 MPC_COMMON_MASK_SH_LIST_DCN30(__SHIFT) 597 }; 598 599 static const struct dcn30_mpc_mask mpc_mask = { 600 MPC_COMMON_MASK_SH_LIST_DCN30(_MASK) 601 }; 602 603 #define optc_regs(id)\ 604 [id] = {OPTC_COMMON_REG_LIST_DCN3_1(id)} 605 606 static const struct dcn_optc_registers optc_regs[] = { 607 optc_regs(0), 608 optc_regs(1), 609 optc_regs(2), 610 optc_regs(3) 611 }; 612 613 static const struct dcn_optc_shift optc_shift = { 614 OPTC_COMMON_MASK_SH_LIST_DCN3_1(__SHIFT) 615 }; 616 617 static const struct dcn_optc_mask optc_mask = { 618 OPTC_COMMON_MASK_SH_LIST_DCN3_1(_MASK) 619 }; 620 621 #define hubp_regs(id)\ 622 [id] = {\ 623 HUBP_REG_LIST_DCN30(id)\ 624 } 625 626 static const struct dcn_hubp2_registers hubp_regs[] = { 627 hubp_regs(0), 628 hubp_regs(1), 629 hubp_regs(2), 630 hubp_regs(3) 631 }; 632 633 634 static const struct dcn_hubp2_shift hubp_shift = { 635 HUBP_MASK_SH_LIST_DCN31(__SHIFT) 636 }; 637 638 static const struct dcn_hubp2_mask hubp_mask = { 639 HUBP_MASK_SH_LIST_DCN31(_MASK) 640 }; 641 static const struct dcn_hubbub_registers hubbub_reg = { 642 HUBBUB_REG_LIST_DCN31(0) 643 }; 644 645 static const struct dcn_hubbub_shift hubbub_shift = { 646 HUBBUB_MASK_SH_LIST_DCN31(__SHIFT) 647 }; 648 649 static const struct dcn_hubbub_mask hubbub_mask = { 650 HUBBUB_MASK_SH_LIST_DCN31(_MASK) 651 }; 652 653 static const struct dccg_registers dccg_regs = { 654 DCCG_REG_LIST_DCN31() 655 }; 656 657 static const struct dccg_shift dccg_shift = { 658 DCCG_MASK_SH_LIST_DCN31(__SHIFT) 659 }; 660 661 static const struct dccg_mask dccg_mask = { 662 DCCG_MASK_SH_LIST_DCN31(_MASK) 663 }; 664 665 666 #define SRII2(reg_name_pre, reg_name_post, id)\ 667 .reg_name_pre ## _ ## reg_name_post[id] = BASE(reg ## reg_name_pre \ 668 ## id ## _ ## reg_name_post ## _BASE_IDX) + \ 669 reg ## reg_name_pre ## id ## _ ## reg_name_post 670 671 672 #define HWSEQ_DCN31_REG_LIST()\ 673 SR(DCHUBBUB_GLOBAL_TIMER_CNTL), \ 674 SR(DCHUBBUB_ARB_HOSTVM_CNTL), \ 675 SR(DIO_MEM_PWR_CTRL), \ 676 SR(ODM_MEM_PWR_CTRL3), \ 677 SR(DMU_MEM_PWR_CNTL), \ 678 SR(MMHUBBUB_MEM_PWR_CNTL), \ 679 SR(DCCG_GATE_DISABLE_CNTL), \ 680 SR(DCCG_GATE_DISABLE_CNTL2), \ 681 SR(DCFCLK_CNTL),\ 682 SR(DC_MEM_GLOBAL_PWR_REQ_CNTL), \ 683 SRII(PIXEL_RATE_CNTL, OTG, 0), \ 684 SRII(PIXEL_RATE_CNTL, OTG, 1),\ 685 SRII(PIXEL_RATE_CNTL, OTG, 2),\ 686 SRII(PIXEL_RATE_CNTL, OTG, 3),\ 687 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 0),\ 688 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 1),\ 689 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 2),\ 690 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 3),\ 691 SR(MICROSECOND_TIME_BASE_DIV), \ 692 SR(MILLISECOND_TIME_BASE_DIV), \ 693 SR(DISPCLK_FREQ_CHANGE_CNTL), \ 694 SR(RBBMIF_TIMEOUT_DIS), \ 695 SR(RBBMIF_TIMEOUT_DIS_2), \ 696 SR(DCHUBBUB_CRC_CTRL), \ 697 SR(DPP_TOP0_DPP_CRC_CTRL), \ 698 SR(DPP_TOP0_DPP_CRC_VAL_B_A), \ 699 SR(DPP_TOP0_DPP_CRC_VAL_R_G), \ 700 SR(MPC_CRC_CTRL), \ 701 SR(MPC_CRC_RESULT_GB), \ 702 SR(MPC_CRC_RESULT_C), \ 703 SR(MPC_CRC_RESULT_AR), \ 704 SR(DOMAIN0_PG_CONFIG), \ 705 SR(DOMAIN1_PG_CONFIG), \ 706 SR(DOMAIN2_PG_CONFIG), \ 707 SR(DOMAIN3_PG_CONFIG), \ 708 SR(DOMAIN16_PG_CONFIG), \ 709 SR(DOMAIN17_PG_CONFIG), \ 710 SR(DOMAIN18_PG_CONFIG), \ 711 SR(DOMAIN0_PG_STATUS), \ 712 SR(DOMAIN1_PG_STATUS), \ 713 SR(DOMAIN2_PG_STATUS), \ 714 SR(DOMAIN3_PG_STATUS), \ 715 SR(DOMAIN16_PG_STATUS), \ 716 SR(DOMAIN17_PG_STATUS), \ 717 SR(DOMAIN18_PG_STATUS), \ 718 SR(D1VGA_CONTROL), \ 719 SR(D2VGA_CONTROL), \ 720 SR(D3VGA_CONTROL), \ 721 SR(D4VGA_CONTROL), \ 722 SR(D5VGA_CONTROL), \ 723 SR(D6VGA_CONTROL), \ 724 SR(DC_IP_REQUEST_CNTL), \ 725 SR(AZALIA_AUDIO_DTO), \ 726 SR(AZALIA_CONTROLLER_CLOCK_GATING), \ 727 SR(HPO_TOP_HW_CONTROL) 728 729 static const struct dce_hwseq_registers hwseq_reg = { 730 HWSEQ_DCN31_REG_LIST() 731 }; 732 733 #define HWSEQ_DCN31_MASK_SH_LIST(mask_sh)\ 734 HWSEQ_DCN_MASK_SH_LIST(mask_sh), \ 735 HWS_SF(, DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_REFDIV, mask_sh), \ 736 HWS_SF(, DCHUBBUB_ARB_HOSTVM_CNTL, DISABLE_HOSTVM_FORCE_ALLOW_PSTATE, mask_sh), \ 737 HWS_SF(, DOMAIN0_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ 738 HWS_SF(, DOMAIN0_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ 739 HWS_SF(, DOMAIN1_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ 740 HWS_SF(, DOMAIN1_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ 741 HWS_SF(, DOMAIN2_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ 742 HWS_SF(, DOMAIN2_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ 743 HWS_SF(, DOMAIN3_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ 744 HWS_SF(, DOMAIN3_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ 745 HWS_SF(, DOMAIN16_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ 746 HWS_SF(, DOMAIN16_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ 747 HWS_SF(, DOMAIN17_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ 748 HWS_SF(, DOMAIN17_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ 749 HWS_SF(, DOMAIN18_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ 750 HWS_SF(, DOMAIN18_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ 751 HWS_SF(, DOMAIN0_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ 752 HWS_SF(, DOMAIN1_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ 753 HWS_SF(, DOMAIN2_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ 754 HWS_SF(, DOMAIN3_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ 755 HWS_SF(, DOMAIN16_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ 756 HWS_SF(, DOMAIN17_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ 757 HWS_SF(, DOMAIN18_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ 758 HWS_SF(, DC_IP_REQUEST_CNTL, IP_REQUEST_EN, mask_sh), \ 759 HWS_SF(, AZALIA_AUDIO_DTO, AZALIA_AUDIO_DTO_MODULE, mask_sh), \ 760 HWS_SF(, HPO_TOP_CLOCK_CONTROL, HPO_HDMISTREAMCLK_G_GATE_DIS, mask_sh), \ 761 HWS_SF(, DMU_MEM_PWR_CNTL, DMCU_ERAM_MEM_PWR_FORCE, mask_sh), \ 762 HWS_SF(, ODM_MEM_PWR_CTRL3, ODM_MEM_UNASSIGNED_PWR_MODE, mask_sh), \ 763 HWS_SF(, ODM_MEM_PWR_CTRL3, ODM_MEM_VBLANK_PWR_MODE, mask_sh), \ 764 HWS_SF(, MMHUBBUB_MEM_PWR_CNTL, VGA_MEM_PWR_FORCE, mask_sh), \ 765 HWS_SF(, DIO_MEM_PWR_CTRL, I2C_LIGHT_SLEEP_FORCE, mask_sh), \ 766 HWS_SF(, HPO_TOP_HW_CONTROL, HPO_IO_EN, mask_sh) 767 768 static const struct dce_hwseq_shift hwseq_shift = { 769 HWSEQ_DCN31_MASK_SH_LIST(__SHIFT) 770 }; 771 772 static const struct dce_hwseq_mask hwseq_mask = { 773 HWSEQ_DCN31_MASK_SH_LIST(_MASK) 774 }; 775 #define vmid_regs(id)\ 776 [id] = {\ 777 DCN20_VMID_REG_LIST(id)\ 778 } 779 780 static const struct dcn_vmid_registers vmid_regs[] = { 781 vmid_regs(0), 782 vmid_regs(1), 783 vmid_regs(2), 784 vmid_regs(3), 785 vmid_regs(4), 786 vmid_regs(5), 787 vmid_regs(6), 788 vmid_regs(7), 789 vmid_regs(8), 790 vmid_regs(9), 791 vmid_regs(10), 792 vmid_regs(11), 793 vmid_regs(12), 794 vmid_regs(13), 795 vmid_regs(14), 796 vmid_regs(15) 797 }; 798 799 static const struct dcn20_vmid_shift vmid_shifts = { 800 DCN20_VMID_MASK_SH_LIST(__SHIFT) 801 }; 802 803 static const struct dcn20_vmid_mask vmid_masks = { 804 DCN20_VMID_MASK_SH_LIST(_MASK) 805 }; 806 807 static const struct resource_caps res_cap_dcn31 = { 808 .num_timing_generator = 4, 809 .num_opp = 4, 810 .num_video_plane = 4, 811 .num_audio = 5, 812 .num_stream_encoder = 5, 813 .num_dig_link_enc = 5, 814 .num_hpo_dp_stream_encoder = 4, 815 .num_hpo_dp_link_encoder = 2, 816 .num_pll = 5, 817 .num_dwb = 1, 818 .num_ddc = 5, 819 .num_vmid = 16, 820 .num_mpc_3dlut = 2, 821 .num_dsc = 3, 822 }; 823 824 static const struct dc_plane_cap plane_cap = { 825 .type = DC_PLANE_TYPE_DCN_UNIVERSAL, 826 .blends_with_above = true, 827 .blends_with_below = true, 828 .per_pixel_alpha = true, 829 830 .pixel_format_support = { 831 .argb8888 = true, 832 .nv12 = true, 833 .fp16 = true, 834 .p010 = true, 835 .ayuv = false, 836 }, 837 838 .max_upscale_factor = { 839 .argb8888 = 16000, 840 .nv12 = 16000, 841 .fp16 = 16000 842 }, 843 844 // 6:1 downscaling ratio: 1000/6 = 166.666 845 .max_downscale_factor = { 846 .argb8888 = 167, 847 .nv12 = 167, 848 .fp16 = 167 849 }, 850 64, 851 64 852 }; 853 854 static const struct dc_debug_options debug_defaults_drv = { 855 .disable_z10 = true, /*hw not support it*/ 856 .disable_dmcu = true, 857 .force_abm_enable = false, 858 .timing_trace = false, 859 .clock_trace = true, 860 .disable_pplib_clock_request = false, 861 .pipe_split_policy = MPC_SPLIT_DYNAMIC, 862 .force_single_disp_pipe_split = false, 863 .disable_dcc = DCC_ENABLE, 864 .vsr_support = true, 865 .performance_trace = false, 866 .max_downscale_src_width = 4096,/*upto true 4k*/ 867 .disable_pplib_wm_range = false, 868 .scl_reset_length10 = true, 869 .sanity_checks = false, 870 .underflow_assert_delay_us = 0xFFFFFFFF, 871 .dwb_fi_phase = -1, // -1 = disable, 872 .dmub_command_table = true, 873 .pstate_enabled = true, 874 .use_max_lb = true, 875 .enable_mem_low_power = { 876 .bits = { 877 .vga = true, 878 .i2c = true, 879 .dmcu = false, // This is previously known to cause hang on S3 cycles if enabled 880 .dscl = true, 881 .cm = true, 882 .mpc = true, 883 .optc = true, 884 .vpg = true, 885 .afmt = true, 886 } 887 }, 888 .optimize_edp_link_rate = true, 889 .enable_sw_cntl_psr = true, 890 .psr_power_use_phy_fsm = 0, 891 }; 892 893 static const struct dc_debug_options debug_defaults_diags = { 894 .disable_dmcu = true, 895 .force_abm_enable = false, 896 .timing_trace = true, 897 .clock_trace = true, 898 .disable_dpp_power_gate = true, 899 .disable_hubp_power_gate = true, 900 .disable_clock_gate = true, 901 .disable_pplib_clock_request = true, 902 .disable_pplib_wm_range = true, 903 .disable_stutter = false, 904 .scl_reset_length10 = true, 905 .dwb_fi_phase = -1, // -1 = disable 906 .dmub_command_table = true, 907 .enable_tri_buf = true, 908 .use_max_lb = true 909 }; 910 911 static void dcn31_dpp_destroy(struct dpp **dpp) 912 { 913 kfree(TO_DCN20_DPP(*dpp)); 914 *dpp = NULL; 915 } 916 917 static struct dpp *dcn31_dpp_create( 918 struct dc_context *ctx, 919 uint32_t inst) 920 { 921 struct dcn3_dpp *dpp = 922 kzalloc(sizeof(struct dcn3_dpp), GFP_KERNEL); 923 924 if (!dpp) 925 return NULL; 926 927 if (dpp3_construct(dpp, ctx, inst, 928 &dpp_regs[inst], &tf_shift, &tf_mask)) 929 return &dpp->base; 930 931 BREAK_TO_DEBUGGER(); 932 kfree(dpp); 933 return NULL; 934 } 935 936 static struct output_pixel_processor *dcn31_opp_create( 937 struct dc_context *ctx, uint32_t inst) 938 { 939 struct dcn20_opp *opp = 940 kzalloc(sizeof(struct dcn20_opp), GFP_KERNEL); 941 942 if (!opp) { 943 BREAK_TO_DEBUGGER(); 944 return NULL; 945 } 946 947 dcn20_opp_construct(opp, ctx, inst, 948 &opp_regs[inst], &opp_shift, &opp_mask); 949 return &opp->base; 950 } 951 952 static struct dce_aux *dcn31_aux_engine_create( 953 struct dc_context *ctx, 954 uint32_t inst) 955 { 956 struct aux_engine_dce110 *aux_engine = 957 kzalloc(sizeof(struct aux_engine_dce110), GFP_KERNEL); 958 959 if (!aux_engine) 960 return NULL; 961 962 dce110_aux_engine_construct(aux_engine, ctx, inst, 963 SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD, 964 &aux_engine_regs[inst], 965 &aux_mask, 966 &aux_shift, 967 ctx->dc->caps.extended_aux_timeout_support); 968 969 return &aux_engine->base; 970 } 971 #define i2c_inst_regs(id) { I2C_HW_ENGINE_COMMON_REG_LIST_DCN30(id) } 972 973 static const struct dce_i2c_registers i2c_hw_regs[] = { 974 i2c_inst_regs(1), 975 i2c_inst_regs(2), 976 i2c_inst_regs(3), 977 i2c_inst_regs(4), 978 i2c_inst_regs(5), 979 }; 980 981 static const struct dce_i2c_shift i2c_shifts = { 982 I2C_COMMON_MASK_SH_LIST_DCN30(__SHIFT) 983 }; 984 985 static const struct dce_i2c_mask i2c_masks = { 986 I2C_COMMON_MASK_SH_LIST_DCN30(_MASK) 987 }; 988 989 static struct dce_i2c_hw *dcn31_i2c_hw_create( 990 struct dc_context *ctx, 991 uint32_t inst) 992 { 993 struct dce_i2c_hw *dce_i2c_hw = 994 kzalloc(sizeof(struct dce_i2c_hw), GFP_KERNEL); 995 996 if (!dce_i2c_hw) 997 return NULL; 998 999 dcn2_i2c_hw_construct(dce_i2c_hw, ctx, inst, 1000 &i2c_hw_regs[inst], &i2c_shifts, &i2c_masks); 1001 1002 return dce_i2c_hw; 1003 } 1004 static struct mpc *dcn31_mpc_create( 1005 struct dc_context *ctx, 1006 int num_mpcc, 1007 int num_rmu) 1008 { 1009 struct dcn30_mpc *mpc30 = kzalloc(sizeof(struct dcn30_mpc), 1010 GFP_KERNEL); 1011 1012 if (!mpc30) 1013 return NULL; 1014 1015 dcn30_mpc_construct(mpc30, ctx, 1016 &mpc_regs, 1017 &mpc_shift, 1018 &mpc_mask, 1019 num_mpcc, 1020 num_rmu); 1021 1022 return &mpc30->base; 1023 } 1024 1025 static struct hubbub *dcn31_hubbub_create(struct dc_context *ctx) 1026 { 1027 int i; 1028 1029 struct dcn20_hubbub *hubbub3 = kzalloc(sizeof(struct dcn20_hubbub), 1030 GFP_KERNEL); 1031 1032 if (!hubbub3) 1033 return NULL; 1034 1035 hubbub31_construct(hubbub3, ctx, 1036 &hubbub_reg, 1037 &hubbub_shift, 1038 &hubbub_mask, 1039 dcn3_15_ip.det_buffer_size_kbytes, 1040 dcn3_15_ip.pixel_chunk_size_kbytes, 1041 dcn3_15_ip.config_return_buffer_size_in_kbytes); 1042 1043 1044 for (i = 0; i < res_cap_dcn31.num_vmid; i++) { 1045 struct dcn20_vmid *vmid = &hubbub3->vmid[i]; 1046 1047 vmid->ctx = ctx; 1048 1049 vmid->regs = &vmid_regs[i]; 1050 vmid->shifts = &vmid_shifts; 1051 vmid->masks = &vmid_masks; 1052 } 1053 1054 return &hubbub3->base; 1055 } 1056 1057 static struct timing_generator *dcn31_timing_generator_create( 1058 struct dc_context *ctx, 1059 uint32_t instance) 1060 { 1061 struct optc *tgn10 = 1062 kzalloc(sizeof(struct optc), GFP_KERNEL); 1063 1064 if (!tgn10) 1065 return NULL; 1066 1067 tgn10->base.inst = instance; 1068 tgn10->base.ctx = ctx; 1069 1070 tgn10->tg_regs = &optc_regs[instance]; 1071 tgn10->tg_shift = &optc_shift; 1072 tgn10->tg_mask = &optc_mask; 1073 1074 dcn31_timing_generator_init(tgn10); 1075 1076 return &tgn10->base; 1077 } 1078 1079 static const struct encoder_feature_support link_enc_feature = { 1080 .max_hdmi_deep_color = COLOR_DEPTH_121212, 1081 .max_hdmi_pixel_clock = 600000, 1082 .hdmi_ycbcr420_supported = true, 1083 .dp_ycbcr420_supported = true, 1084 .fec_supported = true, 1085 .flags.bits.IS_HBR2_CAPABLE = true, 1086 .flags.bits.IS_HBR3_CAPABLE = true, 1087 .flags.bits.IS_TPS3_CAPABLE = true, 1088 .flags.bits.IS_TPS4_CAPABLE = true 1089 }; 1090 1091 static struct link_encoder *dcn31_link_encoder_create( 1092 const struct encoder_init_data *enc_init_data) 1093 { 1094 struct dcn20_link_encoder *enc20 = 1095 kzalloc(sizeof(struct dcn20_link_encoder), GFP_KERNEL); 1096 1097 if (!enc20) 1098 return NULL; 1099 1100 dcn31_link_encoder_construct(enc20, 1101 enc_init_data, 1102 &link_enc_feature, 1103 &link_enc_regs[enc_init_data->transmitter], 1104 &link_enc_aux_regs[enc_init_data->channel - 1], 1105 &link_enc_hpd_regs[enc_init_data->hpd_source], 1106 &le_shift, 1107 &le_mask); 1108 1109 return &enc20->enc10.base; 1110 } 1111 1112 /* Create a minimal link encoder object not associated with a particular 1113 * physical connector. 1114 * resource_funcs.link_enc_create_minimal 1115 */ 1116 static struct link_encoder *dcn31_link_enc_create_minimal( 1117 struct dc_context *ctx, enum engine_id eng_id) 1118 { 1119 struct dcn20_link_encoder *enc20; 1120 1121 if ((eng_id - ENGINE_ID_DIGA) > ctx->dc->res_pool->res_cap->num_dig_link_enc) 1122 return NULL; 1123 1124 enc20 = kzalloc(sizeof(struct dcn20_link_encoder), GFP_KERNEL); 1125 if (!enc20) 1126 return NULL; 1127 1128 dcn31_link_encoder_construct_minimal( 1129 enc20, 1130 ctx, 1131 &link_enc_feature, 1132 &link_enc_regs[eng_id - ENGINE_ID_DIGA], 1133 eng_id); 1134 1135 return &enc20->enc10.base; 1136 } 1137 1138 static struct panel_cntl *dcn31_panel_cntl_create(const struct panel_cntl_init_data *init_data) 1139 { 1140 struct dcn31_panel_cntl *panel_cntl = 1141 kzalloc(sizeof(struct dcn31_panel_cntl), GFP_KERNEL); 1142 1143 if (!panel_cntl) 1144 return NULL; 1145 1146 dcn31_panel_cntl_construct(panel_cntl, init_data); 1147 1148 return &panel_cntl->base; 1149 } 1150 1151 static void read_dce_straps( 1152 struct dc_context *ctx, 1153 struct resource_straps *straps) 1154 { 1155 generic_reg_get(ctx, regDC_PINSTRAPS + BASE(regDC_PINSTRAPS_BASE_IDX), 1156 FN(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO), &straps->dc_pinstraps_audio); 1157 1158 } 1159 1160 static struct audio *dcn31_create_audio( 1161 struct dc_context *ctx, unsigned int inst) 1162 { 1163 return dce_audio_create(ctx, inst, 1164 &audio_regs[inst], &audio_shift, &audio_mask); 1165 } 1166 1167 static struct vpg *dcn31_vpg_create( 1168 struct dc_context *ctx, 1169 uint32_t inst) 1170 { 1171 struct dcn31_vpg *vpg31 = kzalloc(sizeof(struct dcn31_vpg), GFP_KERNEL); 1172 1173 if (!vpg31) 1174 return NULL; 1175 1176 vpg31_construct(vpg31, ctx, inst, 1177 &vpg_regs[inst], 1178 &vpg_shift, 1179 &vpg_mask); 1180 1181 return &vpg31->base; 1182 } 1183 1184 static struct afmt *dcn31_afmt_create( 1185 struct dc_context *ctx, 1186 uint32_t inst) 1187 { 1188 struct dcn31_afmt *afmt31 = kzalloc(sizeof(struct dcn31_afmt), GFP_KERNEL); 1189 1190 if (!afmt31) 1191 return NULL; 1192 1193 afmt31_construct(afmt31, ctx, inst, 1194 &afmt_regs[inst], 1195 &afmt_shift, 1196 &afmt_mask); 1197 1198 // Light sleep by default, no need to power down here 1199 1200 return &afmt31->base; 1201 } 1202 1203 static struct apg *dcn31_apg_create( 1204 struct dc_context *ctx, 1205 uint32_t inst) 1206 { 1207 struct dcn31_apg *apg31 = kzalloc(sizeof(struct dcn31_apg), GFP_KERNEL); 1208 1209 if (!apg31) 1210 return NULL; 1211 1212 apg31_construct(apg31, ctx, inst, 1213 &apg_regs[inst], 1214 &apg_shift, 1215 &apg_mask); 1216 1217 return &apg31->base; 1218 } 1219 1220 static struct stream_encoder *dcn315_stream_encoder_create( 1221 enum engine_id eng_id, 1222 struct dc_context *ctx) 1223 { 1224 struct dcn10_stream_encoder *enc1; 1225 struct vpg *vpg; 1226 struct afmt *afmt; 1227 int vpg_inst; 1228 int afmt_inst; 1229 1230 /*PHYB is wired off in HW, allow front end to remapping, otherwise needs more changes*/ 1231 1232 /* Mapping of VPG, AFMT, DME register blocks to DIO block instance */ 1233 if (eng_id <= ENGINE_ID_DIGF) { 1234 vpg_inst = eng_id; 1235 afmt_inst = eng_id; 1236 } else 1237 return NULL; 1238 1239 enc1 = kzalloc(sizeof(struct dcn10_stream_encoder), GFP_KERNEL); 1240 vpg = dcn31_vpg_create(ctx, vpg_inst); 1241 afmt = dcn31_afmt_create(ctx, afmt_inst); 1242 1243 if (!enc1 || !vpg || !afmt) { 1244 kfree(enc1); 1245 kfree(vpg); 1246 kfree(afmt); 1247 return NULL; 1248 } 1249 1250 dcn30_dio_stream_encoder_construct(enc1, ctx, ctx->dc_bios, 1251 eng_id, vpg, afmt, 1252 &stream_enc_regs[eng_id], 1253 &se_shift, &se_mask); 1254 1255 return &enc1->base; 1256 } 1257 1258 static struct hpo_dp_stream_encoder *dcn31_hpo_dp_stream_encoder_create( 1259 enum engine_id eng_id, 1260 struct dc_context *ctx) 1261 { 1262 struct dcn31_hpo_dp_stream_encoder *hpo_dp_enc31; 1263 struct vpg *vpg; 1264 struct apg *apg; 1265 uint32_t hpo_dp_inst; 1266 uint32_t vpg_inst; 1267 uint32_t apg_inst; 1268 1269 ASSERT((eng_id >= ENGINE_ID_HPO_DP_0) && (eng_id <= ENGINE_ID_HPO_DP_3)); 1270 hpo_dp_inst = eng_id - ENGINE_ID_HPO_DP_0; 1271 1272 /* Mapping of VPG register blocks to HPO DP block instance: 1273 * VPG[6] -> HPO_DP[0] 1274 * VPG[7] -> HPO_DP[1] 1275 * VPG[8] -> HPO_DP[2] 1276 * VPG[9] -> HPO_DP[3] 1277 */ 1278 vpg_inst = hpo_dp_inst + 6; 1279 1280 /* Mapping of APG register blocks to HPO DP block instance: 1281 * APG[0] -> HPO_DP[0] 1282 * APG[1] -> HPO_DP[1] 1283 * APG[2] -> HPO_DP[2] 1284 * APG[3] -> HPO_DP[3] 1285 */ 1286 apg_inst = hpo_dp_inst; 1287 1288 /* allocate HPO stream encoder and create VPG sub-block */ 1289 hpo_dp_enc31 = kzalloc(sizeof(struct dcn31_hpo_dp_stream_encoder), GFP_KERNEL); 1290 vpg = dcn31_vpg_create(ctx, vpg_inst); 1291 apg = dcn31_apg_create(ctx, apg_inst); 1292 1293 if (!hpo_dp_enc31 || !vpg || !apg) { 1294 kfree(hpo_dp_enc31); 1295 kfree(vpg); 1296 kfree(apg); 1297 return NULL; 1298 } 1299 1300 dcn31_hpo_dp_stream_encoder_construct(hpo_dp_enc31, ctx, ctx->dc_bios, 1301 hpo_dp_inst, eng_id, vpg, apg, 1302 &hpo_dp_stream_enc_regs[hpo_dp_inst], 1303 &hpo_dp_se_shift, &hpo_dp_se_mask); 1304 1305 return &hpo_dp_enc31->base; 1306 } 1307 1308 static struct hpo_dp_link_encoder *dcn31_hpo_dp_link_encoder_create( 1309 uint8_t inst, 1310 struct dc_context *ctx) 1311 { 1312 struct dcn31_hpo_dp_link_encoder *hpo_dp_enc31; 1313 1314 /* allocate HPO link encoder */ 1315 hpo_dp_enc31 = kzalloc(sizeof(struct dcn31_hpo_dp_link_encoder), GFP_KERNEL); 1316 1317 hpo_dp_link_encoder31_construct(hpo_dp_enc31, ctx, inst, 1318 &hpo_dp_link_enc_regs[inst], 1319 &hpo_dp_le_shift, &hpo_dp_le_mask); 1320 1321 return &hpo_dp_enc31->base; 1322 } 1323 1324 static struct dce_hwseq *dcn31_hwseq_create( 1325 struct dc_context *ctx) 1326 { 1327 struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_KERNEL); 1328 1329 if (hws) { 1330 hws->ctx = ctx; 1331 hws->regs = &hwseq_reg; 1332 hws->shifts = &hwseq_shift; 1333 hws->masks = &hwseq_mask; 1334 /* DCN3.1 FPGA Workaround 1335 * Need to enable HPO DP Stream Encoder before setting OTG master enable. 1336 * To do so, move calling function enable_stream_timing to only be done AFTER calling 1337 * function core_link_enable_stream 1338 */ 1339 if (IS_FPGA_MAXIMUS_DC(ctx->dce_environment)) 1340 hws->wa.dp_hpo_and_otg_sequence = true; 1341 } 1342 return hws; 1343 } 1344 static const struct resource_create_funcs res_create_funcs = { 1345 .read_dce_straps = read_dce_straps, 1346 .create_audio = dcn31_create_audio, 1347 .create_stream_encoder = dcn315_stream_encoder_create, 1348 .create_hpo_dp_stream_encoder = dcn31_hpo_dp_stream_encoder_create, 1349 .create_hpo_dp_link_encoder = dcn31_hpo_dp_link_encoder_create, 1350 .create_hwseq = dcn31_hwseq_create, 1351 }; 1352 1353 static const struct resource_create_funcs res_create_maximus_funcs = { 1354 .read_dce_straps = NULL, 1355 .create_audio = NULL, 1356 .create_stream_encoder = NULL, 1357 .create_hpo_dp_stream_encoder = dcn31_hpo_dp_stream_encoder_create, 1358 .create_hpo_dp_link_encoder = dcn31_hpo_dp_link_encoder_create, 1359 .create_hwseq = dcn31_hwseq_create, 1360 }; 1361 1362 static void dcn315_resource_destruct(struct dcn315_resource_pool *pool) 1363 { 1364 unsigned int i; 1365 1366 for (i = 0; i < pool->base.stream_enc_count; i++) { 1367 if (pool->base.stream_enc[i] != NULL) { 1368 if (pool->base.stream_enc[i]->vpg != NULL) { 1369 kfree(DCN30_VPG_FROM_VPG(pool->base.stream_enc[i]->vpg)); 1370 pool->base.stream_enc[i]->vpg = NULL; 1371 } 1372 if (pool->base.stream_enc[i]->afmt != NULL) { 1373 kfree(DCN30_AFMT_FROM_AFMT(pool->base.stream_enc[i]->afmt)); 1374 pool->base.stream_enc[i]->afmt = NULL; 1375 } 1376 kfree(DCN10STRENC_FROM_STRENC(pool->base.stream_enc[i])); 1377 pool->base.stream_enc[i] = NULL; 1378 } 1379 } 1380 1381 for (i = 0; i < pool->base.hpo_dp_stream_enc_count; i++) { 1382 if (pool->base.hpo_dp_stream_enc[i] != NULL) { 1383 if (pool->base.hpo_dp_stream_enc[i]->vpg != NULL) { 1384 kfree(DCN30_VPG_FROM_VPG(pool->base.hpo_dp_stream_enc[i]->vpg)); 1385 pool->base.hpo_dp_stream_enc[i]->vpg = NULL; 1386 } 1387 if (pool->base.hpo_dp_stream_enc[i]->apg != NULL) { 1388 kfree(DCN31_APG_FROM_APG(pool->base.hpo_dp_stream_enc[i]->apg)); 1389 pool->base.hpo_dp_stream_enc[i]->apg = NULL; 1390 } 1391 kfree(DCN3_1_HPO_DP_STREAM_ENC_FROM_HPO_STREAM_ENC(pool->base.hpo_dp_stream_enc[i])); 1392 pool->base.hpo_dp_stream_enc[i] = NULL; 1393 } 1394 } 1395 1396 for (i = 0; i < pool->base.hpo_dp_link_enc_count; i++) { 1397 if (pool->base.hpo_dp_link_enc[i] != NULL) { 1398 kfree(DCN3_1_HPO_DP_LINK_ENC_FROM_HPO_LINK_ENC(pool->base.hpo_dp_link_enc[i])); 1399 pool->base.hpo_dp_link_enc[i] = NULL; 1400 } 1401 } 1402 1403 for (i = 0; i < pool->base.res_cap->num_dsc; i++) { 1404 if (pool->base.dscs[i] != NULL) 1405 dcn20_dsc_destroy(&pool->base.dscs[i]); 1406 } 1407 1408 if (pool->base.mpc != NULL) { 1409 kfree(TO_DCN20_MPC(pool->base.mpc)); 1410 pool->base.mpc = NULL; 1411 } 1412 if (pool->base.hubbub != NULL) { 1413 kfree(pool->base.hubbub); 1414 pool->base.hubbub = NULL; 1415 } 1416 for (i = 0; i < pool->base.pipe_count; i++) { 1417 if (pool->base.dpps[i] != NULL) 1418 dcn31_dpp_destroy(&pool->base.dpps[i]); 1419 1420 if (pool->base.ipps[i] != NULL) 1421 pool->base.ipps[i]->funcs->ipp_destroy(&pool->base.ipps[i]); 1422 1423 if (pool->base.hubps[i] != NULL) { 1424 kfree(TO_DCN20_HUBP(pool->base.hubps[i])); 1425 pool->base.hubps[i] = NULL; 1426 } 1427 1428 if (pool->base.irqs != NULL) { 1429 dal_irq_service_destroy(&pool->base.irqs); 1430 } 1431 } 1432 1433 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { 1434 if (pool->base.engines[i] != NULL) 1435 dce110_engine_destroy(&pool->base.engines[i]); 1436 if (pool->base.hw_i2cs[i] != NULL) { 1437 kfree(pool->base.hw_i2cs[i]); 1438 pool->base.hw_i2cs[i] = NULL; 1439 } 1440 if (pool->base.sw_i2cs[i] != NULL) { 1441 kfree(pool->base.sw_i2cs[i]); 1442 pool->base.sw_i2cs[i] = NULL; 1443 } 1444 } 1445 1446 for (i = 0; i < pool->base.res_cap->num_opp; i++) { 1447 if (pool->base.opps[i] != NULL) 1448 pool->base.opps[i]->funcs->opp_destroy(&pool->base.opps[i]); 1449 } 1450 1451 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { 1452 if (pool->base.timing_generators[i] != NULL) { 1453 kfree(DCN10TG_FROM_TG(pool->base.timing_generators[i])); 1454 pool->base.timing_generators[i] = NULL; 1455 } 1456 } 1457 1458 for (i = 0; i < pool->base.res_cap->num_dwb; i++) { 1459 if (pool->base.dwbc[i] != NULL) { 1460 kfree(TO_DCN30_DWBC(pool->base.dwbc[i])); 1461 pool->base.dwbc[i] = NULL; 1462 } 1463 if (pool->base.mcif_wb[i] != NULL) { 1464 kfree(TO_DCN30_MMHUBBUB(pool->base.mcif_wb[i])); 1465 pool->base.mcif_wb[i] = NULL; 1466 } 1467 } 1468 1469 for (i = 0; i < pool->base.audio_count; i++) { 1470 if (pool->base.audios[i]) 1471 dce_aud_destroy(&pool->base.audios[i]); 1472 } 1473 1474 for (i = 0; i < pool->base.clk_src_count; i++) { 1475 if (pool->base.clock_sources[i] != NULL) { 1476 dcn20_clock_source_destroy(&pool->base.clock_sources[i]); 1477 pool->base.clock_sources[i] = NULL; 1478 } 1479 } 1480 1481 for (i = 0; i < pool->base.res_cap->num_mpc_3dlut; i++) { 1482 if (pool->base.mpc_lut[i] != NULL) { 1483 dc_3dlut_func_release(pool->base.mpc_lut[i]); 1484 pool->base.mpc_lut[i] = NULL; 1485 } 1486 if (pool->base.mpc_shaper[i] != NULL) { 1487 dc_transfer_func_release(pool->base.mpc_shaper[i]); 1488 pool->base.mpc_shaper[i] = NULL; 1489 } 1490 } 1491 1492 if (pool->base.dp_clock_source != NULL) { 1493 dcn20_clock_source_destroy(&pool->base.dp_clock_source); 1494 pool->base.dp_clock_source = NULL; 1495 } 1496 1497 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { 1498 if (pool->base.multiple_abms[i] != NULL) 1499 dce_abm_destroy(&pool->base.multiple_abms[i]); 1500 } 1501 1502 if (pool->base.psr != NULL) 1503 dmub_psr_destroy(&pool->base.psr); 1504 1505 if (pool->base.dccg != NULL) 1506 dcn_dccg_destroy(&pool->base.dccg); 1507 } 1508 1509 static struct hubp *dcn31_hubp_create( 1510 struct dc_context *ctx, 1511 uint32_t inst) 1512 { 1513 struct dcn20_hubp *hubp2 = 1514 kzalloc(sizeof(struct dcn20_hubp), GFP_KERNEL); 1515 1516 if (!hubp2) 1517 return NULL; 1518 1519 if (hubp31_construct(hubp2, ctx, inst, 1520 &hubp_regs[inst], &hubp_shift, &hubp_mask)) 1521 return &hubp2->base; 1522 1523 BREAK_TO_DEBUGGER(); 1524 kfree(hubp2); 1525 return NULL; 1526 } 1527 1528 static bool dcn31_dwbc_create(struct dc_context *ctx, struct resource_pool *pool) 1529 { 1530 int i; 1531 uint32_t pipe_count = pool->res_cap->num_dwb; 1532 1533 for (i = 0; i < pipe_count; i++) { 1534 struct dcn30_dwbc *dwbc30 = kzalloc(sizeof(struct dcn30_dwbc), 1535 GFP_KERNEL); 1536 1537 if (!dwbc30) { 1538 dm_error("DC: failed to create dwbc30!\n"); 1539 return false; 1540 } 1541 1542 dcn30_dwbc_construct(dwbc30, ctx, 1543 &dwbc30_regs[i], 1544 &dwbc30_shift, 1545 &dwbc30_mask, 1546 i); 1547 1548 pool->dwbc[i] = &dwbc30->base; 1549 } 1550 return true; 1551 } 1552 1553 static bool dcn31_mmhubbub_create(struct dc_context *ctx, struct resource_pool *pool) 1554 { 1555 int i; 1556 uint32_t pipe_count = pool->res_cap->num_dwb; 1557 1558 for (i = 0; i < pipe_count; i++) { 1559 struct dcn30_mmhubbub *mcif_wb30 = kzalloc(sizeof(struct dcn30_mmhubbub), 1560 GFP_KERNEL); 1561 1562 if (!mcif_wb30) { 1563 dm_error("DC: failed to create mcif_wb30!\n"); 1564 return false; 1565 } 1566 1567 dcn30_mmhubbub_construct(mcif_wb30, ctx, 1568 &mcif_wb30_regs[i], 1569 &mcif_wb30_shift, 1570 &mcif_wb30_mask, 1571 i); 1572 1573 pool->mcif_wb[i] = &mcif_wb30->base; 1574 } 1575 return true; 1576 } 1577 1578 static struct display_stream_compressor *dcn31_dsc_create( 1579 struct dc_context *ctx, uint32_t inst) 1580 { 1581 struct dcn20_dsc *dsc = 1582 kzalloc(sizeof(struct dcn20_dsc), GFP_KERNEL); 1583 1584 if (!dsc) { 1585 BREAK_TO_DEBUGGER(); 1586 return NULL; 1587 } 1588 1589 dsc2_construct(dsc, ctx, inst, &dsc_regs[inst], &dsc_shift, &dsc_mask); 1590 return &dsc->base; 1591 } 1592 1593 static void dcn315_destroy_resource_pool(struct resource_pool **pool) 1594 { 1595 struct dcn315_resource_pool *dcn31_pool = TO_DCN315_RES_POOL(*pool); 1596 1597 dcn315_resource_destruct(dcn31_pool); 1598 kfree(dcn31_pool); 1599 *pool = NULL; 1600 } 1601 1602 static struct clock_source *dcn31_clock_source_create( 1603 struct dc_context *ctx, 1604 struct dc_bios *bios, 1605 enum clock_source_id id, 1606 const struct dce110_clk_src_regs *regs, 1607 bool dp_clk_src) 1608 { 1609 struct dce110_clk_src *clk_src = 1610 kzalloc(sizeof(struct dce110_clk_src), GFP_KERNEL); 1611 1612 if (!clk_src) 1613 return NULL; 1614 1615 if (dcn31_clk_src_construct(clk_src, ctx, bios, id, 1616 regs, &cs_shift, &cs_mask)) { 1617 clk_src->base.dp_clk_src = dp_clk_src; 1618 return &clk_src->base; 1619 } 1620 1621 BREAK_TO_DEBUGGER(); 1622 return NULL; 1623 } 1624 1625 static bool is_dual_plane(enum surface_pixel_format format) 1626 { 1627 return format >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN || format == SURFACE_PIXEL_FORMAT_GRPH_RGBE_ALPHA; 1628 } 1629 1630 static int dcn315_populate_dml_pipes_from_context( 1631 struct dc *dc, struct dc_state *context, 1632 display_e2e_pipe_params_st *pipes, 1633 bool fast_validate) 1634 { 1635 int i, pipe_cnt; 1636 struct resource_context *res_ctx = &context->res_ctx; 1637 struct pipe_ctx *pipe; 1638 const int max_usable_det = context->bw_ctx.dml.ip.config_return_buffer_size_in_kbytes - DCN3_15_MIN_COMPBUF_SIZE_KB; 1639 1640 DC_FP_START(); 1641 dcn20_populate_dml_pipes_from_context(dc, context, pipes, fast_validate); 1642 DC_FP_END(); 1643 1644 for (i = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) { 1645 struct dc_crtc_timing *timing; 1646 1647 if (!res_ctx->pipe_ctx[i].stream) 1648 continue; 1649 pipe = &res_ctx->pipe_ctx[i]; 1650 timing = &pipe->stream->timing; 1651 1652 /* 1653 * Immediate flip can be set dynamically after enabling the plane. 1654 * We need to require support for immediate flip or underflow can be 1655 * intermittently experienced depending on peak b/w requirements. 1656 */ 1657 pipes[pipe_cnt].pipe.src.immediate_flip = true; 1658 1659 pipes[pipe_cnt].pipe.src.unbounded_req_mode = false; 1660 pipes[pipe_cnt].pipe.src.gpuvm = true; 1661 pipes[pipe_cnt].pipe.src.dcc_fraction_of_zs_req_luma = 0; 1662 pipes[pipe_cnt].pipe.src.dcc_fraction_of_zs_req_chroma = 0; 1663 pipes[pipe_cnt].pipe.dest.vfront_porch = timing->v_front_porch; 1664 pipes[pipe_cnt].pipe.src.dcc_rate = 3; 1665 pipes[pipe_cnt].dout.dsc_input_bpc = 0; 1666 1667 if (pipes[pipe_cnt].dout.dsc_enable) { 1668 switch (timing->display_color_depth) { 1669 case COLOR_DEPTH_888: 1670 pipes[pipe_cnt].dout.dsc_input_bpc = 8; 1671 break; 1672 case COLOR_DEPTH_101010: 1673 pipes[pipe_cnt].dout.dsc_input_bpc = 10; 1674 break; 1675 case COLOR_DEPTH_121212: 1676 pipes[pipe_cnt].dout.dsc_input_bpc = 12; 1677 break; 1678 default: 1679 ASSERT(0); 1680 break; 1681 } 1682 } 1683 1684 pipe_cnt++; 1685 } 1686 1687 if (pipe_cnt) 1688 context->bw_ctx.dml.ip.det_buffer_size_kbytes = 1689 (max_usable_det / DCN3_15_CRB_SEGMENT_SIZE_KB / pipe_cnt) * DCN3_15_CRB_SEGMENT_SIZE_KB; 1690 if (context->bw_ctx.dml.ip.det_buffer_size_kbytes > DCN3_15_MAX_DET_SIZE) 1691 context->bw_ctx.dml.ip.det_buffer_size_kbytes = DCN3_15_MAX_DET_SIZE; 1692 ASSERT(context->bw_ctx.dml.ip.det_buffer_size_kbytes >= DCN3_15_DEFAULT_DET_SIZE); 1693 dc->config.enable_4to1MPC = false; 1694 if (pipe_cnt == 1 && pipe->plane_state && !dc->debug.disable_z9_mpc) { 1695 if (is_dual_plane(pipe->plane_state->format) 1696 && pipe->plane_state->src_rect.width <= 1920 && pipe->plane_state->src_rect.height <= 1080) { 1697 dc->config.enable_4to1MPC = true; 1698 context->bw_ctx.dml.ip.det_buffer_size_kbytes = 1699 (max_usable_det / DCN3_15_CRB_SEGMENT_SIZE_KB / 4) * DCN3_15_CRB_SEGMENT_SIZE_KB; 1700 } else if (!is_dual_plane(pipe->plane_state->format) && pipe->plane_state->src_rect.width <= 5120) { 1701 /* Limit to 5k max to avoid forced pipe split when there is not enough detile for swath */ 1702 context->bw_ctx.dml.ip.det_buffer_size_kbytes = 192; 1703 pipes[0].pipe.src.unbounded_req_mode = true; 1704 } 1705 } 1706 1707 return pipe_cnt; 1708 } 1709 1710 static struct dc_cap_funcs cap_funcs = { 1711 .get_dcc_compression_cap = dcn20_get_dcc_compression_cap 1712 }; 1713 1714 static struct resource_funcs dcn315_res_pool_funcs = { 1715 .destroy = dcn315_destroy_resource_pool, 1716 .link_enc_create = dcn31_link_encoder_create, 1717 .link_enc_create_minimal = dcn31_link_enc_create_minimal, 1718 .link_encs_assign = link_enc_cfg_link_encs_assign, 1719 .link_enc_unassign = link_enc_cfg_link_enc_unassign, 1720 .panel_cntl_create = dcn31_panel_cntl_create, 1721 .validate_bandwidth = dcn31_validate_bandwidth, 1722 .calculate_wm_and_dlg = dcn31_calculate_wm_and_dlg, 1723 .update_soc_for_wm_a = dcn31_update_soc_for_wm_a, 1724 .populate_dml_pipes = dcn315_populate_dml_pipes_from_context, 1725 .acquire_idle_pipe_for_layer = dcn20_acquire_idle_pipe_for_layer, 1726 .add_stream_to_ctx = dcn30_add_stream_to_ctx, 1727 .add_dsc_to_stream_resource = dcn20_add_dsc_to_stream_resource, 1728 .remove_stream_from_ctx = dcn20_remove_stream_from_ctx, 1729 .populate_dml_writeback_from_context = dcn31_populate_dml_writeback_from_context, 1730 .set_mcif_arb_params = dcn31_set_mcif_arb_params, 1731 .find_first_free_match_stream_enc_for_link = dcn10_find_first_free_match_stream_enc_for_link, 1732 .acquire_post_bldn_3dlut = dcn30_acquire_post_bldn_3dlut, 1733 .release_post_bldn_3dlut = dcn30_release_post_bldn_3dlut, 1734 .update_bw_bounding_box = dcn315_update_bw_bounding_box, 1735 .patch_unknown_plane_state = dcn20_patch_unknown_plane_state, 1736 }; 1737 1738 static bool dcn315_resource_construct( 1739 uint8_t num_virtual_links, 1740 struct dc *dc, 1741 struct dcn315_resource_pool *pool) 1742 { 1743 int i; 1744 struct dc_context *ctx = dc->ctx; 1745 struct irq_service_init_data init_data; 1746 1747 ctx->dc_bios->regs = &bios_regs; 1748 1749 pool->base.res_cap = &res_cap_dcn31; 1750 1751 pool->base.funcs = &dcn315_res_pool_funcs; 1752 1753 /************************************************* 1754 * Resource + asic cap harcoding * 1755 *************************************************/ 1756 pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE; 1757 pool->base.pipe_count = pool->base.res_cap->num_timing_generator; 1758 pool->base.mpcc_count = pool->base.res_cap->num_timing_generator; 1759 dc->caps.max_downscale_ratio = 600; 1760 dc->caps.i2c_speed_in_khz = 100; 1761 dc->caps.i2c_speed_in_khz_hdcp = 100; 1762 dc->caps.max_cursor_size = 256; 1763 dc->caps.min_horizontal_blanking_period = 80; 1764 dc->caps.dmdata_alloc_size = 2048; 1765 dc->caps.max_slave_planes = 1; 1766 dc->caps.max_slave_yuv_planes = 1; 1767 dc->caps.max_slave_rgb_planes = 1; 1768 dc->caps.post_blend_color_processing = true; 1769 dc->caps.force_dp_tps4_for_cp2520 = true; 1770 dc->caps.dp_hpo = true; 1771 dc->caps.edp_dsc_support = true; 1772 dc->caps.extended_aux_timeout_support = true; 1773 dc->caps.dmcub_support = true; 1774 dc->caps.is_apu = true; 1775 1776 /* Color pipeline capabilities */ 1777 dc->caps.color.dpp.dcn_arch = 1; 1778 dc->caps.color.dpp.input_lut_shared = 0; 1779 dc->caps.color.dpp.icsc = 1; 1780 dc->caps.color.dpp.dgam_ram = 0; // must use gamma_corr 1781 dc->caps.color.dpp.dgam_rom_caps.srgb = 1; 1782 dc->caps.color.dpp.dgam_rom_caps.bt2020 = 1; 1783 dc->caps.color.dpp.dgam_rom_caps.gamma2_2 = 1; 1784 dc->caps.color.dpp.dgam_rom_caps.pq = 1; 1785 dc->caps.color.dpp.dgam_rom_caps.hlg = 1; 1786 dc->caps.color.dpp.post_csc = 1; 1787 dc->caps.color.dpp.gamma_corr = 1; 1788 dc->caps.color.dpp.dgam_rom_for_yuv = 0; 1789 1790 dc->caps.color.dpp.hw_3d_lut = 1; 1791 dc->caps.color.dpp.ogam_ram = 1; 1792 // no OGAM ROM on DCN301 1793 dc->caps.color.dpp.ogam_rom_caps.srgb = 0; 1794 dc->caps.color.dpp.ogam_rom_caps.bt2020 = 0; 1795 dc->caps.color.dpp.ogam_rom_caps.gamma2_2 = 0; 1796 dc->caps.color.dpp.ogam_rom_caps.pq = 0; 1797 dc->caps.color.dpp.ogam_rom_caps.hlg = 0; 1798 dc->caps.color.dpp.ocsc = 0; 1799 1800 dc->caps.color.mpc.gamut_remap = 1; 1801 dc->caps.color.mpc.num_3dluts = pool->base.res_cap->num_mpc_3dlut; //2 1802 dc->caps.color.mpc.ogam_ram = 1; 1803 dc->caps.color.mpc.ogam_rom_caps.srgb = 0; 1804 dc->caps.color.mpc.ogam_rom_caps.bt2020 = 0; 1805 dc->caps.color.mpc.ogam_rom_caps.gamma2_2 = 0; 1806 dc->caps.color.mpc.ogam_rom_caps.pq = 0; 1807 dc->caps.color.mpc.ogam_rom_caps.hlg = 0; 1808 dc->caps.color.mpc.ocsc = 1; 1809 1810 /* read VBIOS LTTPR caps */ 1811 { 1812 if (ctx->dc_bios->funcs->get_lttpr_caps) { 1813 enum bp_result bp_query_result; 1814 uint8_t is_vbios_lttpr_enable = 0; 1815 1816 bp_query_result = ctx->dc_bios->funcs->get_lttpr_caps(ctx->dc_bios, &is_vbios_lttpr_enable); 1817 dc->caps.vbios_lttpr_enable = (bp_query_result == BP_RESULT_OK) && !!is_vbios_lttpr_enable; 1818 } 1819 1820 /* interop bit is implicit */ 1821 { 1822 dc->caps.vbios_lttpr_aware = true; 1823 } 1824 } 1825 1826 if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV) 1827 dc->debug = debug_defaults_drv; 1828 else if (dc->ctx->dce_environment == DCE_ENV_FPGA_MAXIMUS) { 1829 dc->debug = debug_defaults_diags; 1830 } else 1831 dc->debug = debug_defaults_diags; 1832 // Init the vm_helper 1833 if (dc->vm_helper) 1834 vm_helper_init(dc->vm_helper, 16); 1835 1836 /************************************************* 1837 * Create resources * 1838 *************************************************/ 1839 1840 /* Clock Sources for Pixel Clock*/ 1841 pool->base.clock_sources[DCN31_CLK_SRC_PLL0] = 1842 dcn31_clock_source_create(ctx, ctx->dc_bios, 1843 CLOCK_SOURCE_COMBO_PHY_PLL0, 1844 &clk_src_regs[0], false); 1845 pool->base.clock_sources[DCN31_CLK_SRC_PLL1] = 1846 dcn31_clock_source_create(ctx, ctx->dc_bios, 1847 CLOCK_SOURCE_COMBO_PHY_PLL1, 1848 &clk_src_regs[1], false); 1849 pool->base.clock_sources[DCN31_CLK_SRC_PLL2] = 1850 dcn31_clock_source_create(ctx, ctx->dc_bios, 1851 CLOCK_SOURCE_COMBO_PHY_PLL2, 1852 &clk_src_regs[2], false); 1853 pool->base.clock_sources[DCN31_CLK_SRC_PLL3] = 1854 dcn31_clock_source_create(ctx, ctx->dc_bios, 1855 CLOCK_SOURCE_COMBO_PHY_PLL3, 1856 &clk_src_regs[3], false); 1857 pool->base.clock_sources[DCN31_CLK_SRC_PLL4] = 1858 dcn31_clock_source_create(ctx, ctx->dc_bios, 1859 CLOCK_SOURCE_COMBO_PHY_PLL4, 1860 &clk_src_regs[4], false); 1861 1862 pool->base.clk_src_count = DCN30_CLK_SRC_TOTAL; 1863 1864 /* todo: not reuse phy_pll registers */ 1865 pool->base.dp_clock_source = 1866 dcn31_clock_source_create(ctx, ctx->dc_bios, 1867 CLOCK_SOURCE_ID_DP_DTO, 1868 &clk_src_regs[0], true); 1869 1870 for (i = 0; i < pool->base.clk_src_count; i++) { 1871 if (pool->base.clock_sources[i] == NULL) { 1872 dm_error("DC: failed to create clock sources!\n"); 1873 BREAK_TO_DEBUGGER(); 1874 goto create_fail; 1875 } 1876 } 1877 1878 /* TODO: DCCG */ 1879 pool->base.dccg = dccg31_create(ctx, &dccg_regs, &dccg_shift, &dccg_mask); 1880 if (pool->base.dccg == NULL) { 1881 dm_error("DC: failed to create dccg!\n"); 1882 BREAK_TO_DEBUGGER(); 1883 goto create_fail; 1884 } 1885 1886 /* TODO: IRQ */ 1887 init_data.ctx = dc->ctx; 1888 pool->base.irqs = dal_irq_service_dcn315_create(&init_data); 1889 if (!pool->base.irqs) 1890 goto create_fail; 1891 1892 /* HUBBUB */ 1893 pool->base.hubbub = dcn31_hubbub_create(ctx); 1894 if (pool->base.hubbub == NULL) { 1895 BREAK_TO_DEBUGGER(); 1896 dm_error("DC: failed to create hubbub!\n"); 1897 goto create_fail; 1898 } 1899 1900 /* HUBPs, DPPs, OPPs and TGs */ 1901 for (i = 0; i < pool->base.pipe_count; i++) { 1902 pool->base.hubps[i] = dcn31_hubp_create(ctx, i); 1903 if (pool->base.hubps[i] == NULL) { 1904 BREAK_TO_DEBUGGER(); 1905 dm_error( 1906 "DC: failed to create hubps!\n"); 1907 goto create_fail; 1908 } 1909 1910 pool->base.dpps[i] = dcn31_dpp_create(ctx, i); 1911 if (pool->base.dpps[i] == NULL) { 1912 BREAK_TO_DEBUGGER(); 1913 dm_error( 1914 "DC: failed to create dpps!\n"); 1915 goto create_fail; 1916 } 1917 } 1918 1919 for (i = 0; i < pool->base.res_cap->num_opp; i++) { 1920 pool->base.opps[i] = dcn31_opp_create(ctx, i); 1921 if (pool->base.opps[i] == NULL) { 1922 BREAK_TO_DEBUGGER(); 1923 dm_error( 1924 "DC: failed to create output pixel processor!\n"); 1925 goto create_fail; 1926 } 1927 } 1928 1929 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { 1930 pool->base.timing_generators[i] = dcn31_timing_generator_create( 1931 ctx, i); 1932 if (pool->base.timing_generators[i] == NULL) { 1933 BREAK_TO_DEBUGGER(); 1934 dm_error("DC: failed to create tg!\n"); 1935 goto create_fail; 1936 } 1937 } 1938 pool->base.timing_generator_count = i; 1939 1940 /* PSR */ 1941 pool->base.psr = dmub_psr_create(ctx); 1942 if (pool->base.psr == NULL) { 1943 dm_error("DC: failed to create psr obj!\n"); 1944 BREAK_TO_DEBUGGER(); 1945 goto create_fail; 1946 } 1947 1948 /* ABM */ 1949 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { 1950 pool->base.multiple_abms[i] = dmub_abm_create(ctx, 1951 &abm_regs[i], 1952 &abm_shift, 1953 &abm_mask); 1954 if (pool->base.multiple_abms[i] == NULL) { 1955 dm_error("DC: failed to create abm for pipe %d!\n", i); 1956 BREAK_TO_DEBUGGER(); 1957 goto create_fail; 1958 } 1959 } 1960 1961 /* MPC and DSC */ 1962 pool->base.mpc = dcn31_mpc_create(ctx, pool->base.mpcc_count, pool->base.res_cap->num_mpc_3dlut); 1963 if (pool->base.mpc == NULL) { 1964 BREAK_TO_DEBUGGER(); 1965 dm_error("DC: failed to create mpc!\n"); 1966 goto create_fail; 1967 } 1968 1969 for (i = 0; i < pool->base.res_cap->num_dsc; i++) { 1970 pool->base.dscs[i] = dcn31_dsc_create(ctx, i); 1971 if (pool->base.dscs[i] == NULL) { 1972 BREAK_TO_DEBUGGER(); 1973 dm_error("DC: failed to create display stream compressor %d!\n", i); 1974 goto create_fail; 1975 } 1976 } 1977 1978 /* DWB and MMHUBBUB */ 1979 if (!dcn31_dwbc_create(ctx, &pool->base)) { 1980 BREAK_TO_DEBUGGER(); 1981 dm_error("DC: failed to create dwbc!\n"); 1982 goto create_fail; 1983 } 1984 1985 if (!dcn31_mmhubbub_create(ctx, &pool->base)) { 1986 BREAK_TO_DEBUGGER(); 1987 dm_error("DC: failed to create mcif_wb!\n"); 1988 goto create_fail; 1989 } 1990 1991 /* AUX and I2C */ 1992 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { 1993 pool->base.engines[i] = dcn31_aux_engine_create(ctx, i); 1994 if (pool->base.engines[i] == NULL) { 1995 BREAK_TO_DEBUGGER(); 1996 dm_error( 1997 "DC:failed to create aux engine!!\n"); 1998 goto create_fail; 1999 } 2000 pool->base.hw_i2cs[i] = dcn31_i2c_hw_create(ctx, i); 2001 if (pool->base.hw_i2cs[i] == NULL) { 2002 BREAK_TO_DEBUGGER(); 2003 dm_error( 2004 "DC:failed to create hw i2c!!\n"); 2005 goto create_fail; 2006 } 2007 pool->base.sw_i2cs[i] = NULL; 2008 } 2009 2010 /* Audio, Stream Encoders including HPO and virtual, MPC 3D LUTs */ 2011 if (!resource_construct(num_virtual_links, dc, &pool->base, 2012 (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment) ? 2013 &res_create_funcs : &res_create_maximus_funcs))) 2014 goto create_fail; 2015 2016 /* HW Sequencer and Plane caps */ 2017 dcn31_hw_sequencer_construct(dc); 2018 2019 dc->caps.max_planes = pool->base.pipe_count; 2020 2021 for (i = 0; i < dc->caps.max_planes; ++i) 2022 dc->caps.planes[i] = plane_cap; 2023 2024 dc->cap_funcs = cap_funcs; 2025 2026 dc->dcn_ip->max_num_dpp = dcn3_15_ip.max_num_dpp; 2027 2028 return true; 2029 2030 create_fail: 2031 2032 dcn315_resource_destruct(pool); 2033 2034 return false; 2035 } 2036 2037 struct resource_pool *dcn315_create_resource_pool( 2038 const struct dc_init_data *init_data, 2039 struct dc *dc) 2040 { 2041 struct dcn315_resource_pool *pool = 2042 kzalloc(sizeof(struct dcn315_resource_pool), GFP_KERNEL); 2043 2044 if (!pool) 2045 return NULL; 2046 2047 if (dcn315_resource_construct(init_data->num_virtual_links, dc, pool)) 2048 return &pool->base; 2049 2050 BREAK_TO_DEBUGGER(); 2051 kfree(pool); 2052 return NULL; 2053 } 2054