1 // SPDX-License-Identifier: MIT 2 /* 3 * Copyright 2022 Advanced Micro Devices, Inc. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 * 23 * Authors: AMD 24 * 25 */ 26 27 28 #include "dm_services.h" 29 #include "dc.h" 30 31 #include "dcn31/dcn31_init.h" 32 #include "dcn314/dcn314_init.h" 33 34 #include "resource.h" 35 #include "include/irq_service_interface.h" 36 #include "dcn314_resource.h" 37 38 #include "dcn20/dcn20_resource.h" 39 #include "dcn30/dcn30_resource.h" 40 #include "dcn31/dcn31_resource.h" 41 42 #include "dcn10/dcn10_ipp.h" 43 #include "dcn30/dcn30_hubbub.h" 44 #include "dcn31/dcn31_hubbub.h" 45 #include "dcn30/dcn30_mpc.h" 46 #include "dcn31/dcn31_hubp.h" 47 #include "irq/dcn31/irq_service_dcn31.h" 48 #include "irq/dcn314/irq_service_dcn314.h" 49 #include "dcn30/dcn30_dpp.h" 50 #include "dcn314/dcn314_optc.h" 51 #include "dcn20/dcn20_hwseq.h" 52 #include "dcn30/dcn30_hwseq.h" 53 #include "dce110/dce110_hw_sequencer.h" 54 #include "dcn30/dcn30_opp.h" 55 #include "dcn20/dcn20_dsc.h" 56 #include "dcn30/dcn30_vpg.h" 57 #include "dcn30/dcn30_afmt.h" 58 #include "dcn31/dcn31_dio_link_encoder.h" 59 #include "dcn314/dcn314_dio_stream_encoder.h" 60 #include "dcn31/dcn31_hpo_dp_stream_encoder.h" 61 #include "dcn31/dcn31_hpo_dp_link_encoder.h" 62 #include "dcn31/dcn31_apg.h" 63 #include "dcn31/dcn31_vpg.h" 64 #include "dcn31/dcn31_afmt.h" 65 #include "dce/dce_clock_source.h" 66 #include "dce/dce_audio.h" 67 #include "dce/dce_hwseq.h" 68 #include "clk_mgr.h" 69 #include "virtual/virtual_stream_encoder.h" 70 #include "dce110/dce110_resource.h" 71 #include "dml/display_mode_vba.h" 72 #include "dml/dcn31/dcn31_fpu.h" 73 #include "dml/dcn314/dcn314_fpu.h" 74 #include "dcn314/dcn314_dccg.h" 75 #include "dcn10/dcn10_resource.h" 76 #include "dcn31/dcn31_panel_cntl.h" 77 #include "dcn314/dcn314_hwseq.h" 78 79 #include "dcn30/dcn30_dwb.h" 80 #include "dcn30/dcn30_mmhubbub.h" 81 82 #include "dcn/dcn_3_1_4_offset.h" 83 #include "dcn/dcn_3_1_4_sh_mask.h" 84 #include "dpcs/dpcs_3_1_4_offset.h" 85 #include "dpcs/dpcs_3_1_4_sh_mask.h" 86 87 #define DCHUBBUB_DEBUG_CTRL_0__DET_DEPTH__SHIFT 0x10 88 #define DCHUBBUB_DEBUG_CTRL_0__DET_DEPTH_MASK 0x01FF0000L 89 90 #define DSCC0_DSCC_CONFIG0__ICH_RESET_AT_END_OF_LINE__SHIFT 0x0 91 #define DSCC0_DSCC_CONFIG0__ICH_RESET_AT_END_OF_LINE_MASK 0x0000000FL 92 93 #include "reg_helper.h" 94 #include "dce/dmub_abm.h" 95 #include "dce/dmub_psr.h" 96 #include "dce/dce_aux.h" 97 #include "dce/dce_i2c.h" 98 #include "dml/dcn314/display_mode_vba_314.h" 99 #include "vm_helper.h" 100 #include "dcn20/dcn20_vmid.h" 101 102 #include "link_enc_cfg.h" 103 104 #define DCN_BASE__INST0_SEG1 0x000000C0 105 #define DCN_BASE__INST0_SEG2 0x000034C0 106 #define DCN_BASE__INST0_SEG3 0x00009000 107 108 #define NBIO_BASE__INST0_SEG1 0x00000014 109 110 #define MAX_INSTANCE 7 111 #define MAX_SEGMENT 8 112 113 #define regBIF_BX2_BIOS_SCRATCH_2 0x003a 114 #define regBIF_BX2_BIOS_SCRATCH_2_BASE_IDX 1 115 #define regBIF_BX2_BIOS_SCRATCH_3 0x003b 116 #define regBIF_BX2_BIOS_SCRATCH_3_BASE_IDX 1 117 #define regBIF_BX2_BIOS_SCRATCH_6 0x003e 118 #define regBIF_BX2_BIOS_SCRATCH_6_BASE_IDX 1 119 120 struct IP_BASE_INSTANCE { 121 unsigned int segment[MAX_SEGMENT]; 122 }; 123 124 struct IP_BASE { 125 struct IP_BASE_INSTANCE instance[MAX_INSTANCE]; 126 }; 127 128 static const struct IP_BASE DCN_BASE = { { { { 0x00000012, 0x000000C0, 0x000034C0, 0x00009000, 0x02403C00, 0, 0, 0 } }, 129 { { 0, 0, 0, 0, 0, 0, 0, 0 } }, 130 { { 0, 0, 0, 0, 0, 0, 0, 0 } }, 131 { { 0, 0, 0, 0, 0, 0, 0, 0 } }, 132 { { 0, 0, 0, 0, 0, 0, 0, 0 } }, 133 { { 0, 0, 0, 0, 0, 0, 0, 0 } }, 134 { { 0, 0, 0, 0, 0, 0, 0, 0 } } } }; 135 136 137 #define DC_LOGGER_INIT(logger) 138 139 enum dcn31_clk_src_array_id { 140 DCN31_CLK_SRC_PLL0, 141 DCN31_CLK_SRC_PLL1, 142 DCN31_CLK_SRC_PLL2, 143 DCN31_CLK_SRC_PLL3, 144 DCN31_CLK_SRC_PLL4, 145 DCN30_CLK_SRC_TOTAL 146 }; 147 148 /* begin ********************* 149 * macros to expend register list macro defined in HW object header file 150 */ 151 152 /* DCN */ 153 /* TODO awful hack. fixup dcn20_dwb.h */ 154 #undef BASE_INNER 155 #define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg 156 157 #define BASE(seg) BASE_INNER(seg) 158 159 #define SR(reg_name)\ 160 .reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \ 161 reg ## reg_name 162 163 #define SRI(reg_name, block, id)\ 164 .reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 165 reg ## block ## id ## _ ## reg_name 166 167 #define SRI2(reg_name, block, id)\ 168 .reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \ 169 reg ## reg_name 170 171 #define SRIR(var_name, reg_name, block, id)\ 172 .var_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 173 reg ## block ## id ## _ ## reg_name 174 175 #define SRII(reg_name, block, id)\ 176 .reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 177 reg ## block ## id ## _ ## reg_name 178 179 #define SRII_MPC_RMU(reg_name, block, id)\ 180 .RMU##_##reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 181 reg ## block ## id ## _ ## reg_name 182 183 #define SRII_DWB(reg_name, temp_name, block, id)\ 184 .reg_name[id] = BASE(reg ## block ## id ## _ ## temp_name ## _BASE_IDX) + \ 185 reg ## block ## id ## _ ## temp_name 186 187 #define SF_DWB2(reg_name, block, id, field_name, post_fix) \ 188 .field_name = reg_name ## __ ## field_name ## post_fix 189 190 #define DCCG_SRII(reg_name, block, id)\ 191 .block ## _ ## reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 192 reg ## block ## id ## _ ## reg_name 193 194 #define VUPDATE_SRII(reg_name, block, id)\ 195 .reg_name[id] = BASE(reg ## reg_name ## _ ## block ## id ## _BASE_IDX) + \ 196 reg ## reg_name ## _ ## block ## id 197 198 /* NBIO */ 199 #define NBIO_BASE_INNER(seg) \ 200 NBIO_BASE__INST0_SEG ## seg 201 202 #define NBIO_BASE(seg) \ 203 NBIO_BASE_INNER(seg) 204 205 #define NBIO_SR(reg_name)\ 206 .reg_name = NBIO_BASE(regBIF_BX2_ ## reg_name ## _BASE_IDX) + \ 207 regBIF_BX2_ ## reg_name 208 209 /* MMHUB */ 210 #define MMHUB_BASE_INNER(seg) \ 211 MMHUB_BASE__INST0_SEG ## seg 212 213 #define MMHUB_BASE(seg) \ 214 MMHUB_BASE_INNER(seg) 215 216 #define MMHUB_SR(reg_name)\ 217 .reg_name = MMHUB_BASE(reg ## reg_name ## _BASE_IDX) + \ 218 reg ## reg_name 219 220 /* CLOCK */ 221 #define CLK_BASE_INNER(seg) \ 222 CLK_BASE__INST0_SEG ## seg 223 224 #define CLK_BASE(seg) \ 225 CLK_BASE_INNER(seg) 226 227 #define CLK_SRI(reg_name, block, inst)\ 228 .reg_name = CLK_BASE(reg ## block ## _ ## inst ## _ ## reg_name ## _BASE_IDX) + \ 229 reg ## block ## _ ## inst ## _ ## reg_name 230 231 232 static const struct bios_registers bios_regs = { 233 NBIO_SR(BIOS_SCRATCH_3), 234 NBIO_SR(BIOS_SCRATCH_6) 235 }; 236 237 #define clk_src_regs(index, pllid)\ 238 [index] = {\ 239 CS_COMMON_REG_LIST_DCN3_0(index, pllid),\ 240 } 241 242 static const struct dce110_clk_src_regs clk_src_regs[] = { 243 clk_src_regs(0, A), 244 clk_src_regs(1, B), 245 clk_src_regs(2, C), 246 clk_src_regs(3, D), 247 clk_src_regs(4, E) 248 }; 249 250 static const struct dce110_clk_src_shift cs_shift = { 251 CS_COMMON_MASK_SH_LIST_DCN3_1_4(__SHIFT) 252 }; 253 254 static const struct dce110_clk_src_mask cs_mask = { 255 CS_COMMON_MASK_SH_LIST_DCN3_1_4(_MASK) 256 }; 257 258 #define abm_regs(id)\ 259 [id] = {\ 260 ABM_DCN302_REG_LIST(id)\ 261 } 262 263 static const struct dce_abm_registers abm_regs[] = { 264 abm_regs(0), 265 abm_regs(1), 266 abm_regs(2), 267 abm_regs(3), 268 }; 269 270 static const struct dce_abm_shift abm_shift = { 271 ABM_MASK_SH_LIST_DCN30(__SHIFT) 272 }; 273 274 static const struct dce_abm_mask abm_mask = { 275 ABM_MASK_SH_LIST_DCN30(_MASK) 276 }; 277 278 #define audio_regs(id)\ 279 [id] = {\ 280 AUD_COMMON_REG_LIST(id)\ 281 } 282 283 static const struct dce_audio_registers audio_regs[] = { 284 audio_regs(0), 285 audio_regs(1), 286 audio_regs(2), 287 audio_regs(3), 288 audio_regs(4), 289 audio_regs(5), 290 audio_regs(6) 291 }; 292 293 #define DCE120_AUD_COMMON_MASK_SH_LIST(mask_sh)\ 294 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX, AZALIA_ENDPOINT_REG_INDEX, mask_sh),\ 295 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA, AZALIA_ENDPOINT_REG_DATA, mask_sh),\ 296 AUD_COMMON_MASK_SH_LIST_BASE(mask_sh) 297 298 static const struct dce_audio_shift audio_shift = { 299 DCE120_AUD_COMMON_MASK_SH_LIST(__SHIFT) 300 }; 301 302 static const struct dce_audio_mask audio_mask = { 303 DCE120_AUD_COMMON_MASK_SH_LIST(_MASK) 304 }; 305 306 #define vpg_regs(id)\ 307 [id] = {\ 308 VPG_DCN31_REG_LIST(id)\ 309 } 310 311 static const struct dcn31_vpg_registers vpg_regs[] = { 312 vpg_regs(0), 313 vpg_regs(1), 314 vpg_regs(2), 315 vpg_regs(3), 316 vpg_regs(4), 317 vpg_regs(5), 318 vpg_regs(6), 319 vpg_regs(7), 320 vpg_regs(8), 321 vpg_regs(9), 322 }; 323 324 static const struct dcn31_vpg_shift vpg_shift = { 325 DCN31_VPG_MASK_SH_LIST(__SHIFT) 326 }; 327 328 static const struct dcn31_vpg_mask vpg_mask = { 329 DCN31_VPG_MASK_SH_LIST(_MASK) 330 }; 331 332 #define afmt_regs(id)\ 333 [id] = {\ 334 AFMT_DCN31_REG_LIST(id)\ 335 } 336 337 static const struct dcn31_afmt_registers afmt_regs[] = { 338 afmt_regs(0), 339 afmt_regs(1), 340 afmt_regs(2), 341 afmt_regs(3), 342 afmt_regs(4), 343 afmt_regs(5) 344 }; 345 346 static const struct dcn31_afmt_shift afmt_shift = { 347 DCN31_AFMT_MASK_SH_LIST(__SHIFT) 348 }; 349 350 static const struct dcn31_afmt_mask afmt_mask = { 351 DCN31_AFMT_MASK_SH_LIST(_MASK) 352 }; 353 354 #define apg_regs(id)\ 355 [id] = {\ 356 APG_DCN31_REG_LIST(id)\ 357 } 358 359 static const struct dcn31_apg_registers apg_regs[] = { 360 apg_regs(0), 361 apg_regs(1), 362 apg_regs(2), 363 apg_regs(3) 364 }; 365 366 static const struct dcn31_apg_shift apg_shift = { 367 DCN31_APG_MASK_SH_LIST(__SHIFT) 368 }; 369 370 static const struct dcn31_apg_mask apg_mask = { 371 DCN31_APG_MASK_SH_LIST(_MASK) 372 }; 373 374 #define stream_enc_regs(id)\ 375 [id] = {\ 376 SE_DCN314_REG_LIST(id)\ 377 } 378 379 static const struct dcn10_stream_enc_registers stream_enc_regs[] = { 380 stream_enc_regs(0), 381 stream_enc_regs(1), 382 stream_enc_regs(2), 383 stream_enc_regs(3), 384 stream_enc_regs(4) 385 }; 386 387 static const struct dcn10_stream_encoder_shift se_shift = { 388 SE_COMMON_MASK_SH_LIST_DCN314(__SHIFT) 389 }; 390 391 static const struct dcn10_stream_encoder_mask se_mask = { 392 SE_COMMON_MASK_SH_LIST_DCN314(_MASK) 393 }; 394 395 396 #define aux_regs(id)\ 397 [id] = {\ 398 DCN2_AUX_REG_LIST(id)\ 399 } 400 401 static const struct dcn10_link_enc_aux_registers link_enc_aux_regs[] = { 402 aux_regs(0), 403 aux_regs(1), 404 aux_regs(2), 405 aux_regs(3), 406 aux_regs(4) 407 }; 408 409 #define hpd_regs(id)\ 410 [id] = {\ 411 HPD_REG_LIST(id)\ 412 } 413 414 static const struct dcn10_link_enc_hpd_registers link_enc_hpd_regs[] = { 415 hpd_regs(0), 416 hpd_regs(1), 417 hpd_regs(2), 418 hpd_regs(3), 419 hpd_regs(4) 420 }; 421 422 #define link_regs(id, phyid)\ 423 [id] = {\ 424 LE_DCN31_REG_LIST(id), \ 425 UNIPHY_DCN2_REG_LIST(phyid), \ 426 } 427 428 static const struct dce110_aux_registers_shift aux_shift = { 429 DCN_AUX_MASK_SH_LIST(__SHIFT) 430 }; 431 432 static const struct dce110_aux_registers_mask aux_mask = { 433 DCN_AUX_MASK_SH_LIST(_MASK) 434 }; 435 436 static const struct dcn10_link_enc_registers link_enc_regs[] = { 437 link_regs(0, A), 438 link_regs(1, B), 439 link_regs(2, C), 440 link_regs(3, D), 441 link_regs(4, E) 442 }; 443 444 static const struct dcn10_link_enc_shift le_shift = { 445 LINK_ENCODER_MASK_SH_LIST_DCN31(__SHIFT), 446 DPCS_DCN31_MASK_SH_LIST(__SHIFT) 447 }; 448 449 static const struct dcn10_link_enc_mask le_mask = { 450 LINK_ENCODER_MASK_SH_LIST_DCN31(_MASK), 451 DPCS_DCN31_MASK_SH_LIST(_MASK) 452 }; 453 454 #define hpo_dp_stream_encoder_reg_list(id)\ 455 [id] = {\ 456 DCN3_1_HPO_DP_STREAM_ENC_REG_LIST(id)\ 457 } 458 459 static const struct dcn31_hpo_dp_stream_encoder_registers hpo_dp_stream_enc_regs[] = { 460 hpo_dp_stream_encoder_reg_list(0), 461 hpo_dp_stream_encoder_reg_list(1), 462 hpo_dp_stream_encoder_reg_list(2), 463 hpo_dp_stream_encoder_reg_list(3) 464 }; 465 466 static const struct dcn31_hpo_dp_stream_encoder_shift hpo_dp_se_shift = { 467 DCN3_1_HPO_DP_STREAM_ENC_MASK_SH_LIST(__SHIFT) 468 }; 469 470 static const struct dcn31_hpo_dp_stream_encoder_mask hpo_dp_se_mask = { 471 DCN3_1_HPO_DP_STREAM_ENC_MASK_SH_LIST(_MASK) 472 }; 473 474 475 #define hpo_dp_link_encoder_reg_list(id)\ 476 [id] = {\ 477 DCN3_1_HPO_DP_LINK_ENC_REG_LIST(id),\ 478 DCN3_1_RDPCSTX_REG_LIST(0),\ 479 DCN3_1_RDPCSTX_REG_LIST(1),\ 480 DCN3_1_RDPCSTX_REG_LIST(2),\ 481 } 482 483 static const struct dcn31_hpo_dp_link_encoder_registers hpo_dp_link_enc_regs[] = { 484 hpo_dp_link_encoder_reg_list(0), 485 hpo_dp_link_encoder_reg_list(1), 486 }; 487 488 static const struct dcn31_hpo_dp_link_encoder_shift hpo_dp_le_shift = { 489 DCN3_1_HPO_DP_LINK_ENC_MASK_SH_LIST(__SHIFT) 490 }; 491 492 static const struct dcn31_hpo_dp_link_encoder_mask hpo_dp_le_mask = { 493 DCN3_1_HPO_DP_LINK_ENC_MASK_SH_LIST(_MASK) 494 }; 495 496 #define dpp_regs(id)\ 497 [id] = {\ 498 DPP_REG_LIST_DCN30(id),\ 499 } 500 501 static const struct dcn3_dpp_registers dpp_regs[] = { 502 dpp_regs(0), 503 dpp_regs(1), 504 dpp_regs(2), 505 dpp_regs(3) 506 }; 507 508 static const struct dcn3_dpp_shift tf_shift = { 509 DPP_REG_LIST_SH_MASK_DCN30(__SHIFT) 510 }; 511 512 static const struct dcn3_dpp_mask tf_mask = { 513 DPP_REG_LIST_SH_MASK_DCN30(_MASK) 514 }; 515 516 #define opp_regs(id)\ 517 [id] = {\ 518 OPP_REG_LIST_DCN30(id),\ 519 } 520 521 static const struct dcn20_opp_registers opp_regs[] = { 522 opp_regs(0), 523 opp_regs(1), 524 opp_regs(2), 525 opp_regs(3) 526 }; 527 528 static const struct dcn20_opp_shift opp_shift = { 529 OPP_MASK_SH_LIST_DCN20(__SHIFT) 530 }; 531 532 static const struct dcn20_opp_mask opp_mask = { 533 OPP_MASK_SH_LIST_DCN20(_MASK) 534 }; 535 536 #define aux_engine_regs(id)\ 537 [id] = {\ 538 AUX_COMMON_REG_LIST0(id), \ 539 .AUXN_IMPCAL = 0, \ 540 .AUXP_IMPCAL = 0, \ 541 .AUX_RESET_MASK = DP_AUX0_AUX_CONTROL__AUX_RESET_MASK, \ 542 } 543 544 static const struct dce110_aux_registers aux_engine_regs[] = { 545 aux_engine_regs(0), 546 aux_engine_regs(1), 547 aux_engine_regs(2), 548 aux_engine_regs(3), 549 aux_engine_regs(4) 550 }; 551 552 #define dwbc_regs_dcn3(id)\ 553 [id] = {\ 554 DWBC_COMMON_REG_LIST_DCN30(id),\ 555 } 556 557 static const struct dcn30_dwbc_registers dwbc30_regs[] = { 558 dwbc_regs_dcn3(0), 559 }; 560 561 static const struct dcn30_dwbc_shift dwbc30_shift = { 562 DWBC_COMMON_MASK_SH_LIST_DCN30(__SHIFT) 563 }; 564 565 static const struct dcn30_dwbc_mask dwbc30_mask = { 566 DWBC_COMMON_MASK_SH_LIST_DCN30(_MASK) 567 }; 568 569 #define mcif_wb_regs_dcn3(id)\ 570 [id] = {\ 571 MCIF_WB_COMMON_REG_LIST_DCN30(id),\ 572 } 573 574 static const struct dcn30_mmhubbub_registers mcif_wb30_regs[] = { 575 mcif_wb_regs_dcn3(0) 576 }; 577 578 static const struct dcn30_mmhubbub_shift mcif_wb30_shift = { 579 MCIF_WB_COMMON_MASK_SH_LIST_DCN30(__SHIFT) 580 }; 581 582 static const struct dcn30_mmhubbub_mask mcif_wb30_mask = { 583 MCIF_WB_COMMON_MASK_SH_LIST_DCN30(_MASK) 584 }; 585 586 #define dsc_regsDCN314(id)\ 587 [id] = {\ 588 DSC_REG_LIST_DCN20(id)\ 589 } 590 591 static const struct dcn20_dsc_registers dsc_regs[] = { 592 dsc_regsDCN314(0), 593 dsc_regsDCN314(1), 594 dsc_regsDCN314(2), 595 dsc_regsDCN314(3) 596 }; 597 598 static const struct dcn20_dsc_shift dsc_shift = { 599 DSC_REG_LIST_SH_MASK_DCN20(__SHIFT) 600 }; 601 602 static const struct dcn20_dsc_mask dsc_mask = { 603 DSC_REG_LIST_SH_MASK_DCN20(_MASK) 604 }; 605 606 static const struct dcn30_mpc_registers mpc_regs = { 607 MPC_REG_LIST_DCN3_0(0), 608 MPC_REG_LIST_DCN3_0(1), 609 MPC_REG_LIST_DCN3_0(2), 610 MPC_REG_LIST_DCN3_0(3), 611 MPC_OUT_MUX_REG_LIST_DCN3_0(0), 612 MPC_OUT_MUX_REG_LIST_DCN3_0(1), 613 MPC_OUT_MUX_REG_LIST_DCN3_0(2), 614 MPC_OUT_MUX_REG_LIST_DCN3_0(3), 615 MPC_RMU_GLOBAL_REG_LIST_DCN3AG, 616 MPC_RMU_REG_LIST_DCN3AG(0), 617 MPC_RMU_REG_LIST_DCN3AG(1), 618 //MPC_RMU_REG_LIST_DCN3AG(2), 619 MPC_DWB_MUX_REG_LIST_DCN3_0(0), 620 }; 621 622 static const struct dcn30_mpc_shift mpc_shift = { 623 MPC_COMMON_MASK_SH_LIST_DCN30(__SHIFT) 624 }; 625 626 static const struct dcn30_mpc_mask mpc_mask = { 627 MPC_COMMON_MASK_SH_LIST_DCN30(_MASK) 628 }; 629 630 #define optc_regs(id)\ 631 [id] = {OPTC_COMMON_REG_LIST_DCN3_14(id)} 632 633 static const struct dcn_optc_registers optc_regs[] = { 634 optc_regs(0), 635 optc_regs(1), 636 optc_regs(2), 637 optc_regs(3) 638 }; 639 640 static const struct dcn_optc_shift optc_shift = { 641 OPTC_COMMON_MASK_SH_LIST_DCN3_14(__SHIFT) 642 }; 643 644 static const struct dcn_optc_mask optc_mask = { 645 OPTC_COMMON_MASK_SH_LIST_DCN3_14(_MASK) 646 }; 647 648 #define hubp_regs(id)\ 649 [id] = {\ 650 HUBP_REG_LIST_DCN30(id)\ 651 } 652 653 static const struct dcn_hubp2_registers hubp_regs[] = { 654 hubp_regs(0), 655 hubp_regs(1), 656 hubp_regs(2), 657 hubp_regs(3) 658 }; 659 660 661 static const struct dcn_hubp2_shift hubp_shift = { 662 HUBP_MASK_SH_LIST_DCN31(__SHIFT) 663 }; 664 665 static const struct dcn_hubp2_mask hubp_mask = { 666 HUBP_MASK_SH_LIST_DCN31(_MASK) 667 }; 668 static const struct dcn_hubbub_registers hubbub_reg = { 669 HUBBUB_REG_LIST_DCN31(0) 670 }; 671 672 static const struct dcn_hubbub_shift hubbub_shift = { 673 HUBBUB_MASK_SH_LIST_DCN31(__SHIFT) 674 }; 675 676 static const struct dcn_hubbub_mask hubbub_mask = { 677 HUBBUB_MASK_SH_LIST_DCN31(_MASK) 678 }; 679 680 static const struct dccg_registers dccg_regs = { 681 DCCG_REG_LIST_DCN314() 682 }; 683 684 static const struct dccg_shift dccg_shift = { 685 DCCG_MASK_SH_LIST_DCN314(__SHIFT) 686 }; 687 688 static const struct dccg_mask dccg_mask = { 689 DCCG_MASK_SH_LIST_DCN314(_MASK) 690 }; 691 692 693 #define SRII2(reg_name_pre, reg_name_post, id)\ 694 .reg_name_pre ## _ ## reg_name_post[id] = BASE(reg ## reg_name_pre \ 695 ## id ## _ ## reg_name_post ## _BASE_IDX) + \ 696 reg ## reg_name_pre ## id ## _ ## reg_name_post 697 698 699 #define HWSEQ_DCN31_REG_LIST()\ 700 SR(DCHUBBUB_GLOBAL_TIMER_CNTL), \ 701 SR(DCHUBBUB_ARB_HOSTVM_CNTL), \ 702 SR(DIO_MEM_PWR_CTRL), \ 703 SR(ODM_MEM_PWR_CTRL3), \ 704 SR(DMU_MEM_PWR_CNTL), \ 705 SR(MMHUBBUB_MEM_PWR_CNTL), \ 706 SR(DCCG_GATE_DISABLE_CNTL), \ 707 SR(DCCG_GATE_DISABLE_CNTL2), \ 708 SR(DCFCLK_CNTL),\ 709 SR(DC_MEM_GLOBAL_PWR_REQ_CNTL), \ 710 SRII(PIXEL_RATE_CNTL, OTG, 0), \ 711 SRII(PIXEL_RATE_CNTL, OTG, 1),\ 712 SRII(PIXEL_RATE_CNTL, OTG, 2),\ 713 SRII(PIXEL_RATE_CNTL, OTG, 3),\ 714 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 0),\ 715 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 1),\ 716 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 2),\ 717 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 3),\ 718 SR(MICROSECOND_TIME_BASE_DIV), \ 719 SR(MILLISECOND_TIME_BASE_DIV), \ 720 SR(DISPCLK_FREQ_CHANGE_CNTL), \ 721 SR(RBBMIF_TIMEOUT_DIS), \ 722 SR(RBBMIF_TIMEOUT_DIS_2), \ 723 SR(DCHUBBUB_CRC_CTRL), \ 724 SR(DPP_TOP0_DPP_CRC_CTRL), \ 725 SR(DPP_TOP0_DPP_CRC_VAL_B_A), \ 726 SR(DPP_TOP0_DPP_CRC_VAL_R_G), \ 727 SR(MPC_CRC_CTRL), \ 728 SR(MPC_CRC_RESULT_GB), \ 729 SR(MPC_CRC_RESULT_C), \ 730 SR(MPC_CRC_RESULT_AR), \ 731 SR(DOMAIN0_PG_CONFIG), \ 732 SR(DOMAIN1_PG_CONFIG), \ 733 SR(DOMAIN2_PG_CONFIG), \ 734 SR(DOMAIN3_PG_CONFIG), \ 735 SR(DOMAIN16_PG_CONFIG), \ 736 SR(DOMAIN17_PG_CONFIG), \ 737 SR(DOMAIN18_PG_CONFIG), \ 738 SR(DOMAIN19_PG_CONFIG), \ 739 SR(DOMAIN0_PG_STATUS), \ 740 SR(DOMAIN1_PG_STATUS), \ 741 SR(DOMAIN2_PG_STATUS), \ 742 SR(DOMAIN3_PG_STATUS), \ 743 SR(DOMAIN16_PG_STATUS), \ 744 SR(DOMAIN17_PG_STATUS), \ 745 SR(DOMAIN18_PG_STATUS), \ 746 SR(DOMAIN19_PG_STATUS), \ 747 SR(D1VGA_CONTROL), \ 748 SR(D2VGA_CONTROL), \ 749 SR(D3VGA_CONTROL), \ 750 SR(D4VGA_CONTROL), \ 751 SR(D5VGA_CONTROL), \ 752 SR(D6VGA_CONTROL), \ 753 SR(DC_IP_REQUEST_CNTL), \ 754 SR(AZALIA_AUDIO_DTO), \ 755 SR(AZALIA_CONTROLLER_CLOCK_GATING), \ 756 SR(HPO_TOP_HW_CONTROL) 757 758 static const struct dce_hwseq_registers hwseq_reg = { 759 HWSEQ_DCN31_REG_LIST() 760 }; 761 762 #define HWSEQ_DCN31_MASK_SH_LIST(mask_sh)\ 763 HWSEQ_DCN_MASK_SH_LIST(mask_sh), \ 764 HWS_SF(, DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_REFDIV, mask_sh), \ 765 HWS_SF(, DCHUBBUB_ARB_HOSTVM_CNTL, DISABLE_HOSTVM_FORCE_ALLOW_PSTATE, mask_sh), \ 766 HWS_SF(, DOMAIN0_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ 767 HWS_SF(, DOMAIN0_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ 768 HWS_SF(, DOMAIN1_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ 769 HWS_SF(, DOMAIN1_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ 770 HWS_SF(, DOMAIN2_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ 771 HWS_SF(, DOMAIN2_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ 772 HWS_SF(, DOMAIN3_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ 773 HWS_SF(, DOMAIN3_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ 774 HWS_SF(, DOMAIN16_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ 775 HWS_SF(, DOMAIN16_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ 776 HWS_SF(, DOMAIN17_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ 777 HWS_SF(, DOMAIN17_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ 778 HWS_SF(, DOMAIN18_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ 779 HWS_SF(, DOMAIN18_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ 780 HWS_SF(, DOMAIN19_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ 781 HWS_SF(, DOMAIN19_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ 782 HWS_SF(, DOMAIN0_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ 783 HWS_SF(, DOMAIN1_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ 784 HWS_SF(, DOMAIN2_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ 785 HWS_SF(, DOMAIN3_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ 786 HWS_SF(, DOMAIN16_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ 787 HWS_SF(, DOMAIN17_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ 788 HWS_SF(, DOMAIN18_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ 789 HWS_SF(, DOMAIN19_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ 790 HWS_SF(, DC_IP_REQUEST_CNTL, IP_REQUEST_EN, mask_sh), \ 791 HWS_SF(, AZALIA_AUDIO_DTO, AZALIA_AUDIO_DTO_MODULE, mask_sh), \ 792 HWS_SF(, HPO_TOP_CLOCK_CONTROL, HPO_HDMISTREAMCLK_G_GATE_DIS, mask_sh), \ 793 HWS_SF(, DMU_MEM_PWR_CNTL, DMCU_ERAM_MEM_PWR_FORCE, mask_sh), \ 794 HWS_SF(, ODM_MEM_PWR_CTRL3, ODM_MEM_UNASSIGNED_PWR_MODE, mask_sh), \ 795 HWS_SF(, ODM_MEM_PWR_CTRL3, ODM_MEM_VBLANK_PWR_MODE, mask_sh), \ 796 HWS_SF(, MMHUBBUB_MEM_PWR_CNTL, VGA_MEM_PWR_FORCE, mask_sh), \ 797 HWS_SF(, DIO_MEM_PWR_CTRL, I2C_LIGHT_SLEEP_FORCE, mask_sh), \ 798 HWS_SF(, HPO_TOP_HW_CONTROL, HPO_IO_EN, mask_sh) 799 800 static const struct dce_hwseq_shift hwseq_shift = { 801 HWSEQ_DCN31_MASK_SH_LIST(__SHIFT) 802 }; 803 804 static const struct dce_hwseq_mask hwseq_mask = { 805 HWSEQ_DCN31_MASK_SH_LIST(_MASK) 806 }; 807 #define vmid_regs(id)\ 808 [id] = {\ 809 DCN20_VMID_REG_LIST(id)\ 810 } 811 812 static const struct dcn_vmid_registers vmid_regs[] = { 813 vmid_regs(0), 814 vmid_regs(1), 815 vmid_regs(2), 816 vmid_regs(3), 817 vmid_regs(4), 818 vmid_regs(5), 819 vmid_regs(6), 820 vmid_regs(7), 821 vmid_regs(8), 822 vmid_regs(9), 823 vmid_regs(10), 824 vmid_regs(11), 825 vmid_regs(12), 826 vmid_regs(13), 827 vmid_regs(14), 828 vmid_regs(15) 829 }; 830 831 static const struct dcn20_vmid_shift vmid_shifts = { 832 DCN20_VMID_MASK_SH_LIST(__SHIFT) 833 }; 834 835 static const struct dcn20_vmid_mask vmid_masks = { 836 DCN20_VMID_MASK_SH_LIST(_MASK) 837 }; 838 839 static const struct resource_caps res_cap_dcn314 = { 840 .num_timing_generator = 4, 841 .num_opp = 4, 842 .num_video_plane = 4, 843 .num_audio = 5, 844 .num_stream_encoder = 5, 845 .num_dig_link_enc = 5, 846 .num_hpo_dp_stream_encoder = 4, 847 .num_hpo_dp_link_encoder = 2, 848 .num_pll = 5, 849 .num_dwb = 1, 850 .num_ddc = 5, 851 .num_vmid = 16, 852 .num_mpc_3dlut = 2, 853 .num_dsc = 4, 854 }; 855 856 static const struct dc_plane_cap plane_cap = { 857 .type = DC_PLANE_TYPE_DCN_UNIVERSAL, 858 .blends_with_above = true, 859 .blends_with_below = true, 860 .per_pixel_alpha = true, 861 862 .pixel_format_support = { 863 .argb8888 = true, 864 .nv12 = true, 865 .fp16 = true, 866 .p010 = true, 867 .ayuv = false, 868 }, 869 870 .max_upscale_factor = { 871 .argb8888 = 16000, 872 .nv12 = 16000, 873 .fp16 = 16000 874 }, 875 876 // 6:1 downscaling ratio: 1000/6 = 166.666 877 .max_downscale_factor = { 878 .argb8888 = 167, 879 .nv12 = 167, 880 .fp16 = 167 881 }, 882 64, 883 64 884 }; 885 886 static const struct dc_debug_options debug_defaults_drv = { 887 .disable_z10 = false, 888 .enable_z9_disable_interface = true, 889 .disable_dmcu = true, 890 .force_abm_enable = false, 891 .timing_trace = false, 892 .clock_trace = true, 893 .disable_pplib_clock_request = false, 894 .pipe_split_policy = MPC_SPLIT_DYNAMIC, 895 .force_single_disp_pipe_split = false, 896 .disable_dcc = DCC_ENABLE, 897 .vsr_support = true, 898 .performance_trace = false, 899 .max_downscale_src_width = 4096,/*upto true 4k*/ 900 .disable_pplib_wm_range = false, 901 .scl_reset_length10 = true, 902 .sanity_checks = false, 903 .underflow_assert_delay_us = 0xFFFFFFFF, 904 .dwb_fi_phase = -1, // -1 = disable, 905 .dmub_command_table = true, 906 .pstate_enabled = true, 907 .use_max_lb = true, 908 .enable_mem_low_power = { 909 .bits = { 910 .vga = true, 911 .i2c = true, 912 .dmcu = false, // This is previously known to cause hang on S3 cycles if enabled 913 .dscl = true, 914 .cm = true, 915 .mpc = true, 916 .optc = true, 917 .vpg = true, 918 .afmt = true, 919 } 920 }, 921 .seamless_boot_odm_combine = true 922 }; 923 924 static const struct dc_debug_options debug_defaults_diags = { 925 .disable_dmcu = true, 926 .force_abm_enable = false, 927 .timing_trace = true, 928 .clock_trace = true, 929 .disable_dpp_power_gate = true, 930 .disable_hubp_power_gate = true, 931 .disable_clock_gate = true, 932 .disable_pplib_clock_request = true, 933 .disable_pplib_wm_range = true, 934 .disable_stutter = false, 935 .scl_reset_length10 = true, 936 .dwb_fi_phase = -1, // -1 = disable 937 .dmub_command_table = true, 938 .enable_tri_buf = true, 939 .use_max_lb = true 940 }; 941 942 static const struct dc_panel_config panel_config_defaults = { 943 .psr = { 944 .disable_psr = false, 945 .disallow_psrsu = false, 946 }, 947 .ilr = { 948 .optimize_edp_link_rate = true, 949 }, 950 }; 951 952 static void dcn31_dpp_destroy(struct dpp **dpp) 953 { 954 kfree(TO_DCN20_DPP(*dpp)); 955 *dpp = NULL; 956 } 957 958 static struct dpp *dcn31_dpp_create( 959 struct dc_context *ctx, 960 uint32_t inst) 961 { 962 struct dcn3_dpp *dpp = 963 kzalloc(sizeof(struct dcn3_dpp), GFP_KERNEL); 964 965 if (!dpp) 966 return NULL; 967 968 if (dpp3_construct(dpp, ctx, inst, 969 &dpp_regs[inst], &tf_shift, &tf_mask)) 970 return &dpp->base; 971 972 BREAK_TO_DEBUGGER(); 973 kfree(dpp); 974 return NULL; 975 } 976 977 static struct output_pixel_processor *dcn31_opp_create( 978 struct dc_context *ctx, uint32_t inst) 979 { 980 struct dcn20_opp *opp = 981 kzalloc(sizeof(struct dcn20_opp), GFP_KERNEL); 982 983 if (!opp) { 984 BREAK_TO_DEBUGGER(); 985 return NULL; 986 } 987 988 dcn20_opp_construct(opp, ctx, inst, 989 &opp_regs[inst], &opp_shift, &opp_mask); 990 return &opp->base; 991 } 992 993 static struct dce_aux *dcn31_aux_engine_create( 994 struct dc_context *ctx, 995 uint32_t inst) 996 { 997 struct aux_engine_dce110 *aux_engine = 998 kzalloc(sizeof(struct aux_engine_dce110), GFP_KERNEL); 999 1000 if (!aux_engine) 1001 return NULL; 1002 1003 dce110_aux_engine_construct(aux_engine, ctx, inst, 1004 SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD, 1005 &aux_engine_regs[inst], 1006 &aux_mask, 1007 &aux_shift, 1008 ctx->dc->caps.extended_aux_timeout_support); 1009 1010 return &aux_engine->base; 1011 } 1012 #define i2c_inst_regs(id) { I2C_HW_ENGINE_COMMON_REG_LIST_DCN30(id) } 1013 1014 static const struct dce_i2c_registers i2c_hw_regs[] = { 1015 i2c_inst_regs(1), 1016 i2c_inst_regs(2), 1017 i2c_inst_regs(3), 1018 i2c_inst_regs(4), 1019 i2c_inst_regs(5), 1020 }; 1021 1022 static const struct dce_i2c_shift i2c_shifts = { 1023 I2C_COMMON_MASK_SH_LIST_DCN30(__SHIFT) 1024 }; 1025 1026 static const struct dce_i2c_mask i2c_masks = { 1027 I2C_COMMON_MASK_SH_LIST_DCN30(_MASK) 1028 }; 1029 1030 static struct dce_i2c_hw *dcn31_i2c_hw_create( 1031 struct dc_context *ctx, 1032 uint32_t inst) 1033 { 1034 struct dce_i2c_hw *dce_i2c_hw = 1035 kzalloc(sizeof(struct dce_i2c_hw), GFP_KERNEL); 1036 1037 if (!dce_i2c_hw) 1038 return NULL; 1039 1040 dcn2_i2c_hw_construct(dce_i2c_hw, ctx, inst, 1041 &i2c_hw_regs[inst], &i2c_shifts, &i2c_masks); 1042 1043 return dce_i2c_hw; 1044 } 1045 static struct mpc *dcn31_mpc_create( 1046 struct dc_context *ctx, 1047 int num_mpcc, 1048 int num_rmu) 1049 { 1050 struct dcn30_mpc *mpc30 = kzalloc(sizeof(struct dcn30_mpc), 1051 GFP_KERNEL); 1052 1053 if (!mpc30) 1054 return NULL; 1055 1056 dcn30_mpc_construct(mpc30, ctx, 1057 &mpc_regs, 1058 &mpc_shift, 1059 &mpc_mask, 1060 num_mpcc, 1061 num_rmu); 1062 1063 return &mpc30->base; 1064 } 1065 1066 static struct hubbub *dcn31_hubbub_create(struct dc_context *ctx) 1067 { 1068 int i; 1069 1070 struct dcn20_hubbub *hubbub3 = kzalloc(sizeof(struct dcn20_hubbub), 1071 GFP_KERNEL); 1072 1073 if (!hubbub3) 1074 return NULL; 1075 1076 hubbub31_construct(hubbub3, ctx, 1077 &hubbub_reg, 1078 &hubbub_shift, 1079 &hubbub_mask, 1080 dcn3_14_ip.det_buffer_size_kbytes, 1081 dcn3_14_ip.pixel_chunk_size_kbytes, 1082 dcn3_14_ip.config_return_buffer_size_in_kbytes); 1083 1084 1085 for (i = 0; i < res_cap_dcn314.num_vmid; i++) { 1086 struct dcn20_vmid *vmid = &hubbub3->vmid[i]; 1087 1088 vmid->ctx = ctx; 1089 1090 vmid->regs = &vmid_regs[i]; 1091 vmid->shifts = &vmid_shifts; 1092 vmid->masks = &vmid_masks; 1093 } 1094 1095 return &hubbub3->base; 1096 } 1097 1098 static struct timing_generator *dcn31_timing_generator_create( 1099 struct dc_context *ctx, 1100 uint32_t instance) 1101 { 1102 struct optc *tgn10 = 1103 kzalloc(sizeof(struct optc), GFP_KERNEL); 1104 1105 if (!tgn10) 1106 return NULL; 1107 1108 tgn10->base.inst = instance; 1109 tgn10->base.ctx = ctx; 1110 1111 tgn10->tg_regs = &optc_regs[instance]; 1112 tgn10->tg_shift = &optc_shift; 1113 tgn10->tg_mask = &optc_mask; 1114 1115 dcn314_timing_generator_init(tgn10); 1116 1117 return &tgn10->base; 1118 } 1119 1120 static const struct encoder_feature_support link_enc_feature = { 1121 .max_hdmi_deep_color = COLOR_DEPTH_121212, 1122 .max_hdmi_pixel_clock = 600000, 1123 .hdmi_ycbcr420_supported = true, 1124 .dp_ycbcr420_supported = true, 1125 .fec_supported = true, 1126 .flags.bits.IS_HBR2_CAPABLE = true, 1127 .flags.bits.IS_HBR3_CAPABLE = true, 1128 .flags.bits.IS_TPS3_CAPABLE = true, 1129 .flags.bits.IS_TPS4_CAPABLE = true 1130 }; 1131 1132 static struct link_encoder *dcn31_link_encoder_create( 1133 struct dc_context *ctx, 1134 const struct encoder_init_data *enc_init_data) 1135 { 1136 struct dcn20_link_encoder *enc20 = 1137 kzalloc(sizeof(struct dcn20_link_encoder), GFP_KERNEL); 1138 1139 if (!enc20) 1140 return NULL; 1141 1142 dcn31_link_encoder_construct(enc20, 1143 enc_init_data, 1144 &link_enc_feature, 1145 &link_enc_regs[enc_init_data->transmitter], 1146 &link_enc_aux_regs[enc_init_data->channel - 1], 1147 &link_enc_hpd_regs[enc_init_data->hpd_source], 1148 &le_shift, 1149 &le_mask); 1150 1151 return &enc20->enc10.base; 1152 } 1153 1154 /* Create a minimal link encoder object not associated with a particular 1155 * physical connector. 1156 * resource_funcs.link_enc_create_minimal 1157 */ 1158 static struct link_encoder *dcn31_link_enc_create_minimal( 1159 struct dc_context *ctx, enum engine_id eng_id) 1160 { 1161 struct dcn20_link_encoder *enc20; 1162 1163 if ((eng_id - ENGINE_ID_DIGA) > ctx->dc->res_pool->res_cap->num_dig_link_enc) 1164 return NULL; 1165 1166 enc20 = kzalloc(sizeof(struct dcn20_link_encoder), GFP_KERNEL); 1167 if (!enc20) 1168 return NULL; 1169 1170 dcn31_link_encoder_construct_minimal( 1171 enc20, 1172 ctx, 1173 &link_enc_feature, 1174 &link_enc_regs[eng_id - ENGINE_ID_DIGA], 1175 eng_id); 1176 1177 return &enc20->enc10.base; 1178 } 1179 1180 static struct panel_cntl *dcn31_panel_cntl_create(const struct panel_cntl_init_data *init_data) 1181 { 1182 struct dcn31_panel_cntl *panel_cntl = 1183 kzalloc(sizeof(struct dcn31_panel_cntl), GFP_KERNEL); 1184 1185 if (!panel_cntl) 1186 return NULL; 1187 1188 dcn31_panel_cntl_construct(panel_cntl, init_data); 1189 1190 return &panel_cntl->base; 1191 } 1192 1193 static void read_dce_straps( 1194 struct dc_context *ctx, 1195 struct resource_straps *straps) 1196 { 1197 generic_reg_get(ctx, regDC_PINSTRAPS + BASE(regDC_PINSTRAPS_BASE_IDX), 1198 FN(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO), &straps->dc_pinstraps_audio); 1199 1200 } 1201 1202 static struct audio *dcn31_create_audio( 1203 struct dc_context *ctx, unsigned int inst) 1204 { 1205 return dce_audio_create(ctx, inst, 1206 &audio_regs[inst], &audio_shift, &audio_mask); 1207 } 1208 1209 static struct vpg *dcn31_vpg_create( 1210 struct dc_context *ctx, 1211 uint32_t inst) 1212 { 1213 struct dcn31_vpg *vpg31 = kzalloc(sizeof(struct dcn31_vpg), GFP_KERNEL); 1214 1215 if (!vpg31) 1216 return NULL; 1217 1218 vpg31_construct(vpg31, ctx, inst, 1219 &vpg_regs[inst], 1220 &vpg_shift, 1221 &vpg_mask); 1222 1223 return &vpg31->base; 1224 } 1225 1226 static struct afmt *dcn31_afmt_create( 1227 struct dc_context *ctx, 1228 uint32_t inst) 1229 { 1230 struct dcn31_afmt *afmt31 = kzalloc(sizeof(struct dcn31_afmt), GFP_KERNEL); 1231 1232 if (!afmt31) 1233 return NULL; 1234 1235 afmt31_construct(afmt31, ctx, inst, 1236 &afmt_regs[inst], 1237 &afmt_shift, 1238 &afmt_mask); 1239 1240 // Light sleep by default, no need to power down here 1241 1242 return &afmt31->base; 1243 } 1244 1245 static struct apg *dcn31_apg_create( 1246 struct dc_context *ctx, 1247 uint32_t inst) 1248 { 1249 struct dcn31_apg *apg31 = kzalloc(sizeof(struct dcn31_apg), GFP_KERNEL); 1250 1251 if (!apg31) 1252 return NULL; 1253 1254 apg31_construct(apg31, ctx, inst, 1255 &apg_regs[inst], 1256 &apg_shift, 1257 &apg_mask); 1258 1259 return &apg31->base; 1260 } 1261 1262 static struct stream_encoder *dcn314_stream_encoder_create( 1263 enum engine_id eng_id, 1264 struct dc_context *ctx) 1265 { 1266 struct dcn10_stream_encoder *enc1; 1267 struct vpg *vpg; 1268 struct afmt *afmt; 1269 int vpg_inst; 1270 int afmt_inst; 1271 1272 /* Mapping of VPG, AFMT, DME register blocks to DIO block instance */ 1273 if (eng_id < ENGINE_ID_DIGF) { 1274 vpg_inst = eng_id; 1275 afmt_inst = eng_id; 1276 } else 1277 return NULL; 1278 1279 enc1 = kzalloc(sizeof(struct dcn10_stream_encoder), GFP_KERNEL); 1280 vpg = dcn31_vpg_create(ctx, vpg_inst); 1281 afmt = dcn31_afmt_create(ctx, afmt_inst); 1282 1283 if (!enc1 || !vpg || !afmt) { 1284 kfree(enc1); 1285 kfree(vpg); 1286 kfree(afmt); 1287 return NULL; 1288 } 1289 1290 dcn314_dio_stream_encoder_construct(enc1, ctx, ctx->dc_bios, 1291 eng_id, vpg, afmt, 1292 &stream_enc_regs[eng_id], 1293 &se_shift, &se_mask); 1294 1295 return &enc1->base; 1296 } 1297 1298 static struct hpo_dp_stream_encoder *dcn31_hpo_dp_stream_encoder_create( 1299 enum engine_id eng_id, 1300 struct dc_context *ctx) 1301 { 1302 struct dcn31_hpo_dp_stream_encoder *hpo_dp_enc31; 1303 struct vpg *vpg; 1304 struct apg *apg; 1305 uint32_t hpo_dp_inst; 1306 uint32_t vpg_inst; 1307 uint32_t apg_inst; 1308 1309 ASSERT((eng_id >= ENGINE_ID_HPO_DP_0) && (eng_id <= ENGINE_ID_HPO_DP_3)); 1310 hpo_dp_inst = eng_id - ENGINE_ID_HPO_DP_0; 1311 1312 /* Mapping of VPG register blocks to HPO DP block instance: 1313 * VPG[6] -> HPO_DP[0] 1314 * VPG[7] -> HPO_DP[1] 1315 * VPG[8] -> HPO_DP[2] 1316 * VPG[9] -> HPO_DP[3] 1317 */ 1318 //Uses offset index 5-8, but actually maps to vpg_inst 6-9 1319 vpg_inst = hpo_dp_inst + 5; 1320 1321 /* Mapping of APG register blocks to HPO DP block instance: 1322 * APG[0] -> HPO_DP[0] 1323 * APG[1] -> HPO_DP[1] 1324 * APG[2] -> HPO_DP[2] 1325 * APG[3] -> HPO_DP[3] 1326 */ 1327 apg_inst = hpo_dp_inst; 1328 1329 /* allocate HPO stream encoder and create VPG sub-block */ 1330 hpo_dp_enc31 = kzalloc(sizeof(struct dcn31_hpo_dp_stream_encoder), GFP_KERNEL); 1331 vpg = dcn31_vpg_create(ctx, vpg_inst); 1332 apg = dcn31_apg_create(ctx, apg_inst); 1333 1334 if (!hpo_dp_enc31 || !vpg || !apg) { 1335 kfree(hpo_dp_enc31); 1336 kfree(vpg); 1337 kfree(apg); 1338 return NULL; 1339 } 1340 1341 dcn31_hpo_dp_stream_encoder_construct(hpo_dp_enc31, ctx, ctx->dc_bios, 1342 hpo_dp_inst, eng_id, vpg, apg, 1343 &hpo_dp_stream_enc_regs[hpo_dp_inst], 1344 &hpo_dp_se_shift, &hpo_dp_se_mask); 1345 1346 return &hpo_dp_enc31->base; 1347 } 1348 1349 static struct hpo_dp_link_encoder *dcn31_hpo_dp_link_encoder_create( 1350 uint8_t inst, 1351 struct dc_context *ctx) 1352 { 1353 struct dcn31_hpo_dp_link_encoder *hpo_dp_enc31; 1354 1355 /* allocate HPO link encoder */ 1356 hpo_dp_enc31 = kzalloc(sizeof(struct dcn31_hpo_dp_link_encoder), GFP_KERNEL); 1357 1358 hpo_dp_link_encoder31_construct(hpo_dp_enc31, ctx, inst, 1359 &hpo_dp_link_enc_regs[inst], 1360 &hpo_dp_le_shift, &hpo_dp_le_mask); 1361 1362 return &hpo_dp_enc31->base; 1363 } 1364 1365 static struct dce_hwseq *dcn314_hwseq_create( 1366 struct dc_context *ctx) 1367 { 1368 struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_KERNEL); 1369 1370 if (hws) { 1371 hws->ctx = ctx; 1372 hws->regs = &hwseq_reg; 1373 hws->shifts = &hwseq_shift; 1374 hws->masks = &hwseq_mask; 1375 /* DCN3.1 FPGA Workaround 1376 * Need to enable HPO DP Stream Encoder before setting OTG master enable. 1377 * To do so, move calling function enable_stream_timing to only be done AFTER calling 1378 * function core_link_enable_stream 1379 */ 1380 if (IS_FPGA_MAXIMUS_DC(ctx->dce_environment)) 1381 hws->wa.dp_hpo_and_otg_sequence = true; 1382 } 1383 return hws; 1384 } 1385 static const struct resource_create_funcs res_create_funcs = { 1386 .read_dce_straps = read_dce_straps, 1387 .create_audio = dcn31_create_audio, 1388 .create_stream_encoder = dcn314_stream_encoder_create, 1389 .create_hpo_dp_stream_encoder = dcn31_hpo_dp_stream_encoder_create, 1390 .create_hpo_dp_link_encoder = dcn31_hpo_dp_link_encoder_create, 1391 .create_hwseq = dcn314_hwseq_create, 1392 }; 1393 1394 static const struct resource_create_funcs res_create_maximus_funcs = { 1395 .read_dce_straps = NULL, 1396 .create_audio = NULL, 1397 .create_stream_encoder = NULL, 1398 .create_hpo_dp_stream_encoder = dcn31_hpo_dp_stream_encoder_create, 1399 .create_hpo_dp_link_encoder = dcn31_hpo_dp_link_encoder_create, 1400 .create_hwseq = dcn314_hwseq_create, 1401 }; 1402 1403 static void dcn314_resource_destruct(struct dcn314_resource_pool *pool) 1404 { 1405 unsigned int i; 1406 1407 for (i = 0; i < pool->base.stream_enc_count; i++) { 1408 if (pool->base.stream_enc[i] != NULL) { 1409 if (pool->base.stream_enc[i]->vpg != NULL) { 1410 kfree(DCN30_VPG_FROM_VPG(pool->base.stream_enc[i]->vpg)); 1411 pool->base.stream_enc[i]->vpg = NULL; 1412 } 1413 if (pool->base.stream_enc[i]->afmt != NULL) { 1414 kfree(DCN30_AFMT_FROM_AFMT(pool->base.stream_enc[i]->afmt)); 1415 pool->base.stream_enc[i]->afmt = NULL; 1416 } 1417 kfree(DCN10STRENC_FROM_STRENC(pool->base.stream_enc[i])); 1418 pool->base.stream_enc[i] = NULL; 1419 } 1420 } 1421 1422 for (i = 0; i < pool->base.hpo_dp_stream_enc_count; i++) { 1423 if (pool->base.hpo_dp_stream_enc[i] != NULL) { 1424 if (pool->base.hpo_dp_stream_enc[i]->vpg != NULL) { 1425 kfree(DCN30_VPG_FROM_VPG(pool->base.hpo_dp_stream_enc[i]->vpg)); 1426 pool->base.hpo_dp_stream_enc[i]->vpg = NULL; 1427 } 1428 if (pool->base.hpo_dp_stream_enc[i]->apg != NULL) { 1429 kfree(DCN31_APG_FROM_APG(pool->base.hpo_dp_stream_enc[i]->apg)); 1430 pool->base.hpo_dp_stream_enc[i]->apg = NULL; 1431 } 1432 kfree(DCN3_1_HPO_DP_STREAM_ENC_FROM_HPO_STREAM_ENC(pool->base.hpo_dp_stream_enc[i])); 1433 pool->base.hpo_dp_stream_enc[i] = NULL; 1434 } 1435 } 1436 1437 for (i = 0; i < pool->base.hpo_dp_link_enc_count; i++) { 1438 if (pool->base.hpo_dp_link_enc[i] != NULL) { 1439 kfree(DCN3_1_HPO_DP_LINK_ENC_FROM_HPO_LINK_ENC(pool->base.hpo_dp_link_enc[i])); 1440 pool->base.hpo_dp_link_enc[i] = NULL; 1441 } 1442 } 1443 1444 for (i = 0; i < pool->base.res_cap->num_dsc; i++) { 1445 if (pool->base.dscs[i] != NULL) 1446 dcn20_dsc_destroy(&pool->base.dscs[i]); 1447 } 1448 1449 if (pool->base.mpc != NULL) { 1450 kfree(TO_DCN20_MPC(pool->base.mpc)); 1451 pool->base.mpc = NULL; 1452 } 1453 if (pool->base.hubbub != NULL) { 1454 kfree(pool->base.hubbub); 1455 pool->base.hubbub = NULL; 1456 } 1457 for (i = 0; i < pool->base.pipe_count; i++) { 1458 if (pool->base.dpps[i] != NULL) 1459 dcn31_dpp_destroy(&pool->base.dpps[i]); 1460 1461 if (pool->base.ipps[i] != NULL) 1462 pool->base.ipps[i]->funcs->ipp_destroy(&pool->base.ipps[i]); 1463 1464 if (pool->base.hubps[i] != NULL) { 1465 kfree(TO_DCN20_HUBP(pool->base.hubps[i])); 1466 pool->base.hubps[i] = NULL; 1467 } 1468 1469 if (pool->base.irqs != NULL) 1470 dal_irq_service_destroy(&pool->base.irqs); 1471 } 1472 1473 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { 1474 if (pool->base.engines[i] != NULL) 1475 dce110_engine_destroy(&pool->base.engines[i]); 1476 if (pool->base.hw_i2cs[i] != NULL) { 1477 kfree(pool->base.hw_i2cs[i]); 1478 pool->base.hw_i2cs[i] = NULL; 1479 } 1480 if (pool->base.sw_i2cs[i] != NULL) { 1481 kfree(pool->base.sw_i2cs[i]); 1482 pool->base.sw_i2cs[i] = NULL; 1483 } 1484 } 1485 1486 for (i = 0; i < pool->base.res_cap->num_opp; i++) { 1487 if (pool->base.opps[i] != NULL) 1488 pool->base.opps[i]->funcs->opp_destroy(&pool->base.opps[i]); 1489 } 1490 1491 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { 1492 if (pool->base.timing_generators[i] != NULL) { 1493 kfree(DCN10TG_FROM_TG(pool->base.timing_generators[i])); 1494 pool->base.timing_generators[i] = NULL; 1495 } 1496 } 1497 1498 for (i = 0; i < pool->base.res_cap->num_dwb; i++) { 1499 if (pool->base.dwbc[i] != NULL) { 1500 kfree(TO_DCN30_DWBC(pool->base.dwbc[i])); 1501 pool->base.dwbc[i] = NULL; 1502 } 1503 if (pool->base.mcif_wb[i] != NULL) { 1504 kfree(TO_DCN30_MMHUBBUB(pool->base.mcif_wb[i])); 1505 pool->base.mcif_wb[i] = NULL; 1506 } 1507 } 1508 1509 for (i = 0; i < pool->base.audio_count; i++) { 1510 if (pool->base.audios[i]) 1511 dce_aud_destroy(&pool->base.audios[i]); 1512 } 1513 1514 for (i = 0; i < pool->base.clk_src_count; i++) { 1515 if (pool->base.clock_sources[i] != NULL) { 1516 dcn20_clock_source_destroy(&pool->base.clock_sources[i]); 1517 pool->base.clock_sources[i] = NULL; 1518 } 1519 } 1520 1521 for (i = 0; i < pool->base.res_cap->num_mpc_3dlut; i++) { 1522 if (pool->base.mpc_lut[i] != NULL) { 1523 dc_3dlut_func_release(pool->base.mpc_lut[i]); 1524 pool->base.mpc_lut[i] = NULL; 1525 } 1526 if (pool->base.mpc_shaper[i] != NULL) { 1527 dc_transfer_func_release(pool->base.mpc_shaper[i]); 1528 pool->base.mpc_shaper[i] = NULL; 1529 } 1530 } 1531 1532 if (pool->base.dp_clock_source != NULL) { 1533 dcn20_clock_source_destroy(&pool->base.dp_clock_source); 1534 pool->base.dp_clock_source = NULL; 1535 } 1536 1537 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { 1538 if (pool->base.multiple_abms[i] != NULL) 1539 dce_abm_destroy(&pool->base.multiple_abms[i]); 1540 } 1541 1542 if (pool->base.psr != NULL) 1543 dmub_psr_destroy(&pool->base.psr); 1544 1545 if (pool->base.dccg != NULL) 1546 dcn_dccg_destroy(&pool->base.dccg); 1547 } 1548 1549 static struct hubp *dcn31_hubp_create( 1550 struct dc_context *ctx, 1551 uint32_t inst) 1552 { 1553 struct dcn20_hubp *hubp2 = 1554 kzalloc(sizeof(struct dcn20_hubp), GFP_KERNEL); 1555 1556 if (!hubp2) 1557 return NULL; 1558 1559 if (hubp31_construct(hubp2, ctx, inst, 1560 &hubp_regs[inst], &hubp_shift, &hubp_mask)) 1561 return &hubp2->base; 1562 1563 BREAK_TO_DEBUGGER(); 1564 kfree(hubp2); 1565 return NULL; 1566 } 1567 1568 static bool dcn31_dwbc_create(struct dc_context *ctx, struct resource_pool *pool) 1569 { 1570 int i; 1571 uint32_t pipe_count = pool->res_cap->num_dwb; 1572 1573 for (i = 0; i < pipe_count; i++) { 1574 struct dcn30_dwbc *dwbc30 = kzalloc(sizeof(struct dcn30_dwbc), 1575 GFP_KERNEL); 1576 1577 if (!dwbc30) { 1578 dm_error("DC: failed to create dwbc30!\n"); 1579 return false; 1580 } 1581 1582 dcn30_dwbc_construct(dwbc30, ctx, 1583 &dwbc30_regs[i], 1584 &dwbc30_shift, 1585 &dwbc30_mask, 1586 i); 1587 1588 pool->dwbc[i] = &dwbc30->base; 1589 } 1590 return true; 1591 } 1592 1593 static bool dcn31_mmhubbub_create(struct dc_context *ctx, struct resource_pool *pool) 1594 { 1595 int i; 1596 uint32_t pipe_count = pool->res_cap->num_dwb; 1597 1598 for (i = 0; i < pipe_count; i++) { 1599 struct dcn30_mmhubbub *mcif_wb30 = kzalloc(sizeof(struct dcn30_mmhubbub), 1600 GFP_KERNEL); 1601 1602 if (!mcif_wb30) { 1603 dm_error("DC: failed to create mcif_wb30!\n"); 1604 return false; 1605 } 1606 1607 dcn30_mmhubbub_construct(mcif_wb30, ctx, 1608 &mcif_wb30_regs[i], 1609 &mcif_wb30_shift, 1610 &mcif_wb30_mask, 1611 i); 1612 1613 pool->mcif_wb[i] = &mcif_wb30->base; 1614 } 1615 return true; 1616 } 1617 1618 static struct display_stream_compressor *dcn314_dsc_create( 1619 struct dc_context *ctx, uint32_t inst) 1620 { 1621 struct dcn20_dsc *dsc = 1622 kzalloc(sizeof(struct dcn20_dsc), GFP_KERNEL); 1623 1624 if (!dsc) { 1625 BREAK_TO_DEBUGGER(); 1626 return NULL; 1627 } 1628 1629 dsc2_construct(dsc, ctx, inst, &dsc_regs[inst], &dsc_shift, &dsc_mask); 1630 return &dsc->base; 1631 } 1632 1633 static void dcn314_destroy_resource_pool(struct resource_pool **pool) 1634 { 1635 struct dcn314_resource_pool *dcn314_pool = TO_DCN314_RES_POOL(*pool); 1636 1637 dcn314_resource_destruct(dcn314_pool); 1638 kfree(dcn314_pool); 1639 *pool = NULL; 1640 } 1641 1642 static struct clock_source *dcn31_clock_source_create( 1643 struct dc_context *ctx, 1644 struct dc_bios *bios, 1645 enum clock_source_id id, 1646 const struct dce110_clk_src_regs *regs, 1647 bool dp_clk_src) 1648 { 1649 struct dce110_clk_src *clk_src = 1650 kzalloc(sizeof(struct dce110_clk_src), GFP_KERNEL); 1651 1652 if (!clk_src) 1653 return NULL; 1654 1655 if (dcn31_clk_src_construct(clk_src, ctx, bios, id, 1656 regs, &cs_shift, &cs_mask)) { 1657 clk_src->base.dp_clk_src = dp_clk_src; 1658 return &clk_src->base; 1659 } 1660 1661 BREAK_TO_DEBUGGER(); 1662 kfree(clk_src); 1663 return NULL; 1664 } 1665 1666 static int dcn314_populate_dml_pipes_from_context( 1667 struct dc *dc, struct dc_state *context, 1668 display_e2e_pipe_params_st *pipes, 1669 bool fast_validate) 1670 { 1671 int pipe_cnt; 1672 1673 DC_FP_START(); 1674 pipe_cnt = dcn314_populate_dml_pipes_from_context_fpu(dc, context, pipes, fast_validate); 1675 DC_FP_END(); 1676 1677 return pipe_cnt; 1678 } 1679 1680 static struct dc_cap_funcs cap_funcs = { 1681 .get_dcc_compression_cap = dcn20_get_dcc_compression_cap 1682 }; 1683 1684 static void dcn314_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params) 1685 { 1686 DC_FP_START(); 1687 dcn314_update_bw_bounding_box_fpu(dc, bw_params); 1688 DC_FP_END(); 1689 } 1690 1691 static void dcn314_get_panel_config_defaults(struct dc_panel_config *panel_config) 1692 { 1693 *panel_config = panel_config_defaults; 1694 } 1695 1696 static struct resource_funcs dcn314_res_pool_funcs = { 1697 .destroy = dcn314_destroy_resource_pool, 1698 .link_enc_create = dcn31_link_encoder_create, 1699 .link_enc_create_minimal = dcn31_link_enc_create_minimal, 1700 .link_encs_assign = link_enc_cfg_link_encs_assign, 1701 .link_enc_unassign = link_enc_cfg_link_enc_unassign, 1702 .panel_cntl_create = dcn31_panel_cntl_create, 1703 .validate_bandwidth = dcn31_validate_bandwidth, 1704 .calculate_wm_and_dlg = dcn31_calculate_wm_and_dlg, 1705 .update_soc_for_wm_a = dcn31_update_soc_for_wm_a, 1706 .populate_dml_pipes = dcn314_populate_dml_pipes_from_context, 1707 .acquire_idle_pipe_for_layer = dcn20_acquire_idle_pipe_for_layer, 1708 .add_stream_to_ctx = dcn30_add_stream_to_ctx, 1709 .add_dsc_to_stream_resource = dcn20_add_dsc_to_stream_resource, 1710 .remove_stream_from_ctx = dcn20_remove_stream_from_ctx, 1711 .populate_dml_writeback_from_context = dcn30_populate_dml_writeback_from_context, 1712 .set_mcif_arb_params = dcn30_set_mcif_arb_params, 1713 .find_first_free_match_stream_enc_for_link = dcn10_find_first_free_match_stream_enc_for_link, 1714 .acquire_post_bldn_3dlut = dcn30_acquire_post_bldn_3dlut, 1715 .release_post_bldn_3dlut = dcn30_release_post_bldn_3dlut, 1716 .update_bw_bounding_box = dcn314_update_bw_bounding_box, 1717 .patch_unknown_plane_state = dcn20_patch_unknown_plane_state, 1718 .get_panel_config_defaults = dcn314_get_panel_config_defaults, 1719 }; 1720 1721 static struct clock_source *dcn30_clock_source_create( 1722 struct dc_context *ctx, 1723 struct dc_bios *bios, 1724 enum clock_source_id id, 1725 const struct dce110_clk_src_regs *regs, 1726 bool dp_clk_src) 1727 { 1728 struct dce110_clk_src *clk_src = 1729 kzalloc(sizeof(struct dce110_clk_src), GFP_KERNEL); 1730 1731 if (!clk_src) 1732 return NULL; 1733 1734 if (dcn31_clk_src_construct(clk_src, ctx, bios, id, 1735 regs, &cs_shift, &cs_mask)) { 1736 clk_src->base.dp_clk_src = dp_clk_src; 1737 return &clk_src->base; 1738 } 1739 1740 BREAK_TO_DEBUGGER(); 1741 kfree(clk_src); 1742 return NULL; 1743 } 1744 1745 static bool dcn314_resource_construct( 1746 uint8_t num_virtual_links, 1747 struct dc *dc, 1748 struct dcn314_resource_pool *pool) 1749 { 1750 int i; 1751 struct dc_context *ctx = dc->ctx; 1752 struct irq_service_init_data init_data; 1753 1754 ctx->dc_bios->regs = &bios_regs; 1755 1756 pool->base.res_cap = &res_cap_dcn314; 1757 pool->base.funcs = &dcn314_res_pool_funcs; 1758 1759 /************************************************* 1760 * Resource + asic cap harcoding * 1761 *************************************************/ 1762 pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE; 1763 pool->base.pipe_count = pool->base.res_cap->num_timing_generator; 1764 pool->base.mpcc_count = pool->base.res_cap->num_timing_generator; 1765 dc->caps.max_downscale_ratio = 600; 1766 dc->caps.i2c_speed_in_khz = 100; 1767 dc->caps.i2c_speed_in_khz_hdcp = 100; 1768 dc->caps.max_cursor_size = 256; 1769 dc->caps.min_horizontal_blanking_period = 80; 1770 dc->caps.dmdata_alloc_size = 2048; 1771 dc->caps.max_slave_planes = 2; 1772 dc->caps.max_slave_yuv_planes = 2; 1773 dc->caps.max_slave_rgb_planes = 2; 1774 dc->caps.post_blend_color_processing = true; 1775 dc->caps.force_dp_tps4_for_cp2520 = true; 1776 if (dc->config.forceHBR2CP2520) 1777 dc->caps.force_dp_tps4_for_cp2520 = false; 1778 dc->caps.dp_hpo = true; 1779 dc->caps.dp_hdmi21_pcon_support = true; 1780 dc->caps.edp_dsc_support = true; 1781 dc->caps.extended_aux_timeout_support = true; 1782 dc->caps.dmcub_support = true; 1783 dc->caps.is_apu = true; 1784 dc->caps.seamless_odm = true; 1785 1786 dc->caps.zstate_support = true; 1787 1788 /* Color pipeline capabilities */ 1789 dc->caps.color.dpp.dcn_arch = 1; 1790 dc->caps.color.dpp.input_lut_shared = 0; 1791 dc->caps.color.dpp.icsc = 1; 1792 dc->caps.color.dpp.dgam_ram = 0; // must use gamma_corr 1793 dc->caps.color.dpp.dgam_rom_caps.srgb = 1; 1794 dc->caps.color.dpp.dgam_rom_caps.bt2020 = 1; 1795 dc->caps.color.dpp.dgam_rom_caps.gamma2_2 = 1; 1796 dc->caps.color.dpp.dgam_rom_caps.pq = 1; 1797 dc->caps.color.dpp.dgam_rom_caps.hlg = 1; 1798 dc->caps.color.dpp.post_csc = 1; 1799 dc->caps.color.dpp.gamma_corr = 1; 1800 dc->caps.color.dpp.dgam_rom_for_yuv = 0; 1801 1802 dc->caps.color.dpp.hw_3d_lut = 1; 1803 dc->caps.color.dpp.ogam_ram = 1; 1804 // no OGAM ROM on DCN301 1805 dc->caps.color.dpp.ogam_rom_caps.srgb = 0; 1806 dc->caps.color.dpp.ogam_rom_caps.bt2020 = 0; 1807 dc->caps.color.dpp.ogam_rom_caps.gamma2_2 = 0; 1808 dc->caps.color.dpp.ogam_rom_caps.pq = 0; 1809 dc->caps.color.dpp.ogam_rom_caps.hlg = 0; 1810 dc->caps.color.dpp.ocsc = 0; 1811 1812 dc->caps.color.mpc.gamut_remap = 1; 1813 dc->caps.color.mpc.num_3dluts = pool->base.res_cap->num_mpc_3dlut; //2 1814 dc->caps.color.mpc.ogam_ram = 1; 1815 dc->caps.color.mpc.ogam_rom_caps.srgb = 0; 1816 dc->caps.color.mpc.ogam_rom_caps.bt2020 = 0; 1817 dc->caps.color.mpc.ogam_rom_caps.gamma2_2 = 0; 1818 dc->caps.color.mpc.ogam_rom_caps.pq = 0; 1819 dc->caps.color.mpc.ogam_rom_caps.hlg = 0; 1820 dc->caps.color.mpc.ocsc = 1; 1821 1822 /* Use pipe context based otg sync logic */ 1823 dc->config.use_pipe_ctx_sync_logic = true; 1824 1825 /* read VBIOS LTTPR caps */ 1826 { 1827 if (ctx->dc_bios->funcs->get_lttpr_caps) { 1828 enum bp_result bp_query_result; 1829 uint8_t is_vbios_lttpr_enable = 0; 1830 1831 bp_query_result = ctx->dc_bios->funcs->get_lttpr_caps(ctx->dc_bios, &is_vbios_lttpr_enable); 1832 dc->caps.vbios_lttpr_enable = (bp_query_result == BP_RESULT_OK) && !!is_vbios_lttpr_enable; 1833 } 1834 1835 /* interop bit is implicit */ 1836 { 1837 dc->caps.vbios_lttpr_aware = true; 1838 } 1839 } 1840 1841 if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV) 1842 dc->debug = debug_defaults_drv; 1843 else 1844 dc->debug = debug_defaults_diags; 1845 // Init the vm_helper 1846 if (dc->vm_helper) 1847 vm_helper_init(dc->vm_helper, 16); 1848 1849 /************************************************* 1850 * Create resources * 1851 *************************************************/ 1852 1853 /* Clock Sources for Pixel Clock*/ 1854 pool->base.clock_sources[DCN31_CLK_SRC_PLL0] = 1855 dcn30_clock_source_create(ctx, ctx->dc_bios, 1856 CLOCK_SOURCE_COMBO_PHY_PLL0, 1857 &clk_src_regs[0], false); 1858 pool->base.clock_sources[DCN31_CLK_SRC_PLL1] = 1859 dcn30_clock_source_create(ctx, ctx->dc_bios, 1860 CLOCK_SOURCE_COMBO_PHY_PLL1, 1861 &clk_src_regs[1], false); 1862 pool->base.clock_sources[DCN31_CLK_SRC_PLL2] = 1863 dcn30_clock_source_create(ctx, ctx->dc_bios, 1864 CLOCK_SOURCE_COMBO_PHY_PLL2, 1865 &clk_src_regs[2], false); 1866 pool->base.clock_sources[DCN31_CLK_SRC_PLL3] = 1867 dcn30_clock_source_create(ctx, ctx->dc_bios, 1868 CLOCK_SOURCE_COMBO_PHY_PLL3, 1869 &clk_src_regs[3], false); 1870 pool->base.clock_sources[DCN31_CLK_SRC_PLL4] = 1871 dcn30_clock_source_create(ctx, ctx->dc_bios, 1872 CLOCK_SOURCE_COMBO_PHY_PLL4, 1873 &clk_src_regs[4], false); 1874 1875 pool->base.clk_src_count = DCN30_CLK_SRC_TOTAL; 1876 1877 /* todo: not reuse phy_pll registers */ 1878 pool->base.dp_clock_source = 1879 dcn31_clock_source_create(ctx, ctx->dc_bios, 1880 CLOCK_SOURCE_ID_DP_DTO, 1881 &clk_src_regs[0], true); 1882 1883 for (i = 0; i < pool->base.clk_src_count; i++) { 1884 if (pool->base.clock_sources[i] == NULL) { 1885 dm_error("DC: failed to create clock sources!\n"); 1886 BREAK_TO_DEBUGGER(); 1887 goto create_fail; 1888 } 1889 } 1890 1891 pool->base.dccg = dccg314_create(ctx, &dccg_regs, &dccg_shift, &dccg_mask); 1892 if (pool->base.dccg == NULL) { 1893 dm_error("DC: failed to create dccg!\n"); 1894 BREAK_TO_DEBUGGER(); 1895 goto create_fail; 1896 } 1897 1898 init_data.ctx = dc->ctx; 1899 pool->base.irqs = dal_irq_service_dcn314_create(&init_data); 1900 if (!pool->base.irqs) 1901 goto create_fail; 1902 1903 /* HUBBUB */ 1904 pool->base.hubbub = dcn31_hubbub_create(ctx); 1905 if (pool->base.hubbub == NULL) { 1906 BREAK_TO_DEBUGGER(); 1907 dm_error("DC: failed to create hubbub!\n"); 1908 goto create_fail; 1909 } 1910 1911 /* HUBPs, DPPs, OPPs and TGs */ 1912 for (i = 0; i < pool->base.pipe_count; i++) { 1913 pool->base.hubps[i] = dcn31_hubp_create(ctx, i); 1914 if (pool->base.hubps[i] == NULL) { 1915 BREAK_TO_DEBUGGER(); 1916 dm_error( 1917 "DC: failed to create hubps!\n"); 1918 goto create_fail; 1919 } 1920 1921 pool->base.dpps[i] = dcn31_dpp_create(ctx, i); 1922 if (pool->base.dpps[i] == NULL) { 1923 BREAK_TO_DEBUGGER(); 1924 dm_error( 1925 "DC: failed to create dpps!\n"); 1926 goto create_fail; 1927 } 1928 } 1929 1930 for (i = 0; i < pool->base.res_cap->num_opp; i++) { 1931 pool->base.opps[i] = dcn31_opp_create(ctx, i); 1932 if (pool->base.opps[i] == NULL) { 1933 BREAK_TO_DEBUGGER(); 1934 dm_error( 1935 "DC: failed to create output pixel processor!\n"); 1936 goto create_fail; 1937 } 1938 } 1939 1940 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { 1941 pool->base.timing_generators[i] = dcn31_timing_generator_create( 1942 ctx, i); 1943 if (pool->base.timing_generators[i] == NULL) { 1944 BREAK_TO_DEBUGGER(); 1945 dm_error("DC: failed to create tg!\n"); 1946 goto create_fail; 1947 } 1948 } 1949 pool->base.timing_generator_count = i; 1950 1951 /* PSR */ 1952 pool->base.psr = dmub_psr_create(ctx); 1953 if (pool->base.psr == NULL) { 1954 dm_error("DC: failed to create psr obj!\n"); 1955 BREAK_TO_DEBUGGER(); 1956 goto create_fail; 1957 } 1958 1959 /* ABM */ 1960 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { 1961 pool->base.multiple_abms[i] = dmub_abm_create(ctx, 1962 &abm_regs[i], 1963 &abm_shift, 1964 &abm_mask); 1965 if (pool->base.multiple_abms[i] == NULL) { 1966 dm_error("DC: failed to create abm for pipe %d!\n", i); 1967 BREAK_TO_DEBUGGER(); 1968 goto create_fail; 1969 } 1970 } 1971 1972 /* MPC and DSC */ 1973 pool->base.mpc = dcn31_mpc_create(ctx, pool->base.mpcc_count, pool->base.res_cap->num_mpc_3dlut); 1974 if (pool->base.mpc == NULL) { 1975 BREAK_TO_DEBUGGER(); 1976 dm_error("DC: failed to create mpc!\n"); 1977 goto create_fail; 1978 } 1979 1980 for (i = 0; i < pool->base.res_cap->num_dsc; i++) { 1981 pool->base.dscs[i] = dcn314_dsc_create(ctx, i); 1982 if (pool->base.dscs[i] == NULL) { 1983 BREAK_TO_DEBUGGER(); 1984 dm_error("DC: failed to create display stream compressor %d!\n", i); 1985 goto create_fail; 1986 } 1987 } 1988 1989 /* DWB and MMHUBBUB */ 1990 if (!dcn31_dwbc_create(ctx, &pool->base)) { 1991 BREAK_TO_DEBUGGER(); 1992 dm_error("DC: failed to create dwbc!\n"); 1993 goto create_fail; 1994 } 1995 1996 if (!dcn31_mmhubbub_create(ctx, &pool->base)) { 1997 BREAK_TO_DEBUGGER(); 1998 dm_error("DC: failed to create mcif_wb!\n"); 1999 goto create_fail; 2000 } 2001 2002 /* AUX and I2C */ 2003 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { 2004 pool->base.engines[i] = dcn31_aux_engine_create(ctx, i); 2005 if (pool->base.engines[i] == NULL) { 2006 BREAK_TO_DEBUGGER(); 2007 dm_error( 2008 "DC:failed to create aux engine!!\n"); 2009 goto create_fail; 2010 } 2011 pool->base.hw_i2cs[i] = dcn31_i2c_hw_create(ctx, i); 2012 if (pool->base.hw_i2cs[i] == NULL) { 2013 BREAK_TO_DEBUGGER(); 2014 dm_error( 2015 "DC:failed to create hw i2c!!\n"); 2016 goto create_fail; 2017 } 2018 pool->base.sw_i2cs[i] = NULL; 2019 } 2020 2021 /* DCN314 has 4 DPIA */ 2022 pool->base.usb4_dpia_count = 4; 2023 2024 /* Audio, Stream Encoders including HPO and virtual, MPC 3D LUTs */ 2025 if (!resource_construct(num_virtual_links, dc, &pool->base, 2026 (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment) ? 2027 &res_create_funcs : &res_create_maximus_funcs))) 2028 goto create_fail; 2029 2030 /* HW Sequencer and Plane caps */ 2031 dcn314_hw_sequencer_construct(dc); 2032 2033 dc->caps.max_planes = pool->base.pipe_count; 2034 2035 for (i = 0; i < dc->caps.max_planes; ++i) 2036 dc->caps.planes[i] = plane_cap; 2037 2038 dc->cap_funcs = cap_funcs; 2039 2040 dc->dcn_ip->max_num_dpp = dcn3_14_ip.max_num_dpp; 2041 2042 return true; 2043 2044 create_fail: 2045 2046 dcn314_resource_destruct(pool); 2047 2048 return false; 2049 } 2050 2051 struct resource_pool *dcn314_create_resource_pool( 2052 const struct dc_init_data *init_data, 2053 struct dc *dc) 2054 { 2055 struct dcn314_resource_pool *pool = 2056 kzalloc(sizeof(struct dcn314_resource_pool), GFP_KERNEL); 2057 2058 if (!pool) 2059 return NULL; 2060 2061 if (dcn314_resource_construct(init_data->num_virtual_links, dc, pool)) 2062 return &pool->base; 2063 2064 BREAK_TO_DEBUGGER(); 2065 kfree(pool); 2066 return NULL; 2067 } 2068