1 // SPDX-License-Identifier: MIT 2 /* 3 * Copyright 2022 Advanced Micro Devices, Inc. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 * 23 * Authors: AMD 24 * 25 */ 26 27 28 #include "dm_services.h" 29 #include "dc.h" 30 31 #include "dcn31/dcn31_init.h" 32 #include "dcn314/dcn314_init.h" 33 34 #include "resource.h" 35 #include "include/irq_service_interface.h" 36 #include "dcn314_resource.h" 37 38 #include "dcn20/dcn20_resource.h" 39 #include "dcn30/dcn30_resource.h" 40 #include "dcn31/dcn31_resource.h" 41 42 #include "dcn10/dcn10_ipp.h" 43 #include "dcn30/dcn30_hubbub.h" 44 #include "dcn31/dcn31_hubbub.h" 45 #include "dcn30/dcn30_mpc.h" 46 #include "dcn31/dcn31_hubp.h" 47 #include "irq/dcn31/irq_service_dcn31.h" 48 #include "irq/dcn314/irq_service_dcn314.h" 49 #include "dcn30/dcn30_dpp.h" 50 #include "dcn314/dcn314_optc.h" 51 #include "dcn20/dcn20_hwseq.h" 52 #include "dcn30/dcn30_hwseq.h" 53 #include "dce110/dce110_hw_sequencer.h" 54 #include "dcn30/dcn30_opp.h" 55 #include "dcn20/dcn20_dsc.h" 56 #include "dcn30/dcn30_vpg.h" 57 #include "dcn30/dcn30_afmt.h" 58 #include "dcn31/dcn31_dio_link_encoder.h" 59 #include "dcn314/dcn314_dio_stream_encoder.h" 60 #include "dcn31/dcn31_hpo_dp_stream_encoder.h" 61 #include "dcn31/dcn31_hpo_dp_link_encoder.h" 62 #include "dcn31/dcn31_apg.h" 63 #include "dcn31/dcn31_vpg.h" 64 #include "dcn31/dcn31_afmt.h" 65 #include "dce/dce_clock_source.h" 66 #include "dce/dce_audio.h" 67 #include "dce/dce_hwseq.h" 68 #include "clk_mgr.h" 69 #include "virtual/virtual_stream_encoder.h" 70 #include "dce110/dce110_resource.h" 71 #include "dml/display_mode_vba.h" 72 #include "dml/dcn31/dcn31_fpu.h" 73 #include "dml/dcn314/dcn314_fpu.h" 74 #include "dcn314/dcn314_dccg.h" 75 #include "dcn10/dcn10_resource.h" 76 #include "dcn31/dcn31_panel_cntl.h" 77 #include "dcn314/dcn314_hwseq.h" 78 79 #include "dcn30/dcn30_dwb.h" 80 #include "dcn30/dcn30_mmhubbub.h" 81 82 #include "dcn/dcn_3_1_4_offset.h" 83 #include "dcn/dcn_3_1_4_sh_mask.h" 84 #include "dpcs/dpcs_3_1_4_offset.h" 85 #include "dpcs/dpcs_3_1_4_sh_mask.h" 86 87 #define DCHUBBUB_DEBUG_CTRL_0__DET_DEPTH__SHIFT 0x10 88 #define DCHUBBUB_DEBUG_CTRL_0__DET_DEPTH_MASK 0x01FF0000L 89 90 #define DSCC0_DSCC_CONFIG0__ICH_RESET_AT_END_OF_LINE__SHIFT 0x0 91 #define DSCC0_DSCC_CONFIG0__ICH_RESET_AT_END_OF_LINE_MASK 0x0000000FL 92 93 #include "reg_helper.h" 94 #include "dce/dmub_abm.h" 95 #include "dce/dmub_psr.h" 96 #include "dce/dce_aux.h" 97 #include "dce/dce_i2c.h" 98 #include "dml/dcn314/display_mode_vba_314.h" 99 #include "vm_helper.h" 100 #include "dcn20/dcn20_vmid.h" 101 102 #include "link_enc_cfg.h" 103 104 #define DCN_BASE__INST0_SEG1 0x000000C0 105 #define DCN_BASE__INST0_SEG2 0x000034C0 106 #define DCN_BASE__INST0_SEG3 0x00009000 107 108 #define NBIO_BASE__INST0_SEG1 0x00000014 109 110 #define MAX_INSTANCE 7 111 #define MAX_SEGMENT 8 112 113 #define regBIF_BX2_BIOS_SCRATCH_2 0x003a 114 #define regBIF_BX2_BIOS_SCRATCH_2_BASE_IDX 1 115 #define regBIF_BX2_BIOS_SCRATCH_3 0x003b 116 #define regBIF_BX2_BIOS_SCRATCH_3_BASE_IDX 1 117 #define regBIF_BX2_BIOS_SCRATCH_6 0x003e 118 #define regBIF_BX2_BIOS_SCRATCH_6_BASE_IDX 1 119 120 #define DC_LOGGER_INIT(logger) 121 122 enum dcn31_clk_src_array_id { 123 DCN31_CLK_SRC_PLL0, 124 DCN31_CLK_SRC_PLL1, 125 DCN31_CLK_SRC_PLL2, 126 DCN31_CLK_SRC_PLL3, 127 DCN31_CLK_SRC_PLL4, 128 DCN30_CLK_SRC_TOTAL 129 }; 130 131 /* begin ********************* 132 * macros to expend register list macro defined in HW object header file 133 */ 134 135 /* DCN */ 136 /* TODO awful hack. fixup dcn20_dwb.h */ 137 #undef BASE_INNER 138 #define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg 139 140 #define BASE(seg) BASE_INNER(seg) 141 142 #define SR(reg_name)\ 143 .reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \ 144 reg ## reg_name 145 146 #define SRI(reg_name, block, id)\ 147 .reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 148 reg ## block ## id ## _ ## reg_name 149 150 #define SRI2(reg_name, block, id)\ 151 .reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \ 152 reg ## reg_name 153 154 #define SRIR(var_name, reg_name, block, id)\ 155 .var_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 156 reg ## block ## id ## _ ## reg_name 157 158 #define SRII(reg_name, block, id)\ 159 .reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 160 reg ## block ## id ## _ ## reg_name 161 162 #define SRII_MPC_RMU(reg_name, block, id)\ 163 .RMU##_##reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 164 reg ## block ## id ## _ ## reg_name 165 166 #define SRII_DWB(reg_name, temp_name, block, id)\ 167 .reg_name[id] = BASE(reg ## block ## id ## _ ## temp_name ## _BASE_IDX) + \ 168 reg ## block ## id ## _ ## temp_name 169 170 #define SF_DWB2(reg_name, block, id, field_name, post_fix) \ 171 .field_name = reg_name ## __ ## field_name ## post_fix 172 173 #define DCCG_SRII(reg_name, block, id)\ 174 .block ## _ ## reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 175 reg ## block ## id ## _ ## reg_name 176 177 #define VUPDATE_SRII(reg_name, block, id)\ 178 .reg_name[id] = BASE(reg ## reg_name ## _ ## block ## id ## _BASE_IDX) + \ 179 reg ## reg_name ## _ ## block ## id 180 181 /* NBIO */ 182 #define NBIO_BASE_INNER(seg) \ 183 NBIO_BASE__INST0_SEG ## seg 184 185 #define NBIO_BASE(seg) \ 186 NBIO_BASE_INNER(seg) 187 188 #define NBIO_SR(reg_name)\ 189 .reg_name = NBIO_BASE(regBIF_BX2_ ## reg_name ## _BASE_IDX) + \ 190 regBIF_BX2_ ## reg_name 191 192 /* MMHUB */ 193 #define MMHUB_BASE_INNER(seg) \ 194 MMHUB_BASE__INST0_SEG ## seg 195 196 #define MMHUB_BASE(seg) \ 197 MMHUB_BASE_INNER(seg) 198 199 #define MMHUB_SR(reg_name)\ 200 .reg_name = MMHUB_BASE(reg ## reg_name ## _BASE_IDX) + \ 201 reg ## reg_name 202 203 /* CLOCK */ 204 #define CLK_BASE_INNER(seg) \ 205 CLK_BASE__INST0_SEG ## seg 206 207 #define CLK_BASE(seg) \ 208 CLK_BASE_INNER(seg) 209 210 #define CLK_SRI(reg_name, block, inst)\ 211 .reg_name = CLK_BASE(reg ## block ## _ ## inst ## _ ## reg_name ## _BASE_IDX) + \ 212 reg ## block ## _ ## inst ## _ ## reg_name 213 214 215 static const struct bios_registers bios_regs = { 216 NBIO_SR(BIOS_SCRATCH_3), 217 NBIO_SR(BIOS_SCRATCH_6) 218 }; 219 220 #define clk_src_regs(index, pllid)\ 221 [index] = {\ 222 CS_COMMON_REG_LIST_DCN3_0(index, pllid),\ 223 } 224 225 static const struct dce110_clk_src_regs clk_src_regs[] = { 226 clk_src_regs(0, A), 227 clk_src_regs(1, B), 228 clk_src_regs(2, C), 229 clk_src_regs(3, D), 230 clk_src_regs(4, E) 231 }; 232 233 static const struct dce110_clk_src_shift cs_shift = { 234 CS_COMMON_MASK_SH_LIST_DCN3_1_4(__SHIFT) 235 }; 236 237 static const struct dce110_clk_src_mask cs_mask = { 238 CS_COMMON_MASK_SH_LIST_DCN3_1_4(_MASK) 239 }; 240 241 #define abm_regs(id)\ 242 [id] = {\ 243 ABM_DCN302_REG_LIST(id)\ 244 } 245 246 static const struct dce_abm_registers abm_regs[] = { 247 abm_regs(0), 248 abm_regs(1), 249 abm_regs(2), 250 abm_regs(3), 251 }; 252 253 static const struct dce_abm_shift abm_shift = { 254 ABM_MASK_SH_LIST_DCN30(__SHIFT) 255 }; 256 257 static const struct dce_abm_mask abm_mask = { 258 ABM_MASK_SH_LIST_DCN30(_MASK) 259 }; 260 261 #define audio_regs(id)\ 262 [id] = {\ 263 AUD_COMMON_REG_LIST(id)\ 264 } 265 266 static const struct dce_audio_registers audio_regs[] = { 267 audio_regs(0), 268 audio_regs(1), 269 audio_regs(2), 270 audio_regs(3), 271 audio_regs(4), 272 audio_regs(5), 273 audio_regs(6) 274 }; 275 276 #define DCE120_AUD_COMMON_MASK_SH_LIST(mask_sh)\ 277 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX, AZALIA_ENDPOINT_REG_INDEX, mask_sh),\ 278 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA, AZALIA_ENDPOINT_REG_DATA, mask_sh),\ 279 AUD_COMMON_MASK_SH_LIST_BASE(mask_sh) 280 281 static const struct dce_audio_shift audio_shift = { 282 DCE120_AUD_COMMON_MASK_SH_LIST(__SHIFT) 283 }; 284 285 static const struct dce_audio_mask audio_mask = { 286 DCE120_AUD_COMMON_MASK_SH_LIST(_MASK) 287 }; 288 289 #define vpg_regs(id)\ 290 [id] = {\ 291 VPG_DCN31_REG_LIST(id)\ 292 } 293 294 static const struct dcn31_vpg_registers vpg_regs[] = { 295 vpg_regs(0), 296 vpg_regs(1), 297 vpg_regs(2), 298 vpg_regs(3), 299 vpg_regs(4), 300 vpg_regs(5), 301 vpg_regs(6), 302 vpg_regs(7), 303 vpg_regs(8), 304 vpg_regs(9), 305 }; 306 307 static const struct dcn31_vpg_shift vpg_shift = { 308 DCN31_VPG_MASK_SH_LIST(__SHIFT) 309 }; 310 311 static const struct dcn31_vpg_mask vpg_mask = { 312 DCN31_VPG_MASK_SH_LIST(_MASK) 313 }; 314 315 #define afmt_regs(id)\ 316 [id] = {\ 317 AFMT_DCN31_REG_LIST(id)\ 318 } 319 320 static const struct dcn31_afmt_registers afmt_regs[] = { 321 afmt_regs(0), 322 afmt_regs(1), 323 afmt_regs(2), 324 afmt_regs(3), 325 afmt_regs(4), 326 afmt_regs(5) 327 }; 328 329 static const struct dcn31_afmt_shift afmt_shift = { 330 DCN31_AFMT_MASK_SH_LIST(__SHIFT) 331 }; 332 333 static const struct dcn31_afmt_mask afmt_mask = { 334 DCN31_AFMT_MASK_SH_LIST(_MASK) 335 }; 336 337 #define apg_regs(id)\ 338 [id] = {\ 339 APG_DCN31_REG_LIST(id)\ 340 } 341 342 static const struct dcn31_apg_registers apg_regs[] = { 343 apg_regs(0), 344 apg_regs(1), 345 apg_regs(2), 346 apg_regs(3) 347 }; 348 349 static const struct dcn31_apg_shift apg_shift = { 350 DCN31_APG_MASK_SH_LIST(__SHIFT) 351 }; 352 353 static const struct dcn31_apg_mask apg_mask = { 354 DCN31_APG_MASK_SH_LIST(_MASK) 355 }; 356 357 #define stream_enc_regs(id)\ 358 [id] = {\ 359 SE_DCN314_REG_LIST(id)\ 360 } 361 362 static const struct dcn10_stream_enc_registers stream_enc_regs[] = { 363 stream_enc_regs(0), 364 stream_enc_regs(1), 365 stream_enc_regs(2), 366 stream_enc_regs(3), 367 stream_enc_regs(4) 368 }; 369 370 static const struct dcn10_stream_encoder_shift se_shift = { 371 SE_COMMON_MASK_SH_LIST_DCN314(__SHIFT) 372 }; 373 374 static const struct dcn10_stream_encoder_mask se_mask = { 375 SE_COMMON_MASK_SH_LIST_DCN314(_MASK) 376 }; 377 378 379 #define aux_regs(id)\ 380 [id] = {\ 381 DCN2_AUX_REG_LIST(id)\ 382 } 383 384 static const struct dcn10_link_enc_aux_registers link_enc_aux_regs[] = { 385 aux_regs(0), 386 aux_regs(1), 387 aux_regs(2), 388 aux_regs(3), 389 aux_regs(4) 390 }; 391 392 #define hpd_regs(id)\ 393 [id] = {\ 394 HPD_REG_LIST(id)\ 395 } 396 397 static const struct dcn10_link_enc_hpd_registers link_enc_hpd_regs[] = { 398 hpd_regs(0), 399 hpd_regs(1), 400 hpd_regs(2), 401 hpd_regs(3), 402 hpd_regs(4) 403 }; 404 405 #define link_regs(id, phyid)\ 406 [id] = {\ 407 LE_DCN31_REG_LIST(id), \ 408 UNIPHY_DCN2_REG_LIST(phyid), \ 409 } 410 411 static const struct dce110_aux_registers_shift aux_shift = { 412 DCN_AUX_MASK_SH_LIST(__SHIFT) 413 }; 414 415 static const struct dce110_aux_registers_mask aux_mask = { 416 DCN_AUX_MASK_SH_LIST(_MASK) 417 }; 418 419 static const struct dcn10_link_enc_registers link_enc_regs[] = { 420 link_regs(0, A), 421 link_regs(1, B), 422 link_regs(2, C), 423 link_regs(3, D), 424 link_regs(4, E) 425 }; 426 427 static const struct dcn10_link_enc_shift le_shift = { 428 LINK_ENCODER_MASK_SH_LIST_DCN31(__SHIFT), 429 DPCS_DCN31_MASK_SH_LIST(__SHIFT) 430 }; 431 432 static const struct dcn10_link_enc_mask le_mask = { 433 LINK_ENCODER_MASK_SH_LIST_DCN31(_MASK), 434 DPCS_DCN31_MASK_SH_LIST(_MASK) 435 }; 436 437 #define hpo_dp_stream_encoder_reg_list(id)\ 438 [id] = {\ 439 DCN3_1_HPO_DP_STREAM_ENC_REG_LIST(id)\ 440 } 441 442 static const struct dcn31_hpo_dp_stream_encoder_registers hpo_dp_stream_enc_regs[] = { 443 hpo_dp_stream_encoder_reg_list(0), 444 hpo_dp_stream_encoder_reg_list(1), 445 hpo_dp_stream_encoder_reg_list(2), 446 hpo_dp_stream_encoder_reg_list(3) 447 }; 448 449 static const struct dcn31_hpo_dp_stream_encoder_shift hpo_dp_se_shift = { 450 DCN3_1_HPO_DP_STREAM_ENC_MASK_SH_LIST(__SHIFT) 451 }; 452 453 static const struct dcn31_hpo_dp_stream_encoder_mask hpo_dp_se_mask = { 454 DCN3_1_HPO_DP_STREAM_ENC_MASK_SH_LIST(_MASK) 455 }; 456 457 458 #define hpo_dp_link_encoder_reg_list(id)\ 459 [id] = {\ 460 DCN3_1_HPO_DP_LINK_ENC_REG_LIST(id),\ 461 DCN3_1_RDPCSTX_REG_LIST(0),\ 462 DCN3_1_RDPCSTX_REG_LIST(1),\ 463 DCN3_1_RDPCSTX_REG_LIST(2),\ 464 } 465 466 static const struct dcn31_hpo_dp_link_encoder_registers hpo_dp_link_enc_regs[] = { 467 hpo_dp_link_encoder_reg_list(0), 468 hpo_dp_link_encoder_reg_list(1), 469 }; 470 471 static const struct dcn31_hpo_dp_link_encoder_shift hpo_dp_le_shift = { 472 DCN3_1_HPO_DP_LINK_ENC_MASK_SH_LIST(__SHIFT) 473 }; 474 475 static const struct dcn31_hpo_dp_link_encoder_mask hpo_dp_le_mask = { 476 DCN3_1_HPO_DP_LINK_ENC_MASK_SH_LIST(_MASK) 477 }; 478 479 #define dpp_regs(id)\ 480 [id] = {\ 481 DPP_REG_LIST_DCN30(id),\ 482 } 483 484 static const struct dcn3_dpp_registers dpp_regs[] = { 485 dpp_regs(0), 486 dpp_regs(1), 487 dpp_regs(2), 488 dpp_regs(3) 489 }; 490 491 static const struct dcn3_dpp_shift tf_shift = { 492 DPP_REG_LIST_SH_MASK_DCN30(__SHIFT) 493 }; 494 495 static const struct dcn3_dpp_mask tf_mask = { 496 DPP_REG_LIST_SH_MASK_DCN30(_MASK) 497 }; 498 499 #define opp_regs(id)\ 500 [id] = {\ 501 OPP_REG_LIST_DCN30(id),\ 502 } 503 504 static const struct dcn20_opp_registers opp_regs[] = { 505 opp_regs(0), 506 opp_regs(1), 507 opp_regs(2), 508 opp_regs(3) 509 }; 510 511 static const struct dcn20_opp_shift opp_shift = { 512 OPP_MASK_SH_LIST_DCN20(__SHIFT) 513 }; 514 515 static const struct dcn20_opp_mask opp_mask = { 516 OPP_MASK_SH_LIST_DCN20(_MASK) 517 }; 518 519 #define aux_engine_regs(id)\ 520 [id] = {\ 521 AUX_COMMON_REG_LIST0(id), \ 522 .AUXN_IMPCAL = 0, \ 523 .AUXP_IMPCAL = 0, \ 524 .AUX_RESET_MASK = DP_AUX0_AUX_CONTROL__AUX_RESET_MASK, \ 525 } 526 527 static const struct dce110_aux_registers aux_engine_regs[] = { 528 aux_engine_regs(0), 529 aux_engine_regs(1), 530 aux_engine_regs(2), 531 aux_engine_regs(3), 532 aux_engine_regs(4) 533 }; 534 535 #define dwbc_regs_dcn3(id)\ 536 [id] = {\ 537 DWBC_COMMON_REG_LIST_DCN30(id),\ 538 } 539 540 static const struct dcn30_dwbc_registers dwbc30_regs[] = { 541 dwbc_regs_dcn3(0), 542 }; 543 544 static const struct dcn30_dwbc_shift dwbc30_shift = { 545 DWBC_COMMON_MASK_SH_LIST_DCN30(__SHIFT) 546 }; 547 548 static const struct dcn30_dwbc_mask dwbc30_mask = { 549 DWBC_COMMON_MASK_SH_LIST_DCN30(_MASK) 550 }; 551 552 #define mcif_wb_regs_dcn3(id)\ 553 [id] = {\ 554 MCIF_WB_COMMON_REG_LIST_DCN30(id),\ 555 } 556 557 static const struct dcn30_mmhubbub_registers mcif_wb30_regs[] = { 558 mcif_wb_regs_dcn3(0) 559 }; 560 561 static const struct dcn30_mmhubbub_shift mcif_wb30_shift = { 562 MCIF_WB_COMMON_MASK_SH_LIST_DCN30(__SHIFT) 563 }; 564 565 static const struct dcn30_mmhubbub_mask mcif_wb30_mask = { 566 MCIF_WB_COMMON_MASK_SH_LIST_DCN30(_MASK) 567 }; 568 569 #define dsc_regsDCN314(id)\ 570 [id] = {\ 571 DSC_REG_LIST_DCN20(id)\ 572 } 573 574 static const struct dcn20_dsc_registers dsc_regs[] = { 575 dsc_regsDCN314(0), 576 dsc_regsDCN314(1), 577 dsc_regsDCN314(2), 578 dsc_regsDCN314(3) 579 }; 580 581 static const struct dcn20_dsc_shift dsc_shift = { 582 DSC_REG_LIST_SH_MASK_DCN20(__SHIFT) 583 }; 584 585 static const struct dcn20_dsc_mask dsc_mask = { 586 DSC_REG_LIST_SH_MASK_DCN20(_MASK) 587 }; 588 589 static const struct dcn30_mpc_registers mpc_regs = { 590 MPC_REG_LIST_DCN3_0(0), 591 MPC_REG_LIST_DCN3_0(1), 592 MPC_REG_LIST_DCN3_0(2), 593 MPC_REG_LIST_DCN3_0(3), 594 MPC_OUT_MUX_REG_LIST_DCN3_0(0), 595 MPC_OUT_MUX_REG_LIST_DCN3_0(1), 596 MPC_OUT_MUX_REG_LIST_DCN3_0(2), 597 MPC_OUT_MUX_REG_LIST_DCN3_0(3), 598 MPC_RMU_GLOBAL_REG_LIST_DCN3AG, 599 MPC_RMU_REG_LIST_DCN3AG(0), 600 MPC_RMU_REG_LIST_DCN3AG(1), 601 //MPC_RMU_REG_LIST_DCN3AG(2), 602 MPC_DWB_MUX_REG_LIST_DCN3_0(0), 603 }; 604 605 static const struct dcn30_mpc_shift mpc_shift = { 606 MPC_COMMON_MASK_SH_LIST_DCN30(__SHIFT) 607 }; 608 609 static const struct dcn30_mpc_mask mpc_mask = { 610 MPC_COMMON_MASK_SH_LIST_DCN30(_MASK) 611 }; 612 613 #define optc_regs(id)\ 614 [id] = {OPTC_COMMON_REG_LIST_DCN3_14(id)} 615 616 static const struct dcn_optc_registers optc_regs[] = { 617 optc_regs(0), 618 optc_regs(1), 619 optc_regs(2), 620 optc_regs(3) 621 }; 622 623 static const struct dcn_optc_shift optc_shift = { 624 OPTC_COMMON_MASK_SH_LIST_DCN3_14(__SHIFT) 625 }; 626 627 static const struct dcn_optc_mask optc_mask = { 628 OPTC_COMMON_MASK_SH_LIST_DCN3_14(_MASK) 629 }; 630 631 #define hubp_regs(id)\ 632 [id] = {\ 633 HUBP_REG_LIST_DCN30(id)\ 634 } 635 636 static const struct dcn_hubp2_registers hubp_regs[] = { 637 hubp_regs(0), 638 hubp_regs(1), 639 hubp_regs(2), 640 hubp_regs(3) 641 }; 642 643 644 static const struct dcn_hubp2_shift hubp_shift = { 645 HUBP_MASK_SH_LIST_DCN31(__SHIFT) 646 }; 647 648 static const struct dcn_hubp2_mask hubp_mask = { 649 HUBP_MASK_SH_LIST_DCN31(_MASK) 650 }; 651 static const struct dcn_hubbub_registers hubbub_reg = { 652 HUBBUB_REG_LIST_DCN31(0) 653 }; 654 655 static const struct dcn_hubbub_shift hubbub_shift = { 656 HUBBUB_MASK_SH_LIST_DCN31(__SHIFT) 657 }; 658 659 static const struct dcn_hubbub_mask hubbub_mask = { 660 HUBBUB_MASK_SH_LIST_DCN31(_MASK) 661 }; 662 663 static const struct dccg_registers dccg_regs = { 664 DCCG_REG_LIST_DCN314() 665 }; 666 667 static const struct dccg_shift dccg_shift = { 668 DCCG_MASK_SH_LIST_DCN314(__SHIFT) 669 }; 670 671 static const struct dccg_mask dccg_mask = { 672 DCCG_MASK_SH_LIST_DCN314(_MASK) 673 }; 674 675 676 #define SRII2(reg_name_pre, reg_name_post, id)\ 677 .reg_name_pre ## _ ## reg_name_post[id] = BASE(reg ## reg_name_pre \ 678 ## id ## _ ## reg_name_post ## _BASE_IDX) + \ 679 reg ## reg_name_pre ## id ## _ ## reg_name_post 680 681 682 #define HWSEQ_DCN31_REG_LIST()\ 683 SR(DCHUBBUB_GLOBAL_TIMER_CNTL), \ 684 SR(DCHUBBUB_ARB_HOSTVM_CNTL), \ 685 SR(DIO_MEM_PWR_CTRL), \ 686 SR(ODM_MEM_PWR_CTRL3), \ 687 SR(DMU_MEM_PWR_CNTL), \ 688 SR(MMHUBBUB_MEM_PWR_CNTL), \ 689 SR(DCCG_GATE_DISABLE_CNTL), \ 690 SR(DCCG_GATE_DISABLE_CNTL2), \ 691 SR(DCFCLK_CNTL),\ 692 SR(DC_MEM_GLOBAL_PWR_REQ_CNTL), \ 693 SRII(PIXEL_RATE_CNTL, OTG, 0), \ 694 SRII(PIXEL_RATE_CNTL, OTG, 1),\ 695 SRII(PIXEL_RATE_CNTL, OTG, 2),\ 696 SRII(PIXEL_RATE_CNTL, OTG, 3),\ 697 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 0),\ 698 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 1),\ 699 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 2),\ 700 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 3),\ 701 SR(MICROSECOND_TIME_BASE_DIV), \ 702 SR(MILLISECOND_TIME_BASE_DIV), \ 703 SR(DISPCLK_FREQ_CHANGE_CNTL), \ 704 SR(RBBMIF_TIMEOUT_DIS), \ 705 SR(RBBMIF_TIMEOUT_DIS_2), \ 706 SR(DCHUBBUB_CRC_CTRL), \ 707 SR(DPP_TOP0_DPP_CRC_CTRL), \ 708 SR(DPP_TOP0_DPP_CRC_VAL_B_A), \ 709 SR(DPP_TOP0_DPP_CRC_VAL_R_G), \ 710 SR(MPC_CRC_CTRL), \ 711 SR(MPC_CRC_RESULT_GB), \ 712 SR(MPC_CRC_RESULT_C), \ 713 SR(MPC_CRC_RESULT_AR), \ 714 SR(DOMAIN0_PG_CONFIG), \ 715 SR(DOMAIN1_PG_CONFIG), \ 716 SR(DOMAIN2_PG_CONFIG), \ 717 SR(DOMAIN3_PG_CONFIG), \ 718 SR(DOMAIN16_PG_CONFIG), \ 719 SR(DOMAIN17_PG_CONFIG), \ 720 SR(DOMAIN18_PG_CONFIG), \ 721 SR(DOMAIN19_PG_CONFIG), \ 722 SR(DOMAIN0_PG_STATUS), \ 723 SR(DOMAIN1_PG_STATUS), \ 724 SR(DOMAIN2_PG_STATUS), \ 725 SR(DOMAIN3_PG_STATUS), \ 726 SR(DOMAIN16_PG_STATUS), \ 727 SR(DOMAIN17_PG_STATUS), \ 728 SR(DOMAIN18_PG_STATUS), \ 729 SR(DOMAIN19_PG_STATUS), \ 730 SR(D1VGA_CONTROL), \ 731 SR(D2VGA_CONTROL), \ 732 SR(D3VGA_CONTROL), \ 733 SR(D4VGA_CONTROL), \ 734 SR(D5VGA_CONTROL), \ 735 SR(D6VGA_CONTROL), \ 736 SR(DC_IP_REQUEST_CNTL), \ 737 SR(AZALIA_AUDIO_DTO), \ 738 SR(AZALIA_CONTROLLER_CLOCK_GATING), \ 739 SR(HPO_TOP_HW_CONTROL) 740 741 static const struct dce_hwseq_registers hwseq_reg = { 742 HWSEQ_DCN31_REG_LIST() 743 }; 744 745 #define HWSEQ_DCN31_MASK_SH_LIST(mask_sh)\ 746 HWSEQ_DCN_MASK_SH_LIST(mask_sh), \ 747 HWS_SF(, DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_REFDIV, mask_sh), \ 748 HWS_SF(, DCHUBBUB_ARB_HOSTVM_CNTL, DISABLE_HOSTVM_FORCE_ALLOW_PSTATE, mask_sh), \ 749 HWS_SF(, DOMAIN0_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ 750 HWS_SF(, DOMAIN0_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ 751 HWS_SF(, DOMAIN1_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ 752 HWS_SF(, DOMAIN1_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ 753 HWS_SF(, DOMAIN2_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ 754 HWS_SF(, DOMAIN2_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ 755 HWS_SF(, DOMAIN3_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ 756 HWS_SF(, DOMAIN3_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ 757 HWS_SF(, DOMAIN16_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ 758 HWS_SF(, DOMAIN16_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ 759 HWS_SF(, DOMAIN17_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ 760 HWS_SF(, DOMAIN17_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ 761 HWS_SF(, DOMAIN18_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ 762 HWS_SF(, DOMAIN18_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ 763 HWS_SF(, DOMAIN19_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ 764 HWS_SF(, DOMAIN19_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ 765 HWS_SF(, DOMAIN0_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ 766 HWS_SF(, DOMAIN1_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ 767 HWS_SF(, DOMAIN2_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ 768 HWS_SF(, DOMAIN3_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ 769 HWS_SF(, DOMAIN16_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ 770 HWS_SF(, DOMAIN17_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ 771 HWS_SF(, DOMAIN18_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ 772 HWS_SF(, DOMAIN19_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ 773 HWS_SF(, DC_IP_REQUEST_CNTL, IP_REQUEST_EN, mask_sh), \ 774 HWS_SF(, AZALIA_AUDIO_DTO, AZALIA_AUDIO_DTO_MODULE, mask_sh), \ 775 HWS_SF(, HPO_TOP_CLOCK_CONTROL, HPO_HDMISTREAMCLK_G_GATE_DIS, mask_sh), \ 776 HWS_SF(, DMU_MEM_PWR_CNTL, DMCU_ERAM_MEM_PWR_FORCE, mask_sh), \ 777 HWS_SF(, ODM_MEM_PWR_CTRL3, ODM_MEM_UNASSIGNED_PWR_MODE, mask_sh), \ 778 HWS_SF(, ODM_MEM_PWR_CTRL3, ODM_MEM_VBLANK_PWR_MODE, mask_sh), \ 779 HWS_SF(, MMHUBBUB_MEM_PWR_CNTL, VGA_MEM_PWR_FORCE, mask_sh), \ 780 HWS_SF(, DIO_MEM_PWR_CTRL, I2C_LIGHT_SLEEP_FORCE, mask_sh), \ 781 HWS_SF(, HPO_TOP_HW_CONTROL, HPO_IO_EN, mask_sh) 782 783 static const struct dce_hwseq_shift hwseq_shift = { 784 HWSEQ_DCN31_MASK_SH_LIST(__SHIFT) 785 }; 786 787 static const struct dce_hwseq_mask hwseq_mask = { 788 HWSEQ_DCN31_MASK_SH_LIST(_MASK) 789 }; 790 #define vmid_regs(id)\ 791 [id] = {\ 792 DCN20_VMID_REG_LIST(id)\ 793 } 794 795 static const struct dcn_vmid_registers vmid_regs[] = { 796 vmid_regs(0), 797 vmid_regs(1), 798 vmid_regs(2), 799 vmid_regs(3), 800 vmid_regs(4), 801 vmid_regs(5), 802 vmid_regs(6), 803 vmid_regs(7), 804 vmid_regs(8), 805 vmid_regs(9), 806 vmid_regs(10), 807 vmid_regs(11), 808 vmid_regs(12), 809 vmid_regs(13), 810 vmid_regs(14), 811 vmid_regs(15) 812 }; 813 814 static const struct dcn20_vmid_shift vmid_shifts = { 815 DCN20_VMID_MASK_SH_LIST(__SHIFT) 816 }; 817 818 static const struct dcn20_vmid_mask vmid_masks = { 819 DCN20_VMID_MASK_SH_LIST(_MASK) 820 }; 821 822 static const struct resource_caps res_cap_dcn314 = { 823 .num_timing_generator = 4, 824 .num_opp = 4, 825 .num_video_plane = 4, 826 .num_audio = 5, 827 .num_stream_encoder = 5, 828 .num_dig_link_enc = 5, 829 .num_hpo_dp_stream_encoder = 4, 830 .num_hpo_dp_link_encoder = 2, 831 .num_pll = 5, 832 .num_dwb = 1, 833 .num_ddc = 5, 834 .num_vmid = 16, 835 .num_mpc_3dlut = 2, 836 .num_dsc = 4, 837 }; 838 839 static const struct dc_plane_cap plane_cap = { 840 .type = DC_PLANE_TYPE_DCN_UNIVERSAL, 841 .per_pixel_alpha = true, 842 843 .pixel_format_support = { 844 .argb8888 = true, 845 .nv12 = true, 846 .fp16 = true, 847 .p010 = true, 848 .ayuv = false, 849 }, 850 851 .max_upscale_factor = { 852 .argb8888 = 16000, 853 .nv12 = 16000, 854 .fp16 = 16000 855 }, 856 857 // 6:1 downscaling ratio: 1000/6 = 166.666 858 // 4:1 downscaling ratio for ARGB888 to prevent underflow during P010 playback: 1000/4 = 250 859 .max_downscale_factor = { 860 .argb8888 = 250, 861 .nv12 = 167, 862 .fp16 = 167 863 }, 864 64, 865 64 866 }; 867 868 static const struct dc_debug_options debug_defaults_drv = { 869 .disable_z10 = false, 870 .enable_z9_disable_interface = true, 871 .minimum_z8_residency_time = 2000, 872 .psr_skip_crtc_disable = true, 873 .disable_dmcu = true, 874 .force_abm_enable = false, 875 .timing_trace = false, 876 .clock_trace = true, 877 .disable_dpp_power_gate = false, 878 .disable_hubp_power_gate = false, 879 .disable_pplib_clock_request = false, 880 .pipe_split_policy = MPC_SPLIT_DYNAMIC, 881 .force_single_disp_pipe_split = false, 882 .disable_dcc = DCC_ENABLE, 883 .vsr_support = true, 884 .performance_trace = false, 885 .max_downscale_src_width = 4096,/*upto true 4k*/ 886 .disable_pplib_wm_range = false, 887 .scl_reset_length10 = true, 888 .sanity_checks = true, 889 .underflow_assert_delay_us = 0xFFFFFFFF, 890 .dwb_fi_phase = -1, // -1 = disable, 891 .dmub_command_table = true, 892 .pstate_enabled = true, 893 .use_max_lb = true, 894 .enable_mem_low_power = { 895 .bits = { 896 .vga = true, 897 .i2c = true, 898 .dmcu = false, // This is previously known to cause hang on S3 cycles if enabled 899 .dscl = true, 900 .cm = true, 901 .mpc = true, 902 .optc = true, 903 .vpg = true, 904 .afmt = true, 905 } 906 }, 907 908 .root_clock_optimization = { 909 .bits = { 910 .dpp = true, 911 .dsc = false, 912 .hdmistream = false, 913 .hdmichar = false, 914 .dpstream = false, 915 .symclk32_se = false, 916 .symclk32_le = false, 917 .symclk_fe = false, 918 .physymclk = false, 919 .dpiasymclk = false, 920 } 921 }, 922 923 .seamless_boot_odm_combine = true 924 }; 925 926 static const struct dc_debug_options debug_defaults_diags = { 927 .disable_dmcu = true, 928 .force_abm_enable = false, 929 .timing_trace = true, 930 .clock_trace = true, 931 .disable_dpp_power_gate = true, 932 .disable_hubp_power_gate = true, 933 .disable_clock_gate = true, 934 .disable_pplib_clock_request = true, 935 .disable_pplib_wm_range = true, 936 .disable_stutter = false, 937 .scl_reset_length10 = true, 938 .dwb_fi_phase = -1, // -1 = disable 939 .dmub_command_table = true, 940 .enable_tri_buf = true, 941 .use_max_lb = true 942 }; 943 944 static const struct dc_panel_config panel_config_defaults = { 945 .psr = { 946 .disable_psr = false, 947 .disallow_psrsu = false, 948 }, 949 .ilr = { 950 .optimize_edp_link_rate = true, 951 }, 952 }; 953 954 static void dcn31_dpp_destroy(struct dpp **dpp) 955 { 956 kfree(TO_DCN20_DPP(*dpp)); 957 *dpp = NULL; 958 } 959 960 static struct dpp *dcn31_dpp_create( 961 struct dc_context *ctx, 962 uint32_t inst) 963 { 964 struct dcn3_dpp *dpp = 965 kzalloc(sizeof(struct dcn3_dpp), GFP_KERNEL); 966 967 if (!dpp) 968 return NULL; 969 970 if (dpp3_construct(dpp, ctx, inst, 971 &dpp_regs[inst], &tf_shift, &tf_mask)) 972 return &dpp->base; 973 974 BREAK_TO_DEBUGGER(); 975 kfree(dpp); 976 return NULL; 977 } 978 979 static struct output_pixel_processor *dcn31_opp_create( 980 struct dc_context *ctx, uint32_t inst) 981 { 982 struct dcn20_opp *opp = 983 kzalloc(sizeof(struct dcn20_opp), GFP_KERNEL); 984 985 if (!opp) { 986 BREAK_TO_DEBUGGER(); 987 return NULL; 988 } 989 990 dcn20_opp_construct(opp, ctx, inst, 991 &opp_regs[inst], &opp_shift, &opp_mask); 992 return &opp->base; 993 } 994 995 static struct dce_aux *dcn31_aux_engine_create( 996 struct dc_context *ctx, 997 uint32_t inst) 998 { 999 struct aux_engine_dce110 *aux_engine = 1000 kzalloc(sizeof(struct aux_engine_dce110), GFP_KERNEL); 1001 1002 if (!aux_engine) 1003 return NULL; 1004 1005 dce110_aux_engine_construct(aux_engine, ctx, inst, 1006 SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD, 1007 &aux_engine_regs[inst], 1008 &aux_mask, 1009 &aux_shift, 1010 ctx->dc->caps.extended_aux_timeout_support); 1011 1012 return &aux_engine->base; 1013 } 1014 #define i2c_inst_regs(id) { I2C_HW_ENGINE_COMMON_REG_LIST_DCN30(id) } 1015 1016 static const struct dce_i2c_registers i2c_hw_regs[] = { 1017 i2c_inst_regs(1), 1018 i2c_inst_regs(2), 1019 i2c_inst_regs(3), 1020 i2c_inst_regs(4), 1021 i2c_inst_regs(5), 1022 }; 1023 1024 static const struct dce_i2c_shift i2c_shifts = { 1025 I2C_COMMON_MASK_SH_LIST_DCN30(__SHIFT) 1026 }; 1027 1028 static const struct dce_i2c_mask i2c_masks = { 1029 I2C_COMMON_MASK_SH_LIST_DCN30(_MASK) 1030 }; 1031 1032 static struct dce_i2c_hw *dcn31_i2c_hw_create( 1033 struct dc_context *ctx, 1034 uint32_t inst) 1035 { 1036 struct dce_i2c_hw *dce_i2c_hw = 1037 kzalloc(sizeof(struct dce_i2c_hw), GFP_KERNEL); 1038 1039 if (!dce_i2c_hw) 1040 return NULL; 1041 1042 dcn2_i2c_hw_construct(dce_i2c_hw, ctx, inst, 1043 &i2c_hw_regs[inst], &i2c_shifts, &i2c_masks); 1044 1045 return dce_i2c_hw; 1046 } 1047 static struct mpc *dcn31_mpc_create( 1048 struct dc_context *ctx, 1049 int num_mpcc, 1050 int num_rmu) 1051 { 1052 struct dcn30_mpc *mpc30 = kzalloc(sizeof(struct dcn30_mpc), 1053 GFP_KERNEL); 1054 1055 if (!mpc30) 1056 return NULL; 1057 1058 dcn30_mpc_construct(mpc30, ctx, 1059 &mpc_regs, 1060 &mpc_shift, 1061 &mpc_mask, 1062 num_mpcc, 1063 num_rmu); 1064 1065 return &mpc30->base; 1066 } 1067 1068 static struct hubbub *dcn31_hubbub_create(struct dc_context *ctx) 1069 { 1070 int i; 1071 1072 struct dcn20_hubbub *hubbub3 = kzalloc(sizeof(struct dcn20_hubbub), 1073 GFP_KERNEL); 1074 1075 if (!hubbub3) 1076 return NULL; 1077 1078 hubbub31_construct(hubbub3, ctx, 1079 &hubbub_reg, 1080 &hubbub_shift, 1081 &hubbub_mask, 1082 dcn3_14_ip.det_buffer_size_kbytes, 1083 dcn3_14_ip.pixel_chunk_size_kbytes, 1084 dcn3_14_ip.config_return_buffer_size_in_kbytes); 1085 1086 1087 for (i = 0; i < res_cap_dcn314.num_vmid; i++) { 1088 struct dcn20_vmid *vmid = &hubbub3->vmid[i]; 1089 1090 vmid->ctx = ctx; 1091 1092 vmid->regs = &vmid_regs[i]; 1093 vmid->shifts = &vmid_shifts; 1094 vmid->masks = &vmid_masks; 1095 } 1096 1097 return &hubbub3->base; 1098 } 1099 1100 static struct timing_generator *dcn31_timing_generator_create( 1101 struct dc_context *ctx, 1102 uint32_t instance) 1103 { 1104 struct optc *tgn10 = 1105 kzalloc(sizeof(struct optc), GFP_KERNEL); 1106 1107 if (!tgn10) 1108 return NULL; 1109 1110 tgn10->base.inst = instance; 1111 tgn10->base.ctx = ctx; 1112 1113 tgn10->tg_regs = &optc_regs[instance]; 1114 tgn10->tg_shift = &optc_shift; 1115 tgn10->tg_mask = &optc_mask; 1116 1117 dcn314_timing_generator_init(tgn10); 1118 1119 return &tgn10->base; 1120 } 1121 1122 static const struct encoder_feature_support link_enc_feature = { 1123 .max_hdmi_deep_color = COLOR_DEPTH_121212, 1124 .max_hdmi_pixel_clock = 600000, 1125 .hdmi_ycbcr420_supported = true, 1126 .dp_ycbcr420_supported = true, 1127 .fec_supported = true, 1128 .flags.bits.IS_HBR2_CAPABLE = true, 1129 .flags.bits.IS_HBR3_CAPABLE = true, 1130 .flags.bits.IS_TPS3_CAPABLE = true, 1131 .flags.bits.IS_TPS4_CAPABLE = true 1132 }; 1133 1134 static struct link_encoder *dcn31_link_encoder_create( 1135 struct dc_context *ctx, 1136 const struct encoder_init_data *enc_init_data) 1137 { 1138 struct dcn20_link_encoder *enc20 = 1139 kzalloc(sizeof(struct dcn20_link_encoder), GFP_KERNEL); 1140 1141 if (!enc20) 1142 return NULL; 1143 1144 dcn31_link_encoder_construct(enc20, 1145 enc_init_data, 1146 &link_enc_feature, 1147 &link_enc_regs[enc_init_data->transmitter], 1148 &link_enc_aux_regs[enc_init_data->channel - 1], 1149 &link_enc_hpd_regs[enc_init_data->hpd_source], 1150 &le_shift, 1151 &le_mask); 1152 1153 return &enc20->enc10.base; 1154 } 1155 1156 /* Create a minimal link encoder object not associated with a particular 1157 * physical connector. 1158 * resource_funcs.link_enc_create_minimal 1159 */ 1160 static struct link_encoder *dcn31_link_enc_create_minimal( 1161 struct dc_context *ctx, enum engine_id eng_id) 1162 { 1163 struct dcn20_link_encoder *enc20; 1164 1165 if ((eng_id - ENGINE_ID_DIGA) > ctx->dc->res_pool->res_cap->num_dig_link_enc) 1166 return NULL; 1167 1168 enc20 = kzalloc(sizeof(struct dcn20_link_encoder), GFP_KERNEL); 1169 if (!enc20) 1170 return NULL; 1171 1172 dcn31_link_encoder_construct_minimal( 1173 enc20, 1174 ctx, 1175 &link_enc_feature, 1176 &link_enc_regs[eng_id - ENGINE_ID_DIGA], 1177 eng_id); 1178 1179 return &enc20->enc10.base; 1180 } 1181 1182 static struct panel_cntl *dcn31_panel_cntl_create(const struct panel_cntl_init_data *init_data) 1183 { 1184 struct dcn31_panel_cntl *panel_cntl = 1185 kzalloc(sizeof(struct dcn31_panel_cntl), GFP_KERNEL); 1186 1187 if (!panel_cntl) 1188 return NULL; 1189 1190 dcn31_panel_cntl_construct(panel_cntl, init_data); 1191 1192 return &panel_cntl->base; 1193 } 1194 1195 static void read_dce_straps( 1196 struct dc_context *ctx, 1197 struct resource_straps *straps) 1198 { 1199 generic_reg_get(ctx, regDC_PINSTRAPS + BASE(regDC_PINSTRAPS_BASE_IDX), 1200 FN(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO), &straps->dc_pinstraps_audio); 1201 1202 } 1203 1204 static struct audio *dcn31_create_audio( 1205 struct dc_context *ctx, unsigned int inst) 1206 { 1207 return dce_audio_create(ctx, inst, 1208 &audio_regs[inst], &audio_shift, &audio_mask); 1209 } 1210 1211 static struct vpg *dcn31_vpg_create( 1212 struct dc_context *ctx, 1213 uint32_t inst) 1214 { 1215 struct dcn31_vpg *vpg31 = kzalloc(sizeof(struct dcn31_vpg), GFP_KERNEL); 1216 1217 if (!vpg31) 1218 return NULL; 1219 1220 vpg31_construct(vpg31, ctx, inst, 1221 &vpg_regs[inst], 1222 &vpg_shift, 1223 &vpg_mask); 1224 1225 return &vpg31->base; 1226 } 1227 1228 static struct afmt *dcn31_afmt_create( 1229 struct dc_context *ctx, 1230 uint32_t inst) 1231 { 1232 struct dcn31_afmt *afmt31 = kzalloc(sizeof(struct dcn31_afmt), GFP_KERNEL); 1233 1234 if (!afmt31) 1235 return NULL; 1236 1237 afmt31_construct(afmt31, ctx, inst, 1238 &afmt_regs[inst], 1239 &afmt_shift, 1240 &afmt_mask); 1241 1242 // Light sleep by default, no need to power down here 1243 1244 return &afmt31->base; 1245 } 1246 1247 static struct apg *dcn31_apg_create( 1248 struct dc_context *ctx, 1249 uint32_t inst) 1250 { 1251 struct dcn31_apg *apg31 = kzalloc(sizeof(struct dcn31_apg), GFP_KERNEL); 1252 1253 if (!apg31) 1254 return NULL; 1255 1256 apg31_construct(apg31, ctx, inst, 1257 &apg_regs[inst], 1258 &apg_shift, 1259 &apg_mask); 1260 1261 return &apg31->base; 1262 } 1263 1264 static struct stream_encoder *dcn314_stream_encoder_create( 1265 enum engine_id eng_id, 1266 struct dc_context *ctx) 1267 { 1268 struct dcn10_stream_encoder *enc1; 1269 struct vpg *vpg; 1270 struct afmt *afmt; 1271 int vpg_inst; 1272 int afmt_inst; 1273 1274 /* Mapping of VPG, AFMT, DME register blocks to DIO block instance */ 1275 if (eng_id < ENGINE_ID_DIGF) { 1276 vpg_inst = eng_id; 1277 afmt_inst = eng_id; 1278 } else 1279 return NULL; 1280 1281 enc1 = kzalloc(sizeof(struct dcn10_stream_encoder), GFP_KERNEL); 1282 vpg = dcn31_vpg_create(ctx, vpg_inst); 1283 afmt = dcn31_afmt_create(ctx, afmt_inst); 1284 1285 if (!enc1 || !vpg || !afmt) { 1286 kfree(enc1); 1287 kfree(vpg); 1288 kfree(afmt); 1289 return NULL; 1290 } 1291 1292 dcn314_dio_stream_encoder_construct(enc1, ctx, ctx->dc_bios, 1293 eng_id, vpg, afmt, 1294 &stream_enc_regs[eng_id], 1295 &se_shift, &se_mask); 1296 1297 return &enc1->base; 1298 } 1299 1300 static struct hpo_dp_stream_encoder *dcn31_hpo_dp_stream_encoder_create( 1301 enum engine_id eng_id, 1302 struct dc_context *ctx) 1303 { 1304 struct dcn31_hpo_dp_stream_encoder *hpo_dp_enc31; 1305 struct vpg *vpg; 1306 struct apg *apg; 1307 uint32_t hpo_dp_inst; 1308 uint32_t vpg_inst; 1309 uint32_t apg_inst; 1310 1311 ASSERT((eng_id >= ENGINE_ID_HPO_DP_0) && (eng_id <= ENGINE_ID_HPO_DP_3)); 1312 hpo_dp_inst = eng_id - ENGINE_ID_HPO_DP_0; 1313 1314 /* Mapping of VPG register blocks to HPO DP block instance: 1315 * VPG[6] -> HPO_DP[0] 1316 * VPG[7] -> HPO_DP[1] 1317 * VPG[8] -> HPO_DP[2] 1318 * VPG[9] -> HPO_DP[3] 1319 */ 1320 //Uses offset index 5-8, but actually maps to vpg_inst 6-9 1321 vpg_inst = hpo_dp_inst + 5; 1322 1323 /* Mapping of APG register blocks to HPO DP block instance: 1324 * APG[0] -> HPO_DP[0] 1325 * APG[1] -> HPO_DP[1] 1326 * APG[2] -> HPO_DP[2] 1327 * APG[3] -> HPO_DP[3] 1328 */ 1329 apg_inst = hpo_dp_inst; 1330 1331 /* allocate HPO stream encoder and create VPG sub-block */ 1332 hpo_dp_enc31 = kzalloc(sizeof(struct dcn31_hpo_dp_stream_encoder), GFP_KERNEL); 1333 vpg = dcn31_vpg_create(ctx, vpg_inst); 1334 apg = dcn31_apg_create(ctx, apg_inst); 1335 1336 if (!hpo_dp_enc31 || !vpg || !apg) { 1337 kfree(hpo_dp_enc31); 1338 kfree(vpg); 1339 kfree(apg); 1340 return NULL; 1341 } 1342 1343 dcn31_hpo_dp_stream_encoder_construct(hpo_dp_enc31, ctx, ctx->dc_bios, 1344 hpo_dp_inst, eng_id, vpg, apg, 1345 &hpo_dp_stream_enc_regs[hpo_dp_inst], 1346 &hpo_dp_se_shift, &hpo_dp_se_mask); 1347 1348 return &hpo_dp_enc31->base; 1349 } 1350 1351 static struct hpo_dp_link_encoder *dcn31_hpo_dp_link_encoder_create( 1352 uint8_t inst, 1353 struct dc_context *ctx) 1354 { 1355 struct dcn31_hpo_dp_link_encoder *hpo_dp_enc31; 1356 1357 /* allocate HPO link encoder */ 1358 hpo_dp_enc31 = kzalloc(sizeof(struct dcn31_hpo_dp_link_encoder), GFP_KERNEL); 1359 1360 hpo_dp_link_encoder31_construct(hpo_dp_enc31, ctx, inst, 1361 &hpo_dp_link_enc_regs[inst], 1362 &hpo_dp_le_shift, &hpo_dp_le_mask); 1363 1364 return &hpo_dp_enc31->base; 1365 } 1366 1367 static struct dce_hwseq *dcn314_hwseq_create( 1368 struct dc_context *ctx) 1369 { 1370 struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_KERNEL); 1371 1372 if (hws) { 1373 hws->ctx = ctx; 1374 hws->regs = &hwseq_reg; 1375 hws->shifts = &hwseq_shift; 1376 hws->masks = &hwseq_mask; 1377 } 1378 return hws; 1379 } 1380 static const struct resource_create_funcs res_create_funcs = { 1381 .read_dce_straps = read_dce_straps, 1382 .create_audio = dcn31_create_audio, 1383 .create_stream_encoder = dcn314_stream_encoder_create, 1384 .create_hpo_dp_stream_encoder = dcn31_hpo_dp_stream_encoder_create, 1385 .create_hpo_dp_link_encoder = dcn31_hpo_dp_link_encoder_create, 1386 .create_hwseq = dcn314_hwseq_create, 1387 }; 1388 1389 static void dcn314_resource_destruct(struct dcn314_resource_pool *pool) 1390 { 1391 unsigned int i; 1392 1393 for (i = 0; i < pool->base.stream_enc_count; i++) { 1394 if (pool->base.stream_enc[i] != NULL) { 1395 if (pool->base.stream_enc[i]->vpg != NULL) { 1396 kfree(DCN30_VPG_FROM_VPG(pool->base.stream_enc[i]->vpg)); 1397 pool->base.stream_enc[i]->vpg = NULL; 1398 } 1399 if (pool->base.stream_enc[i]->afmt != NULL) { 1400 kfree(DCN30_AFMT_FROM_AFMT(pool->base.stream_enc[i]->afmt)); 1401 pool->base.stream_enc[i]->afmt = NULL; 1402 } 1403 kfree(DCN10STRENC_FROM_STRENC(pool->base.stream_enc[i])); 1404 pool->base.stream_enc[i] = NULL; 1405 } 1406 } 1407 1408 for (i = 0; i < pool->base.hpo_dp_stream_enc_count; i++) { 1409 if (pool->base.hpo_dp_stream_enc[i] != NULL) { 1410 if (pool->base.hpo_dp_stream_enc[i]->vpg != NULL) { 1411 kfree(DCN30_VPG_FROM_VPG(pool->base.hpo_dp_stream_enc[i]->vpg)); 1412 pool->base.hpo_dp_stream_enc[i]->vpg = NULL; 1413 } 1414 if (pool->base.hpo_dp_stream_enc[i]->apg != NULL) { 1415 kfree(DCN31_APG_FROM_APG(pool->base.hpo_dp_stream_enc[i]->apg)); 1416 pool->base.hpo_dp_stream_enc[i]->apg = NULL; 1417 } 1418 kfree(DCN3_1_HPO_DP_STREAM_ENC_FROM_HPO_STREAM_ENC(pool->base.hpo_dp_stream_enc[i])); 1419 pool->base.hpo_dp_stream_enc[i] = NULL; 1420 } 1421 } 1422 1423 for (i = 0; i < pool->base.hpo_dp_link_enc_count; i++) { 1424 if (pool->base.hpo_dp_link_enc[i] != NULL) { 1425 kfree(DCN3_1_HPO_DP_LINK_ENC_FROM_HPO_LINK_ENC(pool->base.hpo_dp_link_enc[i])); 1426 pool->base.hpo_dp_link_enc[i] = NULL; 1427 } 1428 } 1429 1430 for (i = 0; i < pool->base.res_cap->num_dsc; i++) { 1431 if (pool->base.dscs[i] != NULL) 1432 dcn20_dsc_destroy(&pool->base.dscs[i]); 1433 } 1434 1435 if (pool->base.mpc != NULL) { 1436 kfree(TO_DCN20_MPC(pool->base.mpc)); 1437 pool->base.mpc = NULL; 1438 } 1439 if (pool->base.hubbub != NULL) { 1440 kfree(pool->base.hubbub); 1441 pool->base.hubbub = NULL; 1442 } 1443 for (i = 0; i < pool->base.pipe_count; i++) { 1444 if (pool->base.dpps[i] != NULL) 1445 dcn31_dpp_destroy(&pool->base.dpps[i]); 1446 1447 if (pool->base.ipps[i] != NULL) 1448 pool->base.ipps[i]->funcs->ipp_destroy(&pool->base.ipps[i]); 1449 1450 if (pool->base.hubps[i] != NULL) { 1451 kfree(TO_DCN20_HUBP(pool->base.hubps[i])); 1452 pool->base.hubps[i] = NULL; 1453 } 1454 1455 if (pool->base.irqs != NULL) 1456 dal_irq_service_destroy(&pool->base.irqs); 1457 } 1458 1459 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { 1460 if (pool->base.engines[i] != NULL) 1461 dce110_engine_destroy(&pool->base.engines[i]); 1462 if (pool->base.hw_i2cs[i] != NULL) { 1463 kfree(pool->base.hw_i2cs[i]); 1464 pool->base.hw_i2cs[i] = NULL; 1465 } 1466 if (pool->base.sw_i2cs[i] != NULL) { 1467 kfree(pool->base.sw_i2cs[i]); 1468 pool->base.sw_i2cs[i] = NULL; 1469 } 1470 } 1471 1472 for (i = 0; i < pool->base.res_cap->num_opp; i++) { 1473 if (pool->base.opps[i] != NULL) 1474 pool->base.opps[i]->funcs->opp_destroy(&pool->base.opps[i]); 1475 } 1476 1477 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { 1478 if (pool->base.timing_generators[i] != NULL) { 1479 kfree(DCN10TG_FROM_TG(pool->base.timing_generators[i])); 1480 pool->base.timing_generators[i] = NULL; 1481 } 1482 } 1483 1484 for (i = 0; i < pool->base.res_cap->num_dwb; i++) { 1485 if (pool->base.dwbc[i] != NULL) { 1486 kfree(TO_DCN30_DWBC(pool->base.dwbc[i])); 1487 pool->base.dwbc[i] = NULL; 1488 } 1489 if (pool->base.mcif_wb[i] != NULL) { 1490 kfree(TO_DCN30_MMHUBBUB(pool->base.mcif_wb[i])); 1491 pool->base.mcif_wb[i] = NULL; 1492 } 1493 } 1494 1495 for (i = 0; i < pool->base.audio_count; i++) { 1496 if (pool->base.audios[i]) 1497 dce_aud_destroy(&pool->base.audios[i]); 1498 } 1499 1500 for (i = 0; i < pool->base.clk_src_count; i++) { 1501 if (pool->base.clock_sources[i] != NULL) { 1502 dcn20_clock_source_destroy(&pool->base.clock_sources[i]); 1503 pool->base.clock_sources[i] = NULL; 1504 } 1505 } 1506 1507 for (i = 0; i < pool->base.res_cap->num_mpc_3dlut; i++) { 1508 if (pool->base.mpc_lut[i] != NULL) { 1509 dc_3dlut_func_release(pool->base.mpc_lut[i]); 1510 pool->base.mpc_lut[i] = NULL; 1511 } 1512 if (pool->base.mpc_shaper[i] != NULL) { 1513 dc_transfer_func_release(pool->base.mpc_shaper[i]); 1514 pool->base.mpc_shaper[i] = NULL; 1515 } 1516 } 1517 1518 if (pool->base.dp_clock_source != NULL) { 1519 dcn20_clock_source_destroy(&pool->base.dp_clock_source); 1520 pool->base.dp_clock_source = NULL; 1521 } 1522 1523 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { 1524 if (pool->base.multiple_abms[i] != NULL) 1525 dce_abm_destroy(&pool->base.multiple_abms[i]); 1526 } 1527 1528 if (pool->base.psr != NULL) 1529 dmub_psr_destroy(&pool->base.psr); 1530 1531 if (pool->base.dccg != NULL) 1532 dcn_dccg_destroy(&pool->base.dccg); 1533 } 1534 1535 static struct hubp *dcn31_hubp_create( 1536 struct dc_context *ctx, 1537 uint32_t inst) 1538 { 1539 struct dcn20_hubp *hubp2 = 1540 kzalloc(sizeof(struct dcn20_hubp), GFP_KERNEL); 1541 1542 if (!hubp2) 1543 return NULL; 1544 1545 if (hubp31_construct(hubp2, ctx, inst, 1546 &hubp_regs[inst], &hubp_shift, &hubp_mask)) 1547 return &hubp2->base; 1548 1549 BREAK_TO_DEBUGGER(); 1550 kfree(hubp2); 1551 return NULL; 1552 } 1553 1554 static bool dcn31_dwbc_create(struct dc_context *ctx, struct resource_pool *pool) 1555 { 1556 int i; 1557 uint32_t pipe_count = pool->res_cap->num_dwb; 1558 1559 for (i = 0; i < pipe_count; i++) { 1560 struct dcn30_dwbc *dwbc30 = kzalloc(sizeof(struct dcn30_dwbc), 1561 GFP_KERNEL); 1562 1563 if (!dwbc30) { 1564 dm_error("DC: failed to create dwbc30!\n"); 1565 return false; 1566 } 1567 1568 dcn30_dwbc_construct(dwbc30, ctx, 1569 &dwbc30_regs[i], 1570 &dwbc30_shift, 1571 &dwbc30_mask, 1572 i); 1573 1574 pool->dwbc[i] = &dwbc30->base; 1575 } 1576 return true; 1577 } 1578 1579 static bool dcn31_mmhubbub_create(struct dc_context *ctx, struct resource_pool *pool) 1580 { 1581 int i; 1582 uint32_t pipe_count = pool->res_cap->num_dwb; 1583 1584 for (i = 0; i < pipe_count; i++) { 1585 struct dcn30_mmhubbub *mcif_wb30 = kzalloc(sizeof(struct dcn30_mmhubbub), 1586 GFP_KERNEL); 1587 1588 if (!mcif_wb30) { 1589 dm_error("DC: failed to create mcif_wb30!\n"); 1590 return false; 1591 } 1592 1593 dcn30_mmhubbub_construct(mcif_wb30, ctx, 1594 &mcif_wb30_regs[i], 1595 &mcif_wb30_shift, 1596 &mcif_wb30_mask, 1597 i); 1598 1599 pool->mcif_wb[i] = &mcif_wb30->base; 1600 } 1601 return true; 1602 } 1603 1604 static struct display_stream_compressor *dcn314_dsc_create( 1605 struct dc_context *ctx, uint32_t inst) 1606 { 1607 struct dcn20_dsc *dsc = 1608 kzalloc(sizeof(struct dcn20_dsc), GFP_KERNEL); 1609 1610 if (!dsc) { 1611 BREAK_TO_DEBUGGER(); 1612 return NULL; 1613 } 1614 1615 dsc2_construct(dsc, ctx, inst, &dsc_regs[inst], &dsc_shift, &dsc_mask); 1616 return &dsc->base; 1617 } 1618 1619 static void dcn314_destroy_resource_pool(struct resource_pool **pool) 1620 { 1621 struct dcn314_resource_pool *dcn314_pool = TO_DCN314_RES_POOL(*pool); 1622 1623 dcn314_resource_destruct(dcn314_pool); 1624 kfree(dcn314_pool); 1625 *pool = NULL; 1626 } 1627 1628 static struct clock_source *dcn31_clock_source_create( 1629 struct dc_context *ctx, 1630 struct dc_bios *bios, 1631 enum clock_source_id id, 1632 const struct dce110_clk_src_regs *regs, 1633 bool dp_clk_src) 1634 { 1635 struct dce110_clk_src *clk_src = 1636 kzalloc(sizeof(struct dce110_clk_src), GFP_KERNEL); 1637 1638 if (!clk_src) 1639 return NULL; 1640 1641 if (dcn31_clk_src_construct(clk_src, ctx, bios, id, 1642 regs, &cs_shift, &cs_mask)) { 1643 clk_src->base.dp_clk_src = dp_clk_src; 1644 return &clk_src->base; 1645 } 1646 1647 BREAK_TO_DEBUGGER(); 1648 kfree(clk_src); 1649 return NULL; 1650 } 1651 1652 static int dcn314_populate_dml_pipes_from_context( 1653 struct dc *dc, struct dc_state *context, 1654 display_e2e_pipe_params_st *pipes, 1655 bool fast_validate) 1656 { 1657 int pipe_cnt; 1658 1659 DC_FP_START(); 1660 pipe_cnt = dcn314_populate_dml_pipes_from_context_fpu(dc, context, pipes, fast_validate); 1661 DC_FP_END(); 1662 1663 return pipe_cnt; 1664 } 1665 1666 static struct dc_cap_funcs cap_funcs = { 1667 .get_dcc_compression_cap = dcn20_get_dcc_compression_cap 1668 }; 1669 1670 static void dcn314_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params) 1671 { 1672 DC_FP_START(); 1673 dcn314_update_bw_bounding_box_fpu(dc, bw_params); 1674 DC_FP_END(); 1675 } 1676 1677 static void dcn314_get_panel_config_defaults(struct dc_panel_config *panel_config) 1678 { 1679 *panel_config = panel_config_defaults; 1680 } 1681 1682 static bool filter_modes_for_single_channel_workaround(struct dc *dc, 1683 struct dc_state *context) 1684 { 1685 // Filter 2K@240Hz+8K@24fps above combination timing if memory only has single dimm LPDDR 1686 if (dc->clk_mgr->bw_params->vram_type == 34 && dc->clk_mgr->bw_params->num_channels < 2) { 1687 int total_phy_pix_clk = 0; 1688 1689 for (int i = 0; i < context->stream_count; i++) 1690 if (context->res_ctx.pipe_ctx[i].stream) 1691 total_phy_pix_clk += context->res_ctx.pipe_ctx[i].stream->phy_pix_clk; 1692 1693 if (total_phy_pix_clk >= (1148928+826260)) //2K@240Hz+8K@24fps 1694 return true; 1695 } 1696 return false; 1697 } 1698 1699 bool dcn314_validate_bandwidth(struct dc *dc, 1700 struct dc_state *context, 1701 bool fast_validate) 1702 { 1703 bool out = false; 1704 1705 BW_VAL_TRACE_SETUP(); 1706 1707 int vlevel = 0; 1708 int pipe_cnt = 0; 1709 display_e2e_pipe_params_st *pipes = kzalloc(dc->res_pool->pipe_count * sizeof(display_e2e_pipe_params_st), GFP_KERNEL); 1710 DC_LOGGER_INIT(dc->ctx->logger); 1711 1712 BW_VAL_TRACE_COUNT(); 1713 1714 if (filter_modes_for_single_channel_workaround(dc, context)) 1715 goto validate_fail; 1716 1717 DC_FP_START(); 1718 // do not support self refresh only 1719 out = dcn30_internal_validate_bw(dc, context, pipes, &pipe_cnt, &vlevel, fast_validate, false); 1720 DC_FP_END(); 1721 1722 // Disable fast_validate to set min dcfclk in calculate_wm_and_dlg 1723 if (pipe_cnt == 0) 1724 fast_validate = false; 1725 1726 if (!out) 1727 goto validate_fail; 1728 1729 BW_VAL_TRACE_END_VOLTAGE_LEVEL(); 1730 1731 if (fast_validate) { 1732 BW_VAL_TRACE_SKIP(fast); 1733 goto validate_out; 1734 } 1735 1736 dc->res_pool->funcs->calculate_wm_and_dlg(dc, context, pipes, pipe_cnt, vlevel); 1737 1738 BW_VAL_TRACE_END_WATERMARKS(); 1739 1740 goto validate_out; 1741 1742 validate_fail: 1743 DC_LOG_WARNING("Mode Validation Warning: %s failed validation.\n", 1744 dml_get_status_message(context->bw_ctx.dml.vba.ValidationStatus[context->bw_ctx.dml.vba.soc.num_states])); 1745 1746 BW_VAL_TRACE_SKIP(fail); 1747 out = false; 1748 1749 validate_out: 1750 kfree(pipes); 1751 1752 BW_VAL_TRACE_FINISH(); 1753 1754 return out; 1755 } 1756 1757 static struct resource_funcs dcn314_res_pool_funcs = { 1758 .destroy = dcn314_destroy_resource_pool, 1759 .link_enc_create = dcn31_link_encoder_create, 1760 .link_enc_create_minimal = dcn31_link_enc_create_minimal, 1761 .link_encs_assign = link_enc_cfg_link_encs_assign, 1762 .link_enc_unassign = link_enc_cfg_link_enc_unassign, 1763 .panel_cntl_create = dcn31_panel_cntl_create, 1764 .validate_bandwidth = dcn314_validate_bandwidth, 1765 .calculate_wm_and_dlg = dcn31_calculate_wm_and_dlg, 1766 .update_soc_for_wm_a = dcn31_update_soc_for_wm_a, 1767 .populate_dml_pipes = dcn314_populate_dml_pipes_from_context, 1768 .acquire_idle_pipe_for_layer = dcn20_acquire_idle_pipe_for_layer, 1769 .add_stream_to_ctx = dcn30_add_stream_to_ctx, 1770 .add_dsc_to_stream_resource = dcn20_add_dsc_to_stream_resource, 1771 .remove_stream_from_ctx = dcn20_remove_stream_from_ctx, 1772 .populate_dml_writeback_from_context = dcn30_populate_dml_writeback_from_context, 1773 .set_mcif_arb_params = dcn30_set_mcif_arb_params, 1774 .find_first_free_match_stream_enc_for_link = dcn10_find_first_free_match_stream_enc_for_link, 1775 .acquire_post_bldn_3dlut = dcn30_acquire_post_bldn_3dlut, 1776 .release_post_bldn_3dlut = dcn30_release_post_bldn_3dlut, 1777 .update_bw_bounding_box = dcn314_update_bw_bounding_box, 1778 .patch_unknown_plane_state = dcn20_patch_unknown_plane_state, 1779 .get_panel_config_defaults = dcn314_get_panel_config_defaults, 1780 }; 1781 1782 static struct clock_source *dcn30_clock_source_create( 1783 struct dc_context *ctx, 1784 struct dc_bios *bios, 1785 enum clock_source_id id, 1786 const struct dce110_clk_src_regs *regs, 1787 bool dp_clk_src) 1788 { 1789 struct dce110_clk_src *clk_src = 1790 kzalloc(sizeof(struct dce110_clk_src), GFP_KERNEL); 1791 1792 if (!clk_src) 1793 return NULL; 1794 1795 if (dcn31_clk_src_construct(clk_src, ctx, bios, id, 1796 regs, &cs_shift, &cs_mask)) { 1797 clk_src->base.dp_clk_src = dp_clk_src; 1798 return &clk_src->base; 1799 } 1800 1801 BREAK_TO_DEBUGGER(); 1802 kfree(clk_src); 1803 return NULL; 1804 } 1805 1806 static bool dcn314_resource_construct( 1807 uint8_t num_virtual_links, 1808 struct dc *dc, 1809 struct dcn314_resource_pool *pool) 1810 { 1811 int i; 1812 struct dc_context *ctx = dc->ctx; 1813 struct irq_service_init_data init_data; 1814 1815 ctx->dc_bios->regs = &bios_regs; 1816 1817 pool->base.res_cap = &res_cap_dcn314; 1818 pool->base.funcs = &dcn314_res_pool_funcs; 1819 1820 /************************************************* 1821 * Resource + asic cap harcoding * 1822 *************************************************/ 1823 pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE; 1824 pool->base.pipe_count = pool->base.res_cap->num_timing_generator; 1825 pool->base.mpcc_count = pool->base.res_cap->num_timing_generator; 1826 dc->caps.max_downscale_ratio = 400; 1827 dc->caps.i2c_speed_in_khz = 100; 1828 dc->caps.i2c_speed_in_khz_hdcp = 100; 1829 dc->caps.max_cursor_size = 256; 1830 dc->caps.min_horizontal_blanking_period = 80; 1831 dc->caps.dmdata_alloc_size = 2048; 1832 dc->caps.max_slave_planes = 2; 1833 dc->caps.max_slave_yuv_planes = 2; 1834 dc->caps.max_slave_rgb_planes = 2; 1835 dc->caps.post_blend_color_processing = true; 1836 dc->caps.force_dp_tps4_for_cp2520 = true; 1837 if (dc->config.forceHBR2CP2520) 1838 dc->caps.force_dp_tps4_for_cp2520 = false; 1839 dc->caps.dp_hpo = true; 1840 dc->caps.dp_hdmi21_pcon_support = true; 1841 dc->caps.edp_dsc_support = true; 1842 dc->caps.extended_aux_timeout_support = true; 1843 dc->caps.dmcub_support = true; 1844 dc->caps.is_apu = true; 1845 dc->caps.seamless_odm = true; 1846 1847 dc->caps.zstate_support = true; 1848 1849 /* Color pipeline capabilities */ 1850 dc->caps.color.dpp.dcn_arch = 1; 1851 dc->caps.color.dpp.input_lut_shared = 0; 1852 dc->caps.color.dpp.icsc = 1; 1853 dc->caps.color.dpp.dgam_ram = 0; // must use gamma_corr 1854 dc->caps.color.dpp.dgam_rom_caps.srgb = 1; 1855 dc->caps.color.dpp.dgam_rom_caps.bt2020 = 1; 1856 dc->caps.color.dpp.dgam_rom_caps.gamma2_2 = 1; 1857 dc->caps.color.dpp.dgam_rom_caps.pq = 1; 1858 dc->caps.color.dpp.dgam_rom_caps.hlg = 1; 1859 dc->caps.color.dpp.post_csc = 1; 1860 dc->caps.color.dpp.gamma_corr = 1; 1861 dc->caps.color.dpp.dgam_rom_for_yuv = 0; 1862 1863 dc->caps.color.dpp.hw_3d_lut = 1; 1864 dc->caps.color.dpp.ogam_ram = 1; 1865 // no OGAM ROM on DCN301 1866 dc->caps.color.dpp.ogam_rom_caps.srgb = 0; 1867 dc->caps.color.dpp.ogam_rom_caps.bt2020 = 0; 1868 dc->caps.color.dpp.ogam_rom_caps.gamma2_2 = 0; 1869 dc->caps.color.dpp.ogam_rom_caps.pq = 0; 1870 dc->caps.color.dpp.ogam_rom_caps.hlg = 0; 1871 dc->caps.color.dpp.ocsc = 0; 1872 1873 dc->caps.color.mpc.gamut_remap = 1; 1874 dc->caps.color.mpc.num_3dluts = pool->base.res_cap->num_mpc_3dlut; //2 1875 dc->caps.color.mpc.ogam_ram = 1; 1876 dc->caps.color.mpc.ogam_rom_caps.srgb = 0; 1877 dc->caps.color.mpc.ogam_rom_caps.bt2020 = 0; 1878 dc->caps.color.mpc.ogam_rom_caps.gamma2_2 = 0; 1879 dc->caps.color.mpc.ogam_rom_caps.pq = 0; 1880 dc->caps.color.mpc.ogam_rom_caps.hlg = 0; 1881 dc->caps.color.mpc.ocsc = 1; 1882 1883 /* Use pipe context based otg sync logic */ 1884 dc->config.use_pipe_ctx_sync_logic = true; 1885 1886 /* read VBIOS LTTPR caps */ 1887 { 1888 if (ctx->dc_bios->funcs->get_lttpr_caps) { 1889 enum bp_result bp_query_result; 1890 uint8_t is_vbios_lttpr_enable = 0; 1891 1892 bp_query_result = ctx->dc_bios->funcs->get_lttpr_caps(ctx->dc_bios, &is_vbios_lttpr_enable); 1893 dc->caps.vbios_lttpr_enable = (bp_query_result == BP_RESULT_OK) && !!is_vbios_lttpr_enable; 1894 } 1895 1896 /* interop bit is implicit */ 1897 { 1898 dc->caps.vbios_lttpr_aware = true; 1899 } 1900 } 1901 1902 if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV) 1903 dc->debug = debug_defaults_drv; 1904 else 1905 dc->debug = debug_defaults_diags; 1906 1907 /* Disable pipe power gating */ 1908 dc->debug.disable_dpp_power_gate = true; 1909 dc->debug.disable_hubp_power_gate = true; 1910 1911 /* Disable root clock optimization */ 1912 dc->debug.root_clock_optimization.u32All = 0; 1913 1914 // Init the vm_helper 1915 if (dc->vm_helper) 1916 vm_helper_init(dc->vm_helper, 16); 1917 1918 /************************************************* 1919 * Create resources * 1920 *************************************************/ 1921 1922 /* Clock Sources for Pixel Clock*/ 1923 pool->base.clock_sources[DCN31_CLK_SRC_PLL0] = 1924 dcn30_clock_source_create(ctx, ctx->dc_bios, 1925 CLOCK_SOURCE_COMBO_PHY_PLL0, 1926 &clk_src_regs[0], false); 1927 pool->base.clock_sources[DCN31_CLK_SRC_PLL1] = 1928 dcn30_clock_source_create(ctx, ctx->dc_bios, 1929 CLOCK_SOURCE_COMBO_PHY_PLL1, 1930 &clk_src_regs[1], false); 1931 pool->base.clock_sources[DCN31_CLK_SRC_PLL2] = 1932 dcn30_clock_source_create(ctx, ctx->dc_bios, 1933 CLOCK_SOURCE_COMBO_PHY_PLL2, 1934 &clk_src_regs[2], false); 1935 pool->base.clock_sources[DCN31_CLK_SRC_PLL3] = 1936 dcn30_clock_source_create(ctx, ctx->dc_bios, 1937 CLOCK_SOURCE_COMBO_PHY_PLL3, 1938 &clk_src_regs[3], false); 1939 pool->base.clock_sources[DCN31_CLK_SRC_PLL4] = 1940 dcn30_clock_source_create(ctx, ctx->dc_bios, 1941 CLOCK_SOURCE_COMBO_PHY_PLL4, 1942 &clk_src_regs[4], false); 1943 1944 pool->base.clk_src_count = DCN30_CLK_SRC_TOTAL; 1945 1946 /* todo: not reuse phy_pll registers */ 1947 pool->base.dp_clock_source = 1948 dcn31_clock_source_create(ctx, ctx->dc_bios, 1949 CLOCK_SOURCE_ID_DP_DTO, 1950 &clk_src_regs[0], true); 1951 1952 for (i = 0; i < pool->base.clk_src_count; i++) { 1953 if (pool->base.clock_sources[i] == NULL) { 1954 dm_error("DC: failed to create clock sources!\n"); 1955 BREAK_TO_DEBUGGER(); 1956 goto create_fail; 1957 } 1958 } 1959 1960 pool->base.dccg = dccg314_create(ctx, &dccg_regs, &dccg_shift, &dccg_mask); 1961 if (pool->base.dccg == NULL) { 1962 dm_error("DC: failed to create dccg!\n"); 1963 BREAK_TO_DEBUGGER(); 1964 goto create_fail; 1965 } 1966 1967 init_data.ctx = dc->ctx; 1968 pool->base.irqs = dal_irq_service_dcn314_create(&init_data); 1969 if (!pool->base.irqs) 1970 goto create_fail; 1971 1972 /* HUBBUB */ 1973 pool->base.hubbub = dcn31_hubbub_create(ctx); 1974 if (pool->base.hubbub == NULL) { 1975 BREAK_TO_DEBUGGER(); 1976 dm_error("DC: failed to create hubbub!\n"); 1977 goto create_fail; 1978 } 1979 1980 /* HUBPs, DPPs, OPPs and TGs */ 1981 for (i = 0; i < pool->base.pipe_count; i++) { 1982 pool->base.hubps[i] = dcn31_hubp_create(ctx, i); 1983 if (pool->base.hubps[i] == NULL) { 1984 BREAK_TO_DEBUGGER(); 1985 dm_error( 1986 "DC: failed to create hubps!\n"); 1987 goto create_fail; 1988 } 1989 1990 pool->base.dpps[i] = dcn31_dpp_create(ctx, i); 1991 if (pool->base.dpps[i] == NULL) { 1992 BREAK_TO_DEBUGGER(); 1993 dm_error( 1994 "DC: failed to create dpps!\n"); 1995 goto create_fail; 1996 } 1997 } 1998 1999 for (i = 0; i < pool->base.res_cap->num_opp; i++) { 2000 pool->base.opps[i] = dcn31_opp_create(ctx, i); 2001 if (pool->base.opps[i] == NULL) { 2002 BREAK_TO_DEBUGGER(); 2003 dm_error( 2004 "DC: failed to create output pixel processor!\n"); 2005 goto create_fail; 2006 } 2007 } 2008 2009 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { 2010 pool->base.timing_generators[i] = dcn31_timing_generator_create( 2011 ctx, i); 2012 if (pool->base.timing_generators[i] == NULL) { 2013 BREAK_TO_DEBUGGER(); 2014 dm_error("DC: failed to create tg!\n"); 2015 goto create_fail; 2016 } 2017 } 2018 pool->base.timing_generator_count = i; 2019 2020 /* PSR */ 2021 pool->base.psr = dmub_psr_create(ctx); 2022 if (pool->base.psr == NULL) { 2023 dm_error("DC: failed to create psr obj!\n"); 2024 BREAK_TO_DEBUGGER(); 2025 goto create_fail; 2026 } 2027 2028 /* ABM */ 2029 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { 2030 pool->base.multiple_abms[i] = dmub_abm_create(ctx, 2031 &abm_regs[i], 2032 &abm_shift, 2033 &abm_mask); 2034 if (pool->base.multiple_abms[i] == NULL) { 2035 dm_error("DC: failed to create abm for pipe %d!\n", i); 2036 BREAK_TO_DEBUGGER(); 2037 goto create_fail; 2038 } 2039 } 2040 2041 /* MPC and DSC */ 2042 pool->base.mpc = dcn31_mpc_create(ctx, pool->base.mpcc_count, pool->base.res_cap->num_mpc_3dlut); 2043 if (pool->base.mpc == NULL) { 2044 BREAK_TO_DEBUGGER(); 2045 dm_error("DC: failed to create mpc!\n"); 2046 goto create_fail; 2047 } 2048 2049 for (i = 0; i < pool->base.res_cap->num_dsc; i++) { 2050 pool->base.dscs[i] = dcn314_dsc_create(ctx, i); 2051 if (pool->base.dscs[i] == NULL) { 2052 BREAK_TO_DEBUGGER(); 2053 dm_error("DC: failed to create display stream compressor %d!\n", i); 2054 goto create_fail; 2055 } 2056 } 2057 2058 /* DWB and MMHUBBUB */ 2059 if (!dcn31_dwbc_create(ctx, &pool->base)) { 2060 BREAK_TO_DEBUGGER(); 2061 dm_error("DC: failed to create dwbc!\n"); 2062 goto create_fail; 2063 } 2064 2065 if (!dcn31_mmhubbub_create(ctx, &pool->base)) { 2066 BREAK_TO_DEBUGGER(); 2067 dm_error("DC: failed to create mcif_wb!\n"); 2068 goto create_fail; 2069 } 2070 2071 /* AUX and I2C */ 2072 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { 2073 pool->base.engines[i] = dcn31_aux_engine_create(ctx, i); 2074 if (pool->base.engines[i] == NULL) { 2075 BREAK_TO_DEBUGGER(); 2076 dm_error( 2077 "DC:failed to create aux engine!!\n"); 2078 goto create_fail; 2079 } 2080 pool->base.hw_i2cs[i] = dcn31_i2c_hw_create(ctx, i); 2081 if (pool->base.hw_i2cs[i] == NULL) { 2082 BREAK_TO_DEBUGGER(); 2083 dm_error( 2084 "DC:failed to create hw i2c!!\n"); 2085 goto create_fail; 2086 } 2087 pool->base.sw_i2cs[i] = NULL; 2088 } 2089 2090 /* DCN314 has 4 DPIA */ 2091 pool->base.usb4_dpia_count = 4; 2092 2093 /* Audio, Stream Encoders including HPO and virtual, MPC 3D LUTs */ 2094 if (!resource_construct(num_virtual_links, dc, &pool->base, 2095 &res_create_funcs)) 2096 goto create_fail; 2097 2098 /* HW Sequencer and Plane caps */ 2099 dcn314_hw_sequencer_construct(dc); 2100 2101 dc->caps.max_planes = pool->base.pipe_count; 2102 2103 for (i = 0; i < dc->caps.max_planes; ++i) 2104 dc->caps.planes[i] = plane_cap; 2105 2106 dc->cap_funcs = cap_funcs; 2107 2108 dc->dcn_ip->max_num_dpp = dcn3_14_ip.max_num_dpp; 2109 2110 return true; 2111 2112 create_fail: 2113 2114 dcn314_resource_destruct(pool); 2115 2116 return false; 2117 } 2118 2119 struct resource_pool *dcn314_create_resource_pool( 2120 const struct dc_init_data *init_data, 2121 struct dc *dc) 2122 { 2123 struct dcn314_resource_pool *pool = 2124 kzalloc(sizeof(struct dcn314_resource_pool), GFP_KERNEL); 2125 2126 if (!pool) 2127 return NULL; 2128 2129 if (dcn314_resource_construct(init_data->num_virtual_links, dc, pool)) 2130 return &pool->base; 2131 2132 BREAK_TO_DEBUGGER(); 2133 kfree(pool); 2134 return NULL; 2135 } 2136