1 // SPDX-License-Identifier: MIT 2 /* 3 * Copyright 2022 Advanced Micro Devices, Inc. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 * 23 * Authors: AMD 24 * 25 */ 26 27 28 #include "dm_services.h" 29 #include "dc.h" 30 31 #include "dcn31/dcn31_init.h" 32 #include "dcn314/dcn314_init.h" 33 34 #include "resource.h" 35 #include "include/irq_service_interface.h" 36 #include "dcn314_resource.h" 37 38 #include "dcn20/dcn20_resource.h" 39 #include "dcn30/dcn30_resource.h" 40 #include "dcn31/dcn31_resource.h" 41 42 #include "dcn10/dcn10_ipp.h" 43 #include "dcn30/dcn30_hubbub.h" 44 #include "dcn31/dcn31_hubbub.h" 45 #include "dcn30/dcn30_mpc.h" 46 #include "dcn31/dcn31_hubp.h" 47 #include "irq/dcn31/irq_service_dcn31.h" 48 #include "irq/dcn314/irq_service_dcn314.h" 49 #include "dcn30/dcn30_dpp.h" 50 #include "dcn314/dcn314_optc.h" 51 #include "dcn20/dcn20_hwseq.h" 52 #include "dcn30/dcn30_hwseq.h" 53 #include "dce110/dce110_hw_sequencer.h" 54 #include "dcn30/dcn30_opp.h" 55 #include "dcn20/dcn20_dsc.h" 56 #include "dcn30/dcn30_vpg.h" 57 #include "dcn30/dcn30_afmt.h" 58 #include "dcn31/dcn31_dio_link_encoder.h" 59 #include "dcn314/dcn314_dio_stream_encoder.h" 60 #include "dcn31/dcn31_hpo_dp_stream_encoder.h" 61 #include "dcn31/dcn31_hpo_dp_link_encoder.h" 62 #include "dcn31/dcn31_apg.h" 63 #include "dcn31/dcn31_vpg.h" 64 #include "dcn31/dcn31_afmt.h" 65 #include "dce/dce_clock_source.h" 66 #include "dce/dce_audio.h" 67 #include "dce/dce_hwseq.h" 68 #include "clk_mgr.h" 69 #include "virtual/virtual_stream_encoder.h" 70 #include "dce110/dce110_resource.h" 71 #include "dml/display_mode_vba.h" 72 #include "dml/dcn31/dcn31_fpu.h" 73 #include "dml/dcn314/dcn314_fpu.h" 74 #include "dcn314/dcn314_dccg.h" 75 #include "dcn10/dcn10_resource.h" 76 #include "dcn31/dcn31_panel_cntl.h" 77 #include "dcn314/dcn314_hwseq.h" 78 79 #include "dcn30/dcn30_dwb.h" 80 #include "dcn30/dcn30_mmhubbub.h" 81 82 #include "dcn/dcn_3_1_4_offset.h" 83 #include "dcn/dcn_3_1_4_sh_mask.h" 84 #include "dpcs/dpcs_3_1_4_offset.h" 85 #include "dpcs/dpcs_3_1_4_sh_mask.h" 86 87 #define DCHUBBUB_DEBUG_CTRL_0__DET_DEPTH__SHIFT 0x10 88 #define DCHUBBUB_DEBUG_CTRL_0__DET_DEPTH_MASK 0x01FF0000L 89 90 #define DSCC0_DSCC_CONFIG0__ICH_RESET_AT_END_OF_LINE__SHIFT 0x0 91 #define DSCC0_DSCC_CONFIG0__ICH_RESET_AT_END_OF_LINE_MASK 0x0000000FL 92 93 #include "reg_helper.h" 94 #include "dce/dmub_abm.h" 95 #include "dce/dmub_psr.h" 96 #include "dce/dmub_replay.h" 97 #include "dce/dce_aux.h" 98 #include "dce/dce_i2c.h" 99 #include "dml/dcn314/display_mode_vba_314.h" 100 #include "vm_helper.h" 101 #include "dcn20/dcn20_vmid.h" 102 103 #include "link_enc_cfg.h" 104 105 #define DCN_BASE__INST0_SEG1 0x000000C0 106 #define DCN_BASE__INST0_SEG2 0x000034C0 107 #define DCN_BASE__INST0_SEG3 0x00009000 108 109 #define NBIO_BASE__INST0_SEG1 0x00000014 110 111 #define MAX_INSTANCE 7 112 #define MAX_SEGMENT 8 113 114 #define regBIF_BX2_BIOS_SCRATCH_2 0x003a 115 #define regBIF_BX2_BIOS_SCRATCH_2_BASE_IDX 1 116 #define regBIF_BX2_BIOS_SCRATCH_3 0x003b 117 #define regBIF_BX2_BIOS_SCRATCH_3_BASE_IDX 1 118 #define regBIF_BX2_BIOS_SCRATCH_6 0x003e 119 #define regBIF_BX2_BIOS_SCRATCH_6_BASE_IDX 1 120 121 #define DC_LOGGER_INIT(logger) 122 123 enum dcn31_clk_src_array_id { 124 DCN31_CLK_SRC_PLL0, 125 DCN31_CLK_SRC_PLL1, 126 DCN31_CLK_SRC_PLL2, 127 DCN31_CLK_SRC_PLL3, 128 DCN31_CLK_SRC_PLL4, 129 DCN30_CLK_SRC_TOTAL 130 }; 131 132 /* begin ********************* 133 * macros to expend register list macro defined in HW object header file 134 */ 135 136 /* DCN */ 137 /* TODO awful hack. fixup dcn20_dwb.h */ 138 #undef BASE_INNER 139 #define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg 140 141 #define BASE(seg) BASE_INNER(seg) 142 143 #define SR(reg_name)\ 144 .reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \ 145 reg ## reg_name 146 147 #define SRI(reg_name, block, id)\ 148 .reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 149 reg ## block ## id ## _ ## reg_name 150 151 #define SRI2(reg_name, block, id)\ 152 .reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \ 153 reg ## reg_name 154 155 #define SRIR(var_name, reg_name, block, id)\ 156 .var_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 157 reg ## block ## id ## _ ## reg_name 158 159 #define SRII(reg_name, block, id)\ 160 .reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 161 reg ## block ## id ## _ ## reg_name 162 163 #define SRII_MPC_RMU(reg_name, block, id)\ 164 .RMU##_##reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 165 reg ## block ## id ## _ ## reg_name 166 167 #define SRII_DWB(reg_name, temp_name, block, id)\ 168 .reg_name[id] = BASE(reg ## block ## id ## _ ## temp_name ## _BASE_IDX) + \ 169 reg ## block ## id ## _ ## temp_name 170 171 #define SF_DWB2(reg_name, block, id, field_name, post_fix) \ 172 .field_name = reg_name ## __ ## field_name ## post_fix 173 174 #define DCCG_SRII(reg_name, block, id)\ 175 .block ## _ ## reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 176 reg ## block ## id ## _ ## reg_name 177 178 #define VUPDATE_SRII(reg_name, block, id)\ 179 .reg_name[id] = BASE(reg ## reg_name ## _ ## block ## id ## _BASE_IDX) + \ 180 reg ## reg_name ## _ ## block ## id 181 182 /* NBIO */ 183 #define NBIO_BASE_INNER(seg) \ 184 NBIO_BASE__INST0_SEG ## seg 185 186 #define NBIO_BASE(seg) \ 187 NBIO_BASE_INNER(seg) 188 189 #define NBIO_SR(reg_name)\ 190 .reg_name = NBIO_BASE(regBIF_BX2_ ## reg_name ## _BASE_IDX) + \ 191 regBIF_BX2_ ## reg_name 192 193 /* MMHUB */ 194 #define MMHUB_BASE_INNER(seg) \ 195 MMHUB_BASE__INST0_SEG ## seg 196 197 #define MMHUB_BASE(seg) \ 198 MMHUB_BASE_INNER(seg) 199 200 #define MMHUB_SR(reg_name)\ 201 .reg_name = MMHUB_BASE(reg ## reg_name ## _BASE_IDX) + \ 202 reg ## reg_name 203 204 /* CLOCK */ 205 #define CLK_BASE_INNER(seg) \ 206 CLK_BASE__INST0_SEG ## seg 207 208 #define CLK_BASE(seg) \ 209 CLK_BASE_INNER(seg) 210 211 #define CLK_SRI(reg_name, block, inst)\ 212 .reg_name = CLK_BASE(reg ## block ## _ ## inst ## _ ## reg_name ## _BASE_IDX) + \ 213 reg ## block ## _ ## inst ## _ ## reg_name 214 215 216 static const struct bios_registers bios_regs = { 217 NBIO_SR(BIOS_SCRATCH_3), 218 NBIO_SR(BIOS_SCRATCH_6) 219 }; 220 221 #define clk_src_regs(index, pllid)\ 222 [index] = {\ 223 CS_COMMON_REG_LIST_DCN3_0(index, pllid),\ 224 } 225 226 static const struct dce110_clk_src_regs clk_src_regs[] = { 227 clk_src_regs(0, A), 228 clk_src_regs(1, B), 229 clk_src_regs(2, C), 230 clk_src_regs(3, D), 231 clk_src_regs(4, E) 232 }; 233 234 static const struct dce110_clk_src_shift cs_shift = { 235 CS_COMMON_MASK_SH_LIST_DCN3_1_4(__SHIFT) 236 }; 237 238 static const struct dce110_clk_src_mask cs_mask = { 239 CS_COMMON_MASK_SH_LIST_DCN3_1_4(_MASK) 240 }; 241 242 #define abm_regs(id)\ 243 [id] = {\ 244 ABM_DCN302_REG_LIST(id)\ 245 } 246 247 static const struct dce_abm_registers abm_regs[] = { 248 abm_regs(0), 249 abm_regs(1), 250 abm_regs(2), 251 abm_regs(3), 252 }; 253 254 static const struct dce_abm_shift abm_shift = { 255 ABM_MASK_SH_LIST_DCN30(__SHIFT) 256 }; 257 258 static const struct dce_abm_mask abm_mask = { 259 ABM_MASK_SH_LIST_DCN30(_MASK) 260 }; 261 262 #define audio_regs(id)\ 263 [id] = {\ 264 AUD_COMMON_REG_LIST(id)\ 265 } 266 267 static const struct dce_audio_registers audio_regs[] = { 268 audio_regs(0), 269 audio_regs(1), 270 audio_regs(2), 271 audio_regs(3), 272 audio_regs(4), 273 audio_regs(5), 274 audio_regs(6) 275 }; 276 277 #define DCE120_AUD_COMMON_MASK_SH_LIST(mask_sh)\ 278 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX, AZALIA_ENDPOINT_REG_INDEX, mask_sh),\ 279 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA, AZALIA_ENDPOINT_REG_DATA, mask_sh),\ 280 AUD_COMMON_MASK_SH_LIST_BASE(mask_sh) 281 282 static const struct dce_audio_shift audio_shift = { 283 DCE120_AUD_COMMON_MASK_SH_LIST(__SHIFT) 284 }; 285 286 static const struct dce_audio_mask audio_mask = { 287 DCE120_AUD_COMMON_MASK_SH_LIST(_MASK) 288 }; 289 290 #define vpg_regs(id)\ 291 [id] = {\ 292 VPG_DCN31_REG_LIST(id)\ 293 } 294 295 static const struct dcn31_vpg_registers vpg_regs[] = { 296 vpg_regs(0), 297 vpg_regs(1), 298 vpg_regs(2), 299 vpg_regs(3), 300 vpg_regs(4), 301 vpg_regs(5), 302 vpg_regs(6), 303 vpg_regs(7), 304 vpg_regs(8), 305 vpg_regs(9), 306 }; 307 308 static const struct dcn31_vpg_shift vpg_shift = { 309 DCN31_VPG_MASK_SH_LIST(__SHIFT) 310 }; 311 312 static const struct dcn31_vpg_mask vpg_mask = { 313 DCN31_VPG_MASK_SH_LIST(_MASK) 314 }; 315 316 #define afmt_regs(id)\ 317 [id] = {\ 318 AFMT_DCN31_REG_LIST(id)\ 319 } 320 321 static const struct dcn31_afmt_registers afmt_regs[] = { 322 afmt_regs(0), 323 afmt_regs(1), 324 afmt_regs(2), 325 afmt_regs(3), 326 afmt_regs(4), 327 afmt_regs(5) 328 }; 329 330 static const struct dcn31_afmt_shift afmt_shift = { 331 DCN31_AFMT_MASK_SH_LIST(__SHIFT) 332 }; 333 334 static const struct dcn31_afmt_mask afmt_mask = { 335 DCN31_AFMT_MASK_SH_LIST(_MASK) 336 }; 337 338 #define apg_regs(id)\ 339 [id] = {\ 340 APG_DCN31_REG_LIST(id)\ 341 } 342 343 static const struct dcn31_apg_registers apg_regs[] = { 344 apg_regs(0), 345 apg_regs(1), 346 apg_regs(2), 347 apg_regs(3) 348 }; 349 350 static const struct dcn31_apg_shift apg_shift = { 351 DCN31_APG_MASK_SH_LIST(__SHIFT) 352 }; 353 354 static const struct dcn31_apg_mask apg_mask = { 355 DCN31_APG_MASK_SH_LIST(_MASK) 356 }; 357 358 #define stream_enc_regs(id)\ 359 [id] = {\ 360 SE_DCN314_REG_LIST(id)\ 361 } 362 363 static const struct dcn10_stream_enc_registers stream_enc_regs[] = { 364 stream_enc_regs(0), 365 stream_enc_regs(1), 366 stream_enc_regs(2), 367 stream_enc_regs(3), 368 stream_enc_regs(4) 369 }; 370 371 static const struct dcn10_stream_encoder_shift se_shift = { 372 SE_COMMON_MASK_SH_LIST_DCN314(__SHIFT) 373 }; 374 375 static const struct dcn10_stream_encoder_mask se_mask = { 376 SE_COMMON_MASK_SH_LIST_DCN314(_MASK) 377 }; 378 379 380 #define aux_regs(id)\ 381 [id] = {\ 382 DCN2_AUX_REG_LIST(id)\ 383 } 384 385 static const struct dcn10_link_enc_aux_registers link_enc_aux_regs[] = { 386 aux_regs(0), 387 aux_regs(1), 388 aux_regs(2), 389 aux_regs(3), 390 aux_regs(4) 391 }; 392 393 #define hpd_regs(id)\ 394 [id] = {\ 395 HPD_REG_LIST(id)\ 396 } 397 398 static const struct dcn10_link_enc_hpd_registers link_enc_hpd_regs[] = { 399 hpd_regs(0), 400 hpd_regs(1), 401 hpd_regs(2), 402 hpd_regs(3), 403 hpd_regs(4) 404 }; 405 406 #define link_regs(id, phyid)\ 407 [id] = {\ 408 LE_DCN31_REG_LIST(id), \ 409 UNIPHY_DCN2_REG_LIST(phyid), \ 410 } 411 412 static const struct dce110_aux_registers_shift aux_shift = { 413 DCN_AUX_MASK_SH_LIST(__SHIFT) 414 }; 415 416 static const struct dce110_aux_registers_mask aux_mask = { 417 DCN_AUX_MASK_SH_LIST(_MASK) 418 }; 419 420 static const struct dcn10_link_enc_registers link_enc_regs[] = { 421 link_regs(0, A), 422 link_regs(1, B), 423 link_regs(2, C), 424 link_regs(3, D), 425 link_regs(4, E) 426 }; 427 428 static const struct dcn10_link_enc_shift le_shift = { 429 LINK_ENCODER_MASK_SH_LIST_DCN31(__SHIFT), 430 DPCS_DCN31_MASK_SH_LIST(__SHIFT) 431 }; 432 433 static const struct dcn10_link_enc_mask le_mask = { 434 LINK_ENCODER_MASK_SH_LIST_DCN31(_MASK), 435 DPCS_DCN31_MASK_SH_LIST(_MASK) 436 }; 437 438 #define hpo_dp_stream_encoder_reg_list(id)\ 439 [id] = {\ 440 DCN3_1_HPO_DP_STREAM_ENC_REG_LIST(id)\ 441 } 442 443 static const struct dcn31_hpo_dp_stream_encoder_registers hpo_dp_stream_enc_regs[] = { 444 hpo_dp_stream_encoder_reg_list(0), 445 hpo_dp_stream_encoder_reg_list(1), 446 hpo_dp_stream_encoder_reg_list(2), 447 hpo_dp_stream_encoder_reg_list(3) 448 }; 449 450 static const struct dcn31_hpo_dp_stream_encoder_shift hpo_dp_se_shift = { 451 DCN3_1_HPO_DP_STREAM_ENC_MASK_SH_LIST(__SHIFT) 452 }; 453 454 static const struct dcn31_hpo_dp_stream_encoder_mask hpo_dp_se_mask = { 455 DCN3_1_HPO_DP_STREAM_ENC_MASK_SH_LIST(_MASK) 456 }; 457 458 459 #define hpo_dp_link_encoder_reg_list(id)\ 460 [id] = {\ 461 DCN3_1_HPO_DP_LINK_ENC_REG_LIST(id),\ 462 DCN3_1_RDPCSTX_REG_LIST(0),\ 463 DCN3_1_RDPCSTX_REG_LIST(1),\ 464 DCN3_1_RDPCSTX_REG_LIST(2),\ 465 } 466 467 static const struct dcn31_hpo_dp_link_encoder_registers hpo_dp_link_enc_regs[] = { 468 hpo_dp_link_encoder_reg_list(0), 469 hpo_dp_link_encoder_reg_list(1), 470 }; 471 472 static const struct dcn31_hpo_dp_link_encoder_shift hpo_dp_le_shift = { 473 DCN3_1_HPO_DP_LINK_ENC_MASK_SH_LIST(__SHIFT) 474 }; 475 476 static const struct dcn31_hpo_dp_link_encoder_mask hpo_dp_le_mask = { 477 DCN3_1_HPO_DP_LINK_ENC_MASK_SH_LIST(_MASK) 478 }; 479 480 #define dpp_regs(id)\ 481 [id] = {\ 482 DPP_REG_LIST_DCN30(id),\ 483 } 484 485 static const struct dcn3_dpp_registers dpp_regs[] = { 486 dpp_regs(0), 487 dpp_regs(1), 488 dpp_regs(2), 489 dpp_regs(3) 490 }; 491 492 static const struct dcn3_dpp_shift tf_shift = { 493 DPP_REG_LIST_SH_MASK_DCN30(__SHIFT) 494 }; 495 496 static const struct dcn3_dpp_mask tf_mask = { 497 DPP_REG_LIST_SH_MASK_DCN30(_MASK) 498 }; 499 500 #define opp_regs(id)\ 501 [id] = {\ 502 OPP_REG_LIST_DCN30(id),\ 503 } 504 505 static const struct dcn20_opp_registers opp_regs[] = { 506 opp_regs(0), 507 opp_regs(1), 508 opp_regs(2), 509 opp_regs(3) 510 }; 511 512 static const struct dcn20_opp_shift opp_shift = { 513 OPP_MASK_SH_LIST_DCN20(__SHIFT) 514 }; 515 516 static const struct dcn20_opp_mask opp_mask = { 517 OPP_MASK_SH_LIST_DCN20(_MASK) 518 }; 519 520 #define aux_engine_regs(id)\ 521 [id] = {\ 522 AUX_COMMON_REG_LIST0(id), \ 523 .AUXN_IMPCAL = 0, \ 524 .AUXP_IMPCAL = 0, \ 525 .AUX_RESET_MASK = DP_AUX0_AUX_CONTROL__AUX_RESET_MASK, \ 526 } 527 528 static const struct dce110_aux_registers aux_engine_regs[] = { 529 aux_engine_regs(0), 530 aux_engine_regs(1), 531 aux_engine_regs(2), 532 aux_engine_regs(3), 533 aux_engine_regs(4) 534 }; 535 536 #define dwbc_regs_dcn3(id)\ 537 [id] = {\ 538 DWBC_COMMON_REG_LIST_DCN30(id),\ 539 } 540 541 static const struct dcn30_dwbc_registers dwbc30_regs[] = { 542 dwbc_regs_dcn3(0), 543 }; 544 545 static const struct dcn30_dwbc_shift dwbc30_shift = { 546 DWBC_COMMON_MASK_SH_LIST_DCN30(__SHIFT) 547 }; 548 549 static const struct dcn30_dwbc_mask dwbc30_mask = { 550 DWBC_COMMON_MASK_SH_LIST_DCN30(_MASK) 551 }; 552 553 #define mcif_wb_regs_dcn3(id)\ 554 [id] = {\ 555 MCIF_WB_COMMON_REG_LIST_DCN30(id),\ 556 } 557 558 static const struct dcn30_mmhubbub_registers mcif_wb30_regs[] = { 559 mcif_wb_regs_dcn3(0) 560 }; 561 562 static const struct dcn30_mmhubbub_shift mcif_wb30_shift = { 563 MCIF_WB_COMMON_MASK_SH_LIST_DCN30(__SHIFT) 564 }; 565 566 static const struct dcn30_mmhubbub_mask mcif_wb30_mask = { 567 MCIF_WB_COMMON_MASK_SH_LIST_DCN30(_MASK) 568 }; 569 570 #define dsc_regsDCN314(id)\ 571 [id] = {\ 572 DSC_REG_LIST_DCN20(id)\ 573 } 574 575 static const struct dcn20_dsc_registers dsc_regs[] = { 576 dsc_regsDCN314(0), 577 dsc_regsDCN314(1), 578 dsc_regsDCN314(2), 579 dsc_regsDCN314(3) 580 }; 581 582 static const struct dcn20_dsc_shift dsc_shift = { 583 DSC_REG_LIST_SH_MASK_DCN20(__SHIFT) 584 }; 585 586 static const struct dcn20_dsc_mask dsc_mask = { 587 DSC_REG_LIST_SH_MASK_DCN20(_MASK) 588 }; 589 590 static const struct dcn30_mpc_registers mpc_regs = { 591 MPC_REG_LIST_DCN3_0(0), 592 MPC_REG_LIST_DCN3_0(1), 593 MPC_REG_LIST_DCN3_0(2), 594 MPC_REG_LIST_DCN3_0(3), 595 MPC_OUT_MUX_REG_LIST_DCN3_0(0), 596 MPC_OUT_MUX_REG_LIST_DCN3_0(1), 597 MPC_OUT_MUX_REG_LIST_DCN3_0(2), 598 MPC_OUT_MUX_REG_LIST_DCN3_0(3), 599 MPC_RMU_GLOBAL_REG_LIST_DCN3AG, 600 MPC_RMU_REG_LIST_DCN3AG(0), 601 MPC_RMU_REG_LIST_DCN3AG(1), 602 //MPC_RMU_REG_LIST_DCN3AG(2), 603 MPC_DWB_MUX_REG_LIST_DCN3_0(0), 604 }; 605 606 static const struct dcn30_mpc_shift mpc_shift = { 607 MPC_COMMON_MASK_SH_LIST_DCN30(__SHIFT) 608 }; 609 610 static const struct dcn30_mpc_mask mpc_mask = { 611 MPC_COMMON_MASK_SH_LIST_DCN30(_MASK) 612 }; 613 614 #define optc_regs(id)\ 615 [id] = {OPTC_COMMON_REG_LIST_DCN3_14(id)} 616 617 static const struct dcn_optc_registers optc_regs[] = { 618 optc_regs(0), 619 optc_regs(1), 620 optc_regs(2), 621 optc_regs(3) 622 }; 623 624 static const struct dcn_optc_shift optc_shift = { 625 OPTC_COMMON_MASK_SH_LIST_DCN3_14(__SHIFT) 626 }; 627 628 static const struct dcn_optc_mask optc_mask = { 629 OPTC_COMMON_MASK_SH_LIST_DCN3_14(_MASK) 630 }; 631 632 #define hubp_regs(id)\ 633 [id] = {\ 634 HUBP_REG_LIST_DCN30(id)\ 635 } 636 637 static const struct dcn_hubp2_registers hubp_regs[] = { 638 hubp_regs(0), 639 hubp_regs(1), 640 hubp_regs(2), 641 hubp_regs(3) 642 }; 643 644 645 static const struct dcn_hubp2_shift hubp_shift = { 646 HUBP_MASK_SH_LIST_DCN31(__SHIFT) 647 }; 648 649 static const struct dcn_hubp2_mask hubp_mask = { 650 HUBP_MASK_SH_LIST_DCN31(_MASK) 651 }; 652 static const struct dcn_hubbub_registers hubbub_reg = { 653 HUBBUB_REG_LIST_DCN31(0) 654 }; 655 656 static const struct dcn_hubbub_shift hubbub_shift = { 657 HUBBUB_MASK_SH_LIST_DCN31(__SHIFT) 658 }; 659 660 static const struct dcn_hubbub_mask hubbub_mask = { 661 HUBBUB_MASK_SH_LIST_DCN31(_MASK) 662 }; 663 664 static const struct dccg_registers dccg_regs = { 665 DCCG_REG_LIST_DCN314() 666 }; 667 668 static const struct dccg_shift dccg_shift = { 669 DCCG_MASK_SH_LIST_DCN314(__SHIFT) 670 }; 671 672 static const struct dccg_mask dccg_mask = { 673 DCCG_MASK_SH_LIST_DCN314(_MASK) 674 }; 675 676 677 #define SRII2(reg_name_pre, reg_name_post, id)\ 678 .reg_name_pre ## _ ## reg_name_post[id] = BASE(reg ## reg_name_pre \ 679 ## id ## _ ## reg_name_post ## _BASE_IDX) + \ 680 reg ## reg_name_pre ## id ## _ ## reg_name_post 681 682 683 #define HWSEQ_DCN31_REG_LIST()\ 684 SR(DCHUBBUB_GLOBAL_TIMER_CNTL), \ 685 SR(DCHUBBUB_ARB_HOSTVM_CNTL), \ 686 SR(DIO_MEM_PWR_CTRL), \ 687 SR(ODM_MEM_PWR_CTRL3), \ 688 SR(DMU_MEM_PWR_CNTL), \ 689 SR(MMHUBBUB_MEM_PWR_CNTL), \ 690 SR(DCCG_GATE_DISABLE_CNTL), \ 691 SR(DCCG_GATE_DISABLE_CNTL2), \ 692 SR(DCFCLK_CNTL),\ 693 SR(DC_MEM_GLOBAL_PWR_REQ_CNTL), \ 694 SRII(PIXEL_RATE_CNTL, OTG, 0), \ 695 SRII(PIXEL_RATE_CNTL, OTG, 1),\ 696 SRII(PIXEL_RATE_CNTL, OTG, 2),\ 697 SRII(PIXEL_RATE_CNTL, OTG, 3),\ 698 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 0),\ 699 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 1),\ 700 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 2),\ 701 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 3),\ 702 SR(MICROSECOND_TIME_BASE_DIV), \ 703 SR(MILLISECOND_TIME_BASE_DIV), \ 704 SR(DISPCLK_FREQ_CHANGE_CNTL), \ 705 SR(RBBMIF_TIMEOUT_DIS), \ 706 SR(RBBMIF_TIMEOUT_DIS_2), \ 707 SR(DCHUBBUB_CRC_CTRL), \ 708 SR(DPP_TOP0_DPP_CRC_CTRL), \ 709 SR(DPP_TOP0_DPP_CRC_VAL_B_A), \ 710 SR(DPP_TOP0_DPP_CRC_VAL_R_G), \ 711 SR(MPC_CRC_CTRL), \ 712 SR(MPC_CRC_RESULT_GB), \ 713 SR(MPC_CRC_RESULT_C), \ 714 SR(MPC_CRC_RESULT_AR), \ 715 SR(DOMAIN0_PG_CONFIG), \ 716 SR(DOMAIN1_PG_CONFIG), \ 717 SR(DOMAIN2_PG_CONFIG), \ 718 SR(DOMAIN3_PG_CONFIG), \ 719 SR(DOMAIN16_PG_CONFIG), \ 720 SR(DOMAIN17_PG_CONFIG), \ 721 SR(DOMAIN18_PG_CONFIG), \ 722 SR(DOMAIN19_PG_CONFIG), \ 723 SR(DOMAIN0_PG_STATUS), \ 724 SR(DOMAIN1_PG_STATUS), \ 725 SR(DOMAIN2_PG_STATUS), \ 726 SR(DOMAIN3_PG_STATUS), \ 727 SR(DOMAIN16_PG_STATUS), \ 728 SR(DOMAIN17_PG_STATUS), \ 729 SR(DOMAIN18_PG_STATUS), \ 730 SR(DOMAIN19_PG_STATUS), \ 731 SR(D1VGA_CONTROL), \ 732 SR(D2VGA_CONTROL), \ 733 SR(D3VGA_CONTROL), \ 734 SR(D4VGA_CONTROL), \ 735 SR(D5VGA_CONTROL), \ 736 SR(D6VGA_CONTROL), \ 737 SR(DC_IP_REQUEST_CNTL), \ 738 SR(AZALIA_AUDIO_DTO), \ 739 SR(AZALIA_CONTROLLER_CLOCK_GATING), \ 740 SR(HPO_TOP_HW_CONTROL) 741 742 static const struct dce_hwseq_registers hwseq_reg = { 743 HWSEQ_DCN31_REG_LIST() 744 }; 745 746 #define HWSEQ_DCN31_MASK_SH_LIST(mask_sh)\ 747 HWSEQ_DCN_MASK_SH_LIST(mask_sh), \ 748 HWS_SF(, DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_REFDIV, mask_sh), \ 749 HWS_SF(, DCHUBBUB_ARB_HOSTVM_CNTL, DISABLE_HOSTVM_FORCE_ALLOW_PSTATE, mask_sh), \ 750 HWS_SF(, DOMAIN0_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ 751 HWS_SF(, DOMAIN0_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ 752 HWS_SF(, DOMAIN1_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ 753 HWS_SF(, DOMAIN1_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ 754 HWS_SF(, DOMAIN2_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ 755 HWS_SF(, DOMAIN2_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ 756 HWS_SF(, DOMAIN3_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ 757 HWS_SF(, DOMAIN3_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ 758 HWS_SF(, DOMAIN16_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ 759 HWS_SF(, DOMAIN16_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ 760 HWS_SF(, DOMAIN17_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ 761 HWS_SF(, DOMAIN17_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ 762 HWS_SF(, DOMAIN18_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ 763 HWS_SF(, DOMAIN18_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ 764 HWS_SF(, DOMAIN19_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ 765 HWS_SF(, DOMAIN19_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ 766 HWS_SF(, DOMAIN0_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ 767 HWS_SF(, DOMAIN1_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ 768 HWS_SF(, DOMAIN2_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ 769 HWS_SF(, DOMAIN3_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ 770 HWS_SF(, DOMAIN16_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ 771 HWS_SF(, DOMAIN17_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ 772 HWS_SF(, DOMAIN18_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ 773 HWS_SF(, DOMAIN19_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ 774 HWS_SF(, DC_IP_REQUEST_CNTL, IP_REQUEST_EN, mask_sh), \ 775 HWS_SF(, AZALIA_AUDIO_DTO, AZALIA_AUDIO_DTO_MODULE, mask_sh), \ 776 HWS_SF(, HPO_TOP_CLOCK_CONTROL, HPO_HDMISTREAMCLK_G_GATE_DIS, mask_sh), \ 777 HWS_SF(, DMU_MEM_PWR_CNTL, DMCU_ERAM_MEM_PWR_FORCE, mask_sh), \ 778 HWS_SF(, ODM_MEM_PWR_CTRL3, ODM_MEM_UNASSIGNED_PWR_MODE, mask_sh), \ 779 HWS_SF(, ODM_MEM_PWR_CTRL3, ODM_MEM_VBLANK_PWR_MODE, mask_sh), \ 780 HWS_SF(, MMHUBBUB_MEM_PWR_CNTL, VGA_MEM_PWR_FORCE, mask_sh), \ 781 HWS_SF(, DIO_MEM_PWR_CTRL, I2C_LIGHT_SLEEP_FORCE, mask_sh), \ 782 HWS_SF(, HPO_TOP_HW_CONTROL, HPO_IO_EN, mask_sh) 783 784 static const struct dce_hwseq_shift hwseq_shift = { 785 HWSEQ_DCN31_MASK_SH_LIST(__SHIFT) 786 }; 787 788 static const struct dce_hwseq_mask hwseq_mask = { 789 HWSEQ_DCN31_MASK_SH_LIST(_MASK) 790 }; 791 #define vmid_regs(id)\ 792 [id] = {\ 793 DCN20_VMID_REG_LIST(id)\ 794 } 795 796 static const struct dcn_vmid_registers vmid_regs[] = { 797 vmid_regs(0), 798 vmid_regs(1), 799 vmid_regs(2), 800 vmid_regs(3), 801 vmid_regs(4), 802 vmid_regs(5), 803 vmid_regs(6), 804 vmid_regs(7), 805 vmid_regs(8), 806 vmid_regs(9), 807 vmid_regs(10), 808 vmid_regs(11), 809 vmid_regs(12), 810 vmid_regs(13), 811 vmid_regs(14), 812 vmid_regs(15) 813 }; 814 815 static const struct dcn20_vmid_shift vmid_shifts = { 816 DCN20_VMID_MASK_SH_LIST(__SHIFT) 817 }; 818 819 static const struct dcn20_vmid_mask vmid_masks = { 820 DCN20_VMID_MASK_SH_LIST(_MASK) 821 }; 822 823 static const struct resource_caps res_cap_dcn314 = { 824 .num_timing_generator = 4, 825 .num_opp = 4, 826 .num_video_plane = 4, 827 .num_audio = 5, 828 .num_stream_encoder = 5, 829 .num_dig_link_enc = 5, 830 .num_hpo_dp_stream_encoder = 4, 831 .num_hpo_dp_link_encoder = 2, 832 .num_pll = 5, 833 .num_dwb = 1, 834 .num_ddc = 5, 835 .num_vmid = 16, 836 .num_mpc_3dlut = 2, 837 .num_dsc = 4, 838 }; 839 840 static const struct dc_plane_cap plane_cap = { 841 .type = DC_PLANE_TYPE_DCN_UNIVERSAL, 842 .per_pixel_alpha = true, 843 844 .pixel_format_support = { 845 .argb8888 = true, 846 .nv12 = true, 847 .fp16 = true, 848 .p010 = true, 849 .ayuv = false, 850 }, 851 852 .max_upscale_factor = { 853 .argb8888 = 16000, 854 .nv12 = 16000, 855 .fp16 = 16000 856 }, 857 858 // 6:1 downscaling ratio: 1000/6 = 166.666 859 // 4:1 downscaling ratio for ARGB888 to prevent underflow during P010 playback: 1000/4 = 250 860 .max_downscale_factor = { 861 .argb8888 = 250, 862 .nv12 = 167, 863 .fp16 = 167 864 }, 865 64, 866 64 867 }; 868 869 static const struct dc_debug_options debug_defaults_drv = { 870 .disable_z10 = false, 871 .enable_z9_disable_interface = true, 872 .minimum_z8_residency_time = 2000, 873 .psr_skip_crtc_disable = true, 874 .replay_skip_crtc_disabled = true, 875 .disable_dmcu = true, 876 .force_abm_enable = false, 877 .timing_trace = false, 878 .clock_trace = true, 879 .disable_dpp_power_gate = false, 880 .disable_hubp_power_gate = false, 881 .disable_pplib_clock_request = false, 882 .pipe_split_policy = MPC_SPLIT_DYNAMIC, 883 .force_single_disp_pipe_split = false, 884 .disable_dcc = DCC_ENABLE, 885 .vsr_support = true, 886 .performance_trace = false, 887 .max_downscale_src_width = 4096,/*upto true 4k*/ 888 .disable_pplib_wm_range = false, 889 .scl_reset_length10 = true, 890 .sanity_checks = true, 891 .underflow_assert_delay_us = 0xFFFFFFFF, 892 .dwb_fi_phase = -1, // -1 = disable, 893 .dmub_command_table = true, 894 .pstate_enabled = true, 895 .use_max_lb = true, 896 .enable_mem_low_power = { 897 .bits = { 898 .vga = true, 899 .i2c = true, 900 .dmcu = false, // This is previously known to cause hang on S3 cycles if enabled 901 .dscl = true, 902 .cm = true, 903 .mpc = true, 904 .optc = true, 905 .vpg = true, 906 .afmt = true, 907 } 908 }, 909 910 .root_clock_optimization = { 911 .bits = { 912 .dpp = true, 913 .dsc = true, 914 .hdmistream = true, 915 .hdmichar = true, 916 .dpstream = true, 917 .symclk32_se = true, 918 .symclk32_le = true, 919 .symclk_fe = true, 920 .physymclk = true, 921 .dpiasymclk = true, 922 } 923 }, 924 925 .seamless_boot_odm_combine = true 926 }; 927 928 static const struct dc_debug_options debug_defaults_diags = { 929 .disable_dmcu = true, 930 .force_abm_enable = false, 931 .timing_trace = true, 932 .clock_trace = true, 933 .disable_dpp_power_gate = true, 934 .disable_hubp_power_gate = true, 935 .disable_clock_gate = true, 936 .disable_pplib_clock_request = true, 937 .disable_pplib_wm_range = true, 938 .disable_stutter = false, 939 .scl_reset_length10 = true, 940 .dwb_fi_phase = -1, // -1 = disable 941 .dmub_command_table = true, 942 .enable_tri_buf = true, 943 .use_max_lb = true 944 }; 945 946 static const struct dc_panel_config panel_config_defaults = { 947 .psr = { 948 .disable_psr = false, 949 .disallow_psrsu = false, 950 .disallow_replay = false, 951 }, 952 .ilr = { 953 .optimize_edp_link_rate = true, 954 }, 955 }; 956 957 static void dcn31_dpp_destroy(struct dpp **dpp) 958 { 959 kfree(TO_DCN20_DPP(*dpp)); 960 *dpp = NULL; 961 } 962 963 static struct dpp *dcn31_dpp_create( 964 struct dc_context *ctx, 965 uint32_t inst) 966 { 967 struct dcn3_dpp *dpp = 968 kzalloc(sizeof(struct dcn3_dpp), GFP_KERNEL); 969 970 if (!dpp) 971 return NULL; 972 973 if (dpp3_construct(dpp, ctx, inst, 974 &dpp_regs[inst], &tf_shift, &tf_mask)) 975 return &dpp->base; 976 977 BREAK_TO_DEBUGGER(); 978 kfree(dpp); 979 return NULL; 980 } 981 982 static struct output_pixel_processor *dcn31_opp_create( 983 struct dc_context *ctx, uint32_t inst) 984 { 985 struct dcn20_opp *opp = 986 kzalloc(sizeof(struct dcn20_opp), GFP_KERNEL); 987 988 if (!opp) { 989 BREAK_TO_DEBUGGER(); 990 return NULL; 991 } 992 993 dcn20_opp_construct(opp, ctx, inst, 994 &opp_regs[inst], &opp_shift, &opp_mask); 995 return &opp->base; 996 } 997 998 static struct dce_aux *dcn31_aux_engine_create( 999 struct dc_context *ctx, 1000 uint32_t inst) 1001 { 1002 struct aux_engine_dce110 *aux_engine = 1003 kzalloc(sizeof(struct aux_engine_dce110), GFP_KERNEL); 1004 1005 if (!aux_engine) 1006 return NULL; 1007 1008 dce110_aux_engine_construct(aux_engine, ctx, inst, 1009 SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD, 1010 &aux_engine_regs[inst], 1011 &aux_mask, 1012 &aux_shift, 1013 ctx->dc->caps.extended_aux_timeout_support); 1014 1015 return &aux_engine->base; 1016 } 1017 #define i2c_inst_regs(id) { I2C_HW_ENGINE_COMMON_REG_LIST_DCN30(id) } 1018 1019 static const struct dce_i2c_registers i2c_hw_regs[] = { 1020 i2c_inst_regs(1), 1021 i2c_inst_regs(2), 1022 i2c_inst_regs(3), 1023 i2c_inst_regs(4), 1024 i2c_inst_regs(5), 1025 }; 1026 1027 static const struct dce_i2c_shift i2c_shifts = { 1028 I2C_COMMON_MASK_SH_LIST_DCN30(__SHIFT) 1029 }; 1030 1031 static const struct dce_i2c_mask i2c_masks = { 1032 I2C_COMMON_MASK_SH_LIST_DCN30(_MASK) 1033 }; 1034 1035 static struct dce_i2c_hw *dcn31_i2c_hw_create( 1036 struct dc_context *ctx, 1037 uint32_t inst) 1038 { 1039 struct dce_i2c_hw *dce_i2c_hw = 1040 kzalloc(sizeof(struct dce_i2c_hw), GFP_KERNEL); 1041 1042 if (!dce_i2c_hw) 1043 return NULL; 1044 1045 dcn2_i2c_hw_construct(dce_i2c_hw, ctx, inst, 1046 &i2c_hw_regs[inst], &i2c_shifts, &i2c_masks); 1047 1048 return dce_i2c_hw; 1049 } 1050 static struct mpc *dcn31_mpc_create( 1051 struct dc_context *ctx, 1052 int num_mpcc, 1053 int num_rmu) 1054 { 1055 struct dcn30_mpc *mpc30 = kzalloc(sizeof(struct dcn30_mpc), 1056 GFP_KERNEL); 1057 1058 if (!mpc30) 1059 return NULL; 1060 1061 dcn30_mpc_construct(mpc30, ctx, 1062 &mpc_regs, 1063 &mpc_shift, 1064 &mpc_mask, 1065 num_mpcc, 1066 num_rmu); 1067 1068 return &mpc30->base; 1069 } 1070 1071 static struct hubbub *dcn31_hubbub_create(struct dc_context *ctx) 1072 { 1073 int i; 1074 1075 struct dcn20_hubbub *hubbub3 = kzalloc(sizeof(struct dcn20_hubbub), 1076 GFP_KERNEL); 1077 1078 if (!hubbub3) 1079 return NULL; 1080 1081 hubbub31_construct(hubbub3, ctx, 1082 &hubbub_reg, 1083 &hubbub_shift, 1084 &hubbub_mask, 1085 dcn3_14_ip.det_buffer_size_kbytes, 1086 dcn3_14_ip.pixel_chunk_size_kbytes, 1087 dcn3_14_ip.config_return_buffer_size_in_kbytes); 1088 1089 1090 for (i = 0; i < res_cap_dcn314.num_vmid; i++) { 1091 struct dcn20_vmid *vmid = &hubbub3->vmid[i]; 1092 1093 vmid->ctx = ctx; 1094 1095 vmid->regs = &vmid_regs[i]; 1096 vmid->shifts = &vmid_shifts; 1097 vmid->masks = &vmid_masks; 1098 } 1099 1100 return &hubbub3->base; 1101 } 1102 1103 static struct timing_generator *dcn31_timing_generator_create( 1104 struct dc_context *ctx, 1105 uint32_t instance) 1106 { 1107 struct optc *tgn10 = 1108 kzalloc(sizeof(struct optc), GFP_KERNEL); 1109 1110 if (!tgn10) 1111 return NULL; 1112 1113 tgn10->base.inst = instance; 1114 tgn10->base.ctx = ctx; 1115 1116 tgn10->tg_regs = &optc_regs[instance]; 1117 tgn10->tg_shift = &optc_shift; 1118 tgn10->tg_mask = &optc_mask; 1119 1120 dcn314_timing_generator_init(tgn10); 1121 1122 return &tgn10->base; 1123 } 1124 1125 static const struct encoder_feature_support link_enc_feature = { 1126 .max_hdmi_deep_color = COLOR_DEPTH_121212, 1127 .max_hdmi_pixel_clock = 600000, 1128 .hdmi_ycbcr420_supported = true, 1129 .dp_ycbcr420_supported = true, 1130 .fec_supported = true, 1131 .flags.bits.IS_HBR2_CAPABLE = true, 1132 .flags.bits.IS_HBR3_CAPABLE = true, 1133 .flags.bits.IS_TPS3_CAPABLE = true, 1134 .flags.bits.IS_TPS4_CAPABLE = true 1135 }; 1136 1137 static struct link_encoder *dcn31_link_encoder_create( 1138 struct dc_context *ctx, 1139 const struct encoder_init_data *enc_init_data) 1140 { 1141 struct dcn20_link_encoder *enc20 = 1142 kzalloc(sizeof(struct dcn20_link_encoder), GFP_KERNEL); 1143 1144 if (!enc20) 1145 return NULL; 1146 1147 dcn31_link_encoder_construct(enc20, 1148 enc_init_data, 1149 &link_enc_feature, 1150 &link_enc_regs[enc_init_data->transmitter], 1151 &link_enc_aux_regs[enc_init_data->channel - 1], 1152 &link_enc_hpd_regs[enc_init_data->hpd_source], 1153 &le_shift, 1154 &le_mask); 1155 1156 return &enc20->enc10.base; 1157 } 1158 1159 /* Create a minimal link encoder object not associated with a particular 1160 * physical connector. 1161 * resource_funcs.link_enc_create_minimal 1162 */ 1163 static struct link_encoder *dcn31_link_enc_create_minimal( 1164 struct dc_context *ctx, enum engine_id eng_id) 1165 { 1166 struct dcn20_link_encoder *enc20; 1167 1168 if ((eng_id - ENGINE_ID_DIGA) > ctx->dc->res_pool->res_cap->num_dig_link_enc) 1169 return NULL; 1170 1171 enc20 = kzalloc(sizeof(struct dcn20_link_encoder), GFP_KERNEL); 1172 if (!enc20) 1173 return NULL; 1174 1175 dcn31_link_encoder_construct_minimal( 1176 enc20, 1177 ctx, 1178 &link_enc_feature, 1179 &link_enc_regs[eng_id - ENGINE_ID_DIGA], 1180 eng_id); 1181 1182 return &enc20->enc10.base; 1183 } 1184 1185 static struct panel_cntl *dcn31_panel_cntl_create(const struct panel_cntl_init_data *init_data) 1186 { 1187 struct dcn31_panel_cntl *panel_cntl = 1188 kzalloc(sizeof(struct dcn31_panel_cntl), GFP_KERNEL); 1189 1190 if (!panel_cntl) 1191 return NULL; 1192 1193 dcn31_panel_cntl_construct(panel_cntl, init_data); 1194 1195 return &panel_cntl->base; 1196 } 1197 1198 static void read_dce_straps( 1199 struct dc_context *ctx, 1200 struct resource_straps *straps) 1201 { 1202 generic_reg_get(ctx, regDC_PINSTRAPS + BASE(regDC_PINSTRAPS_BASE_IDX), 1203 FN(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO), &straps->dc_pinstraps_audio); 1204 1205 } 1206 1207 static struct audio *dcn31_create_audio( 1208 struct dc_context *ctx, unsigned int inst) 1209 { 1210 return dce_audio_create(ctx, inst, 1211 &audio_regs[inst], &audio_shift, &audio_mask); 1212 } 1213 1214 static struct vpg *dcn31_vpg_create( 1215 struct dc_context *ctx, 1216 uint32_t inst) 1217 { 1218 struct dcn31_vpg *vpg31 = kzalloc(sizeof(struct dcn31_vpg), GFP_KERNEL); 1219 1220 if (!vpg31) 1221 return NULL; 1222 1223 vpg31_construct(vpg31, ctx, inst, 1224 &vpg_regs[inst], 1225 &vpg_shift, 1226 &vpg_mask); 1227 1228 return &vpg31->base; 1229 } 1230 1231 static struct afmt *dcn31_afmt_create( 1232 struct dc_context *ctx, 1233 uint32_t inst) 1234 { 1235 struct dcn31_afmt *afmt31 = kzalloc(sizeof(struct dcn31_afmt), GFP_KERNEL); 1236 1237 if (!afmt31) 1238 return NULL; 1239 1240 afmt31_construct(afmt31, ctx, inst, 1241 &afmt_regs[inst], 1242 &afmt_shift, 1243 &afmt_mask); 1244 1245 // Light sleep by default, no need to power down here 1246 1247 return &afmt31->base; 1248 } 1249 1250 static struct apg *dcn31_apg_create( 1251 struct dc_context *ctx, 1252 uint32_t inst) 1253 { 1254 struct dcn31_apg *apg31 = kzalloc(sizeof(struct dcn31_apg), GFP_KERNEL); 1255 1256 if (!apg31) 1257 return NULL; 1258 1259 apg31_construct(apg31, ctx, inst, 1260 &apg_regs[inst], 1261 &apg_shift, 1262 &apg_mask); 1263 1264 return &apg31->base; 1265 } 1266 1267 static struct stream_encoder *dcn314_stream_encoder_create( 1268 enum engine_id eng_id, 1269 struct dc_context *ctx) 1270 { 1271 struct dcn10_stream_encoder *enc1; 1272 struct vpg *vpg; 1273 struct afmt *afmt; 1274 int vpg_inst; 1275 int afmt_inst; 1276 1277 /* Mapping of VPG, AFMT, DME register blocks to DIO block instance */ 1278 if (eng_id < ENGINE_ID_DIGF) { 1279 vpg_inst = eng_id; 1280 afmt_inst = eng_id; 1281 } else 1282 return NULL; 1283 1284 enc1 = kzalloc(sizeof(struct dcn10_stream_encoder), GFP_KERNEL); 1285 vpg = dcn31_vpg_create(ctx, vpg_inst); 1286 afmt = dcn31_afmt_create(ctx, afmt_inst); 1287 1288 if (!enc1 || !vpg || !afmt) { 1289 kfree(enc1); 1290 kfree(vpg); 1291 kfree(afmt); 1292 return NULL; 1293 } 1294 1295 dcn314_dio_stream_encoder_construct(enc1, ctx, ctx->dc_bios, 1296 eng_id, vpg, afmt, 1297 &stream_enc_regs[eng_id], 1298 &se_shift, &se_mask); 1299 1300 return &enc1->base; 1301 } 1302 1303 static struct hpo_dp_stream_encoder *dcn31_hpo_dp_stream_encoder_create( 1304 enum engine_id eng_id, 1305 struct dc_context *ctx) 1306 { 1307 struct dcn31_hpo_dp_stream_encoder *hpo_dp_enc31; 1308 struct vpg *vpg; 1309 struct apg *apg; 1310 uint32_t hpo_dp_inst; 1311 uint32_t vpg_inst; 1312 uint32_t apg_inst; 1313 1314 ASSERT((eng_id >= ENGINE_ID_HPO_DP_0) && (eng_id <= ENGINE_ID_HPO_DP_3)); 1315 hpo_dp_inst = eng_id - ENGINE_ID_HPO_DP_0; 1316 1317 /* Mapping of VPG register blocks to HPO DP block instance: 1318 * VPG[6] -> HPO_DP[0] 1319 * VPG[7] -> HPO_DP[1] 1320 * VPG[8] -> HPO_DP[2] 1321 * VPG[9] -> HPO_DP[3] 1322 */ 1323 //Uses offset index 5-8, but actually maps to vpg_inst 6-9 1324 vpg_inst = hpo_dp_inst + 5; 1325 1326 /* Mapping of APG register blocks to HPO DP block instance: 1327 * APG[0] -> HPO_DP[0] 1328 * APG[1] -> HPO_DP[1] 1329 * APG[2] -> HPO_DP[2] 1330 * APG[3] -> HPO_DP[3] 1331 */ 1332 apg_inst = hpo_dp_inst; 1333 1334 /* allocate HPO stream encoder and create VPG sub-block */ 1335 hpo_dp_enc31 = kzalloc(sizeof(struct dcn31_hpo_dp_stream_encoder), GFP_KERNEL); 1336 vpg = dcn31_vpg_create(ctx, vpg_inst); 1337 apg = dcn31_apg_create(ctx, apg_inst); 1338 1339 if (!hpo_dp_enc31 || !vpg || !apg) { 1340 kfree(hpo_dp_enc31); 1341 kfree(vpg); 1342 kfree(apg); 1343 return NULL; 1344 } 1345 1346 dcn31_hpo_dp_stream_encoder_construct(hpo_dp_enc31, ctx, ctx->dc_bios, 1347 hpo_dp_inst, eng_id, vpg, apg, 1348 &hpo_dp_stream_enc_regs[hpo_dp_inst], 1349 &hpo_dp_se_shift, &hpo_dp_se_mask); 1350 1351 return &hpo_dp_enc31->base; 1352 } 1353 1354 static struct hpo_dp_link_encoder *dcn31_hpo_dp_link_encoder_create( 1355 uint8_t inst, 1356 struct dc_context *ctx) 1357 { 1358 struct dcn31_hpo_dp_link_encoder *hpo_dp_enc31; 1359 1360 /* allocate HPO link encoder */ 1361 hpo_dp_enc31 = kzalloc(sizeof(struct dcn31_hpo_dp_link_encoder), GFP_KERNEL); 1362 1363 hpo_dp_link_encoder31_construct(hpo_dp_enc31, ctx, inst, 1364 &hpo_dp_link_enc_regs[inst], 1365 &hpo_dp_le_shift, &hpo_dp_le_mask); 1366 1367 return &hpo_dp_enc31->base; 1368 } 1369 1370 static struct dce_hwseq *dcn314_hwseq_create( 1371 struct dc_context *ctx) 1372 { 1373 struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_KERNEL); 1374 1375 if (hws) { 1376 hws->ctx = ctx; 1377 hws->regs = &hwseq_reg; 1378 hws->shifts = &hwseq_shift; 1379 hws->masks = &hwseq_mask; 1380 } 1381 return hws; 1382 } 1383 static const struct resource_create_funcs res_create_funcs = { 1384 .read_dce_straps = read_dce_straps, 1385 .create_audio = dcn31_create_audio, 1386 .create_stream_encoder = dcn314_stream_encoder_create, 1387 .create_hpo_dp_stream_encoder = dcn31_hpo_dp_stream_encoder_create, 1388 .create_hpo_dp_link_encoder = dcn31_hpo_dp_link_encoder_create, 1389 .create_hwseq = dcn314_hwseq_create, 1390 }; 1391 1392 static void dcn314_resource_destruct(struct dcn314_resource_pool *pool) 1393 { 1394 unsigned int i; 1395 1396 for (i = 0; i < pool->base.stream_enc_count; i++) { 1397 if (pool->base.stream_enc[i] != NULL) { 1398 if (pool->base.stream_enc[i]->vpg != NULL) { 1399 kfree(DCN30_VPG_FROM_VPG(pool->base.stream_enc[i]->vpg)); 1400 pool->base.stream_enc[i]->vpg = NULL; 1401 } 1402 if (pool->base.stream_enc[i]->afmt != NULL) { 1403 kfree(DCN30_AFMT_FROM_AFMT(pool->base.stream_enc[i]->afmt)); 1404 pool->base.stream_enc[i]->afmt = NULL; 1405 } 1406 kfree(DCN10STRENC_FROM_STRENC(pool->base.stream_enc[i])); 1407 pool->base.stream_enc[i] = NULL; 1408 } 1409 } 1410 1411 for (i = 0; i < pool->base.hpo_dp_stream_enc_count; i++) { 1412 if (pool->base.hpo_dp_stream_enc[i] != NULL) { 1413 if (pool->base.hpo_dp_stream_enc[i]->vpg != NULL) { 1414 kfree(DCN30_VPG_FROM_VPG(pool->base.hpo_dp_stream_enc[i]->vpg)); 1415 pool->base.hpo_dp_stream_enc[i]->vpg = NULL; 1416 } 1417 if (pool->base.hpo_dp_stream_enc[i]->apg != NULL) { 1418 kfree(DCN31_APG_FROM_APG(pool->base.hpo_dp_stream_enc[i]->apg)); 1419 pool->base.hpo_dp_stream_enc[i]->apg = NULL; 1420 } 1421 kfree(DCN3_1_HPO_DP_STREAM_ENC_FROM_HPO_STREAM_ENC(pool->base.hpo_dp_stream_enc[i])); 1422 pool->base.hpo_dp_stream_enc[i] = NULL; 1423 } 1424 } 1425 1426 for (i = 0; i < pool->base.hpo_dp_link_enc_count; i++) { 1427 if (pool->base.hpo_dp_link_enc[i] != NULL) { 1428 kfree(DCN3_1_HPO_DP_LINK_ENC_FROM_HPO_LINK_ENC(pool->base.hpo_dp_link_enc[i])); 1429 pool->base.hpo_dp_link_enc[i] = NULL; 1430 } 1431 } 1432 1433 for (i = 0; i < pool->base.res_cap->num_dsc; i++) { 1434 if (pool->base.dscs[i] != NULL) 1435 dcn20_dsc_destroy(&pool->base.dscs[i]); 1436 } 1437 1438 if (pool->base.mpc != NULL) { 1439 kfree(TO_DCN20_MPC(pool->base.mpc)); 1440 pool->base.mpc = NULL; 1441 } 1442 if (pool->base.hubbub != NULL) { 1443 kfree(pool->base.hubbub); 1444 pool->base.hubbub = NULL; 1445 } 1446 for (i = 0; i < pool->base.pipe_count; i++) { 1447 if (pool->base.dpps[i] != NULL) 1448 dcn31_dpp_destroy(&pool->base.dpps[i]); 1449 1450 if (pool->base.ipps[i] != NULL) 1451 pool->base.ipps[i]->funcs->ipp_destroy(&pool->base.ipps[i]); 1452 1453 if (pool->base.hubps[i] != NULL) { 1454 kfree(TO_DCN20_HUBP(pool->base.hubps[i])); 1455 pool->base.hubps[i] = NULL; 1456 } 1457 1458 if (pool->base.irqs != NULL) 1459 dal_irq_service_destroy(&pool->base.irqs); 1460 } 1461 1462 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { 1463 if (pool->base.engines[i] != NULL) 1464 dce110_engine_destroy(&pool->base.engines[i]); 1465 if (pool->base.hw_i2cs[i] != NULL) { 1466 kfree(pool->base.hw_i2cs[i]); 1467 pool->base.hw_i2cs[i] = NULL; 1468 } 1469 if (pool->base.sw_i2cs[i] != NULL) { 1470 kfree(pool->base.sw_i2cs[i]); 1471 pool->base.sw_i2cs[i] = NULL; 1472 } 1473 } 1474 1475 for (i = 0; i < pool->base.res_cap->num_opp; i++) { 1476 if (pool->base.opps[i] != NULL) 1477 pool->base.opps[i]->funcs->opp_destroy(&pool->base.opps[i]); 1478 } 1479 1480 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { 1481 if (pool->base.timing_generators[i] != NULL) { 1482 kfree(DCN10TG_FROM_TG(pool->base.timing_generators[i])); 1483 pool->base.timing_generators[i] = NULL; 1484 } 1485 } 1486 1487 for (i = 0; i < pool->base.res_cap->num_dwb; i++) { 1488 if (pool->base.dwbc[i] != NULL) { 1489 kfree(TO_DCN30_DWBC(pool->base.dwbc[i])); 1490 pool->base.dwbc[i] = NULL; 1491 } 1492 if (pool->base.mcif_wb[i] != NULL) { 1493 kfree(TO_DCN30_MMHUBBUB(pool->base.mcif_wb[i])); 1494 pool->base.mcif_wb[i] = NULL; 1495 } 1496 } 1497 1498 for (i = 0; i < pool->base.audio_count; i++) { 1499 if (pool->base.audios[i]) 1500 dce_aud_destroy(&pool->base.audios[i]); 1501 } 1502 1503 for (i = 0; i < pool->base.clk_src_count; i++) { 1504 if (pool->base.clock_sources[i] != NULL) { 1505 dcn20_clock_source_destroy(&pool->base.clock_sources[i]); 1506 pool->base.clock_sources[i] = NULL; 1507 } 1508 } 1509 1510 for (i = 0; i < pool->base.res_cap->num_mpc_3dlut; i++) { 1511 if (pool->base.mpc_lut[i] != NULL) { 1512 dc_3dlut_func_release(pool->base.mpc_lut[i]); 1513 pool->base.mpc_lut[i] = NULL; 1514 } 1515 if (pool->base.mpc_shaper[i] != NULL) { 1516 dc_transfer_func_release(pool->base.mpc_shaper[i]); 1517 pool->base.mpc_shaper[i] = NULL; 1518 } 1519 } 1520 1521 if (pool->base.dp_clock_source != NULL) { 1522 dcn20_clock_source_destroy(&pool->base.dp_clock_source); 1523 pool->base.dp_clock_source = NULL; 1524 } 1525 1526 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { 1527 if (pool->base.multiple_abms[i] != NULL) 1528 dce_abm_destroy(&pool->base.multiple_abms[i]); 1529 } 1530 1531 if (pool->base.psr != NULL) 1532 dmub_psr_destroy(&pool->base.psr); 1533 1534 if (pool->base.replay != NULL) 1535 dmub_replay_destroy(&pool->base.replay); 1536 1537 if (pool->base.dccg != NULL) 1538 dcn_dccg_destroy(&pool->base.dccg); 1539 } 1540 1541 static struct hubp *dcn31_hubp_create( 1542 struct dc_context *ctx, 1543 uint32_t inst) 1544 { 1545 struct dcn20_hubp *hubp2 = 1546 kzalloc(sizeof(struct dcn20_hubp), GFP_KERNEL); 1547 1548 if (!hubp2) 1549 return NULL; 1550 1551 if (hubp31_construct(hubp2, ctx, inst, 1552 &hubp_regs[inst], &hubp_shift, &hubp_mask)) 1553 return &hubp2->base; 1554 1555 BREAK_TO_DEBUGGER(); 1556 kfree(hubp2); 1557 return NULL; 1558 } 1559 1560 static bool dcn31_dwbc_create(struct dc_context *ctx, struct resource_pool *pool) 1561 { 1562 int i; 1563 uint32_t pipe_count = pool->res_cap->num_dwb; 1564 1565 for (i = 0; i < pipe_count; i++) { 1566 struct dcn30_dwbc *dwbc30 = kzalloc(sizeof(struct dcn30_dwbc), 1567 GFP_KERNEL); 1568 1569 if (!dwbc30) { 1570 dm_error("DC: failed to create dwbc30!\n"); 1571 return false; 1572 } 1573 1574 dcn30_dwbc_construct(dwbc30, ctx, 1575 &dwbc30_regs[i], 1576 &dwbc30_shift, 1577 &dwbc30_mask, 1578 i); 1579 1580 pool->dwbc[i] = &dwbc30->base; 1581 } 1582 return true; 1583 } 1584 1585 static bool dcn31_mmhubbub_create(struct dc_context *ctx, struct resource_pool *pool) 1586 { 1587 int i; 1588 uint32_t pipe_count = pool->res_cap->num_dwb; 1589 1590 for (i = 0; i < pipe_count; i++) { 1591 struct dcn30_mmhubbub *mcif_wb30 = kzalloc(sizeof(struct dcn30_mmhubbub), 1592 GFP_KERNEL); 1593 1594 if (!mcif_wb30) { 1595 dm_error("DC: failed to create mcif_wb30!\n"); 1596 return false; 1597 } 1598 1599 dcn30_mmhubbub_construct(mcif_wb30, ctx, 1600 &mcif_wb30_regs[i], 1601 &mcif_wb30_shift, 1602 &mcif_wb30_mask, 1603 i); 1604 1605 pool->mcif_wb[i] = &mcif_wb30->base; 1606 } 1607 return true; 1608 } 1609 1610 static struct display_stream_compressor *dcn314_dsc_create( 1611 struct dc_context *ctx, uint32_t inst) 1612 { 1613 struct dcn20_dsc *dsc = 1614 kzalloc(sizeof(struct dcn20_dsc), GFP_KERNEL); 1615 1616 if (!dsc) { 1617 BREAK_TO_DEBUGGER(); 1618 return NULL; 1619 } 1620 1621 dsc2_construct(dsc, ctx, inst, &dsc_regs[inst], &dsc_shift, &dsc_mask); 1622 return &dsc->base; 1623 } 1624 1625 static void dcn314_destroy_resource_pool(struct resource_pool **pool) 1626 { 1627 struct dcn314_resource_pool *dcn314_pool = TO_DCN314_RES_POOL(*pool); 1628 1629 dcn314_resource_destruct(dcn314_pool); 1630 kfree(dcn314_pool); 1631 *pool = NULL; 1632 } 1633 1634 static struct clock_source *dcn31_clock_source_create( 1635 struct dc_context *ctx, 1636 struct dc_bios *bios, 1637 enum clock_source_id id, 1638 const struct dce110_clk_src_regs *regs, 1639 bool dp_clk_src) 1640 { 1641 struct dce110_clk_src *clk_src = 1642 kzalloc(sizeof(struct dce110_clk_src), GFP_KERNEL); 1643 1644 if (!clk_src) 1645 return NULL; 1646 1647 if (dcn31_clk_src_construct(clk_src, ctx, bios, id, 1648 regs, &cs_shift, &cs_mask)) { 1649 clk_src->base.dp_clk_src = dp_clk_src; 1650 return &clk_src->base; 1651 } 1652 1653 BREAK_TO_DEBUGGER(); 1654 kfree(clk_src); 1655 return NULL; 1656 } 1657 1658 static int dcn314_populate_dml_pipes_from_context( 1659 struct dc *dc, struct dc_state *context, 1660 display_e2e_pipe_params_st *pipes, 1661 bool fast_validate) 1662 { 1663 int pipe_cnt; 1664 1665 DC_FP_START(); 1666 pipe_cnt = dcn314_populate_dml_pipes_from_context_fpu(dc, context, pipes, fast_validate); 1667 DC_FP_END(); 1668 1669 return pipe_cnt; 1670 } 1671 1672 static struct dc_cap_funcs cap_funcs = { 1673 .get_dcc_compression_cap = dcn20_get_dcc_compression_cap 1674 }; 1675 1676 static void dcn314_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params) 1677 { 1678 DC_FP_START(); 1679 dcn314_update_bw_bounding_box_fpu(dc, bw_params); 1680 DC_FP_END(); 1681 } 1682 1683 static void dcn314_get_panel_config_defaults(struct dc_panel_config *panel_config) 1684 { 1685 *panel_config = panel_config_defaults; 1686 } 1687 1688 static bool filter_modes_for_single_channel_workaround(struct dc *dc, 1689 struct dc_state *context) 1690 { 1691 // Filter 2K@240Hz+8K@24fps above combination timing if memory only has single dimm LPDDR 1692 if (dc->clk_mgr->bw_params->vram_type == 34 && 1693 dc->clk_mgr->bw_params->num_channels < 2 && 1694 context->stream_count > 1) { 1695 int total_phy_pix_clk = 0; 1696 1697 for (int i = 0; i < context->stream_count; i++) 1698 if (context->res_ctx.pipe_ctx[i].stream) 1699 total_phy_pix_clk += context->res_ctx.pipe_ctx[i].stream->phy_pix_clk; 1700 1701 if (total_phy_pix_clk >= (1148928+826260)) //2K@240Hz+8K@24fps 1702 return true; 1703 } 1704 return false; 1705 } 1706 1707 bool dcn314_validate_bandwidth(struct dc *dc, 1708 struct dc_state *context, 1709 bool fast_validate) 1710 { 1711 bool out = false; 1712 1713 BW_VAL_TRACE_SETUP(); 1714 1715 int vlevel = 0; 1716 int pipe_cnt = 0; 1717 display_e2e_pipe_params_st *pipes = kzalloc(dc->res_pool->pipe_count * sizeof(display_e2e_pipe_params_st), GFP_KERNEL); 1718 DC_LOGGER_INIT(dc->ctx->logger); 1719 1720 BW_VAL_TRACE_COUNT(); 1721 1722 if (filter_modes_for_single_channel_workaround(dc, context)) 1723 goto validate_fail; 1724 1725 DC_FP_START(); 1726 // do not support self refresh only 1727 out = dcn30_internal_validate_bw(dc, context, pipes, &pipe_cnt, &vlevel, fast_validate, false); 1728 DC_FP_END(); 1729 1730 // Disable fast_validate to set min dcfclk in calculate_wm_and_dlg 1731 if (pipe_cnt == 0) 1732 fast_validate = false; 1733 1734 if (!out) 1735 goto validate_fail; 1736 1737 BW_VAL_TRACE_END_VOLTAGE_LEVEL(); 1738 1739 if (fast_validate) { 1740 BW_VAL_TRACE_SKIP(fast); 1741 goto validate_out; 1742 } 1743 if (dc->res_pool->funcs->calculate_wm_and_dlg) 1744 dc->res_pool->funcs->calculate_wm_and_dlg(dc, context, pipes, pipe_cnt, vlevel); 1745 1746 BW_VAL_TRACE_END_WATERMARKS(); 1747 1748 goto validate_out; 1749 1750 validate_fail: 1751 DC_LOG_WARNING("Mode Validation Warning: %s failed validation.\n", 1752 dml_get_status_message(context->bw_ctx.dml.vba.ValidationStatus[context->bw_ctx.dml.vba.soc.num_states])); 1753 1754 BW_VAL_TRACE_SKIP(fail); 1755 out = false; 1756 1757 validate_out: 1758 kfree(pipes); 1759 1760 BW_VAL_TRACE_FINISH(); 1761 1762 return out; 1763 } 1764 1765 static struct resource_funcs dcn314_res_pool_funcs = { 1766 .destroy = dcn314_destroy_resource_pool, 1767 .link_enc_create = dcn31_link_encoder_create, 1768 .link_enc_create_minimal = dcn31_link_enc_create_minimal, 1769 .link_encs_assign = link_enc_cfg_link_encs_assign, 1770 .link_enc_unassign = link_enc_cfg_link_enc_unassign, 1771 .panel_cntl_create = dcn31_panel_cntl_create, 1772 .validate_bandwidth = dcn314_validate_bandwidth, 1773 .calculate_wm_and_dlg = dcn31_calculate_wm_and_dlg, 1774 .update_soc_for_wm_a = dcn31_update_soc_for_wm_a, 1775 .populate_dml_pipes = dcn314_populate_dml_pipes_from_context, 1776 .acquire_free_pipe_as_secondary_dpp_pipe = dcn20_acquire_free_pipe_for_layer, 1777 .add_stream_to_ctx = dcn30_add_stream_to_ctx, 1778 .add_dsc_to_stream_resource = dcn20_add_dsc_to_stream_resource, 1779 .remove_stream_from_ctx = dcn20_remove_stream_from_ctx, 1780 .populate_dml_writeback_from_context = dcn30_populate_dml_writeback_from_context, 1781 .set_mcif_arb_params = dcn30_set_mcif_arb_params, 1782 .find_first_free_match_stream_enc_for_link = dcn10_find_first_free_match_stream_enc_for_link, 1783 .acquire_post_bldn_3dlut = dcn30_acquire_post_bldn_3dlut, 1784 .release_post_bldn_3dlut = dcn30_release_post_bldn_3dlut, 1785 .update_bw_bounding_box = dcn314_update_bw_bounding_box, 1786 .patch_unknown_plane_state = dcn20_patch_unknown_plane_state, 1787 .get_panel_config_defaults = dcn314_get_panel_config_defaults, 1788 }; 1789 1790 static struct clock_source *dcn30_clock_source_create( 1791 struct dc_context *ctx, 1792 struct dc_bios *bios, 1793 enum clock_source_id id, 1794 const struct dce110_clk_src_regs *regs, 1795 bool dp_clk_src) 1796 { 1797 struct dce110_clk_src *clk_src = 1798 kzalloc(sizeof(struct dce110_clk_src), GFP_KERNEL); 1799 1800 if (!clk_src) 1801 return NULL; 1802 1803 if (dcn31_clk_src_construct(clk_src, ctx, bios, id, 1804 regs, &cs_shift, &cs_mask)) { 1805 clk_src->base.dp_clk_src = dp_clk_src; 1806 return &clk_src->base; 1807 } 1808 1809 BREAK_TO_DEBUGGER(); 1810 kfree(clk_src); 1811 return NULL; 1812 } 1813 1814 static bool dcn314_resource_construct( 1815 uint8_t num_virtual_links, 1816 struct dc *dc, 1817 struct dcn314_resource_pool *pool) 1818 { 1819 int i; 1820 struct dc_context *ctx = dc->ctx; 1821 struct irq_service_init_data init_data; 1822 1823 ctx->dc_bios->regs = &bios_regs; 1824 1825 pool->base.res_cap = &res_cap_dcn314; 1826 pool->base.funcs = &dcn314_res_pool_funcs; 1827 1828 /************************************************* 1829 * Resource + asic cap harcoding * 1830 *************************************************/ 1831 pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE; 1832 pool->base.pipe_count = pool->base.res_cap->num_timing_generator; 1833 pool->base.mpcc_count = pool->base.res_cap->num_timing_generator; 1834 dc->caps.max_downscale_ratio = 400; 1835 dc->caps.i2c_speed_in_khz = 100; 1836 dc->caps.i2c_speed_in_khz_hdcp = 100; 1837 dc->caps.max_cursor_size = 256; 1838 dc->caps.min_horizontal_blanking_period = 80; 1839 dc->caps.dmdata_alloc_size = 2048; 1840 dc->caps.max_slave_planes = 2; 1841 dc->caps.max_slave_yuv_planes = 2; 1842 dc->caps.max_slave_rgb_planes = 2; 1843 dc->caps.post_blend_color_processing = true; 1844 dc->caps.force_dp_tps4_for_cp2520 = true; 1845 if (dc->config.forceHBR2CP2520) 1846 dc->caps.force_dp_tps4_for_cp2520 = false; 1847 dc->caps.dp_hpo = true; 1848 dc->caps.dp_hdmi21_pcon_support = true; 1849 dc->caps.edp_dsc_support = true; 1850 dc->caps.extended_aux_timeout_support = true; 1851 dc->caps.dmcub_support = true; 1852 dc->caps.is_apu = true; 1853 dc->caps.seamless_odm = true; 1854 1855 dc->caps.zstate_support = true; 1856 1857 /* Color pipeline capabilities */ 1858 dc->caps.color.dpp.dcn_arch = 1; 1859 dc->caps.color.dpp.input_lut_shared = 0; 1860 dc->caps.color.dpp.icsc = 1; 1861 dc->caps.color.dpp.dgam_ram = 0; // must use gamma_corr 1862 dc->caps.color.dpp.dgam_rom_caps.srgb = 1; 1863 dc->caps.color.dpp.dgam_rom_caps.bt2020 = 1; 1864 dc->caps.color.dpp.dgam_rom_caps.gamma2_2 = 1; 1865 dc->caps.color.dpp.dgam_rom_caps.pq = 1; 1866 dc->caps.color.dpp.dgam_rom_caps.hlg = 1; 1867 dc->caps.color.dpp.post_csc = 1; 1868 dc->caps.color.dpp.gamma_corr = 1; 1869 dc->caps.color.dpp.dgam_rom_for_yuv = 0; 1870 1871 dc->caps.color.dpp.hw_3d_lut = 1; 1872 dc->caps.color.dpp.ogam_ram = 1; 1873 // no OGAM ROM on DCN301 1874 dc->caps.color.dpp.ogam_rom_caps.srgb = 0; 1875 dc->caps.color.dpp.ogam_rom_caps.bt2020 = 0; 1876 dc->caps.color.dpp.ogam_rom_caps.gamma2_2 = 0; 1877 dc->caps.color.dpp.ogam_rom_caps.pq = 0; 1878 dc->caps.color.dpp.ogam_rom_caps.hlg = 0; 1879 dc->caps.color.dpp.ocsc = 0; 1880 1881 dc->caps.color.mpc.gamut_remap = 1; 1882 dc->caps.color.mpc.num_3dluts = pool->base.res_cap->num_mpc_3dlut; //2 1883 dc->caps.color.mpc.ogam_ram = 1; 1884 dc->caps.color.mpc.ogam_rom_caps.srgb = 0; 1885 dc->caps.color.mpc.ogam_rom_caps.bt2020 = 0; 1886 dc->caps.color.mpc.ogam_rom_caps.gamma2_2 = 0; 1887 dc->caps.color.mpc.ogam_rom_caps.pq = 0; 1888 dc->caps.color.mpc.ogam_rom_caps.hlg = 0; 1889 dc->caps.color.mpc.ocsc = 1; 1890 1891 /* Use pipe context based otg sync logic */ 1892 dc->config.use_pipe_ctx_sync_logic = true; 1893 1894 /* read VBIOS LTTPR caps */ 1895 { 1896 if (ctx->dc_bios->funcs->get_lttpr_caps) { 1897 enum bp_result bp_query_result; 1898 uint8_t is_vbios_lttpr_enable = 0; 1899 1900 bp_query_result = ctx->dc_bios->funcs->get_lttpr_caps(ctx->dc_bios, &is_vbios_lttpr_enable); 1901 dc->caps.vbios_lttpr_enable = (bp_query_result == BP_RESULT_OK) && !!is_vbios_lttpr_enable; 1902 } 1903 1904 /* interop bit is implicit */ 1905 { 1906 dc->caps.vbios_lttpr_aware = true; 1907 } 1908 } 1909 1910 if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV) 1911 dc->debug = debug_defaults_drv; 1912 else 1913 dc->debug = debug_defaults_diags; 1914 1915 /* Disable pipe power gating */ 1916 dc->debug.disable_dpp_power_gate = true; 1917 dc->debug.disable_hubp_power_gate = true; 1918 1919 /* Disable root clock optimization */ 1920 dc->debug.root_clock_optimization.u32All = 0; 1921 1922 // Init the vm_helper 1923 if (dc->vm_helper) 1924 vm_helper_init(dc->vm_helper, 16); 1925 1926 /************************************************* 1927 * Create resources * 1928 *************************************************/ 1929 1930 /* Clock Sources for Pixel Clock*/ 1931 pool->base.clock_sources[DCN31_CLK_SRC_PLL0] = 1932 dcn30_clock_source_create(ctx, ctx->dc_bios, 1933 CLOCK_SOURCE_COMBO_PHY_PLL0, 1934 &clk_src_regs[0], false); 1935 pool->base.clock_sources[DCN31_CLK_SRC_PLL1] = 1936 dcn30_clock_source_create(ctx, ctx->dc_bios, 1937 CLOCK_SOURCE_COMBO_PHY_PLL1, 1938 &clk_src_regs[1], false); 1939 pool->base.clock_sources[DCN31_CLK_SRC_PLL2] = 1940 dcn30_clock_source_create(ctx, ctx->dc_bios, 1941 CLOCK_SOURCE_COMBO_PHY_PLL2, 1942 &clk_src_regs[2], false); 1943 pool->base.clock_sources[DCN31_CLK_SRC_PLL3] = 1944 dcn30_clock_source_create(ctx, ctx->dc_bios, 1945 CLOCK_SOURCE_COMBO_PHY_PLL3, 1946 &clk_src_regs[3], false); 1947 pool->base.clock_sources[DCN31_CLK_SRC_PLL4] = 1948 dcn30_clock_source_create(ctx, ctx->dc_bios, 1949 CLOCK_SOURCE_COMBO_PHY_PLL4, 1950 &clk_src_regs[4], false); 1951 1952 pool->base.clk_src_count = DCN30_CLK_SRC_TOTAL; 1953 1954 /* todo: not reuse phy_pll registers */ 1955 pool->base.dp_clock_source = 1956 dcn31_clock_source_create(ctx, ctx->dc_bios, 1957 CLOCK_SOURCE_ID_DP_DTO, 1958 &clk_src_regs[0], true); 1959 1960 for (i = 0; i < pool->base.clk_src_count; i++) { 1961 if (pool->base.clock_sources[i] == NULL) { 1962 dm_error("DC: failed to create clock sources!\n"); 1963 BREAK_TO_DEBUGGER(); 1964 goto create_fail; 1965 } 1966 } 1967 1968 pool->base.dccg = dccg314_create(ctx, &dccg_regs, &dccg_shift, &dccg_mask); 1969 if (pool->base.dccg == NULL) { 1970 dm_error("DC: failed to create dccg!\n"); 1971 BREAK_TO_DEBUGGER(); 1972 goto create_fail; 1973 } 1974 1975 init_data.ctx = dc->ctx; 1976 pool->base.irqs = dal_irq_service_dcn314_create(&init_data); 1977 if (!pool->base.irqs) 1978 goto create_fail; 1979 1980 /* HUBBUB */ 1981 pool->base.hubbub = dcn31_hubbub_create(ctx); 1982 if (pool->base.hubbub == NULL) { 1983 BREAK_TO_DEBUGGER(); 1984 dm_error("DC: failed to create hubbub!\n"); 1985 goto create_fail; 1986 } 1987 1988 /* HUBPs, DPPs, OPPs and TGs */ 1989 for (i = 0; i < pool->base.pipe_count; i++) { 1990 pool->base.hubps[i] = dcn31_hubp_create(ctx, i); 1991 if (pool->base.hubps[i] == NULL) { 1992 BREAK_TO_DEBUGGER(); 1993 dm_error( 1994 "DC: failed to create hubps!\n"); 1995 goto create_fail; 1996 } 1997 1998 pool->base.dpps[i] = dcn31_dpp_create(ctx, i); 1999 if (pool->base.dpps[i] == NULL) { 2000 BREAK_TO_DEBUGGER(); 2001 dm_error( 2002 "DC: failed to create dpps!\n"); 2003 goto create_fail; 2004 } 2005 } 2006 2007 for (i = 0; i < pool->base.res_cap->num_opp; i++) { 2008 pool->base.opps[i] = dcn31_opp_create(ctx, i); 2009 if (pool->base.opps[i] == NULL) { 2010 BREAK_TO_DEBUGGER(); 2011 dm_error( 2012 "DC: failed to create output pixel processor!\n"); 2013 goto create_fail; 2014 } 2015 } 2016 2017 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { 2018 pool->base.timing_generators[i] = dcn31_timing_generator_create( 2019 ctx, i); 2020 if (pool->base.timing_generators[i] == NULL) { 2021 BREAK_TO_DEBUGGER(); 2022 dm_error("DC: failed to create tg!\n"); 2023 goto create_fail; 2024 } 2025 } 2026 pool->base.timing_generator_count = i; 2027 2028 /* PSR */ 2029 pool->base.psr = dmub_psr_create(ctx); 2030 if (pool->base.psr == NULL) { 2031 dm_error("DC: failed to create psr obj!\n"); 2032 BREAK_TO_DEBUGGER(); 2033 goto create_fail; 2034 } 2035 2036 /* Replay */ 2037 pool->base.replay = dmub_replay_create(ctx); 2038 if (pool->base.replay == NULL) { 2039 dm_error("DC: failed to create replay obj!\n"); 2040 BREAK_TO_DEBUGGER(); 2041 goto create_fail; 2042 } 2043 2044 /* ABM */ 2045 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { 2046 pool->base.multiple_abms[i] = dmub_abm_create(ctx, 2047 &abm_regs[i], 2048 &abm_shift, 2049 &abm_mask); 2050 if (pool->base.multiple_abms[i] == NULL) { 2051 dm_error("DC: failed to create abm for pipe %d!\n", i); 2052 BREAK_TO_DEBUGGER(); 2053 goto create_fail; 2054 } 2055 } 2056 2057 /* MPC and DSC */ 2058 pool->base.mpc = dcn31_mpc_create(ctx, pool->base.mpcc_count, pool->base.res_cap->num_mpc_3dlut); 2059 if (pool->base.mpc == NULL) { 2060 BREAK_TO_DEBUGGER(); 2061 dm_error("DC: failed to create mpc!\n"); 2062 goto create_fail; 2063 } 2064 2065 for (i = 0; i < pool->base.res_cap->num_dsc; i++) { 2066 pool->base.dscs[i] = dcn314_dsc_create(ctx, i); 2067 if (pool->base.dscs[i] == NULL) { 2068 BREAK_TO_DEBUGGER(); 2069 dm_error("DC: failed to create display stream compressor %d!\n", i); 2070 goto create_fail; 2071 } 2072 } 2073 2074 /* DWB and MMHUBBUB */ 2075 if (!dcn31_dwbc_create(ctx, &pool->base)) { 2076 BREAK_TO_DEBUGGER(); 2077 dm_error("DC: failed to create dwbc!\n"); 2078 goto create_fail; 2079 } 2080 2081 if (!dcn31_mmhubbub_create(ctx, &pool->base)) { 2082 BREAK_TO_DEBUGGER(); 2083 dm_error("DC: failed to create mcif_wb!\n"); 2084 goto create_fail; 2085 } 2086 2087 /* AUX and I2C */ 2088 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { 2089 pool->base.engines[i] = dcn31_aux_engine_create(ctx, i); 2090 if (pool->base.engines[i] == NULL) { 2091 BREAK_TO_DEBUGGER(); 2092 dm_error( 2093 "DC:failed to create aux engine!!\n"); 2094 goto create_fail; 2095 } 2096 pool->base.hw_i2cs[i] = dcn31_i2c_hw_create(ctx, i); 2097 if (pool->base.hw_i2cs[i] == NULL) { 2098 BREAK_TO_DEBUGGER(); 2099 dm_error( 2100 "DC:failed to create hw i2c!!\n"); 2101 goto create_fail; 2102 } 2103 pool->base.sw_i2cs[i] = NULL; 2104 } 2105 2106 /* DCN314 has 4 DPIA */ 2107 pool->base.usb4_dpia_count = 4; 2108 2109 /* Audio, Stream Encoders including HPO and virtual, MPC 3D LUTs */ 2110 if (!resource_construct(num_virtual_links, dc, &pool->base, 2111 &res_create_funcs)) 2112 goto create_fail; 2113 2114 /* HW Sequencer and Plane caps */ 2115 dcn314_hw_sequencer_construct(dc); 2116 2117 dc->caps.max_planes = pool->base.pipe_count; 2118 2119 for (i = 0; i < dc->caps.max_planes; ++i) 2120 dc->caps.planes[i] = plane_cap; 2121 2122 dc->cap_funcs = cap_funcs; 2123 2124 dc->dcn_ip->max_num_dpp = dcn3_14_ip.max_num_dpp; 2125 2126 return true; 2127 2128 create_fail: 2129 2130 dcn314_resource_destruct(pool); 2131 2132 return false; 2133 } 2134 2135 struct resource_pool *dcn314_create_resource_pool( 2136 const struct dc_init_data *init_data, 2137 struct dc *dc) 2138 { 2139 struct dcn314_resource_pool *pool = 2140 kzalloc(sizeof(struct dcn314_resource_pool), GFP_KERNEL); 2141 2142 if (!pool) 2143 return NULL; 2144 2145 if (dcn314_resource_construct(init_data->num_virtual_links, dc, pool)) 2146 return &pool->base; 2147 2148 BREAK_TO_DEBUGGER(); 2149 kfree(pool); 2150 return NULL; 2151 } 2152