1 // SPDX-License-Identifier: MIT 2 /* 3 * Copyright 2022 Advanced Micro Devices, Inc. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 * 23 * Authors: AMD 24 * 25 */ 26 27 28 #include "dm_services.h" 29 #include "dc.h" 30 31 #include "dcn31/dcn31_init.h" 32 #include "dcn314/dcn314_init.h" 33 34 #include "resource.h" 35 #include "include/irq_service_interface.h" 36 #include "dcn314_resource.h" 37 38 #include "dcn20/dcn20_resource.h" 39 #include "dcn30/dcn30_resource.h" 40 #include "dcn31/dcn31_resource.h" 41 42 #include "dcn10/dcn10_ipp.h" 43 #include "dcn30/dcn30_hubbub.h" 44 #include "dcn31/dcn31_hubbub.h" 45 #include "dcn30/dcn30_mpc.h" 46 #include "dcn31/dcn31_hubp.h" 47 #include "irq/dcn31/irq_service_dcn31.h" 48 #include "irq/dcn314/irq_service_dcn314.h" 49 #include "dcn30/dcn30_dpp.h" 50 #include "dcn314/dcn314_optc.h" 51 #include "dcn20/dcn20_hwseq.h" 52 #include "dcn30/dcn30_hwseq.h" 53 #include "dce110/dce110_hw_sequencer.h" 54 #include "dcn30/dcn30_opp.h" 55 #include "dcn20/dcn20_dsc.h" 56 #include "dcn30/dcn30_vpg.h" 57 #include "dcn30/dcn30_afmt.h" 58 #include "dcn31/dcn31_dio_link_encoder.h" 59 #include "dcn314/dcn314_dio_stream_encoder.h" 60 #include "dcn31/dcn31_hpo_dp_stream_encoder.h" 61 #include "dcn31/dcn31_hpo_dp_link_encoder.h" 62 #include "dcn31/dcn31_apg.h" 63 #include "dcn31/dcn31_vpg.h" 64 #include "dcn31/dcn31_afmt.h" 65 #include "dce/dce_clock_source.h" 66 #include "dce/dce_audio.h" 67 #include "dce/dce_hwseq.h" 68 #include "clk_mgr.h" 69 #include "virtual/virtual_stream_encoder.h" 70 #include "dce110/dce110_resource.h" 71 #include "dml/display_mode_vba.h" 72 #include "dml/dcn31/dcn31_fpu.h" 73 #include "dcn314/dcn314_dccg.h" 74 #include "dcn10/dcn10_resource.h" 75 #include "dcn31/dcn31_panel_cntl.h" 76 #include "dcn314/dcn314_hwseq.h" 77 78 #include "dcn30/dcn30_dwb.h" 79 #include "dcn30/dcn30_mmhubbub.h" 80 81 #include "dcn/dcn_3_1_4_offset.h" 82 #include "dcn/dcn_3_1_4_sh_mask.h" 83 #include "dpcs/dpcs_3_1_4_offset.h" 84 #include "dpcs/dpcs_3_1_4_sh_mask.h" 85 86 #define DCHUBBUB_DEBUG_CTRL_0__DET_DEPTH__SHIFT 0x10 87 #define DCHUBBUB_DEBUG_CTRL_0__DET_DEPTH_MASK 0x01FF0000L 88 89 #include "reg_helper.h" 90 #include "dce/dmub_abm.h" 91 #include "dce/dmub_psr.h" 92 #include "dce/dce_aux.h" 93 #include "dce/dce_i2c.h" 94 #include "dml/dcn314/display_mode_vba_314.h" 95 #include "vm_helper.h" 96 #include "dcn20/dcn20_vmid.h" 97 98 #include "link_enc_cfg.h" 99 100 #define DCN_BASE__INST0_SEG1 0x000000C0 101 #define DCN_BASE__INST0_SEG2 0x000034C0 102 #define DCN_BASE__INST0_SEG3 0x00009000 103 104 #define NBIO_BASE__INST0_SEG1 0x00000014 105 106 #define MAX_INSTANCE 7 107 #define MAX_SEGMENT 8 108 109 #define regBIF_BX2_BIOS_SCRATCH_2 0x003a 110 #define regBIF_BX2_BIOS_SCRATCH_2_BASE_IDX 1 111 #define regBIF_BX2_BIOS_SCRATCH_3 0x003b 112 #define regBIF_BX2_BIOS_SCRATCH_3_BASE_IDX 1 113 #define regBIF_BX2_BIOS_SCRATCH_6 0x003e 114 #define regBIF_BX2_BIOS_SCRATCH_6_BASE_IDX 1 115 116 struct IP_BASE_INSTANCE { 117 unsigned int segment[MAX_SEGMENT]; 118 }; 119 120 struct IP_BASE { 121 struct IP_BASE_INSTANCE instance[MAX_INSTANCE]; 122 }; 123 124 static const struct IP_BASE DCN_BASE = { { { { 0x00000012, 0x000000C0, 0x000034C0, 0x00009000, 0x02403C00, 0, 0, 0 } }, 125 { { 0, 0, 0, 0, 0, 0, 0, 0 } }, 126 { { 0, 0, 0, 0, 0, 0, 0, 0 } }, 127 { { 0, 0, 0, 0, 0, 0, 0, 0 } }, 128 { { 0, 0, 0, 0, 0, 0, 0, 0 } }, 129 { { 0, 0, 0, 0, 0, 0, 0, 0 } }, 130 { { 0, 0, 0, 0, 0, 0, 0, 0 } } } }; 131 132 133 #define DC_LOGGER_INIT(logger) 134 135 #define DCN3_14_DEFAULT_DET_SIZE 384 136 #define DCN3_14_MAX_DET_SIZE 384 137 #define DCN3_14_MIN_COMPBUF_SIZE_KB 128 138 #define DCN3_14_CRB_SEGMENT_SIZE_KB 64 139 struct _vcs_dpi_ip_params_st dcn3_14_ip = { 140 .VBlankNomDefaultUS = 668, 141 .gpuvm_enable = 1, 142 .gpuvm_max_page_table_levels = 1, 143 .hostvm_enable = 1, 144 .hostvm_max_page_table_levels = 2, 145 .rob_buffer_size_kbytes = 64, 146 .det_buffer_size_kbytes = DCN3_14_DEFAULT_DET_SIZE, 147 .config_return_buffer_size_in_kbytes = 1792, 148 .compressed_buffer_segment_size_in_kbytes = 64, 149 .meta_fifo_size_in_kentries = 32, 150 .zero_size_buffer_entries = 512, 151 .compbuf_reserved_space_64b = 256, 152 .compbuf_reserved_space_zs = 64, 153 .dpp_output_buffer_pixels = 2560, 154 .opp_output_buffer_lines = 1, 155 .pixel_chunk_size_kbytes = 8, 156 .meta_chunk_size_kbytes = 2, 157 .min_meta_chunk_size_bytes = 256, 158 .writeback_chunk_size_kbytes = 8, 159 .ptoi_supported = false, 160 .num_dsc = 4, 161 .maximum_dsc_bits_per_component = 10, 162 .dsc422_native_support = false, 163 .is_line_buffer_bpp_fixed = true, 164 .line_buffer_fixed_bpp = 48, 165 .line_buffer_size_bits = 789504, 166 .max_line_buffer_lines = 12, 167 .writeback_interface_buffer_size_kbytes = 90, 168 .max_num_dpp = 4, 169 .max_num_otg = 4, 170 .max_num_hdmi_frl_outputs = 1, 171 .max_num_wb = 1, 172 .max_dchub_pscl_bw_pix_per_clk = 4, 173 .max_pscl_lb_bw_pix_per_clk = 2, 174 .max_lb_vscl_bw_pix_per_clk = 4, 175 .max_vscl_hscl_bw_pix_per_clk = 4, 176 .max_hscl_ratio = 6, 177 .max_vscl_ratio = 6, 178 .max_hscl_taps = 8, 179 .max_vscl_taps = 8, 180 .dpte_buffer_size_in_pte_reqs_luma = 64, 181 .dpte_buffer_size_in_pte_reqs_chroma = 34, 182 .dispclk_ramp_margin_percent = 1, 183 .max_inter_dcn_tile_repeaters = 8, 184 .cursor_buffer_size = 16, 185 .cursor_chunk_size = 2, 186 .writeback_line_buffer_buffer_size = 0, 187 .writeback_min_hscl_ratio = 1, 188 .writeback_min_vscl_ratio = 1, 189 .writeback_max_hscl_ratio = 1, 190 .writeback_max_vscl_ratio = 1, 191 .writeback_max_hscl_taps = 1, 192 .writeback_max_vscl_taps = 1, 193 .dppclk_delay_subtotal = 46, 194 .dppclk_delay_scl = 50, 195 .dppclk_delay_scl_lb_only = 16, 196 .dppclk_delay_cnvc_formatter = 27, 197 .dppclk_delay_cnvc_cursor = 6, 198 .dispclk_delay_subtotal = 119, 199 .dynamic_metadata_vm_enabled = false, 200 .odm_combine_4to1_supported = false, 201 .dcc_supported = true, 202 }; 203 204 struct _vcs_dpi_soc_bounding_box_st dcn3_14_soc = { 205 /*TODO: correct dispclk/dppclk voltage level determination*/ 206 .clock_limits = { 207 { 208 .state = 0, 209 .dispclk_mhz = 1200.0, 210 .dppclk_mhz = 1200.0, 211 .phyclk_mhz = 600.0, 212 .phyclk_d18_mhz = 667.0, 213 .dscclk_mhz = 186.0, 214 .dtbclk_mhz = 625.0, 215 }, 216 { 217 .state = 1, 218 .dispclk_mhz = 1200.0, 219 .dppclk_mhz = 1200.0, 220 .phyclk_mhz = 810.0, 221 .phyclk_d18_mhz = 667.0, 222 .dscclk_mhz = 209.0, 223 .dtbclk_mhz = 625.0, 224 }, 225 { 226 .state = 2, 227 .dispclk_mhz = 1200.0, 228 .dppclk_mhz = 1200.0, 229 .phyclk_mhz = 810.0, 230 .phyclk_d18_mhz = 667.0, 231 .dscclk_mhz = 209.0, 232 .dtbclk_mhz = 625.0, 233 }, 234 { 235 .state = 3, 236 .dispclk_mhz = 1200.0, 237 .dppclk_mhz = 1200.0, 238 .phyclk_mhz = 810.0, 239 .phyclk_d18_mhz = 667.0, 240 .dscclk_mhz = 371.0, 241 .dtbclk_mhz = 625.0, 242 }, 243 { 244 .state = 4, 245 .dispclk_mhz = 1200.0, 246 .dppclk_mhz = 1200.0, 247 .phyclk_mhz = 810.0, 248 .phyclk_d18_mhz = 667.0, 249 .dscclk_mhz = 417.0, 250 .dtbclk_mhz = 625.0, 251 }, 252 }, 253 .num_states = 5, 254 .sr_exit_time_us = 9.0, 255 .sr_enter_plus_exit_time_us = 11.0, 256 .sr_exit_z8_time_us = 442.0, 257 .sr_enter_plus_exit_z8_time_us = 560.0, 258 .writeback_latency_us = 12.0, 259 .dram_channel_width_bytes = 4, 260 .round_trip_ping_latency_dcfclk_cycles = 106, 261 .urgent_latency_pixel_data_only_us = 4.0, 262 .urgent_latency_pixel_mixed_with_vm_data_us = 4.0, 263 .urgent_latency_vm_data_only_us = 4.0, 264 .urgent_out_of_order_return_per_channel_pixel_only_bytes = 4096, 265 .urgent_out_of_order_return_per_channel_pixel_and_vm_bytes = 4096, 266 .urgent_out_of_order_return_per_channel_vm_only_bytes = 4096, 267 .pct_ideal_sdp_bw_after_urgent = 80.0, 268 .pct_ideal_dram_sdp_bw_after_urgent_pixel_only = 65.0, 269 .pct_ideal_dram_sdp_bw_after_urgent_pixel_and_vm = 60.0, 270 .pct_ideal_dram_sdp_bw_after_urgent_vm_only = 30.0, 271 .max_avg_sdp_bw_use_normal_percent = 60.0, 272 .max_avg_dram_bw_use_normal_percent = 60.0, 273 .fabric_datapath_to_dcn_data_return_bytes = 32, 274 .return_bus_width_bytes = 64, 275 .downspread_percent = 0.38, 276 .dcn_downspread_percent = 0.5, 277 .gpuvm_min_page_size_bytes = 4096, 278 .hostvm_min_page_size_bytes = 4096, 279 .do_urgent_latency_adjustment = false, 280 .urgent_latency_adjustment_fabric_clock_component_us = 0, 281 .urgent_latency_adjustment_fabric_clock_reference_mhz = 0, 282 }; 283 284 enum dcn31_clk_src_array_id { 285 DCN31_CLK_SRC_PLL0, 286 DCN31_CLK_SRC_PLL1, 287 DCN31_CLK_SRC_PLL2, 288 DCN31_CLK_SRC_PLL3, 289 DCN31_CLK_SRC_PLL4, 290 DCN30_CLK_SRC_TOTAL 291 }; 292 293 /* begin ********************* 294 * macros to expend register list macro defined in HW object header file 295 */ 296 297 /* DCN */ 298 /* TODO awful hack. fixup dcn20_dwb.h */ 299 #undef BASE_INNER 300 #define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg 301 302 #define BASE(seg) BASE_INNER(seg) 303 304 #define SR(reg_name)\ 305 .reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \ 306 reg ## reg_name 307 308 #define SRI(reg_name, block, id)\ 309 .reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 310 reg ## block ## id ## _ ## reg_name 311 312 #define SRI2(reg_name, block, id)\ 313 .reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \ 314 reg ## reg_name 315 316 #define SRIR(var_name, reg_name, block, id)\ 317 .var_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 318 reg ## block ## id ## _ ## reg_name 319 320 #define SRII(reg_name, block, id)\ 321 .reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 322 reg ## block ## id ## _ ## reg_name 323 324 #define SRII_MPC_RMU(reg_name, block, id)\ 325 .RMU##_##reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 326 reg ## block ## id ## _ ## reg_name 327 328 #define SRII_DWB(reg_name, temp_name, block, id)\ 329 .reg_name[id] = BASE(reg ## block ## id ## _ ## temp_name ## _BASE_IDX) + \ 330 reg ## block ## id ## _ ## temp_name 331 332 #define DCCG_SRII(reg_name, block, id)\ 333 .block ## _ ## reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 334 reg ## block ## id ## _ ## reg_name 335 336 #define VUPDATE_SRII(reg_name, block, id)\ 337 .reg_name[id] = BASE(reg ## reg_name ## _ ## block ## id ## _BASE_IDX) + \ 338 reg ## reg_name ## _ ## block ## id 339 340 /* NBIO */ 341 #define NBIO_BASE_INNER(seg) \ 342 NBIO_BASE__INST0_SEG ## seg 343 344 #define NBIO_BASE(seg) \ 345 NBIO_BASE_INNER(seg) 346 347 #define NBIO_SR(reg_name)\ 348 .reg_name = NBIO_BASE(regBIF_BX2_ ## reg_name ## _BASE_IDX) + \ 349 regBIF_BX2_ ## reg_name 350 351 /* MMHUB */ 352 #define MMHUB_BASE_INNER(seg) \ 353 MMHUB_BASE__INST0_SEG ## seg 354 355 #define MMHUB_BASE(seg) \ 356 MMHUB_BASE_INNER(seg) 357 358 #define MMHUB_SR(reg_name)\ 359 .reg_name = MMHUB_BASE(reg ## reg_name ## _BASE_IDX) + \ 360 reg ## reg_name 361 362 /* CLOCK */ 363 #define CLK_BASE_INNER(seg) \ 364 CLK_BASE__INST0_SEG ## seg 365 366 #define CLK_BASE(seg) \ 367 CLK_BASE_INNER(seg) 368 369 #define CLK_SRI(reg_name, block, inst)\ 370 .reg_name = CLK_BASE(reg ## block ## _ ## inst ## _ ## reg_name ## _BASE_IDX) + \ 371 reg ## block ## _ ## inst ## _ ## reg_name 372 373 374 static const struct bios_registers bios_regs = { 375 NBIO_SR(BIOS_SCRATCH_3), 376 NBIO_SR(BIOS_SCRATCH_6) 377 }; 378 379 #define clk_src_regs(index, pllid)\ 380 [index] = {\ 381 CS_COMMON_REG_LIST_DCN3_0(index, pllid),\ 382 } 383 384 static const struct dce110_clk_src_regs clk_src_regs[] = { 385 clk_src_regs(0, A), 386 clk_src_regs(1, B), 387 clk_src_regs(2, C), 388 clk_src_regs(3, D), 389 clk_src_regs(4, E) 390 }; 391 392 static const struct dce110_clk_src_shift cs_shift = { 393 CS_COMMON_MASK_SH_LIST_DCN3_1_4(__SHIFT) 394 }; 395 396 static const struct dce110_clk_src_mask cs_mask = { 397 CS_COMMON_MASK_SH_LIST_DCN3_1_4(_MASK) 398 }; 399 400 #define abm_regs(id)\ 401 [id] = {\ 402 ABM_DCN302_REG_LIST(id)\ 403 } 404 405 static const struct dce_abm_registers abm_regs[] = { 406 abm_regs(0), 407 abm_regs(1), 408 abm_regs(2), 409 abm_regs(3), 410 }; 411 412 static const struct dce_abm_shift abm_shift = { 413 ABM_MASK_SH_LIST_DCN30(__SHIFT) 414 }; 415 416 static const struct dce_abm_mask abm_mask = { 417 ABM_MASK_SH_LIST_DCN30(_MASK) 418 }; 419 420 #define audio_regs(id)\ 421 [id] = {\ 422 AUD_COMMON_REG_LIST(id)\ 423 } 424 425 static const struct dce_audio_registers audio_regs[] = { 426 audio_regs(0), 427 audio_regs(1), 428 audio_regs(2), 429 audio_regs(3), 430 audio_regs(4), 431 audio_regs(5), 432 audio_regs(6) 433 }; 434 435 #define DCE120_AUD_COMMON_MASK_SH_LIST(mask_sh)\ 436 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX, AZALIA_ENDPOINT_REG_INDEX, mask_sh),\ 437 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA, AZALIA_ENDPOINT_REG_DATA, mask_sh),\ 438 AUD_COMMON_MASK_SH_LIST_BASE(mask_sh) 439 440 static const struct dce_audio_shift audio_shift = { 441 DCE120_AUD_COMMON_MASK_SH_LIST(__SHIFT) 442 }; 443 444 static const struct dce_audio_mask audio_mask = { 445 DCE120_AUD_COMMON_MASK_SH_LIST(_MASK) 446 }; 447 448 #define vpg_regs(id)\ 449 [id] = {\ 450 VPG_DCN31_REG_LIST(id)\ 451 } 452 453 static const struct dcn31_vpg_registers vpg_regs[] = { 454 vpg_regs(0), 455 vpg_regs(1), 456 vpg_regs(2), 457 vpg_regs(3), 458 vpg_regs(4), 459 vpg_regs(5), 460 vpg_regs(6), 461 vpg_regs(7), 462 vpg_regs(8), 463 vpg_regs(9), 464 }; 465 466 static const struct dcn31_vpg_shift vpg_shift = { 467 DCN31_VPG_MASK_SH_LIST(__SHIFT) 468 }; 469 470 static const struct dcn31_vpg_mask vpg_mask = { 471 DCN31_VPG_MASK_SH_LIST(_MASK) 472 }; 473 474 #define afmt_regs(id)\ 475 [id] = {\ 476 AFMT_DCN31_REG_LIST(id)\ 477 } 478 479 static const struct dcn31_afmt_registers afmt_regs[] = { 480 afmt_regs(0), 481 afmt_regs(1), 482 afmt_regs(2), 483 afmt_regs(3), 484 afmt_regs(4), 485 afmt_regs(5) 486 }; 487 488 static const struct dcn31_afmt_shift afmt_shift = { 489 DCN31_AFMT_MASK_SH_LIST(__SHIFT) 490 }; 491 492 static const struct dcn31_afmt_mask afmt_mask = { 493 DCN31_AFMT_MASK_SH_LIST(_MASK) 494 }; 495 496 #define apg_regs(id)\ 497 [id] = {\ 498 APG_DCN31_REG_LIST(id)\ 499 } 500 501 static const struct dcn31_apg_registers apg_regs[] = { 502 apg_regs(0), 503 apg_regs(1), 504 apg_regs(2), 505 apg_regs(3) 506 }; 507 508 static const struct dcn31_apg_shift apg_shift = { 509 DCN31_APG_MASK_SH_LIST(__SHIFT) 510 }; 511 512 static const struct dcn31_apg_mask apg_mask = { 513 DCN31_APG_MASK_SH_LIST(_MASK) 514 }; 515 516 #define stream_enc_regs(id)\ 517 [id] = {\ 518 SE_DCN314_REG_LIST(id)\ 519 } 520 521 static const struct dcn10_stream_enc_registers stream_enc_regs[] = { 522 stream_enc_regs(0), 523 stream_enc_regs(1), 524 stream_enc_regs(2), 525 stream_enc_regs(3), 526 stream_enc_regs(4) 527 }; 528 529 static const struct dcn10_stream_encoder_shift se_shift = { 530 SE_COMMON_MASK_SH_LIST_DCN314(__SHIFT) 531 }; 532 533 static const struct dcn10_stream_encoder_mask se_mask = { 534 SE_COMMON_MASK_SH_LIST_DCN314(_MASK) 535 }; 536 537 538 #define aux_regs(id)\ 539 [id] = {\ 540 DCN2_AUX_REG_LIST(id)\ 541 } 542 543 static const struct dcn10_link_enc_aux_registers link_enc_aux_regs[] = { 544 aux_regs(0), 545 aux_regs(1), 546 aux_regs(2), 547 aux_regs(3), 548 aux_regs(4) 549 }; 550 551 #define hpd_regs(id)\ 552 [id] = {\ 553 HPD_REG_LIST(id)\ 554 } 555 556 static const struct dcn10_link_enc_hpd_registers link_enc_hpd_regs[] = { 557 hpd_regs(0), 558 hpd_regs(1), 559 hpd_regs(2), 560 hpd_regs(3), 561 hpd_regs(4) 562 }; 563 564 #define link_regs(id, phyid)\ 565 [id] = {\ 566 LE_DCN31_REG_LIST(id), \ 567 UNIPHY_DCN2_REG_LIST(phyid), \ 568 } 569 570 static const struct dce110_aux_registers_shift aux_shift = { 571 DCN_AUX_MASK_SH_LIST(__SHIFT) 572 }; 573 574 static const struct dce110_aux_registers_mask aux_mask = { 575 DCN_AUX_MASK_SH_LIST(_MASK) 576 }; 577 578 static const struct dcn10_link_enc_registers link_enc_regs[] = { 579 link_regs(0, A), 580 link_regs(1, B), 581 link_regs(2, C), 582 link_regs(3, D), 583 link_regs(4, E) 584 }; 585 586 static const struct dcn10_link_enc_shift le_shift = { 587 LINK_ENCODER_MASK_SH_LIST_DCN31(__SHIFT), 588 DPCS_DCN31_MASK_SH_LIST(__SHIFT) 589 }; 590 591 static const struct dcn10_link_enc_mask le_mask = { 592 LINK_ENCODER_MASK_SH_LIST_DCN31(_MASK), 593 DPCS_DCN31_MASK_SH_LIST(_MASK) 594 }; 595 596 #define hpo_dp_stream_encoder_reg_list(id)\ 597 [id] = {\ 598 DCN3_1_HPO_DP_STREAM_ENC_REG_LIST(id)\ 599 } 600 601 static const struct dcn31_hpo_dp_stream_encoder_registers hpo_dp_stream_enc_regs[] = { 602 hpo_dp_stream_encoder_reg_list(0), 603 hpo_dp_stream_encoder_reg_list(1), 604 hpo_dp_stream_encoder_reg_list(2), 605 }; 606 607 static const struct dcn31_hpo_dp_stream_encoder_shift hpo_dp_se_shift = { 608 DCN3_1_HPO_DP_STREAM_ENC_MASK_SH_LIST(__SHIFT) 609 }; 610 611 static const struct dcn31_hpo_dp_stream_encoder_mask hpo_dp_se_mask = { 612 DCN3_1_HPO_DP_STREAM_ENC_MASK_SH_LIST(_MASK) 613 }; 614 615 616 #define hpo_dp_link_encoder_reg_list(id)\ 617 [id] = {\ 618 DCN3_1_HPO_DP_LINK_ENC_REG_LIST(id),\ 619 DCN3_1_RDPCSTX_REG_LIST(0),\ 620 DCN3_1_RDPCSTX_REG_LIST(1),\ 621 DCN3_1_RDPCSTX_REG_LIST(2),\ 622 } 623 624 static const struct dcn31_hpo_dp_link_encoder_registers hpo_dp_link_enc_regs[] = { 625 hpo_dp_link_encoder_reg_list(0), 626 hpo_dp_link_encoder_reg_list(1), 627 }; 628 629 static const struct dcn31_hpo_dp_link_encoder_shift hpo_dp_le_shift = { 630 DCN3_1_HPO_DP_LINK_ENC_MASK_SH_LIST(__SHIFT) 631 }; 632 633 static const struct dcn31_hpo_dp_link_encoder_mask hpo_dp_le_mask = { 634 DCN3_1_HPO_DP_LINK_ENC_MASK_SH_LIST(_MASK) 635 }; 636 637 #define dpp_regs(id)\ 638 [id] = {\ 639 DPP_REG_LIST_DCN30(id),\ 640 } 641 642 static const struct dcn3_dpp_registers dpp_regs[] = { 643 dpp_regs(0), 644 dpp_regs(1), 645 dpp_regs(2), 646 dpp_regs(3) 647 }; 648 649 static const struct dcn3_dpp_shift tf_shift = { 650 DPP_REG_LIST_SH_MASK_DCN30(__SHIFT) 651 }; 652 653 static const struct dcn3_dpp_mask tf_mask = { 654 DPP_REG_LIST_SH_MASK_DCN30(_MASK) 655 }; 656 657 #define opp_regs(id)\ 658 [id] = {\ 659 OPP_REG_LIST_DCN30(id),\ 660 } 661 662 static const struct dcn20_opp_registers opp_regs[] = { 663 opp_regs(0), 664 opp_regs(1), 665 opp_regs(2), 666 opp_regs(3) 667 }; 668 669 static const struct dcn20_opp_shift opp_shift = { 670 OPP_MASK_SH_LIST_DCN20(__SHIFT) 671 }; 672 673 static const struct dcn20_opp_mask opp_mask = { 674 OPP_MASK_SH_LIST_DCN20(_MASK) 675 }; 676 677 #define aux_engine_regs(id)\ 678 [id] = {\ 679 AUX_COMMON_REG_LIST0(id), \ 680 .AUXN_IMPCAL = 0, \ 681 .AUXP_IMPCAL = 0, \ 682 .AUX_RESET_MASK = DP_AUX0_AUX_CONTROL__AUX_RESET_MASK, \ 683 } 684 685 static const struct dce110_aux_registers aux_engine_regs[] = { 686 aux_engine_regs(0), 687 aux_engine_regs(1), 688 aux_engine_regs(2), 689 aux_engine_regs(3), 690 aux_engine_regs(4) 691 }; 692 693 #define dwbc_regs_dcn3(id)\ 694 [id] = {\ 695 DWBC_COMMON_REG_LIST_DCN30(id),\ 696 } 697 698 static const struct dcn30_dwbc_registers dwbc30_regs[] = { 699 dwbc_regs_dcn3(0), 700 }; 701 702 static const struct dcn30_dwbc_shift dwbc30_shift = { 703 DWBC_COMMON_MASK_SH_LIST_DCN30(__SHIFT) 704 }; 705 706 static const struct dcn30_dwbc_mask dwbc30_mask = { 707 DWBC_COMMON_MASK_SH_LIST_DCN30(_MASK) 708 }; 709 710 #define mcif_wb_regs_dcn3(id)\ 711 [id] = {\ 712 MCIF_WB_COMMON_REG_LIST_DCN30(id),\ 713 } 714 715 static const struct dcn30_mmhubbub_registers mcif_wb30_regs[] = { 716 mcif_wb_regs_dcn3(0) 717 }; 718 719 static const struct dcn30_mmhubbub_shift mcif_wb30_shift = { 720 MCIF_WB_COMMON_MASK_SH_LIST_DCN30(__SHIFT) 721 }; 722 723 static const struct dcn30_mmhubbub_mask mcif_wb30_mask = { 724 MCIF_WB_COMMON_MASK_SH_LIST_DCN30(_MASK) 725 }; 726 727 #define dsc_regsDCN314(id)\ 728 [id] = {\ 729 DSC_REG_LIST_DCN314(id)\ 730 } 731 732 static const struct dcn20_dsc_registers dsc_regs[] = { 733 dsc_regsDCN314(0), 734 dsc_regsDCN314(1), 735 dsc_regsDCN314(2), 736 dsc_regsDCN314(3) 737 }; 738 739 static const struct dcn20_dsc_shift dsc_shift = { 740 DSC_REG_LIST_SH_MASK_DCN314(__SHIFT) 741 }; 742 743 static const struct dcn20_dsc_mask dsc_mask = { 744 DSC_REG_LIST_SH_MASK_DCN314(_MASK) 745 }; 746 747 static const struct dcn30_mpc_registers mpc_regs = { 748 MPC_REG_LIST_DCN3_0(0), 749 MPC_REG_LIST_DCN3_0(1), 750 MPC_REG_LIST_DCN3_0(2), 751 MPC_REG_LIST_DCN3_0(3), 752 MPC_OUT_MUX_REG_LIST_DCN3_0(0), 753 MPC_OUT_MUX_REG_LIST_DCN3_0(1), 754 MPC_OUT_MUX_REG_LIST_DCN3_0(2), 755 MPC_OUT_MUX_REG_LIST_DCN3_0(3), 756 MPC_RMU_GLOBAL_REG_LIST_DCN3AG, 757 MPC_RMU_REG_LIST_DCN3AG(0), 758 MPC_RMU_REG_LIST_DCN3AG(1), 759 //MPC_RMU_REG_LIST_DCN3AG(2), 760 MPC_DWB_MUX_REG_LIST_DCN3_0(0), 761 }; 762 763 static const struct dcn30_mpc_shift mpc_shift = { 764 MPC_COMMON_MASK_SH_LIST_DCN30(__SHIFT) 765 }; 766 767 static const struct dcn30_mpc_mask mpc_mask = { 768 MPC_COMMON_MASK_SH_LIST_DCN30(_MASK) 769 }; 770 771 #define optc_regs(id)\ 772 [id] = {OPTC_COMMON_REG_LIST_DCN3_14(id)} 773 774 static const struct dcn_optc_registers optc_regs[] = { 775 optc_regs(0), 776 optc_regs(1), 777 optc_regs(2), 778 optc_regs(3) 779 }; 780 781 static const struct dcn_optc_shift optc_shift = { 782 OPTC_COMMON_MASK_SH_LIST_DCN3_14(__SHIFT) 783 }; 784 785 static const struct dcn_optc_mask optc_mask = { 786 OPTC_COMMON_MASK_SH_LIST_DCN3_14(_MASK) 787 }; 788 789 #define hubp_regs(id)\ 790 [id] = {\ 791 HUBP_REG_LIST_DCN30(id)\ 792 } 793 794 static const struct dcn_hubp2_registers hubp_regs[] = { 795 hubp_regs(0), 796 hubp_regs(1), 797 hubp_regs(2), 798 hubp_regs(3) 799 }; 800 801 802 static const struct dcn_hubp2_shift hubp_shift = { 803 HUBP_MASK_SH_LIST_DCN31(__SHIFT) 804 }; 805 806 static const struct dcn_hubp2_mask hubp_mask = { 807 HUBP_MASK_SH_LIST_DCN31(_MASK) 808 }; 809 static const struct dcn_hubbub_registers hubbub_reg = { 810 HUBBUB_REG_LIST_DCN31(0) 811 }; 812 813 static const struct dcn_hubbub_shift hubbub_shift = { 814 HUBBUB_MASK_SH_LIST_DCN31(__SHIFT) 815 }; 816 817 static const struct dcn_hubbub_mask hubbub_mask = { 818 HUBBUB_MASK_SH_LIST_DCN31(_MASK) 819 }; 820 821 static const struct dccg_registers dccg_regs = { 822 DCCG_REG_LIST_DCN314() 823 }; 824 825 static const struct dccg_shift dccg_shift = { 826 DCCG_MASK_SH_LIST_DCN314(__SHIFT) 827 }; 828 829 static const struct dccg_mask dccg_mask = { 830 DCCG_MASK_SH_LIST_DCN314(_MASK) 831 }; 832 833 834 #define SRII2(reg_name_pre, reg_name_post, id)\ 835 .reg_name_pre ## _ ## reg_name_post[id] = BASE(reg ## reg_name_pre \ 836 ## id ## _ ## reg_name_post ## _BASE_IDX) + \ 837 reg ## reg_name_pre ## id ## _ ## reg_name_post 838 839 840 #define HWSEQ_DCN31_REG_LIST()\ 841 SR(DCHUBBUB_GLOBAL_TIMER_CNTL), \ 842 SR(DCHUBBUB_ARB_HOSTVM_CNTL), \ 843 SR(DIO_MEM_PWR_CTRL), \ 844 SR(ODM_MEM_PWR_CTRL3), \ 845 SR(DMU_MEM_PWR_CNTL), \ 846 SR(MMHUBBUB_MEM_PWR_CNTL), \ 847 SR(DCCG_GATE_DISABLE_CNTL), \ 848 SR(DCCG_GATE_DISABLE_CNTL2), \ 849 SR(DCFCLK_CNTL),\ 850 SR(DC_MEM_GLOBAL_PWR_REQ_CNTL), \ 851 SRII(PIXEL_RATE_CNTL, OTG, 0), \ 852 SRII(PIXEL_RATE_CNTL, OTG, 1),\ 853 SRII(PIXEL_RATE_CNTL, OTG, 2),\ 854 SRII(PIXEL_RATE_CNTL, OTG, 3),\ 855 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 0),\ 856 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 1),\ 857 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 2),\ 858 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 3),\ 859 SR(MICROSECOND_TIME_BASE_DIV), \ 860 SR(MILLISECOND_TIME_BASE_DIV), \ 861 SR(DISPCLK_FREQ_CHANGE_CNTL), \ 862 SR(RBBMIF_TIMEOUT_DIS), \ 863 SR(RBBMIF_TIMEOUT_DIS_2), \ 864 SR(DCHUBBUB_CRC_CTRL), \ 865 SR(DPP_TOP0_DPP_CRC_CTRL), \ 866 SR(DPP_TOP0_DPP_CRC_VAL_B_A), \ 867 SR(DPP_TOP0_DPP_CRC_VAL_R_G), \ 868 SR(MPC_CRC_CTRL), \ 869 SR(MPC_CRC_RESULT_GB), \ 870 SR(MPC_CRC_RESULT_C), \ 871 SR(MPC_CRC_RESULT_AR), \ 872 SR(DOMAIN0_PG_CONFIG), \ 873 SR(DOMAIN1_PG_CONFIG), \ 874 SR(DOMAIN2_PG_CONFIG), \ 875 SR(DOMAIN3_PG_CONFIG), \ 876 SR(DOMAIN16_PG_CONFIG), \ 877 SR(DOMAIN17_PG_CONFIG), \ 878 SR(DOMAIN18_PG_CONFIG), \ 879 SR(DOMAIN19_PG_CONFIG), \ 880 SR(DOMAIN0_PG_STATUS), \ 881 SR(DOMAIN1_PG_STATUS), \ 882 SR(DOMAIN2_PG_STATUS), \ 883 SR(DOMAIN3_PG_STATUS), \ 884 SR(DOMAIN16_PG_STATUS), \ 885 SR(DOMAIN17_PG_STATUS), \ 886 SR(DOMAIN18_PG_STATUS), \ 887 SR(DOMAIN19_PG_STATUS), \ 888 SR(D1VGA_CONTROL), \ 889 SR(D2VGA_CONTROL), \ 890 SR(D3VGA_CONTROL), \ 891 SR(D4VGA_CONTROL), \ 892 SR(D5VGA_CONTROL), \ 893 SR(D6VGA_CONTROL), \ 894 SR(DC_IP_REQUEST_CNTL), \ 895 SR(AZALIA_AUDIO_DTO), \ 896 SR(AZALIA_CONTROLLER_CLOCK_GATING), \ 897 SR(HPO_TOP_HW_CONTROL) 898 899 static const struct dce_hwseq_registers hwseq_reg = { 900 HWSEQ_DCN31_REG_LIST() 901 }; 902 903 #define HWSEQ_DCN31_MASK_SH_LIST(mask_sh)\ 904 HWSEQ_DCN_MASK_SH_LIST(mask_sh), \ 905 HWS_SF(, DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_REFDIV, mask_sh), \ 906 HWS_SF(, DCHUBBUB_ARB_HOSTVM_CNTL, DISABLE_HOSTVM_FORCE_ALLOW_PSTATE, mask_sh), \ 907 HWS_SF(, DOMAIN0_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ 908 HWS_SF(, DOMAIN0_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ 909 HWS_SF(, DOMAIN1_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ 910 HWS_SF(, DOMAIN1_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ 911 HWS_SF(, DOMAIN2_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ 912 HWS_SF(, DOMAIN2_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ 913 HWS_SF(, DOMAIN3_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ 914 HWS_SF(, DOMAIN3_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ 915 HWS_SF(, DOMAIN16_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ 916 HWS_SF(, DOMAIN16_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ 917 HWS_SF(, DOMAIN17_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ 918 HWS_SF(, DOMAIN17_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ 919 HWS_SF(, DOMAIN18_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ 920 HWS_SF(, DOMAIN18_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ 921 HWS_SF(, DOMAIN19_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ 922 HWS_SF(, DOMAIN19_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ 923 HWS_SF(, DOMAIN0_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ 924 HWS_SF(, DOMAIN1_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ 925 HWS_SF(, DOMAIN2_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ 926 HWS_SF(, DOMAIN3_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ 927 HWS_SF(, DOMAIN16_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ 928 HWS_SF(, DOMAIN17_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ 929 HWS_SF(, DOMAIN18_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ 930 HWS_SF(, DOMAIN19_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ 931 HWS_SF(, DC_IP_REQUEST_CNTL, IP_REQUEST_EN, mask_sh), \ 932 HWS_SF(, AZALIA_AUDIO_DTO, AZALIA_AUDIO_DTO_MODULE, mask_sh), \ 933 HWS_SF(, HPO_TOP_CLOCK_CONTROL, HPO_HDMISTREAMCLK_G_GATE_DIS, mask_sh), \ 934 HWS_SF(, DMU_MEM_PWR_CNTL, DMCU_ERAM_MEM_PWR_FORCE, mask_sh), \ 935 HWS_SF(, ODM_MEM_PWR_CTRL3, ODM_MEM_UNASSIGNED_PWR_MODE, mask_sh), \ 936 HWS_SF(, ODM_MEM_PWR_CTRL3, ODM_MEM_VBLANK_PWR_MODE, mask_sh), \ 937 HWS_SF(, MMHUBBUB_MEM_PWR_CNTL, VGA_MEM_PWR_FORCE, mask_sh), \ 938 HWS_SF(, DIO_MEM_PWR_CTRL, I2C_LIGHT_SLEEP_FORCE, mask_sh), \ 939 HWS_SF(, HPO_TOP_HW_CONTROL, HPO_IO_EN, mask_sh) 940 941 static const struct dce_hwseq_shift hwseq_shift = { 942 HWSEQ_DCN31_MASK_SH_LIST(__SHIFT) 943 }; 944 945 static const struct dce_hwseq_mask hwseq_mask = { 946 HWSEQ_DCN31_MASK_SH_LIST(_MASK) 947 }; 948 #define vmid_regs(id)\ 949 [id] = {\ 950 DCN20_VMID_REG_LIST(id)\ 951 } 952 953 static const struct dcn_vmid_registers vmid_regs[] = { 954 vmid_regs(0), 955 vmid_regs(1), 956 vmid_regs(2), 957 vmid_regs(3), 958 vmid_regs(4), 959 vmid_regs(5), 960 vmid_regs(6), 961 vmid_regs(7), 962 vmid_regs(8), 963 vmid_regs(9), 964 vmid_regs(10), 965 vmid_regs(11), 966 vmid_regs(12), 967 vmid_regs(13), 968 vmid_regs(14), 969 vmid_regs(15) 970 }; 971 972 static const struct dcn20_vmid_shift vmid_shifts = { 973 DCN20_VMID_MASK_SH_LIST(__SHIFT) 974 }; 975 976 static const struct dcn20_vmid_mask vmid_masks = { 977 DCN20_VMID_MASK_SH_LIST(_MASK) 978 }; 979 980 static const struct resource_caps res_cap_dcn314 = { 981 .num_timing_generator = 4, 982 .num_opp = 4, 983 .num_video_plane = 4, 984 .num_audio = 5, 985 .num_stream_encoder = 5, 986 .num_dig_link_enc = 5, 987 .num_hpo_dp_stream_encoder = 4, 988 .num_hpo_dp_link_encoder = 2, 989 .num_pll = 5, 990 .num_dwb = 1, 991 .num_ddc = 5, 992 .num_vmid = 16, 993 .num_mpc_3dlut = 2, 994 .num_dsc = 4, 995 }; 996 997 static const struct dc_plane_cap plane_cap = { 998 .type = DC_PLANE_TYPE_DCN_UNIVERSAL, 999 .blends_with_above = true, 1000 .blends_with_below = true, 1001 .per_pixel_alpha = true, 1002 1003 .pixel_format_support = { 1004 .argb8888 = true, 1005 .nv12 = true, 1006 .fp16 = true, 1007 .p010 = true, 1008 .ayuv = false, 1009 }, 1010 1011 .max_upscale_factor = { 1012 .argb8888 = 16000, 1013 .nv12 = 16000, 1014 .fp16 = 16000 1015 }, 1016 1017 // 6:1 downscaling ratio: 1000/6 = 166.666 1018 .max_downscale_factor = { 1019 .argb8888 = 167, 1020 .nv12 = 167, 1021 .fp16 = 167 1022 }, 1023 64, 1024 64 1025 }; 1026 1027 static const struct dc_debug_options debug_defaults_drv = { 1028 .disable_z10 = true, /*hw not support it*/ 1029 .disable_dmcu = true, 1030 .force_abm_enable = false, 1031 .timing_trace = false, 1032 .clock_trace = true, 1033 .disable_pplib_clock_request = false, 1034 .pipe_split_policy = MPC_SPLIT_DYNAMIC, 1035 .force_single_disp_pipe_split = false, 1036 .disable_dcc = DCC_ENABLE, 1037 .vsr_support = true, 1038 .performance_trace = false, 1039 .max_downscale_src_width = 4096,/*upto true 4k*/ 1040 .disable_pplib_wm_range = false, 1041 .scl_reset_length10 = true, 1042 .sanity_checks = false, 1043 .underflow_assert_delay_us = 0xFFFFFFFF, 1044 .dwb_fi_phase = -1, // -1 = disable, 1045 .dmub_command_table = true, 1046 .pstate_enabled = true, 1047 .use_max_lb = true, 1048 .enable_mem_low_power = { 1049 .bits = { 1050 .vga = true, 1051 .i2c = true, 1052 .dmcu = false, // This is previously known to cause hang on S3 cycles if enabled 1053 .dscl = true, 1054 .cm = true, 1055 .mpc = true, 1056 .optc = true, 1057 .vpg = true, 1058 .afmt = true, 1059 } 1060 }, 1061 .optimize_edp_link_rate = true, 1062 .enable_sw_cntl_psr = true, 1063 .seamless_boot_odm_combine = true 1064 }; 1065 1066 static const struct dc_debug_options debug_defaults_diags = { 1067 .disable_dmcu = true, 1068 .force_abm_enable = false, 1069 .timing_trace = true, 1070 .clock_trace = true, 1071 .disable_dpp_power_gate = true, 1072 .disable_hubp_power_gate = true, 1073 .disable_clock_gate = true, 1074 .disable_pplib_clock_request = true, 1075 .disable_pplib_wm_range = true, 1076 .disable_stutter = false, 1077 .scl_reset_length10 = true, 1078 .dwb_fi_phase = -1, // -1 = disable 1079 .dmub_command_table = true, 1080 .enable_tri_buf = true, 1081 .use_max_lb = true 1082 }; 1083 1084 static void dcn31_dpp_destroy(struct dpp **dpp) 1085 { 1086 kfree(TO_DCN20_DPP(*dpp)); 1087 *dpp = NULL; 1088 } 1089 1090 static struct dpp *dcn31_dpp_create( 1091 struct dc_context *ctx, 1092 uint32_t inst) 1093 { 1094 struct dcn3_dpp *dpp = 1095 kzalloc(sizeof(struct dcn3_dpp), GFP_KERNEL); 1096 1097 if (!dpp) 1098 return NULL; 1099 1100 if (dpp3_construct(dpp, ctx, inst, 1101 &dpp_regs[inst], &tf_shift, &tf_mask)) 1102 return &dpp->base; 1103 1104 BREAK_TO_DEBUGGER(); 1105 kfree(dpp); 1106 return NULL; 1107 } 1108 1109 static struct output_pixel_processor *dcn31_opp_create( 1110 struct dc_context *ctx, uint32_t inst) 1111 { 1112 struct dcn20_opp *opp = 1113 kzalloc(sizeof(struct dcn20_opp), GFP_KERNEL); 1114 1115 if (!opp) { 1116 BREAK_TO_DEBUGGER(); 1117 return NULL; 1118 } 1119 1120 dcn20_opp_construct(opp, ctx, inst, 1121 &opp_regs[inst], &opp_shift, &opp_mask); 1122 return &opp->base; 1123 } 1124 1125 static struct dce_aux *dcn31_aux_engine_create( 1126 struct dc_context *ctx, 1127 uint32_t inst) 1128 { 1129 struct aux_engine_dce110 *aux_engine = 1130 kzalloc(sizeof(struct aux_engine_dce110), GFP_KERNEL); 1131 1132 if (!aux_engine) 1133 return NULL; 1134 1135 dce110_aux_engine_construct(aux_engine, ctx, inst, 1136 SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD, 1137 &aux_engine_regs[inst], 1138 &aux_mask, 1139 &aux_shift, 1140 ctx->dc->caps.extended_aux_timeout_support); 1141 1142 return &aux_engine->base; 1143 } 1144 #define i2c_inst_regs(id) { I2C_HW_ENGINE_COMMON_REG_LIST_DCN30(id) } 1145 1146 static const struct dce_i2c_registers i2c_hw_regs[] = { 1147 i2c_inst_regs(1), 1148 i2c_inst_regs(2), 1149 i2c_inst_regs(3), 1150 i2c_inst_regs(4), 1151 i2c_inst_regs(5), 1152 }; 1153 1154 static const struct dce_i2c_shift i2c_shifts = { 1155 I2C_COMMON_MASK_SH_LIST_DCN30(__SHIFT) 1156 }; 1157 1158 static const struct dce_i2c_mask i2c_masks = { 1159 I2C_COMMON_MASK_SH_LIST_DCN30(_MASK) 1160 }; 1161 1162 static struct dce_i2c_hw *dcn31_i2c_hw_create( 1163 struct dc_context *ctx, 1164 uint32_t inst) 1165 { 1166 struct dce_i2c_hw *dce_i2c_hw = 1167 kzalloc(sizeof(struct dce_i2c_hw), GFP_KERNEL); 1168 1169 if (!dce_i2c_hw) 1170 return NULL; 1171 1172 dcn2_i2c_hw_construct(dce_i2c_hw, ctx, inst, 1173 &i2c_hw_regs[inst], &i2c_shifts, &i2c_masks); 1174 1175 return dce_i2c_hw; 1176 } 1177 static struct mpc *dcn31_mpc_create( 1178 struct dc_context *ctx, 1179 int num_mpcc, 1180 int num_rmu) 1181 { 1182 struct dcn30_mpc *mpc30 = kzalloc(sizeof(struct dcn30_mpc), 1183 GFP_KERNEL); 1184 1185 if (!mpc30) 1186 return NULL; 1187 1188 dcn30_mpc_construct(mpc30, ctx, 1189 &mpc_regs, 1190 &mpc_shift, 1191 &mpc_mask, 1192 num_mpcc, 1193 num_rmu); 1194 1195 return &mpc30->base; 1196 } 1197 1198 static struct hubbub *dcn31_hubbub_create(struct dc_context *ctx) 1199 { 1200 int i; 1201 1202 struct dcn20_hubbub *hubbub3 = kzalloc(sizeof(struct dcn20_hubbub), 1203 GFP_KERNEL); 1204 1205 if (!hubbub3) 1206 return NULL; 1207 1208 hubbub31_construct(hubbub3, ctx, 1209 &hubbub_reg, 1210 &hubbub_shift, 1211 &hubbub_mask, 1212 dcn3_14_ip.det_buffer_size_kbytes, 1213 dcn3_14_ip.pixel_chunk_size_kbytes, 1214 dcn3_14_ip.config_return_buffer_size_in_kbytes); 1215 1216 1217 for (i = 0; i < res_cap_dcn314.num_vmid; i++) { 1218 struct dcn20_vmid *vmid = &hubbub3->vmid[i]; 1219 1220 vmid->ctx = ctx; 1221 1222 vmid->regs = &vmid_regs[i]; 1223 vmid->shifts = &vmid_shifts; 1224 vmid->masks = &vmid_masks; 1225 } 1226 1227 return &hubbub3->base; 1228 } 1229 1230 static struct timing_generator *dcn31_timing_generator_create( 1231 struct dc_context *ctx, 1232 uint32_t instance) 1233 { 1234 struct optc *tgn10 = 1235 kzalloc(sizeof(struct optc), GFP_KERNEL); 1236 1237 if (!tgn10) 1238 return NULL; 1239 1240 tgn10->base.inst = instance; 1241 tgn10->base.ctx = ctx; 1242 1243 tgn10->tg_regs = &optc_regs[instance]; 1244 tgn10->tg_shift = &optc_shift; 1245 tgn10->tg_mask = &optc_mask; 1246 1247 dcn314_timing_generator_init(tgn10); 1248 1249 return &tgn10->base; 1250 } 1251 1252 static const struct encoder_feature_support link_enc_feature = { 1253 .max_hdmi_deep_color = COLOR_DEPTH_121212, 1254 .max_hdmi_pixel_clock = 600000, 1255 .hdmi_ycbcr420_supported = true, 1256 .dp_ycbcr420_supported = true, 1257 .fec_supported = true, 1258 .flags.bits.IS_HBR2_CAPABLE = true, 1259 .flags.bits.IS_HBR3_CAPABLE = true, 1260 .flags.bits.IS_TPS3_CAPABLE = true, 1261 .flags.bits.IS_TPS4_CAPABLE = true 1262 }; 1263 1264 static struct link_encoder *dcn31_link_encoder_create( 1265 struct dc_context *ctx, 1266 const struct encoder_init_data *enc_init_data) 1267 { 1268 struct dcn20_link_encoder *enc20 = 1269 kzalloc(sizeof(struct dcn20_link_encoder), GFP_KERNEL); 1270 1271 if (!enc20) 1272 return NULL; 1273 1274 dcn31_link_encoder_construct(enc20, 1275 enc_init_data, 1276 &link_enc_feature, 1277 &link_enc_regs[enc_init_data->transmitter], 1278 &link_enc_aux_regs[enc_init_data->channel - 1], 1279 &link_enc_hpd_regs[enc_init_data->hpd_source], 1280 &le_shift, 1281 &le_mask); 1282 1283 return &enc20->enc10.base; 1284 } 1285 1286 /* Create a minimal link encoder object not associated with a particular 1287 * physical connector. 1288 * resource_funcs.link_enc_create_minimal 1289 */ 1290 static struct link_encoder *dcn31_link_enc_create_minimal( 1291 struct dc_context *ctx, enum engine_id eng_id) 1292 { 1293 struct dcn20_link_encoder *enc20; 1294 1295 if ((eng_id - ENGINE_ID_DIGA) > ctx->dc->res_pool->res_cap->num_dig_link_enc) 1296 return NULL; 1297 1298 enc20 = kzalloc(sizeof(struct dcn20_link_encoder), GFP_KERNEL); 1299 if (!enc20) 1300 return NULL; 1301 1302 dcn31_link_encoder_construct_minimal( 1303 enc20, 1304 ctx, 1305 &link_enc_feature, 1306 &link_enc_regs[eng_id - ENGINE_ID_DIGA], 1307 eng_id); 1308 1309 return &enc20->enc10.base; 1310 } 1311 1312 static struct panel_cntl *dcn31_panel_cntl_create(const struct panel_cntl_init_data *init_data) 1313 { 1314 struct dcn31_panel_cntl *panel_cntl = 1315 kzalloc(sizeof(struct dcn31_panel_cntl), GFP_KERNEL); 1316 1317 if (!panel_cntl) 1318 return NULL; 1319 1320 dcn31_panel_cntl_construct(panel_cntl, init_data); 1321 1322 return &panel_cntl->base; 1323 } 1324 1325 static void read_dce_straps( 1326 struct dc_context *ctx, 1327 struct resource_straps *straps) 1328 { 1329 generic_reg_get(ctx, regDC_PINSTRAPS + BASE(regDC_PINSTRAPS_BASE_IDX), 1330 FN(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO), &straps->dc_pinstraps_audio); 1331 1332 } 1333 1334 static struct audio *dcn31_create_audio( 1335 struct dc_context *ctx, unsigned int inst) 1336 { 1337 return dce_audio_create(ctx, inst, 1338 &audio_regs[inst], &audio_shift, &audio_mask); 1339 } 1340 1341 static struct vpg *dcn31_vpg_create( 1342 struct dc_context *ctx, 1343 uint32_t inst) 1344 { 1345 struct dcn31_vpg *vpg31 = kzalloc(sizeof(struct dcn31_vpg), GFP_KERNEL); 1346 1347 if (!vpg31) 1348 return NULL; 1349 1350 vpg31_construct(vpg31, ctx, inst, 1351 &vpg_regs[inst], 1352 &vpg_shift, 1353 &vpg_mask); 1354 1355 return &vpg31->base; 1356 } 1357 1358 static struct afmt *dcn31_afmt_create( 1359 struct dc_context *ctx, 1360 uint32_t inst) 1361 { 1362 struct dcn31_afmt *afmt31 = kzalloc(sizeof(struct dcn31_afmt), GFP_KERNEL); 1363 1364 if (!afmt31) 1365 return NULL; 1366 1367 afmt31_construct(afmt31, ctx, inst, 1368 &afmt_regs[inst], 1369 &afmt_shift, 1370 &afmt_mask); 1371 1372 // Light sleep by default, no need to power down here 1373 1374 return &afmt31->base; 1375 } 1376 1377 static struct apg *dcn31_apg_create( 1378 struct dc_context *ctx, 1379 uint32_t inst) 1380 { 1381 struct dcn31_apg *apg31 = kzalloc(sizeof(struct dcn31_apg), GFP_KERNEL); 1382 1383 if (!apg31) 1384 return NULL; 1385 1386 apg31_construct(apg31, ctx, inst, 1387 &apg_regs[inst], 1388 &apg_shift, 1389 &apg_mask); 1390 1391 return &apg31->base; 1392 } 1393 1394 static struct stream_encoder *dcn314_stream_encoder_create( 1395 enum engine_id eng_id, 1396 struct dc_context *ctx) 1397 { 1398 struct dcn10_stream_encoder *enc1; 1399 struct vpg *vpg; 1400 struct afmt *afmt; 1401 int vpg_inst; 1402 int afmt_inst; 1403 1404 /* Mapping of VPG, AFMT, DME register blocks to DIO block instance */ 1405 if (eng_id <= ENGINE_ID_DIGF) { 1406 vpg_inst = eng_id; 1407 afmt_inst = eng_id; 1408 } else 1409 return NULL; 1410 1411 enc1 = kzalloc(sizeof(struct dcn10_stream_encoder), GFP_KERNEL); 1412 vpg = dcn31_vpg_create(ctx, vpg_inst); 1413 afmt = dcn31_afmt_create(ctx, afmt_inst); 1414 1415 if (!enc1 || !vpg || !afmt) { 1416 kfree(enc1); 1417 kfree(vpg); 1418 kfree(afmt); 1419 return NULL; 1420 } 1421 1422 dcn314_dio_stream_encoder_construct(enc1, ctx, ctx->dc_bios, 1423 eng_id, vpg, afmt, 1424 &stream_enc_regs[eng_id], 1425 &se_shift, &se_mask); 1426 1427 return &enc1->base; 1428 } 1429 1430 static struct hpo_dp_stream_encoder *dcn31_hpo_dp_stream_encoder_create( 1431 enum engine_id eng_id, 1432 struct dc_context *ctx) 1433 { 1434 struct dcn31_hpo_dp_stream_encoder *hpo_dp_enc31; 1435 struct vpg *vpg; 1436 struct apg *apg; 1437 uint32_t hpo_dp_inst; 1438 uint32_t vpg_inst; 1439 uint32_t apg_inst; 1440 1441 ASSERT((eng_id >= ENGINE_ID_HPO_DP_0) && (eng_id <= ENGINE_ID_HPO_DP_3)); 1442 hpo_dp_inst = eng_id - ENGINE_ID_HPO_DP_0; 1443 1444 /* Mapping of VPG register blocks to HPO DP block instance: 1445 * VPG[6] -> HPO_DP[0] 1446 * VPG[7] -> HPO_DP[1] 1447 * VPG[8] -> HPO_DP[2] 1448 * VPG[9] -> HPO_DP[3] 1449 */ 1450 vpg_inst = hpo_dp_inst + 6; 1451 1452 /* Mapping of APG register blocks to HPO DP block instance: 1453 * APG[0] -> HPO_DP[0] 1454 * APG[1] -> HPO_DP[1] 1455 * APG[2] -> HPO_DP[2] 1456 * APG[3] -> HPO_DP[3] 1457 */ 1458 apg_inst = hpo_dp_inst; 1459 1460 /* allocate HPO stream encoder and create VPG sub-block */ 1461 hpo_dp_enc31 = kzalloc(sizeof(struct dcn31_hpo_dp_stream_encoder), GFP_KERNEL); 1462 vpg = dcn31_vpg_create(ctx, vpg_inst); 1463 apg = dcn31_apg_create(ctx, apg_inst); 1464 1465 if (!hpo_dp_enc31 || !vpg || !apg) { 1466 kfree(hpo_dp_enc31); 1467 kfree(vpg); 1468 kfree(apg); 1469 return NULL; 1470 } 1471 1472 dcn31_hpo_dp_stream_encoder_construct(hpo_dp_enc31, ctx, ctx->dc_bios, 1473 hpo_dp_inst, eng_id, vpg, apg, 1474 &hpo_dp_stream_enc_regs[hpo_dp_inst], 1475 &hpo_dp_se_shift, &hpo_dp_se_mask); 1476 1477 return &hpo_dp_enc31->base; 1478 } 1479 1480 static struct hpo_dp_link_encoder *dcn31_hpo_dp_link_encoder_create( 1481 uint8_t inst, 1482 struct dc_context *ctx) 1483 { 1484 struct dcn31_hpo_dp_link_encoder *hpo_dp_enc31; 1485 1486 /* allocate HPO link encoder */ 1487 hpo_dp_enc31 = kzalloc(sizeof(struct dcn31_hpo_dp_link_encoder), GFP_KERNEL); 1488 1489 hpo_dp_link_encoder31_construct(hpo_dp_enc31, ctx, inst, 1490 &hpo_dp_link_enc_regs[inst], 1491 &hpo_dp_le_shift, &hpo_dp_le_mask); 1492 1493 return &hpo_dp_enc31->base; 1494 } 1495 1496 static struct dce_hwseq *dcn314_hwseq_create( 1497 struct dc_context *ctx) 1498 { 1499 struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_KERNEL); 1500 1501 if (hws) { 1502 hws->ctx = ctx; 1503 hws->regs = &hwseq_reg; 1504 hws->shifts = &hwseq_shift; 1505 hws->masks = &hwseq_mask; 1506 /* DCN3.1 FPGA Workaround 1507 * Need to enable HPO DP Stream Encoder before setting OTG master enable. 1508 * To do so, move calling function enable_stream_timing to only be done AFTER calling 1509 * function core_link_enable_stream 1510 */ 1511 if (IS_FPGA_MAXIMUS_DC(ctx->dce_environment)) 1512 hws->wa.dp_hpo_and_otg_sequence = true; 1513 } 1514 return hws; 1515 } 1516 static const struct resource_create_funcs res_create_funcs = { 1517 .read_dce_straps = read_dce_straps, 1518 .create_audio = dcn31_create_audio, 1519 .create_stream_encoder = dcn314_stream_encoder_create, 1520 .create_hpo_dp_stream_encoder = dcn31_hpo_dp_stream_encoder_create, 1521 .create_hpo_dp_link_encoder = dcn31_hpo_dp_link_encoder_create, 1522 .create_hwseq = dcn314_hwseq_create, 1523 }; 1524 1525 static const struct resource_create_funcs res_create_maximus_funcs = { 1526 .read_dce_straps = NULL, 1527 .create_audio = NULL, 1528 .create_stream_encoder = NULL, 1529 .create_hpo_dp_stream_encoder = dcn31_hpo_dp_stream_encoder_create, 1530 .create_hpo_dp_link_encoder = dcn31_hpo_dp_link_encoder_create, 1531 .create_hwseq = dcn314_hwseq_create, 1532 }; 1533 1534 static void dcn314_resource_destruct(struct dcn314_resource_pool *pool) 1535 { 1536 unsigned int i; 1537 1538 for (i = 0; i < pool->base.stream_enc_count; i++) { 1539 if (pool->base.stream_enc[i] != NULL) { 1540 if (pool->base.stream_enc[i]->vpg != NULL) { 1541 kfree(DCN30_VPG_FROM_VPG(pool->base.stream_enc[i]->vpg)); 1542 pool->base.stream_enc[i]->vpg = NULL; 1543 } 1544 if (pool->base.stream_enc[i]->afmt != NULL) { 1545 kfree(DCN30_AFMT_FROM_AFMT(pool->base.stream_enc[i]->afmt)); 1546 pool->base.stream_enc[i]->afmt = NULL; 1547 } 1548 kfree(DCN10STRENC_FROM_STRENC(pool->base.stream_enc[i])); 1549 pool->base.stream_enc[i] = NULL; 1550 } 1551 } 1552 1553 for (i = 0; i < pool->base.hpo_dp_stream_enc_count; i++) { 1554 if (pool->base.hpo_dp_stream_enc[i] != NULL) { 1555 if (pool->base.hpo_dp_stream_enc[i]->vpg != NULL) { 1556 kfree(DCN30_VPG_FROM_VPG(pool->base.hpo_dp_stream_enc[i]->vpg)); 1557 pool->base.hpo_dp_stream_enc[i]->vpg = NULL; 1558 } 1559 if (pool->base.hpo_dp_stream_enc[i]->apg != NULL) { 1560 kfree(DCN31_APG_FROM_APG(pool->base.hpo_dp_stream_enc[i]->apg)); 1561 pool->base.hpo_dp_stream_enc[i]->apg = NULL; 1562 } 1563 kfree(DCN3_1_HPO_DP_STREAM_ENC_FROM_HPO_STREAM_ENC(pool->base.hpo_dp_stream_enc[i])); 1564 pool->base.hpo_dp_stream_enc[i] = NULL; 1565 } 1566 } 1567 1568 for (i = 0; i < pool->base.hpo_dp_link_enc_count; i++) { 1569 if (pool->base.hpo_dp_link_enc[i] != NULL) { 1570 kfree(DCN3_1_HPO_DP_LINK_ENC_FROM_HPO_LINK_ENC(pool->base.hpo_dp_link_enc[i])); 1571 pool->base.hpo_dp_link_enc[i] = NULL; 1572 } 1573 } 1574 1575 for (i = 0; i < pool->base.res_cap->num_dsc; i++) { 1576 if (pool->base.dscs[i] != NULL) 1577 dcn20_dsc_destroy(&pool->base.dscs[i]); 1578 } 1579 1580 if (pool->base.mpc != NULL) { 1581 kfree(TO_DCN20_MPC(pool->base.mpc)); 1582 pool->base.mpc = NULL; 1583 } 1584 if (pool->base.hubbub != NULL) { 1585 kfree(pool->base.hubbub); 1586 pool->base.hubbub = NULL; 1587 } 1588 for (i = 0; i < pool->base.pipe_count; i++) { 1589 if (pool->base.dpps[i] != NULL) 1590 dcn31_dpp_destroy(&pool->base.dpps[i]); 1591 1592 if (pool->base.ipps[i] != NULL) 1593 pool->base.ipps[i]->funcs->ipp_destroy(&pool->base.ipps[i]); 1594 1595 if (pool->base.hubps[i] != NULL) { 1596 kfree(TO_DCN20_HUBP(pool->base.hubps[i])); 1597 pool->base.hubps[i] = NULL; 1598 } 1599 1600 if (pool->base.irqs != NULL) 1601 dal_irq_service_destroy(&pool->base.irqs); 1602 } 1603 1604 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { 1605 if (pool->base.engines[i] != NULL) 1606 dce110_engine_destroy(&pool->base.engines[i]); 1607 if (pool->base.hw_i2cs[i] != NULL) { 1608 kfree(pool->base.hw_i2cs[i]); 1609 pool->base.hw_i2cs[i] = NULL; 1610 } 1611 if (pool->base.sw_i2cs[i] != NULL) { 1612 kfree(pool->base.sw_i2cs[i]); 1613 pool->base.sw_i2cs[i] = NULL; 1614 } 1615 } 1616 1617 for (i = 0; i < pool->base.res_cap->num_opp; i++) { 1618 if (pool->base.opps[i] != NULL) 1619 pool->base.opps[i]->funcs->opp_destroy(&pool->base.opps[i]); 1620 } 1621 1622 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { 1623 if (pool->base.timing_generators[i] != NULL) { 1624 kfree(DCN10TG_FROM_TG(pool->base.timing_generators[i])); 1625 pool->base.timing_generators[i] = NULL; 1626 } 1627 } 1628 1629 for (i = 0; i < pool->base.res_cap->num_dwb; i++) { 1630 if (pool->base.dwbc[i] != NULL) { 1631 kfree(TO_DCN30_DWBC(pool->base.dwbc[i])); 1632 pool->base.dwbc[i] = NULL; 1633 } 1634 if (pool->base.mcif_wb[i] != NULL) { 1635 kfree(TO_DCN30_MMHUBBUB(pool->base.mcif_wb[i])); 1636 pool->base.mcif_wb[i] = NULL; 1637 } 1638 } 1639 1640 for (i = 0; i < pool->base.audio_count; i++) { 1641 if (pool->base.audios[i]) 1642 dce_aud_destroy(&pool->base.audios[i]); 1643 } 1644 1645 for (i = 0; i < pool->base.clk_src_count; i++) { 1646 if (pool->base.clock_sources[i] != NULL) { 1647 dcn20_clock_source_destroy(&pool->base.clock_sources[i]); 1648 pool->base.clock_sources[i] = NULL; 1649 } 1650 } 1651 1652 for (i = 0; i < pool->base.res_cap->num_mpc_3dlut; i++) { 1653 if (pool->base.mpc_lut[i] != NULL) { 1654 dc_3dlut_func_release(pool->base.mpc_lut[i]); 1655 pool->base.mpc_lut[i] = NULL; 1656 } 1657 if (pool->base.mpc_shaper[i] != NULL) { 1658 dc_transfer_func_release(pool->base.mpc_shaper[i]); 1659 pool->base.mpc_shaper[i] = NULL; 1660 } 1661 } 1662 1663 if (pool->base.dp_clock_source != NULL) { 1664 dcn20_clock_source_destroy(&pool->base.dp_clock_source); 1665 pool->base.dp_clock_source = NULL; 1666 } 1667 1668 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { 1669 if (pool->base.multiple_abms[i] != NULL) 1670 dce_abm_destroy(&pool->base.multiple_abms[i]); 1671 } 1672 1673 if (pool->base.psr != NULL) 1674 dmub_psr_destroy(&pool->base.psr); 1675 1676 if (pool->base.dccg != NULL) 1677 dcn_dccg_destroy(&pool->base.dccg); 1678 } 1679 1680 static struct hubp *dcn31_hubp_create( 1681 struct dc_context *ctx, 1682 uint32_t inst) 1683 { 1684 struct dcn20_hubp *hubp2 = 1685 kzalloc(sizeof(struct dcn20_hubp), GFP_KERNEL); 1686 1687 if (!hubp2) 1688 return NULL; 1689 1690 if (hubp31_construct(hubp2, ctx, inst, 1691 &hubp_regs[inst], &hubp_shift, &hubp_mask)) 1692 return &hubp2->base; 1693 1694 BREAK_TO_DEBUGGER(); 1695 kfree(hubp2); 1696 return NULL; 1697 } 1698 1699 static bool dcn31_dwbc_create(struct dc_context *ctx, struct resource_pool *pool) 1700 { 1701 int i; 1702 uint32_t pipe_count = pool->res_cap->num_dwb; 1703 1704 for (i = 0; i < pipe_count; i++) { 1705 struct dcn30_dwbc *dwbc30 = kzalloc(sizeof(struct dcn30_dwbc), 1706 GFP_KERNEL); 1707 1708 if (!dwbc30) { 1709 dm_error("DC: failed to create dwbc30!\n"); 1710 return false; 1711 } 1712 1713 dcn30_dwbc_construct(dwbc30, ctx, 1714 &dwbc30_regs[i], 1715 &dwbc30_shift, 1716 &dwbc30_mask, 1717 i); 1718 1719 pool->dwbc[i] = &dwbc30->base; 1720 } 1721 return true; 1722 } 1723 1724 static bool dcn31_mmhubbub_create(struct dc_context *ctx, struct resource_pool *pool) 1725 { 1726 int i; 1727 uint32_t pipe_count = pool->res_cap->num_dwb; 1728 1729 for (i = 0; i < pipe_count; i++) { 1730 struct dcn30_mmhubbub *mcif_wb30 = kzalloc(sizeof(struct dcn30_mmhubbub), 1731 GFP_KERNEL); 1732 1733 if (!mcif_wb30) { 1734 dm_error("DC: failed to create mcif_wb30!\n"); 1735 return false; 1736 } 1737 1738 dcn30_mmhubbub_construct(mcif_wb30, ctx, 1739 &mcif_wb30_regs[i], 1740 &mcif_wb30_shift, 1741 &mcif_wb30_mask, 1742 i); 1743 1744 pool->mcif_wb[i] = &mcif_wb30->base; 1745 } 1746 return true; 1747 } 1748 1749 static struct display_stream_compressor *dcn314_dsc_create( 1750 struct dc_context *ctx, uint32_t inst) 1751 { 1752 struct dcn20_dsc *dsc = 1753 kzalloc(sizeof(struct dcn20_dsc), GFP_KERNEL); 1754 1755 if (!dsc) { 1756 BREAK_TO_DEBUGGER(); 1757 return NULL; 1758 } 1759 1760 dsc2_construct(dsc, ctx, inst, &dsc_regs[inst], &dsc_shift, &dsc_mask); 1761 return &dsc->base; 1762 } 1763 1764 static void dcn314_destroy_resource_pool(struct resource_pool **pool) 1765 { 1766 struct dcn314_resource_pool *dcn314_pool = TO_DCN314_RES_POOL(*pool); 1767 1768 dcn314_resource_destruct(dcn314_pool); 1769 kfree(dcn314_pool); 1770 *pool = NULL; 1771 } 1772 1773 static struct clock_source *dcn31_clock_source_create( 1774 struct dc_context *ctx, 1775 struct dc_bios *bios, 1776 enum clock_source_id id, 1777 const struct dce110_clk_src_regs *regs, 1778 bool dp_clk_src) 1779 { 1780 struct dce110_clk_src *clk_src = 1781 kzalloc(sizeof(struct dce110_clk_src), GFP_KERNEL); 1782 1783 if (!clk_src) 1784 return NULL; 1785 1786 if (dcn31_clk_src_construct(clk_src, ctx, bios, id, 1787 regs, &cs_shift, &cs_mask)) { 1788 clk_src->base.dp_clk_src = dp_clk_src; 1789 return &clk_src->base; 1790 } 1791 1792 BREAK_TO_DEBUGGER(); 1793 return NULL; 1794 } 1795 1796 static bool is_dual_plane(enum surface_pixel_format format) 1797 { 1798 return format >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN || format == SURFACE_PIXEL_FORMAT_GRPH_RGBE_ALPHA; 1799 } 1800 1801 static int dcn314_populate_dml_pipes_from_context( 1802 struct dc *dc, struct dc_state *context, 1803 display_e2e_pipe_params_st *pipes, 1804 bool fast_validate) 1805 { 1806 int i, pipe_cnt; 1807 struct resource_context *res_ctx = &context->res_ctx; 1808 struct pipe_ctx *pipe; 1809 bool upscaled = false; 1810 1811 dcn20_populate_dml_pipes_from_context(dc, context, pipes, fast_validate); 1812 1813 for (i = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) { 1814 struct dc_crtc_timing *timing; 1815 1816 if (!res_ctx->pipe_ctx[i].stream) 1817 continue; 1818 pipe = &res_ctx->pipe_ctx[i]; 1819 timing = &pipe->stream->timing; 1820 1821 if (dc_extended_blank_supported(dc) && pipe->stream->adjust.v_total_max == pipe->stream->adjust.v_total_min 1822 && pipe->stream->adjust.v_total_min > timing->v_total) 1823 pipes[pipe_cnt].pipe.dest.vtotal = pipe->stream->adjust.v_total_min; 1824 1825 if (pipe->plane_state && 1826 (pipe->plane_state->src_rect.height < pipe->plane_state->dst_rect.height || 1827 pipe->plane_state->src_rect.width < pipe->plane_state->dst_rect.width)) 1828 upscaled = true; 1829 1830 /* 1831 * Immediate flip can be set dynamically after enabling the plane. 1832 * We need to require support for immediate flip or underflow can be 1833 * intermittently experienced depending on peak b/w requirements. 1834 */ 1835 pipes[pipe_cnt].pipe.src.immediate_flip = true; 1836 1837 pipes[pipe_cnt].pipe.src.unbounded_req_mode = false; 1838 pipes[pipe_cnt].pipe.src.hostvm = dc->res_pool->hubbub->riommu_active; 1839 pipes[pipe_cnt].pipe.src.gpuvm = true; 1840 pipes[pipe_cnt].pipe.src.dcc_fraction_of_zs_req_luma = 0; 1841 pipes[pipe_cnt].pipe.src.dcc_fraction_of_zs_req_chroma = 0; 1842 pipes[pipe_cnt].pipe.dest.vfront_porch = timing->v_front_porch; 1843 pipes[pipe_cnt].pipe.src.dcc_rate = 3; 1844 pipes[pipe_cnt].dout.dsc_input_bpc = 0; 1845 1846 if (pipes[pipe_cnt].dout.dsc_enable) { 1847 switch (timing->display_color_depth) { 1848 case COLOR_DEPTH_888: 1849 pipes[pipe_cnt].dout.dsc_input_bpc = 8; 1850 break; 1851 case COLOR_DEPTH_101010: 1852 pipes[pipe_cnt].dout.dsc_input_bpc = 10; 1853 break; 1854 case COLOR_DEPTH_121212: 1855 pipes[pipe_cnt].dout.dsc_input_bpc = 12; 1856 break; 1857 default: 1858 ASSERT(0); 1859 break; 1860 } 1861 } 1862 1863 pipe_cnt++; 1864 } 1865 context->bw_ctx.dml.ip.det_buffer_size_kbytes = DCN3_14_DEFAULT_DET_SIZE; 1866 1867 dc->config.enable_4to1MPC = false; 1868 if (pipe_cnt == 1 && pipe->plane_state && !dc->debug.disable_z9_mpc) { 1869 if (is_dual_plane(pipe->plane_state->format) 1870 && pipe->plane_state->src_rect.width <= 1920 && pipe->plane_state->src_rect.height <= 1080) { 1871 dc->config.enable_4to1MPC = true; 1872 } else if (!is_dual_plane(pipe->plane_state->format) && pipe->plane_state->src_rect.width <= 5120) { 1873 /* Limit to 5k max to avoid forced pipe split when there is not enough detile for swath */ 1874 context->bw_ctx.dml.ip.det_buffer_size_kbytes = 192; 1875 pipes[0].pipe.src.unbounded_req_mode = true; 1876 } 1877 } else if (context->stream_count >= dc->debug.crb_alloc_policy_min_disp_count 1878 && dc->debug.crb_alloc_policy > DET_SIZE_DEFAULT) { 1879 context->bw_ctx.dml.ip.det_buffer_size_kbytes = dc->debug.crb_alloc_policy * 64; 1880 } else if (context->stream_count >= 3 && upscaled) { 1881 context->bw_ctx.dml.ip.det_buffer_size_kbytes = 192; 1882 } 1883 1884 for (i = 0; i < dc->res_pool->pipe_count; i++) { 1885 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; 1886 1887 if (!pipe->stream) 1888 continue; 1889 1890 if (pipe->stream->signal == SIGNAL_TYPE_EDP && dc->debug.seamless_boot_odm_combine && 1891 pipe->stream->apply_seamless_boot_optimization) { 1892 1893 if (pipe->stream->apply_boot_odm_mode == dm_odm_combine_policy_2to1) { 1894 context->bw_ctx.dml.vba.ODMCombinePolicy = dm_odm_combine_policy_2to1; 1895 break; 1896 } 1897 } 1898 } 1899 1900 return pipe_cnt; 1901 } 1902 1903 static struct dc_cap_funcs cap_funcs = { 1904 .get_dcc_compression_cap = dcn20_get_dcc_compression_cap 1905 }; 1906 1907 static void dcn314_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params) 1908 { 1909 struct clk_limit_table *clk_table = &bw_params->clk_table; 1910 struct _vcs_dpi_voltage_scaling_st *clock_tmp = dcn3_14_soc._clock_tmp; 1911 unsigned int i, closest_clk_lvl; 1912 int max_dispclk_mhz = 0, max_dppclk_mhz = 0; 1913 int j; 1914 1915 // Default clock levels are used for diags, which may lead to overclocking. 1916 if (!IS_DIAG_DC(dc->ctx->dce_environment)) { 1917 1918 dcn3_14_ip.max_num_otg = dc->res_pool->res_cap->num_timing_generator; 1919 dcn3_14_ip.max_num_dpp = dc->res_pool->pipe_count; 1920 1921 if (bw_params->num_channels > 0) 1922 dcn3_14_soc.num_chans = bw_params->num_channels; 1923 1924 ASSERT(dcn3_14_soc.num_chans); 1925 ASSERT(clk_table->num_entries); 1926 1927 /* Prepass to find max clocks independent of voltage level. */ 1928 for (i = 0; i < clk_table->num_entries; ++i) { 1929 if (clk_table->entries[i].dispclk_mhz > max_dispclk_mhz) 1930 max_dispclk_mhz = clk_table->entries[i].dispclk_mhz; 1931 if (clk_table->entries[i].dppclk_mhz > max_dppclk_mhz) 1932 max_dppclk_mhz = clk_table->entries[i].dppclk_mhz; 1933 } 1934 1935 for (i = 0; i < clk_table->num_entries; i++) { 1936 /* loop backwards*/ 1937 for (closest_clk_lvl = 0, j = dcn3_14_soc.num_states - 1; j >= 0; j--) { 1938 if ((unsigned int) dcn3_14_soc.clock_limits[j].dcfclk_mhz <= clk_table->entries[i].dcfclk_mhz) { 1939 closest_clk_lvl = j; 1940 break; 1941 } 1942 } 1943 if (clk_table->num_entries == 1) { 1944 /*smu gives one DPM level, let's take the highest one*/ 1945 closest_clk_lvl = dcn3_14_soc.num_states - 1; 1946 } 1947 1948 clock_tmp[i].state = i; 1949 1950 /* Clocks dependent on voltage level. */ 1951 clock_tmp[i].dcfclk_mhz = clk_table->entries[i].dcfclk_mhz; 1952 if (clk_table->num_entries == 1 && 1953 clock_tmp[i].dcfclk_mhz < dcn3_14_soc.clock_limits[closest_clk_lvl].dcfclk_mhz) { 1954 /*SMU fix not released yet*/ 1955 clock_tmp[i].dcfclk_mhz = dcn3_14_soc.clock_limits[closest_clk_lvl].dcfclk_mhz; 1956 } 1957 clock_tmp[i].fabricclk_mhz = clk_table->entries[i].fclk_mhz; 1958 clock_tmp[i].socclk_mhz = clk_table->entries[i].socclk_mhz; 1959 1960 if (clk_table->entries[i].memclk_mhz && clk_table->entries[i].wck_ratio) 1961 clock_tmp[i].dram_speed_mts = clk_table->entries[i].memclk_mhz * 2 * clk_table->entries[i].wck_ratio; 1962 1963 /* Clocks independent of voltage level. */ 1964 clock_tmp[i].dispclk_mhz = max_dispclk_mhz ? max_dispclk_mhz : 1965 dcn3_14_soc.clock_limits[closest_clk_lvl].dispclk_mhz; 1966 1967 clock_tmp[i].dppclk_mhz = max_dppclk_mhz ? max_dppclk_mhz : 1968 dcn3_14_soc.clock_limits[closest_clk_lvl].dppclk_mhz; 1969 1970 clock_tmp[i].dram_bw_per_chan_gbps = dcn3_14_soc.clock_limits[closest_clk_lvl].dram_bw_per_chan_gbps; 1971 clock_tmp[i].dscclk_mhz = dcn3_14_soc.clock_limits[closest_clk_lvl].dscclk_mhz; 1972 clock_tmp[i].dtbclk_mhz = dcn3_14_soc.clock_limits[closest_clk_lvl].dtbclk_mhz; 1973 clock_tmp[i].phyclk_d18_mhz = dcn3_14_soc.clock_limits[closest_clk_lvl].phyclk_d18_mhz; 1974 clock_tmp[i].phyclk_mhz = dcn3_14_soc.clock_limits[closest_clk_lvl].phyclk_mhz; 1975 } 1976 for (i = 0; i < clk_table->num_entries; i++) 1977 dcn3_14_soc.clock_limits[i] = clock_tmp[i]; 1978 if (clk_table->num_entries) 1979 dcn3_14_soc.num_states = clk_table->num_entries; 1980 } 1981 1982 if (max_dispclk_mhz) { 1983 dcn3_14_soc.dispclk_dppclk_vco_speed_mhz = max_dispclk_mhz * 2; 1984 dc->dml.soc.dispclk_dppclk_vco_speed_mhz = max_dispclk_mhz * 2; 1985 } 1986 1987 if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) 1988 dml_init_instance(&dc->dml, &dcn3_14_soc, &dcn3_14_ip, DML_PROJECT_DCN31); 1989 else 1990 dml_init_instance(&dc->dml, &dcn3_14_soc, &dcn3_14_ip, DML_PROJECT_DCN31_FPGA); 1991 } 1992 1993 static struct resource_funcs dcn314_res_pool_funcs = { 1994 .destroy = dcn314_destroy_resource_pool, 1995 .link_enc_create = dcn31_link_encoder_create, 1996 .link_enc_create_minimal = dcn31_link_enc_create_minimal, 1997 .link_encs_assign = link_enc_cfg_link_encs_assign, 1998 .link_enc_unassign = link_enc_cfg_link_enc_unassign, 1999 .panel_cntl_create = dcn31_panel_cntl_create, 2000 .validate_bandwidth = dcn31_validate_bandwidth, 2001 .calculate_wm_and_dlg = dcn31_calculate_wm_and_dlg, 2002 .update_soc_for_wm_a = dcn31_update_soc_for_wm_a, 2003 .populate_dml_pipes = dcn314_populate_dml_pipes_from_context, 2004 .acquire_idle_pipe_for_layer = dcn20_acquire_idle_pipe_for_layer, 2005 .add_stream_to_ctx = dcn30_add_stream_to_ctx, 2006 .add_dsc_to_stream_resource = dcn20_add_dsc_to_stream_resource, 2007 .remove_stream_from_ctx = dcn20_remove_stream_from_ctx, 2008 .populate_dml_writeback_from_context = dcn30_populate_dml_writeback_from_context, 2009 .set_mcif_arb_params = dcn30_set_mcif_arb_params, 2010 .find_first_free_match_stream_enc_for_link = dcn10_find_first_free_match_stream_enc_for_link, 2011 .acquire_post_bldn_3dlut = dcn30_acquire_post_bldn_3dlut, 2012 .release_post_bldn_3dlut = dcn30_release_post_bldn_3dlut, 2013 .update_bw_bounding_box = dcn314_update_bw_bounding_box, 2014 .patch_unknown_plane_state = dcn20_patch_unknown_plane_state, 2015 }; 2016 2017 static struct clock_source *dcn30_clock_source_create( 2018 struct dc_context *ctx, 2019 struct dc_bios *bios, 2020 enum clock_source_id id, 2021 const struct dce110_clk_src_regs *regs, 2022 bool dp_clk_src) 2023 { 2024 struct dce110_clk_src *clk_src = 2025 kzalloc(sizeof(struct dce110_clk_src), GFP_KERNEL); 2026 2027 if (!clk_src) 2028 return NULL; 2029 2030 if (dcn31_clk_src_construct(clk_src, ctx, bios, id, 2031 regs, &cs_shift, &cs_mask)) { 2032 clk_src->base.dp_clk_src = dp_clk_src; 2033 return &clk_src->base; 2034 } 2035 2036 BREAK_TO_DEBUGGER(); 2037 return NULL; 2038 } 2039 2040 static bool dcn314_resource_construct( 2041 uint8_t num_virtual_links, 2042 struct dc *dc, 2043 struct dcn314_resource_pool *pool) 2044 { 2045 int i; 2046 struct dc_context *ctx = dc->ctx; 2047 struct irq_service_init_data init_data; 2048 2049 ctx->dc_bios->regs = &bios_regs; 2050 2051 pool->base.res_cap = &res_cap_dcn314; 2052 pool->base.funcs = &dcn314_res_pool_funcs; 2053 2054 /************************************************* 2055 * Resource + asic cap harcoding * 2056 *************************************************/ 2057 pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE; 2058 pool->base.pipe_count = pool->base.res_cap->num_timing_generator; 2059 pool->base.mpcc_count = pool->base.res_cap->num_timing_generator; 2060 dc->caps.max_downscale_ratio = 600; 2061 dc->caps.i2c_speed_in_khz = 100; 2062 dc->caps.i2c_speed_in_khz_hdcp = 100; 2063 dc->caps.max_cursor_size = 256; 2064 dc->caps.min_horizontal_blanking_period = 80; 2065 dc->caps.dmdata_alloc_size = 2048; 2066 dc->caps.max_slave_planes = 2; 2067 dc->caps.max_slave_yuv_planes = 2; 2068 dc->caps.max_slave_rgb_planes = 2; 2069 dc->caps.post_blend_color_processing = true; 2070 dc->caps.force_dp_tps4_for_cp2520 = true; 2071 dc->caps.dp_hpo = true; 2072 dc->caps.edp_dsc_support = true; 2073 dc->caps.extended_aux_timeout_support = true; 2074 dc->caps.dmcub_support = true; 2075 dc->caps.is_apu = true; 2076 dc->caps.seamless_odm = true; 2077 2078 dc->caps.zstate_support = true; 2079 2080 /* Color pipeline capabilities */ 2081 dc->caps.color.dpp.dcn_arch = 1; 2082 dc->caps.color.dpp.input_lut_shared = 0; 2083 dc->caps.color.dpp.icsc = 1; 2084 dc->caps.color.dpp.dgam_ram = 0; // must use gamma_corr 2085 dc->caps.color.dpp.dgam_rom_caps.srgb = 1; 2086 dc->caps.color.dpp.dgam_rom_caps.bt2020 = 1; 2087 dc->caps.color.dpp.dgam_rom_caps.gamma2_2 = 1; 2088 dc->caps.color.dpp.dgam_rom_caps.pq = 1; 2089 dc->caps.color.dpp.dgam_rom_caps.hlg = 1; 2090 dc->caps.color.dpp.post_csc = 1; 2091 dc->caps.color.dpp.gamma_corr = 1; 2092 dc->caps.color.dpp.dgam_rom_for_yuv = 0; 2093 2094 dc->caps.color.dpp.hw_3d_lut = 1; 2095 dc->caps.color.dpp.ogam_ram = 1; 2096 // no OGAM ROM on DCN301 2097 dc->caps.color.dpp.ogam_rom_caps.srgb = 0; 2098 dc->caps.color.dpp.ogam_rom_caps.bt2020 = 0; 2099 dc->caps.color.dpp.ogam_rom_caps.gamma2_2 = 0; 2100 dc->caps.color.dpp.ogam_rom_caps.pq = 0; 2101 dc->caps.color.dpp.ogam_rom_caps.hlg = 0; 2102 dc->caps.color.dpp.ocsc = 0; 2103 2104 dc->caps.color.mpc.gamut_remap = 1; 2105 dc->caps.color.mpc.num_3dluts = pool->base.res_cap->num_mpc_3dlut; //2 2106 dc->caps.color.mpc.ogam_ram = 1; 2107 dc->caps.color.mpc.ogam_rom_caps.srgb = 0; 2108 dc->caps.color.mpc.ogam_rom_caps.bt2020 = 0; 2109 dc->caps.color.mpc.ogam_rom_caps.gamma2_2 = 0; 2110 dc->caps.color.mpc.ogam_rom_caps.pq = 0; 2111 dc->caps.color.mpc.ogam_rom_caps.hlg = 0; 2112 dc->caps.color.mpc.ocsc = 1; 2113 2114 /* Use pipe context based otg sync logic */ 2115 dc->config.use_pipe_ctx_sync_logic = true; 2116 2117 /* read VBIOS LTTPR caps */ 2118 { 2119 if (ctx->dc_bios->funcs->get_lttpr_caps) { 2120 enum bp_result bp_query_result; 2121 uint8_t is_vbios_lttpr_enable = 0; 2122 2123 bp_query_result = ctx->dc_bios->funcs->get_lttpr_caps(ctx->dc_bios, &is_vbios_lttpr_enable); 2124 dc->caps.vbios_lttpr_enable = (bp_query_result == BP_RESULT_OK) && !!is_vbios_lttpr_enable; 2125 } 2126 2127 /* interop bit is implicit */ 2128 { 2129 dc->caps.vbios_lttpr_aware = true; 2130 } 2131 } 2132 2133 if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV) 2134 dc->debug = debug_defaults_drv; 2135 else if (dc->ctx->dce_environment == DCE_ENV_FPGA_MAXIMUS) 2136 dc->debug = debug_defaults_diags; 2137 else 2138 dc->debug = debug_defaults_diags; 2139 // Init the vm_helper 2140 if (dc->vm_helper) 2141 vm_helper_init(dc->vm_helper, 16); 2142 2143 /************************************************* 2144 * Create resources * 2145 *************************************************/ 2146 2147 /* Clock Sources for Pixel Clock*/ 2148 pool->base.clock_sources[DCN31_CLK_SRC_PLL0] = 2149 dcn30_clock_source_create(ctx, ctx->dc_bios, 2150 CLOCK_SOURCE_COMBO_PHY_PLL0, 2151 &clk_src_regs[0], false); 2152 pool->base.clock_sources[DCN31_CLK_SRC_PLL1] = 2153 dcn30_clock_source_create(ctx, ctx->dc_bios, 2154 CLOCK_SOURCE_COMBO_PHY_PLL1, 2155 &clk_src_regs[1], false); 2156 pool->base.clock_sources[DCN31_CLK_SRC_PLL2] = 2157 dcn30_clock_source_create(ctx, ctx->dc_bios, 2158 CLOCK_SOURCE_COMBO_PHY_PLL2, 2159 &clk_src_regs[2], false); 2160 pool->base.clock_sources[DCN31_CLK_SRC_PLL3] = 2161 dcn30_clock_source_create(ctx, ctx->dc_bios, 2162 CLOCK_SOURCE_COMBO_PHY_PLL3, 2163 &clk_src_regs[3], false); 2164 pool->base.clock_sources[DCN31_CLK_SRC_PLL4] = 2165 dcn30_clock_source_create(ctx, ctx->dc_bios, 2166 CLOCK_SOURCE_COMBO_PHY_PLL4, 2167 &clk_src_regs[4], false); 2168 2169 pool->base.clk_src_count = DCN30_CLK_SRC_TOTAL; 2170 2171 /* todo: not reuse phy_pll registers */ 2172 pool->base.dp_clock_source = 2173 dcn31_clock_source_create(ctx, ctx->dc_bios, 2174 CLOCK_SOURCE_ID_DP_DTO, 2175 &clk_src_regs[0], true); 2176 2177 for (i = 0; i < pool->base.clk_src_count; i++) { 2178 if (pool->base.clock_sources[i] == NULL) { 2179 dm_error("DC: failed to create clock sources!\n"); 2180 BREAK_TO_DEBUGGER(); 2181 goto create_fail; 2182 } 2183 } 2184 2185 pool->base.dccg = dccg314_create(ctx, &dccg_regs, &dccg_shift, &dccg_mask); 2186 if (pool->base.dccg == NULL) { 2187 dm_error("DC: failed to create dccg!\n"); 2188 BREAK_TO_DEBUGGER(); 2189 goto create_fail; 2190 } 2191 2192 init_data.ctx = dc->ctx; 2193 pool->base.irqs = dal_irq_service_dcn314_create(&init_data); 2194 if (!pool->base.irqs) 2195 goto create_fail; 2196 2197 /* HUBBUB */ 2198 pool->base.hubbub = dcn31_hubbub_create(ctx); 2199 if (pool->base.hubbub == NULL) { 2200 BREAK_TO_DEBUGGER(); 2201 dm_error("DC: failed to create hubbub!\n"); 2202 goto create_fail; 2203 } 2204 2205 /* HUBPs, DPPs, OPPs and TGs */ 2206 for (i = 0; i < pool->base.pipe_count; i++) { 2207 pool->base.hubps[i] = dcn31_hubp_create(ctx, i); 2208 if (pool->base.hubps[i] == NULL) { 2209 BREAK_TO_DEBUGGER(); 2210 dm_error( 2211 "DC: failed to create hubps!\n"); 2212 goto create_fail; 2213 } 2214 2215 pool->base.dpps[i] = dcn31_dpp_create(ctx, i); 2216 if (pool->base.dpps[i] == NULL) { 2217 BREAK_TO_DEBUGGER(); 2218 dm_error( 2219 "DC: failed to create dpps!\n"); 2220 goto create_fail; 2221 } 2222 } 2223 2224 for (i = 0; i < pool->base.res_cap->num_opp; i++) { 2225 pool->base.opps[i] = dcn31_opp_create(ctx, i); 2226 if (pool->base.opps[i] == NULL) { 2227 BREAK_TO_DEBUGGER(); 2228 dm_error( 2229 "DC: failed to create output pixel processor!\n"); 2230 goto create_fail; 2231 } 2232 } 2233 2234 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { 2235 pool->base.timing_generators[i] = dcn31_timing_generator_create( 2236 ctx, i); 2237 if (pool->base.timing_generators[i] == NULL) { 2238 BREAK_TO_DEBUGGER(); 2239 dm_error("DC: failed to create tg!\n"); 2240 goto create_fail; 2241 } 2242 } 2243 pool->base.timing_generator_count = i; 2244 2245 /* PSR */ 2246 pool->base.psr = dmub_psr_create(ctx); 2247 if (pool->base.psr == NULL) { 2248 dm_error("DC: failed to create psr obj!\n"); 2249 BREAK_TO_DEBUGGER(); 2250 goto create_fail; 2251 } 2252 2253 /* ABM */ 2254 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { 2255 pool->base.multiple_abms[i] = dmub_abm_create(ctx, 2256 &abm_regs[i], 2257 &abm_shift, 2258 &abm_mask); 2259 if (pool->base.multiple_abms[i] == NULL) { 2260 dm_error("DC: failed to create abm for pipe %d!\n", i); 2261 BREAK_TO_DEBUGGER(); 2262 goto create_fail; 2263 } 2264 } 2265 2266 /* MPC and DSC */ 2267 pool->base.mpc = dcn31_mpc_create(ctx, pool->base.mpcc_count, pool->base.res_cap->num_mpc_3dlut); 2268 if (pool->base.mpc == NULL) { 2269 BREAK_TO_DEBUGGER(); 2270 dm_error("DC: failed to create mpc!\n"); 2271 goto create_fail; 2272 } 2273 2274 for (i = 0; i < pool->base.res_cap->num_dsc; i++) { 2275 pool->base.dscs[i] = dcn314_dsc_create(ctx, i); 2276 if (pool->base.dscs[i] == NULL) { 2277 BREAK_TO_DEBUGGER(); 2278 dm_error("DC: failed to create display stream compressor %d!\n", i); 2279 goto create_fail; 2280 } 2281 } 2282 2283 /* DWB and MMHUBBUB */ 2284 if (!dcn31_dwbc_create(ctx, &pool->base)) { 2285 BREAK_TO_DEBUGGER(); 2286 dm_error("DC: failed to create dwbc!\n"); 2287 goto create_fail; 2288 } 2289 2290 if (!dcn31_mmhubbub_create(ctx, &pool->base)) { 2291 BREAK_TO_DEBUGGER(); 2292 dm_error("DC: failed to create mcif_wb!\n"); 2293 goto create_fail; 2294 } 2295 2296 /* AUX and I2C */ 2297 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { 2298 pool->base.engines[i] = dcn31_aux_engine_create(ctx, i); 2299 if (pool->base.engines[i] == NULL) { 2300 BREAK_TO_DEBUGGER(); 2301 dm_error( 2302 "DC:failed to create aux engine!!\n"); 2303 goto create_fail; 2304 } 2305 pool->base.hw_i2cs[i] = dcn31_i2c_hw_create(ctx, i); 2306 if (pool->base.hw_i2cs[i] == NULL) { 2307 BREAK_TO_DEBUGGER(); 2308 dm_error( 2309 "DC:failed to create hw i2c!!\n"); 2310 goto create_fail; 2311 } 2312 pool->base.sw_i2cs[i] = NULL; 2313 } 2314 2315 /* DCN314 has 4 DPIA */ 2316 pool->base.usb4_dpia_count = 4; 2317 2318 /* Audio, Stream Encoders including HPO and virtual, MPC 3D LUTs */ 2319 if (!resource_construct(num_virtual_links, dc, &pool->base, 2320 (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment) ? 2321 &res_create_funcs : &res_create_maximus_funcs))) 2322 goto create_fail; 2323 2324 /* HW Sequencer and Plane caps */ 2325 dcn314_hw_sequencer_construct(dc); 2326 2327 dc->caps.max_planes = pool->base.pipe_count; 2328 2329 for (i = 0; i < dc->caps.max_planes; ++i) 2330 dc->caps.planes[i] = plane_cap; 2331 2332 dc->cap_funcs = cap_funcs; 2333 2334 dc->dcn_ip->max_num_dpp = dcn3_14_ip.max_num_dpp; 2335 2336 return true; 2337 2338 create_fail: 2339 2340 dcn314_resource_destruct(pool); 2341 2342 return false; 2343 } 2344 2345 struct resource_pool *dcn314_create_resource_pool( 2346 const struct dc_init_data *init_data, 2347 struct dc *dc) 2348 { 2349 struct dcn314_resource_pool *pool = 2350 kzalloc(sizeof(struct dcn314_resource_pool), GFP_KERNEL); 2351 2352 if (!pool) 2353 return NULL; 2354 2355 if (dcn314_resource_construct(init_data->num_virtual_links, dc, pool)) 2356 return &pool->base; 2357 2358 BREAK_TO_DEBUGGER(); 2359 kfree(pool); 2360 return NULL; 2361 } 2362