1 // SPDX-License-Identifier: MIT
2 /*
3  * Copyright 2022 Advanced Micro Devices, Inc.
4  *
5  * Permission is hereby granted, free of charge, to any person obtaining a
6  * copy of this software and associated documentation files (the "Software"),
7  * to deal in the Software without restriction, including without limitation
8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9  * and/or sell copies of the Software, and to permit persons to whom the
10  * Software is furnished to do so, subject to the following conditions:
11  *
12  * The above copyright notice and this permission notice shall be included in
13  * all copies or substantial portions of the Software.
14  *
15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
18  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21  * OTHER DEALINGS IN THE SOFTWARE.
22  *
23  * Authors: AMD
24  *
25  */
26 
27 
28 #include "dm_services.h"
29 #include "dc.h"
30 
31 #include "dcn31/dcn31_init.h"
32 #include "dcn314/dcn314_init.h"
33 
34 #include "resource.h"
35 #include "include/irq_service_interface.h"
36 #include "dcn314_resource.h"
37 
38 #include "dcn20/dcn20_resource.h"
39 #include "dcn30/dcn30_resource.h"
40 #include "dcn31/dcn31_resource.h"
41 
42 #include "dcn10/dcn10_ipp.h"
43 #include "dcn30/dcn30_hubbub.h"
44 #include "dcn31/dcn31_hubbub.h"
45 #include "dcn30/dcn30_mpc.h"
46 #include "dcn31/dcn31_hubp.h"
47 #include "irq/dcn31/irq_service_dcn31.h"
48 #include "irq/dcn314/irq_service_dcn314.h"
49 #include "dcn30/dcn30_dpp.h"
50 #include "dcn314/dcn314_optc.h"
51 #include "dcn20/dcn20_hwseq.h"
52 #include "dcn30/dcn30_hwseq.h"
53 #include "dce110/dce110_hw_sequencer.h"
54 #include "dcn30/dcn30_opp.h"
55 #include "dcn20/dcn20_dsc.h"
56 #include "dcn30/dcn30_vpg.h"
57 #include "dcn30/dcn30_afmt.h"
58 #include "dcn31/dcn31_dio_link_encoder.h"
59 #include "dcn314/dcn314_dio_stream_encoder.h"
60 #include "dcn31/dcn31_hpo_dp_stream_encoder.h"
61 #include "dcn31/dcn31_hpo_dp_link_encoder.h"
62 #include "dcn31/dcn31_apg.h"
63 #include "dcn31/dcn31_vpg.h"
64 #include "dcn31/dcn31_afmt.h"
65 #include "dce/dce_clock_source.h"
66 #include "dce/dce_audio.h"
67 #include "dce/dce_hwseq.h"
68 #include "clk_mgr.h"
69 #include "virtual/virtual_stream_encoder.h"
70 #include "dce110/dce110_resource.h"
71 #include "dml/display_mode_vba.h"
72 #include "dml/dcn31/dcn31_fpu.h"
73 #include "dml/dcn314/dcn314_fpu.h"
74 #include "dcn314/dcn314_dccg.h"
75 #include "dcn10/dcn10_resource.h"
76 #include "dcn31/dcn31_panel_cntl.h"
77 #include "dcn314/dcn314_hwseq.h"
78 
79 #include "dcn30/dcn30_dwb.h"
80 #include "dcn30/dcn30_mmhubbub.h"
81 
82 #include "dcn/dcn_3_1_4_offset.h"
83 #include "dcn/dcn_3_1_4_sh_mask.h"
84 #include "dpcs/dpcs_3_1_4_offset.h"
85 #include "dpcs/dpcs_3_1_4_sh_mask.h"
86 
87 #define DCHUBBUB_DEBUG_CTRL_0__DET_DEPTH__SHIFT		0x10
88 #define DCHUBBUB_DEBUG_CTRL_0__DET_DEPTH_MASK		0x01FF0000L
89 
90 #define DSCC0_DSCC_CONFIG0__ICH_RESET_AT_END_OF_LINE__SHIFT                   0x0
91 #define DSCC0_DSCC_CONFIG0__ICH_RESET_AT_END_OF_LINE_MASK                     0x0000000FL
92 
93 #include "reg_helper.h"
94 #include "dce/dmub_abm.h"
95 #include "dce/dmub_psr.h"
96 #include "dce/dce_aux.h"
97 #include "dce/dce_i2c.h"
98 #include "dml/dcn314/display_mode_vba_314.h"
99 #include "vm_helper.h"
100 #include "dcn20/dcn20_vmid.h"
101 
102 #include "link_enc_cfg.h"
103 
104 #define DCN_BASE__INST0_SEG1				0x000000C0
105 #define DCN_BASE__INST0_SEG2				0x000034C0
106 #define DCN_BASE__INST0_SEG3				0x00009000
107 
108 #define NBIO_BASE__INST0_SEG1				0x00000014
109 
110 #define MAX_INSTANCE					7
111 #define MAX_SEGMENT					8
112 
113 #define regBIF_BX2_BIOS_SCRATCH_2			0x003a
114 #define regBIF_BX2_BIOS_SCRATCH_2_BASE_IDX		1
115 #define regBIF_BX2_BIOS_SCRATCH_3			0x003b
116 #define regBIF_BX2_BIOS_SCRATCH_3_BASE_IDX		1
117 #define regBIF_BX2_BIOS_SCRATCH_6			0x003e
118 #define regBIF_BX2_BIOS_SCRATCH_6_BASE_IDX		1
119 
120 struct IP_BASE_INSTANCE {
121 	unsigned int segment[MAX_SEGMENT];
122 };
123 
124 struct IP_BASE {
125 	struct IP_BASE_INSTANCE instance[MAX_INSTANCE];
126 };
127 
128 static const struct IP_BASE DCN_BASE = { { { { 0x00000012, 0x000000C0, 0x000034C0, 0x00009000, 0x02403C00, 0, 0, 0 } },
129 					{ { 0, 0, 0, 0, 0, 0, 0, 0 } },
130 					{ { 0, 0, 0, 0, 0, 0, 0, 0 } },
131 					{ { 0, 0, 0, 0, 0, 0, 0, 0 } },
132 					{ { 0, 0, 0, 0, 0, 0, 0, 0 } },
133 					{ { 0, 0, 0, 0, 0, 0, 0, 0 } },
134 					{ { 0, 0, 0, 0, 0, 0, 0, 0 } } } };
135 
136 
137 #define DC_LOGGER_INIT(logger)
138 
139 enum dcn31_clk_src_array_id {
140 	DCN31_CLK_SRC_PLL0,
141 	DCN31_CLK_SRC_PLL1,
142 	DCN31_CLK_SRC_PLL2,
143 	DCN31_CLK_SRC_PLL3,
144 	DCN31_CLK_SRC_PLL4,
145 	DCN30_CLK_SRC_TOTAL
146 };
147 
148 /* begin *********************
149  * macros to expend register list macro defined in HW object header file
150  */
151 
152 /* DCN */
153 /* TODO awful hack. fixup dcn20_dwb.h */
154 #undef BASE_INNER
155 #define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg
156 
157 #define BASE(seg) BASE_INNER(seg)
158 
159 #define SR(reg_name)\
160 		.reg_name = BASE(reg ## reg_name ## _BASE_IDX) +  \
161 					reg ## reg_name
162 
163 #define SRI(reg_name, block, id)\
164 	.reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
165 					reg ## block ## id ## _ ## reg_name
166 
167 #define SRI2(reg_name, block, id)\
168 	.reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \
169 					reg ## reg_name
170 
171 #define SRIR(var_name, reg_name, block, id)\
172 	.var_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
173 					reg ## block ## id ## _ ## reg_name
174 
175 #define SRII(reg_name, block, id)\
176 	.reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
177 					reg ## block ## id ## _ ## reg_name
178 
179 #define SRII_MPC_RMU(reg_name, block, id)\
180 	.RMU##_##reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
181 					reg ## block ## id ## _ ## reg_name
182 
183 #define SRII_DWB(reg_name, temp_name, block, id)\
184 	.reg_name[id] = BASE(reg ## block ## id ## _ ## temp_name ## _BASE_IDX) + \
185 					reg ## block ## id ## _ ## temp_name
186 
187 #define DCCG_SRII(reg_name, block, id)\
188 	.block ## _ ## reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
189 					reg ## block ## id ## _ ## reg_name
190 
191 #define VUPDATE_SRII(reg_name, block, id)\
192 	.reg_name[id] = BASE(reg ## reg_name ## _ ## block ## id ## _BASE_IDX) + \
193 					reg ## reg_name ## _ ## block ## id
194 
195 /* NBIO */
196 #define NBIO_BASE_INNER(seg) \
197 	NBIO_BASE__INST0_SEG ## seg
198 
199 #define NBIO_BASE(seg) \
200 	NBIO_BASE_INNER(seg)
201 
202 #define NBIO_SR(reg_name)\
203 		.reg_name = NBIO_BASE(regBIF_BX2_ ## reg_name ## _BASE_IDX) + \
204 					regBIF_BX2_ ## reg_name
205 
206 /* MMHUB */
207 #define MMHUB_BASE_INNER(seg) \
208 	MMHUB_BASE__INST0_SEG ## seg
209 
210 #define MMHUB_BASE(seg) \
211 	MMHUB_BASE_INNER(seg)
212 
213 #define MMHUB_SR(reg_name)\
214 		.reg_name = MMHUB_BASE(reg ## reg_name ## _BASE_IDX) + \
215 					reg ## reg_name
216 
217 /* CLOCK */
218 #define CLK_BASE_INNER(seg) \
219 	CLK_BASE__INST0_SEG ## seg
220 
221 #define CLK_BASE(seg) \
222 	CLK_BASE_INNER(seg)
223 
224 #define CLK_SRI(reg_name, block, inst)\
225 	.reg_name = CLK_BASE(reg ## block ## _ ## inst ## _ ## reg_name ## _BASE_IDX) + \
226 					reg ## block ## _ ## inst ## _ ## reg_name
227 
228 
229 static const struct bios_registers bios_regs = {
230 		NBIO_SR(BIOS_SCRATCH_3),
231 		NBIO_SR(BIOS_SCRATCH_6)
232 };
233 
234 #define clk_src_regs(index, pllid)\
235 [index] = {\
236 	CS_COMMON_REG_LIST_DCN3_0(index, pllid),\
237 }
238 
239 static const struct dce110_clk_src_regs clk_src_regs[] = {
240 	clk_src_regs(0, A),
241 	clk_src_regs(1, B),
242 	clk_src_regs(2, C),
243 	clk_src_regs(3, D),
244 	clk_src_regs(4, E)
245 };
246 
247 static const struct dce110_clk_src_shift cs_shift = {
248 		CS_COMMON_MASK_SH_LIST_DCN3_1_4(__SHIFT)
249 };
250 
251 static const struct dce110_clk_src_mask cs_mask = {
252 		CS_COMMON_MASK_SH_LIST_DCN3_1_4(_MASK)
253 };
254 
255 #define abm_regs(id)\
256 [id] = {\
257 		ABM_DCN302_REG_LIST(id)\
258 }
259 
260 static const struct dce_abm_registers abm_regs[] = {
261 		abm_regs(0),
262 		abm_regs(1),
263 		abm_regs(2),
264 		abm_regs(3),
265 };
266 
267 static const struct dce_abm_shift abm_shift = {
268 		ABM_MASK_SH_LIST_DCN30(__SHIFT)
269 };
270 
271 static const struct dce_abm_mask abm_mask = {
272 		ABM_MASK_SH_LIST_DCN30(_MASK)
273 };
274 
275 #define audio_regs(id)\
276 [id] = {\
277 		AUD_COMMON_REG_LIST(id)\
278 }
279 
280 static const struct dce_audio_registers audio_regs[] = {
281 	audio_regs(0),
282 	audio_regs(1),
283 	audio_regs(2),
284 	audio_regs(3),
285 	audio_regs(4),
286 	audio_regs(5),
287 	audio_regs(6)
288 };
289 
290 #define DCE120_AUD_COMMON_MASK_SH_LIST(mask_sh)\
291 		SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX, AZALIA_ENDPOINT_REG_INDEX, mask_sh),\
292 		SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA, AZALIA_ENDPOINT_REG_DATA, mask_sh),\
293 		AUD_COMMON_MASK_SH_LIST_BASE(mask_sh)
294 
295 static const struct dce_audio_shift audio_shift = {
296 		DCE120_AUD_COMMON_MASK_SH_LIST(__SHIFT)
297 };
298 
299 static const struct dce_audio_mask audio_mask = {
300 		DCE120_AUD_COMMON_MASK_SH_LIST(_MASK)
301 };
302 
303 #define vpg_regs(id)\
304 [id] = {\
305 	VPG_DCN31_REG_LIST(id)\
306 }
307 
308 static const struct dcn31_vpg_registers vpg_regs[] = {
309 	vpg_regs(0),
310 	vpg_regs(1),
311 	vpg_regs(2),
312 	vpg_regs(3),
313 	vpg_regs(4),
314 	vpg_regs(5),
315 	vpg_regs(6),
316 	vpg_regs(7),
317 	vpg_regs(8),
318 	vpg_regs(9),
319 };
320 
321 static const struct dcn31_vpg_shift vpg_shift = {
322 	DCN31_VPG_MASK_SH_LIST(__SHIFT)
323 };
324 
325 static const struct dcn31_vpg_mask vpg_mask = {
326 	DCN31_VPG_MASK_SH_LIST(_MASK)
327 };
328 
329 #define afmt_regs(id)\
330 [id] = {\
331 	AFMT_DCN31_REG_LIST(id)\
332 }
333 
334 static const struct dcn31_afmt_registers afmt_regs[] = {
335 	afmt_regs(0),
336 	afmt_regs(1),
337 	afmt_regs(2),
338 	afmt_regs(3),
339 	afmt_regs(4),
340 	afmt_regs(5)
341 };
342 
343 static const struct dcn31_afmt_shift afmt_shift = {
344 	DCN31_AFMT_MASK_SH_LIST(__SHIFT)
345 };
346 
347 static const struct dcn31_afmt_mask afmt_mask = {
348 	DCN31_AFMT_MASK_SH_LIST(_MASK)
349 };
350 
351 #define apg_regs(id)\
352 [id] = {\
353 	APG_DCN31_REG_LIST(id)\
354 }
355 
356 static const struct dcn31_apg_registers apg_regs[] = {
357 	apg_regs(0),
358 	apg_regs(1),
359 	apg_regs(2),
360 	apg_regs(3)
361 };
362 
363 static const struct dcn31_apg_shift apg_shift = {
364 	DCN31_APG_MASK_SH_LIST(__SHIFT)
365 };
366 
367 static const struct dcn31_apg_mask apg_mask = {
368 		DCN31_APG_MASK_SH_LIST(_MASK)
369 };
370 
371 #define stream_enc_regs(id)\
372 [id] = {\
373 		SE_DCN314_REG_LIST(id)\
374 }
375 
376 static const struct dcn10_stream_enc_registers stream_enc_regs[] = {
377 	stream_enc_regs(0),
378 	stream_enc_regs(1),
379 	stream_enc_regs(2),
380 	stream_enc_regs(3),
381 	stream_enc_regs(4)
382 };
383 
384 static const struct dcn10_stream_encoder_shift se_shift = {
385 		SE_COMMON_MASK_SH_LIST_DCN314(__SHIFT)
386 };
387 
388 static const struct dcn10_stream_encoder_mask se_mask = {
389 		SE_COMMON_MASK_SH_LIST_DCN314(_MASK)
390 };
391 
392 
393 #define aux_regs(id)\
394 [id] = {\
395 	DCN2_AUX_REG_LIST(id)\
396 }
397 
398 static const struct dcn10_link_enc_aux_registers link_enc_aux_regs[] = {
399 		aux_regs(0),
400 		aux_regs(1),
401 		aux_regs(2),
402 		aux_regs(3),
403 		aux_regs(4)
404 };
405 
406 #define hpd_regs(id)\
407 [id] = {\
408 	HPD_REG_LIST(id)\
409 }
410 
411 static const struct dcn10_link_enc_hpd_registers link_enc_hpd_regs[] = {
412 		hpd_regs(0),
413 		hpd_regs(1),
414 		hpd_regs(2),
415 		hpd_regs(3),
416 		hpd_regs(4)
417 };
418 
419 #define link_regs(id, phyid)\
420 [id] = {\
421 	LE_DCN31_REG_LIST(id), \
422 	UNIPHY_DCN2_REG_LIST(phyid), \
423 }
424 
425 static const struct dce110_aux_registers_shift aux_shift = {
426 	DCN_AUX_MASK_SH_LIST(__SHIFT)
427 };
428 
429 static const struct dce110_aux_registers_mask aux_mask = {
430 	DCN_AUX_MASK_SH_LIST(_MASK)
431 };
432 
433 static const struct dcn10_link_enc_registers link_enc_regs[] = {
434 	link_regs(0, A),
435 	link_regs(1, B),
436 	link_regs(2, C),
437 	link_regs(3, D),
438 	link_regs(4, E)
439 };
440 
441 static const struct dcn10_link_enc_shift le_shift = {
442 	LINK_ENCODER_MASK_SH_LIST_DCN31(__SHIFT),
443 	DPCS_DCN31_MASK_SH_LIST(__SHIFT)
444 };
445 
446 static const struct dcn10_link_enc_mask le_mask = {
447 	LINK_ENCODER_MASK_SH_LIST_DCN31(_MASK),
448 	DPCS_DCN31_MASK_SH_LIST(_MASK)
449 };
450 
451 #define hpo_dp_stream_encoder_reg_list(id)\
452 [id] = {\
453 	DCN3_1_HPO_DP_STREAM_ENC_REG_LIST(id)\
454 }
455 
456 static const struct dcn31_hpo_dp_stream_encoder_registers hpo_dp_stream_enc_regs[] = {
457 	hpo_dp_stream_encoder_reg_list(0),
458 	hpo_dp_stream_encoder_reg_list(1),
459 	hpo_dp_stream_encoder_reg_list(2),
460 	hpo_dp_stream_encoder_reg_list(3)
461 };
462 
463 static const struct dcn31_hpo_dp_stream_encoder_shift hpo_dp_se_shift = {
464 	DCN3_1_HPO_DP_STREAM_ENC_MASK_SH_LIST(__SHIFT)
465 };
466 
467 static const struct dcn31_hpo_dp_stream_encoder_mask hpo_dp_se_mask = {
468 	DCN3_1_HPO_DP_STREAM_ENC_MASK_SH_LIST(_MASK)
469 };
470 
471 
472 #define hpo_dp_link_encoder_reg_list(id)\
473 [id] = {\
474 	DCN3_1_HPO_DP_LINK_ENC_REG_LIST(id),\
475 	DCN3_1_RDPCSTX_REG_LIST(0),\
476 	DCN3_1_RDPCSTX_REG_LIST(1),\
477 	DCN3_1_RDPCSTX_REG_LIST(2),\
478 }
479 
480 static const struct dcn31_hpo_dp_link_encoder_registers hpo_dp_link_enc_regs[] = {
481 	hpo_dp_link_encoder_reg_list(0),
482 	hpo_dp_link_encoder_reg_list(1),
483 };
484 
485 static const struct dcn31_hpo_dp_link_encoder_shift hpo_dp_le_shift = {
486 	DCN3_1_HPO_DP_LINK_ENC_MASK_SH_LIST(__SHIFT)
487 };
488 
489 static const struct dcn31_hpo_dp_link_encoder_mask hpo_dp_le_mask = {
490 	DCN3_1_HPO_DP_LINK_ENC_MASK_SH_LIST(_MASK)
491 };
492 
493 #define dpp_regs(id)\
494 [id] = {\
495 	DPP_REG_LIST_DCN30(id),\
496 }
497 
498 static const struct dcn3_dpp_registers dpp_regs[] = {
499 	dpp_regs(0),
500 	dpp_regs(1),
501 	dpp_regs(2),
502 	dpp_regs(3)
503 };
504 
505 static const struct dcn3_dpp_shift tf_shift = {
506 		DPP_REG_LIST_SH_MASK_DCN30(__SHIFT)
507 };
508 
509 static const struct dcn3_dpp_mask tf_mask = {
510 		DPP_REG_LIST_SH_MASK_DCN30(_MASK)
511 };
512 
513 #define opp_regs(id)\
514 [id] = {\
515 	OPP_REG_LIST_DCN30(id),\
516 }
517 
518 static const struct dcn20_opp_registers opp_regs[] = {
519 	opp_regs(0),
520 	opp_regs(1),
521 	opp_regs(2),
522 	opp_regs(3)
523 };
524 
525 static const struct dcn20_opp_shift opp_shift = {
526 	OPP_MASK_SH_LIST_DCN20(__SHIFT)
527 };
528 
529 static const struct dcn20_opp_mask opp_mask = {
530 	OPP_MASK_SH_LIST_DCN20(_MASK)
531 };
532 
533 #define aux_engine_regs(id)\
534 [id] = {\
535 	AUX_COMMON_REG_LIST0(id), \
536 	.AUXN_IMPCAL = 0, \
537 	.AUXP_IMPCAL = 0, \
538 	.AUX_RESET_MASK = DP_AUX0_AUX_CONTROL__AUX_RESET_MASK, \
539 }
540 
541 static const struct dce110_aux_registers aux_engine_regs[] = {
542 		aux_engine_regs(0),
543 		aux_engine_regs(1),
544 		aux_engine_regs(2),
545 		aux_engine_regs(3),
546 		aux_engine_regs(4)
547 };
548 
549 #define dwbc_regs_dcn3(id)\
550 [id] = {\
551 	DWBC_COMMON_REG_LIST_DCN30(id),\
552 }
553 
554 static const struct dcn30_dwbc_registers dwbc30_regs[] = {
555 	dwbc_regs_dcn3(0),
556 };
557 
558 static const struct dcn30_dwbc_shift dwbc30_shift = {
559 	DWBC_COMMON_MASK_SH_LIST_DCN30(__SHIFT)
560 };
561 
562 static const struct dcn30_dwbc_mask dwbc30_mask = {
563 	DWBC_COMMON_MASK_SH_LIST_DCN30(_MASK)
564 };
565 
566 #define mcif_wb_regs_dcn3(id)\
567 [id] = {\
568 	MCIF_WB_COMMON_REG_LIST_DCN30(id),\
569 }
570 
571 static const struct dcn30_mmhubbub_registers mcif_wb30_regs[] = {
572 	mcif_wb_regs_dcn3(0)
573 };
574 
575 static const struct dcn30_mmhubbub_shift mcif_wb30_shift = {
576 	MCIF_WB_COMMON_MASK_SH_LIST_DCN30(__SHIFT)
577 };
578 
579 static const struct dcn30_mmhubbub_mask mcif_wb30_mask = {
580 	MCIF_WB_COMMON_MASK_SH_LIST_DCN30(_MASK)
581 };
582 
583 #define dsc_regsDCN314(id)\
584 [id] = {\
585 	DSC_REG_LIST_DCN20(id)\
586 }
587 
588 static const struct dcn20_dsc_registers dsc_regs[] = {
589 	dsc_regsDCN314(0),
590 	dsc_regsDCN314(1),
591 	dsc_regsDCN314(2),
592 	dsc_regsDCN314(3)
593 };
594 
595 static const struct dcn20_dsc_shift dsc_shift = {
596 	DSC_REG_LIST_SH_MASK_DCN20(__SHIFT)
597 };
598 
599 static const struct dcn20_dsc_mask dsc_mask = {
600 	DSC_REG_LIST_SH_MASK_DCN20(_MASK)
601 };
602 
603 static const struct dcn30_mpc_registers mpc_regs = {
604 		MPC_REG_LIST_DCN3_0(0),
605 		MPC_REG_LIST_DCN3_0(1),
606 		MPC_REG_LIST_DCN3_0(2),
607 		MPC_REG_LIST_DCN3_0(3),
608 		MPC_OUT_MUX_REG_LIST_DCN3_0(0),
609 		MPC_OUT_MUX_REG_LIST_DCN3_0(1),
610 		MPC_OUT_MUX_REG_LIST_DCN3_0(2),
611 		MPC_OUT_MUX_REG_LIST_DCN3_0(3),
612 		MPC_RMU_GLOBAL_REG_LIST_DCN3AG,
613 		MPC_RMU_REG_LIST_DCN3AG(0),
614 		MPC_RMU_REG_LIST_DCN3AG(1),
615 		//MPC_RMU_REG_LIST_DCN3AG(2),
616 		MPC_DWB_MUX_REG_LIST_DCN3_0(0),
617 };
618 
619 static const struct dcn30_mpc_shift mpc_shift = {
620 	MPC_COMMON_MASK_SH_LIST_DCN30(__SHIFT)
621 };
622 
623 static const struct dcn30_mpc_mask mpc_mask = {
624 	MPC_COMMON_MASK_SH_LIST_DCN30(_MASK)
625 };
626 
627 #define optc_regs(id)\
628 [id] = {OPTC_COMMON_REG_LIST_DCN3_14(id)}
629 
630 static const struct dcn_optc_registers optc_regs[] = {
631 	optc_regs(0),
632 	optc_regs(1),
633 	optc_regs(2),
634 	optc_regs(3)
635 };
636 
637 static const struct dcn_optc_shift optc_shift = {
638 	OPTC_COMMON_MASK_SH_LIST_DCN3_14(__SHIFT)
639 };
640 
641 static const struct dcn_optc_mask optc_mask = {
642 	OPTC_COMMON_MASK_SH_LIST_DCN3_14(_MASK)
643 };
644 
645 #define hubp_regs(id)\
646 [id] = {\
647 	HUBP_REG_LIST_DCN30(id)\
648 }
649 
650 static const struct dcn_hubp2_registers hubp_regs[] = {
651 		hubp_regs(0),
652 		hubp_regs(1),
653 		hubp_regs(2),
654 		hubp_regs(3)
655 };
656 
657 
658 static const struct dcn_hubp2_shift hubp_shift = {
659 		HUBP_MASK_SH_LIST_DCN31(__SHIFT)
660 };
661 
662 static const struct dcn_hubp2_mask hubp_mask = {
663 		HUBP_MASK_SH_LIST_DCN31(_MASK)
664 };
665 static const struct dcn_hubbub_registers hubbub_reg = {
666 		HUBBUB_REG_LIST_DCN31(0)
667 };
668 
669 static const struct dcn_hubbub_shift hubbub_shift = {
670 		HUBBUB_MASK_SH_LIST_DCN31(__SHIFT)
671 };
672 
673 static const struct dcn_hubbub_mask hubbub_mask = {
674 		HUBBUB_MASK_SH_LIST_DCN31(_MASK)
675 };
676 
677 static const struct dccg_registers dccg_regs = {
678 		DCCG_REG_LIST_DCN314()
679 };
680 
681 static const struct dccg_shift dccg_shift = {
682 		DCCG_MASK_SH_LIST_DCN314(__SHIFT)
683 };
684 
685 static const struct dccg_mask dccg_mask = {
686 		DCCG_MASK_SH_LIST_DCN314(_MASK)
687 };
688 
689 
690 #define SRII2(reg_name_pre, reg_name_post, id)\
691 	.reg_name_pre ## _ ##  reg_name_post[id] = BASE(reg ## reg_name_pre \
692 			## id ## _ ## reg_name_post ## _BASE_IDX) + \
693 			reg ## reg_name_pre ## id ## _ ## reg_name_post
694 
695 
696 #define HWSEQ_DCN31_REG_LIST()\
697 	SR(DCHUBBUB_GLOBAL_TIMER_CNTL), \
698 	SR(DCHUBBUB_ARB_HOSTVM_CNTL), \
699 	SR(DIO_MEM_PWR_CTRL), \
700 	SR(ODM_MEM_PWR_CTRL3), \
701 	SR(DMU_MEM_PWR_CNTL), \
702 	SR(MMHUBBUB_MEM_PWR_CNTL), \
703 	SR(DCCG_GATE_DISABLE_CNTL), \
704 	SR(DCCG_GATE_DISABLE_CNTL2), \
705 	SR(DCFCLK_CNTL),\
706 	SR(DC_MEM_GLOBAL_PWR_REQ_CNTL), \
707 	SRII(PIXEL_RATE_CNTL, OTG, 0), \
708 	SRII(PIXEL_RATE_CNTL, OTG, 1),\
709 	SRII(PIXEL_RATE_CNTL, OTG, 2),\
710 	SRII(PIXEL_RATE_CNTL, OTG, 3),\
711 	SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 0),\
712 	SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 1),\
713 	SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 2),\
714 	SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 3),\
715 	SR(MICROSECOND_TIME_BASE_DIV), \
716 	SR(MILLISECOND_TIME_BASE_DIV), \
717 	SR(DISPCLK_FREQ_CHANGE_CNTL), \
718 	SR(RBBMIF_TIMEOUT_DIS), \
719 	SR(RBBMIF_TIMEOUT_DIS_2), \
720 	SR(DCHUBBUB_CRC_CTRL), \
721 	SR(DPP_TOP0_DPP_CRC_CTRL), \
722 	SR(DPP_TOP0_DPP_CRC_VAL_B_A), \
723 	SR(DPP_TOP0_DPP_CRC_VAL_R_G), \
724 	SR(MPC_CRC_CTRL), \
725 	SR(MPC_CRC_RESULT_GB), \
726 	SR(MPC_CRC_RESULT_C), \
727 	SR(MPC_CRC_RESULT_AR), \
728 	SR(DOMAIN0_PG_CONFIG), \
729 	SR(DOMAIN1_PG_CONFIG), \
730 	SR(DOMAIN2_PG_CONFIG), \
731 	SR(DOMAIN3_PG_CONFIG), \
732 	SR(DOMAIN16_PG_CONFIG), \
733 	SR(DOMAIN17_PG_CONFIG), \
734 	SR(DOMAIN18_PG_CONFIG), \
735 	SR(DOMAIN19_PG_CONFIG), \
736 	SR(DOMAIN0_PG_STATUS), \
737 	SR(DOMAIN1_PG_STATUS), \
738 	SR(DOMAIN2_PG_STATUS), \
739 	SR(DOMAIN3_PG_STATUS), \
740 	SR(DOMAIN16_PG_STATUS), \
741 	SR(DOMAIN17_PG_STATUS), \
742 	SR(DOMAIN18_PG_STATUS), \
743 	SR(DOMAIN19_PG_STATUS), \
744 	SR(D1VGA_CONTROL), \
745 	SR(D2VGA_CONTROL), \
746 	SR(D3VGA_CONTROL), \
747 	SR(D4VGA_CONTROL), \
748 	SR(D5VGA_CONTROL), \
749 	SR(D6VGA_CONTROL), \
750 	SR(DC_IP_REQUEST_CNTL), \
751 	SR(AZALIA_AUDIO_DTO), \
752 	SR(AZALIA_CONTROLLER_CLOCK_GATING), \
753 	SR(HPO_TOP_HW_CONTROL)
754 
755 static const struct dce_hwseq_registers hwseq_reg = {
756 		HWSEQ_DCN31_REG_LIST()
757 };
758 
759 #define HWSEQ_DCN31_MASK_SH_LIST(mask_sh)\
760 	HWSEQ_DCN_MASK_SH_LIST(mask_sh), \
761 	HWS_SF(, DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_REFDIV, mask_sh), \
762 	HWS_SF(, DCHUBBUB_ARB_HOSTVM_CNTL, DISABLE_HOSTVM_FORCE_ALLOW_PSTATE, mask_sh), \
763 	HWS_SF(, DOMAIN0_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
764 	HWS_SF(, DOMAIN0_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
765 	HWS_SF(, DOMAIN1_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
766 	HWS_SF(, DOMAIN1_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
767 	HWS_SF(, DOMAIN2_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
768 	HWS_SF(, DOMAIN2_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
769 	HWS_SF(, DOMAIN3_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
770 	HWS_SF(, DOMAIN3_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
771 	HWS_SF(, DOMAIN16_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
772 	HWS_SF(, DOMAIN16_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
773 	HWS_SF(, DOMAIN17_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
774 	HWS_SF(, DOMAIN17_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
775 	HWS_SF(, DOMAIN18_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
776 	HWS_SF(, DOMAIN18_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
777 	HWS_SF(, DOMAIN19_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
778 	HWS_SF(, DOMAIN19_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
779 	HWS_SF(, DOMAIN0_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
780 	HWS_SF(, DOMAIN1_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
781 	HWS_SF(, DOMAIN2_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
782 	HWS_SF(, DOMAIN3_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
783 	HWS_SF(, DOMAIN16_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
784 	HWS_SF(, DOMAIN17_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
785 	HWS_SF(, DOMAIN18_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
786 	HWS_SF(, DOMAIN19_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
787 	HWS_SF(, DC_IP_REQUEST_CNTL, IP_REQUEST_EN, mask_sh), \
788 	HWS_SF(, AZALIA_AUDIO_DTO, AZALIA_AUDIO_DTO_MODULE, mask_sh), \
789 	HWS_SF(, HPO_TOP_CLOCK_CONTROL, HPO_HDMISTREAMCLK_G_GATE_DIS, mask_sh), \
790 	HWS_SF(, DMU_MEM_PWR_CNTL, DMCU_ERAM_MEM_PWR_FORCE, mask_sh), \
791 	HWS_SF(, ODM_MEM_PWR_CTRL3, ODM_MEM_UNASSIGNED_PWR_MODE, mask_sh), \
792 	HWS_SF(, ODM_MEM_PWR_CTRL3, ODM_MEM_VBLANK_PWR_MODE, mask_sh), \
793 	HWS_SF(, MMHUBBUB_MEM_PWR_CNTL, VGA_MEM_PWR_FORCE, mask_sh), \
794 	HWS_SF(, DIO_MEM_PWR_CTRL, I2C_LIGHT_SLEEP_FORCE, mask_sh), \
795 	HWS_SF(, HPO_TOP_HW_CONTROL, HPO_IO_EN, mask_sh)
796 
797 static const struct dce_hwseq_shift hwseq_shift = {
798 		HWSEQ_DCN31_MASK_SH_LIST(__SHIFT)
799 };
800 
801 static const struct dce_hwseq_mask hwseq_mask = {
802 		HWSEQ_DCN31_MASK_SH_LIST(_MASK)
803 };
804 #define vmid_regs(id)\
805 [id] = {\
806 		DCN20_VMID_REG_LIST(id)\
807 }
808 
809 static const struct dcn_vmid_registers vmid_regs[] = {
810 	vmid_regs(0),
811 	vmid_regs(1),
812 	vmid_regs(2),
813 	vmid_regs(3),
814 	vmid_regs(4),
815 	vmid_regs(5),
816 	vmid_regs(6),
817 	vmid_regs(7),
818 	vmid_regs(8),
819 	vmid_regs(9),
820 	vmid_regs(10),
821 	vmid_regs(11),
822 	vmid_regs(12),
823 	vmid_regs(13),
824 	vmid_regs(14),
825 	vmid_regs(15)
826 };
827 
828 static const struct dcn20_vmid_shift vmid_shifts = {
829 		DCN20_VMID_MASK_SH_LIST(__SHIFT)
830 };
831 
832 static const struct dcn20_vmid_mask vmid_masks = {
833 		DCN20_VMID_MASK_SH_LIST(_MASK)
834 };
835 
836 static const struct resource_caps res_cap_dcn314 = {
837 	.num_timing_generator = 4,
838 	.num_opp = 4,
839 	.num_video_plane = 4,
840 	.num_audio = 5,
841 	.num_stream_encoder = 5,
842 	.num_dig_link_enc = 5,
843 	.num_hpo_dp_stream_encoder = 4,
844 	.num_hpo_dp_link_encoder = 2,
845 	.num_pll = 5,
846 	.num_dwb = 1,
847 	.num_ddc = 5,
848 	.num_vmid = 16,
849 	.num_mpc_3dlut = 2,
850 	.num_dsc = 3,
851 };
852 
853 static const struct dc_plane_cap plane_cap = {
854 	.type = DC_PLANE_TYPE_DCN_UNIVERSAL,
855 	.blends_with_above = true,
856 	.blends_with_below = true,
857 	.per_pixel_alpha = true,
858 
859 	.pixel_format_support = {
860 			.argb8888 = true,
861 			.nv12 = true,
862 			.fp16 = true,
863 			.p010 = true,
864 			.ayuv = false,
865 	},
866 
867 	.max_upscale_factor = {
868 			.argb8888 = 16000,
869 			.nv12 = 16000,
870 			.fp16 = 16000
871 	},
872 
873 	// 6:1 downscaling ratio: 1000/6 = 166.666
874 	.max_downscale_factor = {
875 			.argb8888 = 167,
876 			.nv12 = 167,
877 			.fp16 = 167
878 	},
879 	64,
880 	64
881 };
882 
883 static const struct dc_debug_options debug_defaults_drv = {
884 	.disable_z10 = true, /*hw not support it*/
885 	.disable_dmcu = true,
886 	.force_abm_enable = false,
887 	.timing_trace = false,
888 	.clock_trace = true,
889 	.disable_pplib_clock_request = false,
890 	.pipe_split_policy = MPC_SPLIT_DYNAMIC,
891 	.force_single_disp_pipe_split = false,
892 	.disable_dcc = DCC_ENABLE,
893 	.vsr_support = true,
894 	.performance_trace = false,
895 	.max_downscale_src_width = 4096,/*upto true 4k*/
896 	.disable_pplib_wm_range = false,
897 	.scl_reset_length10 = true,
898 	.sanity_checks = false,
899 	.underflow_assert_delay_us = 0xFFFFFFFF,
900 	.dwb_fi_phase = -1, // -1 = disable,
901 	.dmub_command_table = true,
902 	.pstate_enabled = true,
903 	.use_max_lb = true,
904 	.enable_mem_low_power = {
905 		.bits = {
906 			.vga = true,
907 			.i2c = true,
908 			.dmcu = false, // This is previously known to cause hang on S3 cycles if enabled
909 			.dscl = true,
910 			.cm = true,
911 			.mpc = true,
912 			.optc = true,
913 			.vpg = true,
914 			.afmt = true,
915 		}
916 	},
917 	.optimize_edp_link_rate = true,
918 	.enable_sw_cntl_psr = true,
919 	.seamless_boot_odm_combine = true
920 };
921 
922 static const struct dc_debug_options debug_defaults_diags = {
923 	.disable_dmcu = true,
924 	.force_abm_enable = false,
925 	.timing_trace = true,
926 	.clock_trace = true,
927 	.disable_dpp_power_gate = true,
928 	.disable_hubp_power_gate = true,
929 	.disable_clock_gate = true,
930 	.disable_pplib_clock_request = true,
931 	.disable_pplib_wm_range = true,
932 	.disable_stutter = false,
933 	.scl_reset_length10 = true,
934 	.dwb_fi_phase = -1, // -1 = disable
935 	.dmub_command_table = true,
936 	.enable_tri_buf = true,
937 	.use_max_lb = true
938 };
939 
940 static void dcn31_dpp_destroy(struct dpp **dpp)
941 {
942 	kfree(TO_DCN20_DPP(*dpp));
943 	*dpp = NULL;
944 }
945 
946 static struct dpp *dcn31_dpp_create(
947 	struct dc_context *ctx,
948 	uint32_t inst)
949 {
950 	struct dcn3_dpp *dpp =
951 		kzalloc(sizeof(struct dcn3_dpp), GFP_KERNEL);
952 
953 	if (!dpp)
954 		return NULL;
955 
956 	if (dpp3_construct(dpp, ctx, inst,
957 			&dpp_regs[inst], &tf_shift, &tf_mask))
958 		return &dpp->base;
959 
960 	BREAK_TO_DEBUGGER();
961 	kfree(dpp);
962 	return NULL;
963 }
964 
965 static struct output_pixel_processor *dcn31_opp_create(
966 	struct dc_context *ctx, uint32_t inst)
967 {
968 	struct dcn20_opp *opp =
969 		kzalloc(sizeof(struct dcn20_opp), GFP_KERNEL);
970 
971 	if (!opp) {
972 		BREAK_TO_DEBUGGER();
973 		return NULL;
974 	}
975 
976 	dcn20_opp_construct(opp, ctx, inst,
977 			&opp_regs[inst], &opp_shift, &opp_mask);
978 	return &opp->base;
979 }
980 
981 static struct dce_aux *dcn31_aux_engine_create(
982 	struct dc_context *ctx,
983 	uint32_t inst)
984 {
985 	struct aux_engine_dce110 *aux_engine =
986 		kzalloc(sizeof(struct aux_engine_dce110), GFP_KERNEL);
987 
988 	if (!aux_engine)
989 		return NULL;
990 
991 	dce110_aux_engine_construct(aux_engine, ctx, inst,
992 				    SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD,
993 				    &aux_engine_regs[inst],
994 					&aux_mask,
995 					&aux_shift,
996 					ctx->dc->caps.extended_aux_timeout_support);
997 
998 	return &aux_engine->base;
999 }
1000 #define i2c_inst_regs(id) { I2C_HW_ENGINE_COMMON_REG_LIST_DCN30(id) }
1001 
1002 static const struct dce_i2c_registers i2c_hw_regs[] = {
1003 		i2c_inst_regs(1),
1004 		i2c_inst_regs(2),
1005 		i2c_inst_regs(3),
1006 		i2c_inst_regs(4),
1007 		i2c_inst_regs(5),
1008 };
1009 
1010 static const struct dce_i2c_shift i2c_shifts = {
1011 		I2C_COMMON_MASK_SH_LIST_DCN30(__SHIFT)
1012 };
1013 
1014 static const struct dce_i2c_mask i2c_masks = {
1015 		I2C_COMMON_MASK_SH_LIST_DCN30(_MASK)
1016 };
1017 
1018 static struct dce_i2c_hw *dcn31_i2c_hw_create(
1019 	struct dc_context *ctx,
1020 	uint32_t inst)
1021 {
1022 	struct dce_i2c_hw *dce_i2c_hw =
1023 		kzalloc(sizeof(struct dce_i2c_hw), GFP_KERNEL);
1024 
1025 	if (!dce_i2c_hw)
1026 		return NULL;
1027 
1028 	dcn2_i2c_hw_construct(dce_i2c_hw, ctx, inst,
1029 				    &i2c_hw_regs[inst], &i2c_shifts, &i2c_masks);
1030 
1031 	return dce_i2c_hw;
1032 }
1033 static struct mpc *dcn31_mpc_create(
1034 		struct dc_context *ctx,
1035 		int num_mpcc,
1036 		int num_rmu)
1037 {
1038 	struct dcn30_mpc *mpc30 = kzalloc(sizeof(struct dcn30_mpc),
1039 					  GFP_KERNEL);
1040 
1041 	if (!mpc30)
1042 		return NULL;
1043 
1044 	dcn30_mpc_construct(mpc30, ctx,
1045 			&mpc_regs,
1046 			&mpc_shift,
1047 			&mpc_mask,
1048 			num_mpcc,
1049 			num_rmu);
1050 
1051 	return &mpc30->base;
1052 }
1053 
1054 static struct hubbub *dcn31_hubbub_create(struct dc_context *ctx)
1055 {
1056 	int i;
1057 
1058 	struct dcn20_hubbub *hubbub3 = kzalloc(sizeof(struct dcn20_hubbub),
1059 					  GFP_KERNEL);
1060 
1061 	if (!hubbub3)
1062 		return NULL;
1063 
1064 	hubbub31_construct(hubbub3, ctx,
1065 			&hubbub_reg,
1066 			&hubbub_shift,
1067 			&hubbub_mask,
1068 			dcn3_14_ip.det_buffer_size_kbytes,
1069 			dcn3_14_ip.pixel_chunk_size_kbytes,
1070 			dcn3_14_ip.config_return_buffer_size_in_kbytes);
1071 
1072 
1073 	for (i = 0; i < res_cap_dcn314.num_vmid; i++) {
1074 		struct dcn20_vmid *vmid = &hubbub3->vmid[i];
1075 
1076 		vmid->ctx = ctx;
1077 
1078 		vmid->regs = &vmid_regs[i];
1079 		vmid->shifts = &vmid_shifts;
1080 		vmid->masks = &vmid_masks;
1081 	}
1082 
1083 	return &hubbub3->base;
1084 }
1085 
1086 static struct timing_generator *dcn31_timing_generator_create(
1087 		struct dc_context *ctx,
1088 		uint32_t instance)
1089 {
1090 	struct optc *tgn10 =
1091 		kzalloc(sizeof(struct optc), GFP_KERNEL);
1092 
1093 	if (!tgn10)
1094 		return NULL;
1095 
1096 	tgn10->base.inst = instance;
1097 	tgn10->base.ctx = ctx;
1098 
1099 	tgn10->tg_regs = &optc_regs[instance];
1100 	tgn10->tg_shift = &optc_shift;
1101 	tgn10->tg_mask = &optc_mask;
1102 
1103 	dcn314_timing_generator_init(tgn10);
1104 
1105 	return &tgn10->base;
1106 }
1107 
1108 static const struct encoder_feature_support link_enc_feature = {
1109 		.max_hdmi_deep_color = COLOR_DEPTH_121212,
1110 		.max_hdmi_pixel_clock = 600000,
1111 		.hdmi_ycbcr420_supported = true,
1112 		.dp_ycbcr420_supported = true,
1113 		.fec_supported = true,
1114 		.flags.bits.IS_HBR2_CAPABLE = true,
1115 		.flags.bits.IS_HBR3_CAPABLE = true,
1116 		.flags.bits.IS_TPS3_CAPABLE = true,
1117 		.flags.bits.IS_TPS4_CAPABLE = true
1118 };
1119 
1120 static struct link_encoder *dcn31_link_encoder_create(
1121 	struct dc_context *ctx,
1122 	const struct encoder_init_data *enc_init_data)
1123 {
1124 	struct dcn20_link_encoder *enc20 =
1125 		kzalloc(sizeof(struct dcn20_link_encoder), GFP_KERNEL);
1126 
1127 	if (!enc20)
1128 		return NULL;
1129 
1130 	dcn31_link_encoder_construct(enc20,
1131 			enc_init_data,
1132 			&link_enc_feature,
1133 			&link_enc_regs[enc_init_data->transmitter],
1134 			&link_enc_aux_regs[enc_init_data->channel - 1],
1135 			&link_enc_hpd_regs[enc_init_data->hpd_source],
1136 			&le_shift,
1137 			&le_mask);
1138 
1139 	return &enc20->enc10.base;
1140 }
1141 
1142 /* Create a minimal link encoder object not associated with a particular
1143  * physical connector.
1144  * resource_funcs.link_enc_create_minimal
1145  */
1146 static struct link_encoder *dcn31_link_enc_create_minimal(
1147 		struct dc_context *ctx, enum engine_id eng_id)
1148 {
1149 	struct dcn20_link_encoder *enc20;
1150 
1151 	if ((eng_id - ENGINE_ID_DIGA) > ctx->dc->res_pool->res_cap->num_dig_link_enc)
1152 		return NULL;
1153 
1154 	enc20 = kzalloc(sizeof(struct dcn20_link_encoder), GFP_KERNEL);
1155 	if (!enc20)
1156 		return NULL;
1157 
1158 	dcn31_link_encoder_construct_minimal(
1159 			enc20,
1160 			ctx,
1161 			&link_enc_feature,
1162 			&link_enc_regs[eng_id - ENGINE_ID_DIGA],
1163 			eng_id);
1164 
1165 	return &enc20->enc10.base;
1166 }
1167 
1168 static struct panel_cntl *dcn31_panel_cntl_create(const struct panel_cntl_init_data *init_data)
1169 {
1170 	struct dcn31_panel_cntl *panel_cntl =
1171 		kzalloc(sizeof(struct dcn31_panel_cntl), GFP_KERNEL);
1172 
1173 	if (!panel_cntl)
1174 		return NULL;
1175 
1176 	dcn31_panel_cntl_construct(panel_cntl, init_data);
1177 
1178 	return &panel_cntl->base;
1179 }
1180 
1181 static void read_dce_straps(
1182 	struct dc_context *ctx,
1183 	struct resource_straps *straps)
1184 {
1185 	generic_reg_get(ctx, regDC_PINSTRAPS + BASE(regDC_PINSTRAPS_BASE_IDX),
1186 		FN(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO), &straps->dc_pinstraps_audio);
1187 
1188 }
1189 
1190 static struct audio *dcn31_create_audio(
1191 		struct dc_context *ctx, unsigned int inst)
1192 {
1193 	return dce_audio_create(ctx, inst,
1194 			&audio_regs[inst], &audio_shift, &audio_mask);
1195 }
1196 
1197 static struct vpg *dcn31_vpg_create(
1198 	struct dc_context *ctx,
1199 	uint32_t inst)
1200 {
1201 	struct dcn31_vpg *vpg31 = kzalloc(sizeof(struct dcn31_vpg), GFP_KERNEL);
1202 
1203 	if (!vpg31)
1204 		return NULL;
1205 
1206 	vpg31_construct(vpg31, ctx, inst,
1207 			&vpg_regs[inst],
1208 			&vpg_shift,
1209 			&vpg_mask);
1210 
1211 	return &vpg31->base;
1212 }
1213 
1214 static struct afmt *dcn31_afmt_create(
1215 	struct dc_context *ctx,
1216 	uint32_t inst)
1217 {
1218 	struct dcn31_afmt *afmt31 = kzalloc(sizeof(struct dcn31_afmt), GFP_KERNEL);
1219 
1220 	if (!afmt31)
1221 		return NULL;
1222 
1223 	afmt31_construct(afmt31, ctx, inst,
1224 			&afmt_regs[inst],
1225 			&afmt_shift,
1226 			&afmt_mask);
1227 
1228 	// Light sleep by default, no need to power down here
1229 
1230 	return &afmt31->base;
1231 }
1232 
1233 static struct apg *dcn31_apg_create(
1234 	struct dc_context *ctx,
1235 	uint32_t inst)
1236 {
1237 	struct dcn31_apg *apg31 = kzalloc(sizeof(struct dcn31_apg), GFP_KERNEL);
1238 
1239 	if (!apg31)
1240 		return NULL;
1241 
1242 	apg31_construct(apg31, ctx, inst,
1243 			&apg_regs[inst],
1244 			&apg_shift,
1245 			&apg_mask);
1246 
1247 	return &apg31->base;
1248 }
1249 
1250 static struct stream_encoder *dcn314_stream_encoder_create(
1251 	enum engine_id eng_id,
1252 	struct dc_context *ctx)
1253 {
1254 	struct dcn10_stream_encoder *enc1;
1255 	struct vpg *vpg;
1256 	struct afmt *afmt;
1257 	int vpg_inst;
1258 	int afmt_inst;
1259 
1260 	/* Mapping of VPG, AFMT, DME register blocks to DIO block instance */
1261 	if (eng_id < ENGINE_ID_DIGF) {
1262 		vpg_inst = eng_id;
1263 		afmt_inst = eng_id;
1264 	} else
1265 		return NULL;
1266 
1267 	enc1 = kzalloc(sizeof(struct dcn10_stream_encoder), GFP_KERNEL);
1268 	vpg = dcn31_vpg_create(ctx, vpg_inst);
1269 	afmt = dcn31_afmt_create(ctx, afmt_inst);
1270 
1271 	if (!enc1 || !vpg || !afmt) {
1272 		kfree(enc1);
1273 		kfree(vpg);
1274 		kfree(afmt);
1275 		return NULL;
1276 	}
1277 
1278 	dcn314_dio_stream_encoder_construct(enc1, ctx, ctx->dc_bios,
1279 					eng_id, vpg, afmt,
1280 					&stream_enc_regs[eng_id],
1281 					&se_shift, &se_mask);
1282 
1283 	return &enc1->base;
1284 }
1285 
1286 static struct hpo_dp_stream_encoder *dcn31_hpo_dp_stream_encoder_create(
1287 	enum engine_id eng_id,
1288 	struct dc_context *ctx)
1289 {
1290 	struct dcn31_hpo_dp_stream_encoder *hpo_dp_enc31;
1291 	struct vpg *vpg;
1292 	struct apg *apg;
1293 	uint32_t hpo_dp_inst;
1294 	uint32_t vpg_inst;
1295 	uint32_t apg_inst;
1296 
1297 	ASSERT((eng_id >= ENGINE_ID_HPO_DP_0) && (eng_id <= ENGINE_ID_HPO_DP_3));
1298 	hpo_dp_inst = eng_id - ENGINE_ID_HPO_DP_0;
1299 
1300 	/* Mapping of VPG register blocks to HPO DP block instance:
1301 	 * VPG[6] -> HPO_DP[0]
1302 	 * VPG[7] -> HPO_DP[1]
1303 	 * VPG[8] -> HPO_DP[2]
1304 	 * VPG[9] -> HPO_DP[3]
1305 	 */
1306 	//Uses offset index 5-8, but actually maps to vpg_inst 6-9
1307 	vpg_inst = hpo_dp_inst + 5;
1308 
1309 	/* Mapping of APG register blocks to HPO DP block instance:
1310 	 * APG[0] -> HPO_DP[0]
1311 	 * APG[1] -> HPO_DP[1]
1312 	 * APG[2] -> HPO_DP[2]
1313 	 * APG[3] -> HPO_DP[3]
1314 	 */
1315 	apg_inst = hpo_dp_inst;
1316 
1317 	/* allocate HPO stream encoder and create VPG sub-block */
1318 	hpo_dp_enc31 = kzalloc(sizeof(struct dcn31_hpo_dp_stream_encoder), GFP_KERNEL);
1319 	vpg = dcn31_vpg_create(ctx, vpg_inst);
1320 	apg = dcn31_apg_create(ctx, apg_inst);
1321 
1322 	if (!hpo_dp_enc31 || !vpg || !apg) {
1323 		kfree(hpo_dp_enc31);
1324 		kfree(vpg);
1325 		kfree(apg);
1326 		return NULL;
1327 	}
1328 
1329 	dcn31_hpo_dp_stream_encoder_construct(hpo_dp_enc31, ctx, ctx->dc_bios,
1330 					hpo_dp_inst, eng_id, vpg, apg,
1331 					&hpo_dp_stream_enc_regs[hpo_dp_inst],
1332 					&hpo_dp_se_shift, &hpo_dp_se_mask);
1333 
1334 	return &hpo_dp_enc31->base;
1335 }
1336 
1337 static struct hpo_dp_link_encoder *dcn31_hpo_dp_link_encoder_create(
1338 	uint8_t inst,
1339 	struct dc_context *ctx)
1340 {
1341 	struct dcn31_hpo_dp_link_encoder *hpo_dp_enc31;
1342 
1343 	/* allocate HPO link encoder */
1344 	hpo_dp_enc31 = kzalloc(sizeof(struct dcn31_hpo_dp_link_encoder), GFP_KERNEL);
1345 
1346 	hpo_dp_link_encoder31_construct(hpo_dp_enc31, ctx, inst,
1347 					&hpo_dp_link_enc_regs[inst],
1348 					&hpo_dp_le_shift, &hpo_dp_le_mask);
1349 
1350 	return &hpo_dp_enc31->base;
1351 }
1352 
1353 static struct dce_hwseq *dcn314_hwseq_create(
1354 	struct dc_context *ctx)
1355 {
1356 	struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_KERNEL);
1357 
1358 	if (hws) {
1359 		hws->ctx = ctx;
1360 		hws->regs = &hwseq_reg;
1361 		hws->shifts = &hwseq_shift;
1362 		hws->masks = &hwseq_mask;
1363 		/* DCN3.1 FPGA Workaround
1364 		 * Need to enable HPO DP Stream Encoder before setting OTG master enable.
1365 		 * To do so, move calling function enable_stream_timing to only be done AFTER calling
1366 		 * function core_link_enable_stream
1367 		 */
1368 		if (IS_FPGA_MAXIMUS_DC(ctx->dce_environment))
1369 			hws->wa.dp_hpo_and_otg_sequence = true;
1370 	}
1371 	return hws;
1372 }
1373 static const struct resource_create_funcs res_create_funcs = {
1374 	.read_dce_straps = read_dce_straps,
1375 	.create_audio = dcn31_create_audio,
1376 	.create_stream_encoder = dcn314_stream_encoder_create,
1377 	.create_hpo_dp_stream_encoder = dcn31_hpo_dp_stream_encoder_create,
1378 	.create_hpo_dp_link_encoder = dcn31_hpo_dp_link_encoder_create,
1379 	.create_hwseq = dcn314_hwseq_create,
1380 };
1381 
1382 static const struct resource_create_funcs res_create_maximus_funcs = {
1383 	.read_dce_straps = NULL,
1384 	.create_audio = NULL,
1385 	.create_stream_encoder = NULL,
1386 	.create_hpo_dp_stream_encoder = dcn31_hpo_dp_stream_encoder_create,
1387 	.create_hpo_dp_link_encoder = dcn31_hpo_dp_link_encoder_create,
1388 	.create_hwseq = dcn314_hwseq_create,
1389 };
1390 
1391 static void dcn314_resource_destruct(struct dcn314_resource_pool *pool)
1392 {
1393 	unsigned int i;
1394 
1395 	for (i = 0; i < pool->base.stream_enc_count; i++) {
1396 		if (pool->base.stream_enc[i] != NULL) {
1397 			if (pool->base.stream_enc[i]->vpg != NULL) {
1398 				kfree(DCN30_VPG_FROM_VPG(pool->base.stream_enc[i]->vpg));
1399 				pool->base.stream_enc[i]->vpg = NULL;
1400 			}
1401 			if (pool->base.stream_enc[i]->afmt != NULL) {
1402 				kfree(DCN30_AFMT_FROM_AFMT(pool->base.stream_enc[i]->afmt));
1403 				pool->base.stream_enc[i]->afmt = NULL;
1404 			}
1405 			kfree(DCN10STRENC_FROM_STRENC(pool->base.stream_enc[i]));
1406 			pool->base.stream_enc[i] = NULL;
1407 		}
1408 	}
1409 
1410 	for (i = 0; i < pool->base.hpo_dp_stream_enc_count; i++) {
1411 		if (pool->base.hpo_dp_stream_enc[i] != NULL) {
1412 			if (pool->base.hpo_dp_stream_enc[i]->vpg != NULL) {
1413 				kfree(DCN30_VPG_FROM_VPG(pool->base.hpo_dp_stream_enc[i]->vpg));
1414 				pool->base.hpo_dp_stream_enc[i]->vpg = NULL;
1415 			}
1416 			if (pool->base.hpo_dp_stream_enc[i]->apg != NULL) {
1417 				kfree(DCN31_APG_FROM_APG(pool->base.hpo_dp_stream_enc[i]->apg));
1418 				pool->base.hpo_dp_stream_enc[i]->apg = NULL;
1419 			}
1420 			kfree(DCN3_1_HPO_DP_STREAM_ENC_FROM_HPO_STREAM_ENC(pool->base.hpo_dp_stream_enc[i]));
1421 			pool->base.hpo_dp_stream_enc[i] = NULL;
1422 		}
1423 	}
1424 
1425 	for (i = 0; i < pool->base.hpo_dp_link_enc_count; i++) {
1426 		if (pool->base.hpo_dp_link_enc[i] != NULL) {
1427 			kfree(DCN3_1_HPO_DP_LINK_ENC_FROM_HPO_LINK_ENC(pool->base.hpo_dp_link_enc[i]));
1428 			pool->base.hpo_dp_link_enc[i] = NULL;
1429 		}
1430 	}
1431 
1432 	for (i = 0; i < pool->base.res_cap->num_dsc; i++) {
1433 		if (pool->base.dscs[i] != NULL)
1434 			dcn20_dsc_destroy(&pool->base.dscs[i]);
1435 	}
1436 
1437 	if (pool->base.mpc != NULL) {
1438 		kfree(TO_DCN20_MPC(pool->base.mpc));
1439 		pool->base.mpc = NULL;
1440 	}
1441 	if (pool->base.hubbub != NULL) {
1442 		kfree(pool->base.hubbub);
1443 		pool->base.hubbub = NULL;
1444 	}
1445 	for (i = 0; i < pool->base.pipe_count; i++) {
1446 		if (pool->base.dpps[i] != NULL)
1447 			dcn31_dpp_destroy(&pool->base.dpps[i]);
1448 
1449 		if (pool->base.ipps[i] != NULL)
1450 			pool->base.ipps[i]->funcs->ipp_destroy(&pool->base.ipps[i]);
1451 
1452 		if (pool->base.hubps[i] != NULL) {
1453 			kfree(TO_DCN20_HUBP(pool->base.hubps[i]));
1454 			pool->base.hubps[i] = NULL;
1455 		}
1456 
1457 		if (pool->base.irqs != NULL)
1458 			dal_irq_service_destroy(&pool->base.irqs);
1459 	}
1460 
1461 	for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
1462 		if (pool->base.engines[i] != NULL)
1463 			dce110_engine_destroy(&pool->base.engines[i]);
1464 		if (pool->base.hw_i2cs[i] != NULL) {
1465 			kfree(pool->base.hw_i2cs[i]);
1466 			pool->base.hw_i2cs[i] = NULL;
1467 		}
1468 		if (pool->base.sw_i2cs[i] != NULL) {
1469 			kfree(pool->base.sw_i2cs[i]);
1470 			pool->base.sw_i2cs[i] = NULL;
1471 		}
1472 	}
1473 
1474 	for (i = 0; i < pool->base.res_cap->num_opp; i++) {
1475 		if (pool->base.opps[i] != NULL)
1476 			pool->base.opps[i]->funcs->opp_destroy(&pool->base.opps[i]);
1477 	}
1478 
1479 	for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {
1480 		if (pool->base.timing_generators[i] != NULL)	{
1481 			kfree(DCN10TG_FROM_TG(pool->base.timing_generators[i]));
1482 			pool->base.timing_generators[i] = NULL;
1483 		}
1484 	}
1485 
1486 	for (i = 0; i < pool->base.res_cap->num_dwb; i++) {
1487 		if (pool->base.dwbc[i] != NULL) {
1488 			kfree(TO_DCN30_DWBC(pool->base.dwbc[i]));
1489 			pool->base.dwbc[i] = NULL;
1490 		}
1491 		if (pool->base.mcif_wb[i] != NULL) {
1492 			kfree(TO_DCN30_MMHUBBUB(pool->base.mcif_wb[i]));
1493 			pool->base.mcif_wb[i] = NULL;
1494 		}
1495 	}
1496 
1497 	for (i = 0; i < pool->base.audio_count; i++) {
1498 		if (pool->base.audios[i])
1499 			dce_aud_destroy(&pool->base.audios[i]);
1500 	}
1501 
1502 	for (i = 0; i < pool->base.clk_src_count; i++) {
1503 		if (pool->base.clock_sources[i] != NULL) {
1504 			dcn20_clock_source_destroy(&pool->base.clock_sources[i]);
1505 			pool->base.clock_sources[i] = NULL;
1506 		}
1507 	}
1508 
1509 	for (i = 0; i < pool->base.res_cap->num_mpc_3dlut; i++) {
1510 		if (pool->base.mpc_lut[i] != NULL) {
1511 			dc_3dlut_func_release(pool->base.mpc_lut[i]);
1512 			pool->base.mpc_lut[i] = NULL;
1513 		}
1514 		if (pool->base.mpc_shaper[i] != NULL) {
1515 			dc_transfer_func_release(pool->base.mpc_shaper[i]);
1516 			pool->base.mpc_shaper[i] = NULL;
1517 		}
1518 	}
1519 
1520 	if (pool->base.dp_clock_source != NULL) {
1521 		dcn20_clock_source_destroy(&pool->base.dp_clock_source);
1522 		pool->base.dp_clock_source = NULL;
1523 	}
1524 
1525 	for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {
1526 		if (pool->base.multiple_abms[i] != NULL)
1527 			dce_abm_destroy(&pool->base.multiple_abms[i]);
1528 	}
1529 
1530 	if (pool->base.psr != NULL)
1531 		dmub_psr_destroy(&pool->base.psr);
1532 
1533 	if (pool->base.dccg != NULL)
1534 		dcn_dccg_destroy(&pool->base.dccg);
1535 }
1536 
1537 static struct hubp *dcn31_hubp_create(
1538 	struct dc_context *ctx,
1539 	uint32_t inst)
1540 {
1541 	struct dcn20_hubp *hubp2 =
1542 		kzalloc(sizeof(struct dcn20_hubp), GFP_KERNEL);
1543 
1544 	if (!hubp2)
1545 		return NULL;
1546 
1547 	if (hubp31_construct(hubp2, ctx, inst,
1548 			&hubp_regs[inst], &hubp_shift, &hubp_mask))
1549 		return &hubp2->base;
1550 
1551 	BREAK_TO_DEBUGGER();
1552 	kfree(hubp2);
1553 	return NULL;
1554 }
1555 
1556 static bool dcn31_dwbc_create(struct dc_context *ctx, struct resource_pool *pool)
1557 {
1558 	int i;
1559 	uint32_t pipe_count = pool->res_cap->num_dwb;
1560 
1561 	for (i = 0; i < pipe_count; i++) {
1562 		struct dcn30_dwbc *dwbc30 = kzalloc(sizeof(struct dcn30_dwbc),
1563 						    GFP_KERNEL);
1564 
1565 		if (!dwbc30) {
1566 			dm_error("DC: failed to create dwbc30!\n");
1567 			return false;
1568 		}
1569 
1570 		dcn30_dwbc_construct(dwbc30, ctx,
1571 				&dwbc30_regs[i],
1572 				&dwbc30_shift,
1573 				&dwbc30_mask,
1574 				i);
1575 
1576 		pool->dwbc[i] = &dwbc30->base;
1577 	}
1578 	return true;
1579 }
1580 
1581 static bool dcn31_mmhubbub_create(struct dc_context *ctx, struct resource_pool *pool)
1582 {
1583 	int i;
1584 	uint32_t pipe_count = pool->res_cap->num_dwb;
1585 
1586 	for (i = 0; i < pipe_count; i++) {
1587 		struct dcn30_mmhubbub *mcif_wb30 = kzalloc(sizeof(struct dcn30_mmhubbub),
1588 						    GFP_KERNEL);
1589 
1590 		if (!mcif_wb30) {
1591 			dm_error("DC: failed to create mcif_wb30!\n");
1592 			return false;
1593 		}
1594 
1595 		dcn30_mmhubbub_construct(mcif_wb30, ctx,
1596 				&mcif_wb30_regs[i],
1597 				&mcif_wb30_shift,
1598 				&mcif_wb30_mask,
1599 				i);
1600 
1601 		pool->mcif_wb[i] = &mcif_wb30->base;
1602 	}
1603 	return true;
1604 }
1605 
1606 static struct display_stream_compressor *dcn314_dsc_create(
1607 	struct dc_context *ctx, uint32_t inst)
1608 {
1609 	struct dcn20_dsc *dsc =
1610 		kzalloc(sizeof(struct dcn20_dsc), GFP_KERNEL);
1611 
1612 	if (!dsc) {
1613 		BREAK_TO_DEBUGGER();
1614 		return NULL;
1615 	}
1616 
1617 	dsc2_construct(dsc, ctx, inst, &dsc_regs[inst], &dsc_shift, &dsc_mask);
1618 	return &dsc->base;
1619 }
1620 
1621 static void dcn314_destroy_resource_pool(struct resource_pool **pool)
1622 {
1623 	struct dcn314_resource_pool *dcn314_pool = TO_DCN314_RES_POOL(*pool);
1624 
1625 	dcn314_resource_destruct(dcn314_pool);
1626 	kfree(dcn314_pool);
1627 	*pool = NULL;
1628 }
1629 
1630 static struct clock_source *dcn31_clock_source_create(
1631 		struct dc_context *ctx,
1632 		struct dc_bios *bios,
1633 		enum clock_source_id id,
1634 		const struct dce110_clk_src_regs *regs,
1635 		bool dp_clk_src)
1636 {
1637 	struct dce110_clk_src *clk_src =
1638 		kzalloc(sizeof(struct dce110_clk_src), GFP_KERNEL);
1639 
1640 	if (!clk_src)
1641 		return NULL;
1642 
1643 	if (dcn31_clk_src_construct(clk_src, ctx, bios, id,
1644 			regs, &cs_shift, &cs_mask)) {
1645 		clk_src->base.dp_clk_src = dp_clk_src;
1646 		return &clk_src->base;
1647 	}
1648 
1649 	BREAK_TO_DEBUGGER();
1650 	return NULL;
1651 }
1652 
1653 static int dcn314_populate_dml_pipes_from_context(
1654 	struct dc *dc, struct dc_state *context,
1655 	display_e2e_pipe_params_st *pipes,
1656 	bool fast_validate)
1657 {
1658 	int pipe_cnt;
1659 
1660 	DC_FP_START();
1661 	pipe_cnt = dcn314_populate_dml_pipes_from_context_fpu(dc, context, pipes, fast_validate);
1662 	DC_FP_END();
1663 
1664 	return pipe_cnt;
1665 }
1666 
1667 static struct dc_cap_funcs cap_funcs = {
1668 	.get_dcc_compression_cap = dcn20_get_dcc_compression_cap
1669 };
1670 
1671 static void dcn314_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params)
1672 {
1673 	DC_FP_START();
1674 	dcn314_update_bw_bounding_box_fpu(dc, bw_params);
1675 	DC_FP_END();
1676 }
1677 
1678 static struct resource_funcs dcn314_res_pool_funcs = {
1679 	.destroy = dcn314_destroy_resource_pool,
1680 	.link_enc_create = dcn31_link_encoder_create,
1681 	.link_enc_create_minimal = dcn31_link_enc_create_minimal,
1682 	.link_encs_assign = link_enc_cfg_link_encs_assign,
1683 	.link_enc_unassign = link_enc_cfg_link_enc_unassign,
1684 	.panel_cntl_create = dcn31_panel_cntl_create,
1685 	.validate_bandwidth = dcn31_validate_bandwidth,
1686 	.calculate_wm_and_dlg = dcn31_calculate_wm_and_dlg,
1687 	.update_soc_for_wm_a = dcn31_update_soc_for_wm_a,
1688 	.populate_dml_pipes = dcn314_populate_dml_pipes_from_context,
1689 	.acquire_idle_pipe_for_layer = dcn20_acquire_idle_pipe_for_layer,
1690 	.add_stream_to_ctx = dcn30_add_stream_to_ctx,
1691 	.add_dsc_to_stream_resource = dcn20_add_dsc_to_stream_resource,
1692 	.remove_stream_from_ctx = dcn20_remove_stream_from_ctx,
1693 	.populate_dml_writeback_from_context = dcn30_populate_dml_writeback_from_context,
1694 	.set_mcif_arb_params = dcn30_set_mcif_arb_params,
1695 	.find_first_free_match_stream_enc_for_link = dcn10_find_first_free_match_stream_enc_for_link,
1696 	.acquire_post_bldn_3dlut = dcn30_acquire_post_bldn_3dlut,
1697 	.release_post_bldn_3dlut = dcn30_release_post_bldn_3dlut,
1698 	.update_bw_bounding_box = dcn314_update_bw_bounding_box,
1699 	.patch_unknown_plane_state = dcn20_patch_unknown_plane_state,
1700 };
1701 
1702 static struct clock_source *dcn30_clock_source_create(
1703 		struct dc_context *ctx,
1704 		struct dc_bios *bios,
1705 		enum clock_source_id id,
1706 		const struct dce110_clk_src_regs *regs,
1707 		bool dp_clk_src)
1708 {
1709 	struct dce110_clk_src *clk_src =
1710 		kzalloc(sizeof(struct dce110_clk_src), GFP_KERNEL);
1711 
1712 	if (!clk_src)
1713 		return NULL;
1714 
1715 	if (dcn31_clk_src_construct(clk_src, ctx, bios, id,
1716 			regs, &cs_shift, &cs_mask)) {
1717 		clk_src->base.dp_clk_src = dp_clk_src;
1718 		return &clk_src->base;
1719 	}
1720 
1721 	BREAK_TO_DEBUGGER();
1722 	return NULL;
1723 }
1724 
1725 static bool dcn314_resource_construct(
1726 	uint8_t num_virtual_links,
1727 	struct dc *dc,
1728 	struct dcn314_resource_pool *pool)
1729 {
1730 	int i;
1731 	struct dc_context *ctx = dc->ctx;
1732 	struct irq_service_init_data init_data;
1733 
1734 	ctx->dc_bios->regs = &bios_regs;
1735 
1736 	pool->base.res_cap = &res_cap_dcn314;
1737 	pool->base.funcs = &dcn314_res_pool_funcs;
1738 
1739 	/*************************************************
1740 	 *  Resource + asic cap harcoding                *
1741 	 *************************************************/
1742 	pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE;
1743 	pool->base.pipe_count = pool->base.res_cap->num_timing_generator;
1744 	pool->base.mpcc_count = pool->base.res_cap->num_timing_generator;
1745 	dc->caps.max_downscale_ratio = 600;
1746 	dc->caps.i2c_speed_in_khz = 100;
1747 	dc->caps.i2c_speed_in_khz_hdcp = 100;
1748 	dc->caps.max_cursor_size = 256;
1749 	dc->caps.min_horizontal_blanking_period = 80;
1750 	dc->caps.dmdata_alloc_size = 2048;
1751 	dc->caps.max_slave_planes = 2;
1752 	dc->caps.max_slave_yuv_planes = 2;
1753 	dc->caps.max_slave_rgb_planes = 2;
1754 	dc->caps.post_blend_color_processing = true;
1755 	dc->caps.force_dp_tps4_for_cp2520 = true;
1756 	dc->caps.dp_hpo = true;
1757 	dc->caps.dp_hdmi21_pcon_support = true;
1758 	dc->caps.edp_dsc_support = true;
1759 	dc->caps.extended_aux_timeout_support = true;
1760 	dc->caps.dmcub_support = true;
1761 	dc->caps.is_apu = true;
1762 	dc->caps.seamless_odm = true;
1763 
1764 	dc->caps.zstate_support = true;
1765 
1766 	/* Color pipeline capabilities */
1767 	dc->caps.color.dpp.dcn_arch = 1;
1768 	dc->caps.color.dpp.input_lut_shared = 0;
1769 	dc->caps.color.dpp.icsc = 1;
1770 	dc->caps.color.dpp.dgam_ram = 0; // must use gamma_corr
1771 	dc->caps.color.dpp.dgam_rom_caps.srgb = 1;
1772 	dc->caps.color.dpp.dgam_rom_caps.bt2020 = 1;
1773 	dc->caps.color.dpp.dgam_rom_caps.gamma2_2 = 1;
1774 	dc->caps.color.dpp.dgam_rom_caps.pq = 1;
1775 	dc->caps.color.dpp.dgam_rom_caps.hlg = 1;
1776 	dc->caps.color.dpp.post_csc = 1;
1777 	dc->caps.color.dpp.gamma_corr = 1;
1778 	dc->caps.color.dpp.dgam_rom_for_yuv = 0;
1779 
1780 	dc->caps.color.dpp.hw_3d_lut = 1;
1781 	dc->caps.color.dpp.ogam_ram = 1;
1782 	// no OGAM ROM on DCN301
1783 	dc->caps.color.dpp.ogam_rom_caps.srgb = 0;
1784 	dc->caps.color.dpp.ogam_rom_caps.bt2020 = 0;
1785 	dc->caps.color.dpp.ogam_rom_caps.gamma2_2 = 0;
1786 	dc->caps.color.dpp.ogam_rom_caps.pq = 0;
1787 	dc->caps.color.dpp.ogam_rom_caps.hlg = 0;
1788 	dc->caps.color.dpp.ocsc = 0;
1789 
1790 	dc->caps.color.mpc.gamut_remap = 1;
1791 	dc->caps.color.mpc.num_3dluts = pool->base.res_cap->num_mpc_3dlut; //2
1792 	dc->caps.color.mpc.ogam_ram = 1;
1793 	dc->caps.color.mpc.ogam_rom_caps.srgb = 0;
1794 	dc->caps.color.mpc.ogam_rom_caps.bt2020 = 0;
1795 	dc->caps.color.mpc.ogam_rom_caps.gamma2_2 = 0;
1796 	dc->caps.color.mpc.ogam_rom_caps.pq = 0;
1797 	dc->caps.color.mpc.ogam_rom_caps.hlg = 0;
1798 	dc->caps.color.mpc.ocsc = 1;
1799 
1800 	/* Use pipe context based otg sync logic */
1801 	dc->config.use_pipe_ctx_sync_logic = true;
1802 
1803 	/* read VBIOS LTTPR caps */
1804 	{
1805 		if (ctx->dc_bios->funcs->get_lttpr_caps) {
1806 			enum bp_result bp_query_result;
1807 			uint8_t is_vbios_lttpr_enable = 0;
1808 
1809 			bp_query_result = ctx->dc_bios->funcs->get_lttpr_caps(ctx->dc_bios, &is_vbios_lttpr_enable);
1810 			dc->caps.vbios_lttpr_enable = (bp_query_result == BP_RESULT_OK) && !!is_vbios_lttpr_enable;
1811 		}
1812 
1813 		/* interop bit is implicit */
1814 		{
1815 			dc->caps.vbios_lttpr_aware = true;
1816 		}
1817 	}
1818 
1819 	if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV)
1820 		dc->debug = debug_defaults_drv;
1821 	else if (dc->ctx->dce_environment == DCE_ENV_FPGA_MAXIMUS)
1822 		dc->debug = debug_defaults_diags;
1823 	else
1824 		dc->debug = debug_defaults_diags;
1825 	// Init the vm_helper
1826 	if (dc->vm_helper)
1827 		vm_helper_init(dc->vm_helper, 16);
1828 
1829 	/*************************************************
1830 	 *  Create resources                             *
1831 	 *************************************************/
1832 
1833 	/* Clock Sources for Pixel Clock*/
1834 	pool->base.clock_sources[DCN31_CLK_SRC_PLL0] =
1835 			dcn30_clock_source_create(ctx, ctx->dc_bios,
1836 				CLOCK_SOURCE_COMBO_PHY_PLL0,
1837 				&clk_src_regs[0], false);
1838 	pool->base.clock_sources[DCN31_CLK_SRC_PLL1] =
1839 			dcn30_clock_source_create(ctx, ctx->dc_bios,
1840 				CLOCK_SOURCE_COMBO_PHY_PLL1,
1841 				&clk_src_regs[1], false);
1842 	pool->base.clock_sources[DCN31_CLK_SRC_PLL2] =
1843 			dcn30_clock_source_create(ctx, ctx->dc_bios,
1844 				CLOCK_SOURCE_COMBO_PHY_PLL2,
1845 				&clk_src_regs[2], false);
1846 	pool->base.clock_sources[DCN31_CLK_SRC_PLL3] =
1847 			dcn30_clock_source_create(ctx, ctx->dc_bios,
1848 				CLOCK_SOURCE_COMBO_PHY_PLL3,
1849 				&clk_src_regs[3], false);
1850 	pool->base.clock_sources[DCN31_CLK_SRC_PLL4] =
1851 			dcn30_clock_source_create(ctx, ctx->dc_bios,
1852 				CLOCK_SOURCE_COMBO_PHY_PLL4,
1853 				&clk_src_regs[4], false);
1854 
1855 	pool->base.clk_src_count = DCN30_CLK_SRC_TOTAL;
1856 
1857 	/* todo: not reuse phy_pll registers */
1858 	pool->base.dp_clock_source =
1859 			dcn31_clock_source_create(ctx, ctx->dc_bios,
1860 				CLOCK_SOURCE_ID_DP_DTO,
1861 				&clk_src_regs[0], true);
1862 
1863 	for (i = 0; i < pool->base.clk_src_count; i++) {
1864 		if (pool->base.clock_sources[i] == NULL) {
1865 			dm_error("DC: failed to create clock sources!\n");
1866 			BREAK_TO_DEBUGGER();
1867 			goto create_fail;
1868 		}
1869 	}
1870 
1871 	pool->base.dccg = dccg314_create(ctx, &dccg_regs, &dccg_shift, &dccg_mask);
1872 	if (pool->base.dccg == NULL) {
1873 		dm_error("DC: failed to create dccg!\n");
1874 		BREAK_TO_DEBUGGER();
1875 		goto create_fail;
1876 	}
1877 
1878 	init_data.ctx = dc->ctx;
1879 	pool->base.irqs = dal_irq_service_dcn314_create(&init_data);
1880 	if (!pool->base.irqs)
1881 		goto create_fail;
1882 
1883 	/* HUBBUB */
1884 	pool->base.hubbub = dcn31_hubbub_create(ctx);
1885 	if (pool->base.hubbub == NULL) {
1886 		BREAK_TO_DEBUGGER();
1887 		dm_error("DC: failed to create hubbub!\n");
1888 		goto create_fail;
1889 	}
1890 
1891 	/* HUBPs, DPPs, OPPs and TGs */
1892 	for (i = 0; i < pool->base.pipe_count; i++) {
1893 		pool->base.hubps[i] = dcn31_hubp_create(ctx, i);
1894 		if (pool->base.hubps[i] == NULL) {
1895 			BREAK_TO_DEBUGGER();
1896 			dm_error(
1897 				"DC: failed to create hubps!\n");
1898 			goto create_fail;
1899 		}
1900 
1901 		pool->base.dpps[i] = dcn31_dpp_create(ctx, i);
1902 		if (pool->base.dpps[i] == NULL) {
1903 			BREAK_TO_DEBUGGER();
1904 			dm_error(
1905 				"DC: failed to create dpps!\n");
1906 			goto create_fail;
1907 		}
1908 	}
1909 
1910 	for (i = 0; i < pool->base.res_cap->num_opp; i++) {
1911 		pool->base.opps[i] = dcn31_opp_create(ctx, i);
1912 		if (pool->base.opps[i] == NULL) {
1913 			BREAK_TO_DEBUGGER();
1914 			dm_error(
1915 				"DC: failed to create output pixel processor!\n");
1916 			goto create_fail;
1917 		}
1918 	}
1919 
1920 	for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {
1921 		pool->base.timing_generators[i] = dcn31_timing_generator_create(
1922 				ctx, i);
1923 		if (pool->base.timing_generators[i] == NULL) {
1924 			BREAK_TO_DEBUGGER();
1925 			dm_error("DC: failed to create tg!\n");
1926 			goto create_fail;
1927 		}
1928 	}
1929 	pool->base.timing_generator_count = i;
1930 
1931 	/* PSR */
1932 	pool->base.psr = dmub_psr_create(ctx);
1933 	if (pool->base.psr == NULL) {
1934 		dm_error("DC: failed to create psr obj!\n");
1935 		BREAK_TO_DEBUGGER();
1936 		goto create_fail;
1937 	}
1938 
1939 	/* ABM */
1940 	for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {
1941 		pool->base.multiple_abms[i] = dmub_abm_create(ctx,
1942 				&abm_regs[i],
1943 				&abm_shift,
1944 				&abm_mask);
1945 		if (pool->base.multiple_abms[i] == NULL) {
1946 			dm_error("DC: failed to create abm for pipe %d!\n", i);
1947 			BREAK_TO_DEBUGGER();
1948 			goto create_fail;
1949 		}
1950 	}
1951 
1952 	/* MPC and DSC */
1953 	pool->base.mpc = dcn31_mpc_create(ctx, pool->base.mpcc_count, pool->base.res_cap->num_mpc_3dlut);
1954 	if (pool->base.mpc == NULL) {
1955 		BREAK_TO_DEBUGGER();
1956 		dm_error("DC: failed to create mpc!\n");
1957 		goto create_fail;
1958 	}
1959 
1960 	for (i = 0; i < pool->base.res_cap->num_dsc; i++) {
1961 		pool->base.dscs[i] = dcn314_dsc_create(ctx, i);
1962 		if (pool->base.dscs[i] == NULL) {
1963 			BREAK_TO_DEBUGGER();
1964 			dm_error("DC: failed to create display stream compressor %d!\n", i);
1965 			goto create_fail;
1966 		}
1967 	}
1968 
1969 	/* DWB and MMHUBBUB */
1970 	if (!dcn31_dwbc_create(ctx, &pool->base)) {
1971 		BREAK_TO_DEBUGGER();
1972 		dm_error("DC: failed to create dwbc!\n");
1973 		goto create_fail;
1974 	}
1975 
1976 	if (!dcn31_mmhubbub_create(ctx, &pool->base)) {
1977 		BREAK_TO_DEBUGGER();
1978 		dm_error("DC: failed to create mcif_wb!\n");
1979 		goto create_fail;
1980 	}
1981 
1982 	/* AUX and I2C */
1983 	for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
1984 		pool->base.engines[i] = dcn31_aux_engine_create(ctx, i);
1985 		if (pool->base.engines[i] == NULL) {
1986 			BREAK_TO_DEBUGGER();
1987 			dm_error(
1988 				"DC:failed to create aux engine!!\n");
1989 			goto create_fail;
1990 		}
1991 		pool->base.hw_i2cs[i] = dcn31_i2c_hw_create(ctx, i);
1992 		if (pool->base.hw_i2cs[i] == NULL) {
1993 			BREAK_TO_DEBUGGER();
1994 			dm_error(
1995 				"DC:failed to create hw i2c!!\n");
1996 			goto create_fail;
1997 		}
1998 		pool->base.sw_i2cs[i] = NULL;
1999 	}
2000 
2001 	/* DCN314 has 4 DPIA */
2002 	pool->base.usb4_dpia_count = 4;
2003 
2004 	/* Audio, Stream Encoders including HPO and virtual, MPC 3D LUTs */
2005 	if (!resource_construct(num_virtual_links, dc, &pool->base,
2006 				(!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment) ?
2007 				 &res_create_funcs : &res_create_maximus_funcs)))
2008 		goto create_fail;
2009 
2010 	/* HW Sequencer and Plane caps */
2011 	dcn314_hw_sequencer_construct(dc);
2012 
2013 	dc->caps.max_planes =  pool->base.pipe_count;
2014 
2015 	for (i = 0; i < dc->caps.max_planes; ++i)
2016 		dc->caps.planes[i] = plane_cap;
2017 
2018 	dc->cap_funcs = cap_funcs;
2019 
2020 	dc->dcn_ip->max_num_dpp = dcn3_14_ip.max_num_dpp;
2021 
2022 	return true;
2023 
2024 create_fail:
2025 
2026 	dcn314_resource_destruct(pool);
2027 
2028 	return false;
2029 }
2030 
2031 struct resource_pool *dcn314_create_resource_pool(
2032 		const struct dc_init_data *init_data,
2033 		struct dc *dc)
2034 {
2035 	struct dcn314_resource_pool *pool =
2036 		kzalloc(sizeof(struct dcn314_resource_pool), GFP_KERNEL);
2037 
2038 	if (!pool)
2039 		return NULL;
2040 
2041 	if (dcn314_resource_construct(init_data->num_virtual_links, dc, pool))
2042 		return &pool->base;
2043 
2044 	BREAK_TO_DEBUGGER();
2045 	kfree(pool);
2046 	return NULL;
2047 }
2048