1 // SPDX-License-Identifier: MIT 2 /* 3 * Copyright 2022 Advanced Micro Devices, Inc. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 * 23 * Authors: AMD 24 * 25 */ 26 27 28 #include "dm_services.h" 29 #include "dc.h" 30 31 #include "dcn31/dcn31_init.h" 32 #include "dcn314/dcn314_init.h" 33 34 #include "resource.h" 35 #include "include/irq_service_interface.h" 36 #include "dcn314_resource.h" 37 38 #include "dcn20/dcn20_resource.h" 39 #include "dcn30/dcn30_resource.h" 40 #include "dcn31/dcn31_resource.h" 41 42 #include "dcn10/dcn10_ipp.h" 43 #include "dcn30/dcn30_hubbub.h" 44 #include "dcn31/dcn31_hubbub.h" 45 #include "dcn30/dcn30_mpc.h" 46 #include "dcn31/dcn31_hubp.h" 47 #include "irq/dcn31/irq_service_dcn31.h" 48 #include "irq/dcn314/irq_service_dcn314.h" 49 #include "dcn30/dcn30_dpp.h" 50 #include "dcn314/dcn314_optc.h" 51 #include "dcn20/dcn20_hwseq.h" 52 #include "dcn30/dcn30_hwseq.h" 53 #include "dce110/dce110_hw_sequencer.h" 54 #include "dcn30/dcn30_opp.h" 55 #include "dcn20/dcn20_dsc.h" 56 #include "dcn30/dcn30_vpg.h" 57 #include "dcn30/dcn30_afmt.h" 58 #include "dcn31/dcn31_dio_link_encoder.h" 59 #include "dcn314/dcn314_dio_stream_encoder.h" 60 #include "dcn31/dcn31_hpo_dp_stream_encoder.h" 61 #include "dcn31/dcn31_hpo_dp_link_encoder.h" 62 #include "dcn31/dcn31_apg.h" 63 #include "dcn31/dcn31_vpg.h" 64 #include "dcn31/dcn31_afmt.h" 65 #include "dce/dce_clock_source.h" 66 #include "dce/dce_audio.h" 67 #include "dce/dce_hwseq.h" 68 #include "clk_mgr.h" 69 #include "virtual/virtual_stream_encoder.h" 70 #include "dce110/dce110_resource.h" 71 #include "dml/display_mode_vba.h" 72 #include "dml/dcn31/dcn31_fpu.h" 73 #include "dml/dcn314/dcn314_fpu.h" 74 #include "dcn314/dcn314_dccg.h" 75 #include "dcn10/dcn10_resource.h" 76 #include "dcn31/dcn31_panel_cntl.h" 77 #include "dcn314/dcn314_hwseq.h" 78 79 #include "dcn30/dcn30_dwb.h" 80 #include "dcn30/dcn30_mmhubbub.h" 81 82 #include "dcn/dcn_3_1_4_offset.h" 83 #include "dcn/dcn_3_1_4_sh_mask.h" 84 #include "dpcs/dpcs_3_1_4_offset.h" 85 #include "dpcs/dpcs_3_1_4_sh_mask.h" 86 87 #define DCHUBBUB_DEBUG_CTRL_0__DET_DEPTH__SHIFT 0x10 88 #define DCHUBBUB_DEBUG_CTRL_0__DET_DEPTH_MASK 0x01FF0000L 89 90 #define DSCC0_DSCC_CONFIG0__ICH_RESET_AT_END_OF_LINE__SHIFT 0x0 91 #define DSCC0_DSCC_CONFIG0__ICH_RESET_AT_END_OF_LINE_MASK 0x0000000FL 92 93 #include "reg_helper.h" 94 #include "dce/dmub_abm.h" 95 #include "dce/dmub_psr.h" 96 #include "dce/dce_aux.h" 97 #include "dce/dce_i2c.h" 98 #include "dml/dcn314/display_mode_vba_314.h" 99 #include "vm_helper.h" 100 #include "dcn20/dcn20_vmid.h" 101 102 #include "link_enc_cfg.h" 103 104 #define DCN_BASE__INST0_SEG1 0x000000C0 105 #define DCN_BASE__INST0_SEG2 0x000034C0 106 #define DCN_BASE__INST0_SEG3 0x00009000 107 108 #define NBIO_BASE__INST0_SEG1 0x00000014 109 110 #define MAX_INSTANCE 7 111 #define MAX_SEGMENT 8 112 113 #define regBIF_BX2_BIOS_SCRATCH_2 0x003a 114 #define regBIF_BX2_BIOS_SCRATCH_2_BASE_IDX 1 115 #define regBIF_BX2_BIOS_SCRATCH_3 0x003b 116 #define regBIF_BX2_BIOS_SCRATCH_3_BASE_IDX 1 117 #define regBIF_BX2_BIOS_SCRATCH_6 0x003e 118 #define regBIF_BX2_BIOS_SCRATCH_6_BASE_IDX 1 119 120 struct IP_BASE_INSTANCE { 121 unsigned int segment[MAX_SEGMENT]; 122 }; 123 124 struct IP_BASE { 125 struct IP_BASE_INSTANCE instance[MAX_INSTANCE]; 126 }; 127 128 static const struct IP_BASE DCN_BASE = { { { { 0x00000012, 0x000000C0, 0x000034C0, 0x00009000, 0x02403C00, 0, 0, 0 } }, 129 { { 0, 0, 0, 0, 0, 0, 0, 0 } }, 130 { { 0, 0, 0, 0, 0, 0, 0, 0 } }, 131 { { 0, 0, 0, 0, 0, 0, 0, 0 } }, 132 { { 0, 0, 0, 0, 0, 0, 0, 0 } }, 133 { { 0, 0, 0, 0, 0, 0, 0, 0 } }, 134 { { 0, 0, 0, 0, 0, 0, 0, 0 } } } }; 135 136 137 #define DC_LOGGER_INIT(logger) 138 139 enum dcn31_clk_src_array_id { 140 DCN31_CLK_SRC_PLL0, 141 DCN31_CLK_SRC_PLL1, 142 DCN31_CLK_SRC_PLL2, 143 DCN31_CLK_SRC_PLL3, 144 DCN31_CLK_SRC_PLL4, 145 DCN30_CLK_SRC_TOTAL 146 }; 147 148 /* begin ********************* 149 * macros to expend register list macro defined in HW object header file 150 */ 151 152 /* DCN */ 153 /* TODO awful hack. fixup dcn20_dwb.h */ 154 #undef BASE_INNER 155 #define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg 156 157 #define BASE(seg) BASE_INNER(seg) 158 159 #define SR(reg_name)\ 160 .reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \ 161 reg ## reg_name 162 163 #define SRI(reg_name, block, id)\ 164 .reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 165 reg ## block ## id ## _ ## reg_name 166 167 #define SRI2(reg_name, block, id)\ 168 .reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \ 169 reg ## reg_name 170 171 #define SRIR(var_name, reg_name, block, id)\ 172 .var_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 173 reg ## block ## id ## _ ## reg_name 174 175 #define SRII(reg_name, block, id)\ 176 .reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 177 reg ## block ## id ## _ ## reg_name 178 179 #define SRII_MPC_RMU(reg_name, block, id)\ 180 .RMU##_##reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 181 reg ## block ## id ## _ ## reg_name 182 183 #define SRII_DWB(reg_name, temp_name, block, id)\ 184 .reg_name[id] = BASE(reg ## block ## id ## _ ## temp_name ## _BASE_IDX) + \ 185 reg ## block ## id ## _ ## temp_name 186 187 #define DCCG_SRII(reg_name, block, id)\ 188 .block ## _ ## reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 189 reg ## block ## id ## _ ## reg_name 190 191 #define VUPDATE_SRII(reg_name, block, id)\ 192 .reg_name[id] = BASE(reg ## reg_name ## _ ## block ## id ## _BASE_IDX) + \ 193 reg ## reg_name ## _ ## block ## id 194 195 /* NBIO */ 196 #define NBIO_BASE_INNER(seg) \ 197 NBIO_BASE__INST0_SEG ## seg 198 199 #define NBIO_BASE(seg) \ 200 NBIO_BASE_INNER(seg) 201 202 #define NBIO_SR(reg_name)\ 203 .reg_name = NBIO_BASE(regBIF_BX2_ ## reg_name ## _BASE_IDX) + \ 204 regBIF_BX2_ ## reg_name 205 206 /* MMHUB */ 207 #define MMHUB_BASE_INNER(seg) \ 208 MMHUB_BASE__INST0_SEG ## seg 209 210 #define MMHUB_BASE(seg) \ 211 MMHUB_BASE_INNER(seg) 212 213 #define MMHUB_SR(reg_name)\ 214 .reg_name = MMHUB_BASE(reg ## reg_name ## _BASE_IDX) + \ 215 reg ## reg_name 216 217 /* CLOCK */ 218 #define CLK_BASE_INNER(seg) \ 219 CLK_BASE__INST0_SEG ## seg 220 221 #define CLK_BASE(seg) \ 222 CLK_BASE_INNER(seg) 223 224 #define CLK_SRI(reg_name, block, inst)\ 225 .reg_name = CLK_BASE(reg ## block ## _ ## inst ## _ ## reg_name ## _BASE_IDX) + \ 226 reg ## block ## _ ## inst ## _ ## reg_name 227 228 229 static const struct bios_registers bios_regs = { 230 NBIO_SR(BIOS_SCRATCH_3), 231 NBIO_SR(BIOS_SCRATCH_6) 232 }; 233 234 #define clk_src_regs(index, pllid)\ 235 [index] = {\ 236 CS_COMMON_REG_LIST_DCN3_0(index, pllid),\ 237 } 238 239 static const struct dce110_clk_src_regs clk_src_regs[] = { 240 clk_src_regs(0, A), 241 clk_src_regs(1, B), 242 clk_src_regs(2, C), 243 clk_src_regs(3, D), 244 clk_src_regs(4, E) 245 }; 246 247 static const struct dce110_clk_src_shift cs_shift = { 248 CS_COMMON_MASK_SH_LIST_DCN3_1_4(__SHIFT) 249 }; 250 251 static const struct dce110_clk_src_mask cs_mask = { 252 CS_COMMON_MASK_SH_LIST_DCN3_1_4(_MASK) 253 }; 254 255 #define abm_regs(id)\ 256 [id] = {\ 257 ABM_DCN302_REG_LIST(id)\ 258 } 259 260 static const struct dce_abm_registers abm_regs[] = { 261 abm_regs(0), 262 abm_regs(1), 263 abm_regs(2), 264 abm_regs(3), 265 }; 266 267 static const struct dce_abm_shift abm_shift = { 268 ABM_MASK_SH_LIST_DCN30(__SHIFT) 269 }; 270 271 static const struct dce_abm_mask abm_mask = { 272 ABM_MASK_SH_LIST_DCN30(_MASK) 273 }; 274 275 #define audio_regs(id)\ 276 [id] = {\ 277 AUD_COMMON_REG_LIST(id)\ 278 } 279 280 static const struct dce_audio_registers audio_regs[] = { 281 audio_regs(0), 282 audio_regs(1), 283 audio_regs(2), 284 audio_regs(3), 285 audio_regs(4), 286 audio_regs(5), 287 audio_regs(6) 288 }; 289 290 #define DCE120_AUD_COMMON_MASK_SH_LIST(mask_sh)\ 291 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX, AZALIA_ENDPOINT_REG_INDEX, mask_sh),\ 292 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA, AZALIA_ENDPOINT_REG_DATA, mask_sh),\ 293 AUD_COMMON_MASK_SH_LIST_BASE(mask_sh) 294 295 static const struct dce_audio_shift audio_shift = { 296 DCE120_AUD_COMMON_MASK_SH_LIST(__SHIFT) 297 }; 298 299 static const struct dce_audio_mask audio_mask = { 300 DCE120_AUD_COMMON_MASK_SH_LIST(_MASK) 301 }; 302 303 #define vpg_regs(id)\ 304 [id] = {\ 305 VPG_DCN31_REG_LIST(id)\ 306 } 307 308 static const struct dcn31_vpg_registers vpg_regs[] = { 309 vpg_regs(0), 310 vpg_regs(1), 311 vpg_regs(2), 312 vpg_regs(3), 313 vpg_regs(4), 314 vpg_regs(5), 315 vpg_regs(6), 316 vpg_regs(7), 317 vpg_regs(8), 318 vpg_regs(9), 319 }; 320 321 static const struct dcn31_vpg_shift vpg_shift = { 322 DCN31_VPG_MASK_SH_LIST(__SHIFT) 323 }; 324 325 static const struct dcn31_vpg_mask vpg_mask = { 326 DCN31_VPG_MASK_SH_LIST(_MASK) 327 }; 328 329 #define afmt_regs(id)\ 330 [id] = {\ 331 AFMT_DCN31_REG_LIST(id)\ 332 } 333 334 static const struct dcn31_afmt_registers afmt_regs[] = { 335 afmt_regs(0), 336 afmt_regs(1), 337 afmt_regs(2), 338 afmt_regs(3), 339 afmt_regs(4), 340 afmt_regs(5) 341 }; 342 343 static const struct dcn31_afmt_shift afmt_shift = { 344 DCN31_AFMT_MASK_SH_LIST(__SHIFT) 345 }; 346 347 static const struct dcn31_afmt_mask afmt_mask = { 348 DCN31_AFMT_MASK_SH_LIST(_MASK) 349 }; 350 351 #define apg_regs(id)\ 352 [id] = {\ 353 APG_DCN31_REG_LIST(id)\ 354 } 355 356 static const struct dcn31_apg_registers apg_regs[] = { 357 apg_regs(0), 358 apg_regs(1), 359 apg_regs(2), 360 apg_regs(3) 361 }; 362 363 static const struct dcn31_apg_shift apg_shift = { 364 DCN31_APG_MASK_SH_LIST(__SHIFT) 365 }; 366 367 static const struct dcn31_apg_mask apg_mask = { 368 DCN31_APG_MASK_SH_LIST(_MASK) 369 }; 370 371 #define stream_enc_regs(id)\ 372 [id] = {\ 373 SE_DCN314_REG_LIST(id)\ 374 } 375 376 static const struct dcn10_stream_enc_registers stream_enc_regs[] = { 377 stream_enc_regs(0), 378 stream_enc_regs(1), 379 stream_enc_regs(2), 380 stream_enc_regs(3), 381 stream_enc_regs(4) 382 }; 383 384 static const struct dcn10_stream_encoder_shift se_shift = { 385 SE_COMMON_MASK_SH_LIST_DCN314(__SHIFT) 386 }; 387 388 static const struct dcn10_stream_encoder_mask se_mask = { 389 SE_COMMON_MASK_SH_LIST_DCN314(_MASK) 390 }; 391 392 393 #define aux_regs(id)\ 394 [id] = {\ 395 DCN2_AUX_REG_LIST(id)\ 396 } 397 398 static const struct dcn10_link_enc_aux_registers link_enc_aux_regs[] = { 399 aux_regs(0), 400 aux_regs(1), 401 aux_regs(2), 402 aux_regs(3), 403 aux_regs(4) 404 }; 405 406 #define hpd_regs(id)\ 407 [id] = {\ 408 HPD_REG_LIST(id)\ 409 } 410 411 static const struct dcn10_link_enc_hpd_registers link_enc_hpd_regs[] = { 412 hpd_regs(0), 413 hpd_regs(1), 414 hpd_regs(2), 415 hpd_regs(3), 416 hpd_regs(4) 417 }; 418 419 #define link_regs(id, phyid)\ 420 [id] = {\ 421 LE_DCN31_REG_LIST(id), \ 422 UNIPHY_DCN2_REG_LIST(phyid), \ 423 } 424 425 static const struct dce110_aux_registers_shift aux_shift = { 426 DCN_AUX_MASK_SH_LIST(__SHIFT) 427 }; 428 429 static const struct dce110_aux_registers_mask aux_mask = { 430 DCN_AUX_MASK_SH_LIST(_MASK) 431 }; 432 433 static const struct dcn10_link_enc_registers link_enc_regs[] = { 434 link_regs(0, A), 435 link_regs(1, B), 436 link_regs(2, C), 437 link_regs(3, D), 438 link_regs(4, E) 439 }; 440 441 static const struct dcn10_link_enc_shift le_shift = { 442 LINK_ENCODER_MASK_SH_LIST_DCN31(__SHIFT), 443 DPCS_DCN31_MASK_SH_LIST(__SHIFT) 444 }; 445 446 static const struct dcn10_link_enc_mask le_mask = { 447 LINK_ENCODER_MASK_SH_LIST_DCN31(_MASK), 448 DPCS_DCN31_MASK_SH_LIST(_MASK) 449 }; 450 451 #define hpo_dp_stream_encoder_reg_list(id)\ 452 [id] = {\ 453 DCN3_1_HPO_DP_STREAM_ENC_REG_LIST(id)\ 454 } 455 456 static const struct dcn31_hpo_dp_stream_encoder_registers hpo_dp_stream_enc_regs[] = { 457 hpo_dp_stream_encoder_reg_list(0), 458 hpo_dp_stream_encoder_reg_list(1), 459 hpo_dp_stream_encoder_reg_list(2), 460 hpo_dp_stream_encoder_reg_list(3) 461 }; 462 463 static const struct dcn31_hpo_dp_stream_encoder_shift hpo_dp_se_shift = { 464 DCN3_1_HPO_DP_STREAM_ENC_MASK_SH_LIST(__SHIFT) 465 }; 466 467 static const struct dcn31_hpo_dp_stream_encoder_mask hpo_dp_se_mask = { 468 DCN3_1_HPO_DP_STREAM_ENC_MASK_SH_LIST(_MASK) 469 }; 470 471 472 #define hpo_dp_link_encoder_reg_list(id)\ 473 [id] = {\ 474 DCN3_1_HPO_DP_LINK_ENC_REG_LIST(id),\ 475 DCN3_1_RDPCSTX_REG_LIST(0),\ 476 DCN3_1_RDPCSTX_REG_LIST(1),\ 477 DCN3_1_RDPCSTX_REG_LIST(2),\ 478 } 479 480 static const struct dcn31_hpo_dp_link_encoder_registers hpo_dp_link_enc_regs[] = { 481 hpo_dp_link_encoder_reg_list(0), 482 hpo_dp_link_encoder_reg_list(1), 483 }; 484 485 static const struct dcn31_hpo_dp_link_encoder_shift hpo_dp_le_shift = { 486 DCN3_1_HPO_DP_LINK_ENC_MASK_SH_LIST(__SHIFT) 487 }; 488 489 static const struct dcn31_hpo_dp_link_encoder_mask hpo_dp_le_mask = { 490 DCN3_1_HPO_DP_LINK_ENC_MASK_SH_LIST(_MASK) 491 }; 492 493 #define dpp_regs(id)\ 494 [id] = {\ 495 DPP_REG_LIST_DCN30(id),\ 496 } 497 498 static const struct dcn3_dpp_registers dpp_regs[] = { 499 dpp_regs(0), 500 dpp_regs(1), 501 dpp_regs(2), 502 dpp_regs(3) 503 }; 504 505 static const struct dcn3_dpp_shift tf_shift = { 506 DPP_REG_LIST_SH_MASK_DCN30(__SHIFT) 507 }; 508 509 static const struct dcn3_dpp_mask tf_mask = { 510 DPP_REG_LIST_SH_MASK_DCN30(_MASK) 511 }; 512 513 #define opp_regs(id)\ 514 [id] = {\ 515 OPP_REG_LIST_DCN30(id),\ 516 } 517 518 static const struct dcn20_opp_registers opp_regs[] = { 519 opp_regs(0), 520 opp_regs(1), 521 opp_regs(2), 522 opp_regs(3) 523 }; 524 525 static const struct dcn20_opp_shift opp_shift = { 526 OPP_MASK_SH_LIST_DCN20(__SHIFT) 527 }; 528 529 static const struct dcn20_opp_mask opp_mask = { 530 OPP_MASK_SH_LIST_DCN20(_MASK) 531 }; 532 533 #define aux_engine_regs(id)\ 534 [id] = {\ 535 AUX_COMMON_REG_LIST0(id), \ 536 .AUXN_IMPCAL = 0, \ 537 .AUXP_IMPCAL = 0, \ 538 .AUX_RESET_MASK = DP_AUX0_AUX_CONTROL__AUX_RESET_MASK, \ 539 } 540 541 static const struct dce110_aux_registers aux_engine_regs[] = { 542 aux_engine_regs(0), 543 aux_engine_regs(1), 544 aux_engine_regs(2), 545 aux_engine_regs(3), 546 aux_engine_regs(4) 547 }; 548 549 #define dwbc_regs_dcn3(id)\ 550 [id] = {\ 551 DWBC_COMMON_REG_LIST_DCN30(id),\ 552 } 553 554 static const struct dcn30_dwbc_registers dwbc30_regs[] = { 555 dwbc_regs_dcn3(0), 556 }; 557 558 static const struct dcn30_dwbc_shift dwbc30_shift = { 559 DWBC_COMMON_MASK_SH_LIST_DCN30(__SHIFT) 560 }; 561 562 static const struct dcn30_dwbc_mask dwbc30_mask = { 563 DWBC_COMMON_MASK_SH_LIST_DCN30(_MASK) 564 }; 565 566 #define mcif_wb_regs_dcn3(id)\ 567 [id] = {\ 568 MCIF_WB_COMMON_REG_LIST_DCN30(id),\ 569 } 570 571 static const struct dcn30_mmhubbub_registers mcif_wb30_regs[] = { 572 mcif_wb_regs_dcn3(0) 573 }; 574 575 static const struct dcn30_mmhubbub_shift mcif_wb30_shift = { 576 MCIF_WB_COMMON_MASK_SH_LIST_DCN30(__SHIFT) 577 }; 578 579 static const struct dcn30_mmhubbub_mask mcif_wb30_mask = { 580 MCIF_WB_COMMON_MASK_SH_LIST_DCN30(_MASK) 581 }; 582 583 #define dsc_regsDCN314(id)\ 584 [id] = {\ 585 DSC_REG_LIST_DCN20(id)\ 586 } 587 588 static const struct dcn20_dsc_registers dsc_regs[] = { 589 dsc_regsDCN314(0), 590 dsc_regsDCN314(1), 591 dsc_regsDCN314(2), 592 dsc_regsDCN314(3) 593 }; 594 595 static const struct dcn20_dsc_shift dsc_shift = { 596 DSC_REG_LIST_SH_MASK_DCN20(__SHIFT) 597 }; 598 599 static const struct dcn20_dsc_mask dsc_mask = { 600 DSC_REG_LIST_SH_MASK_DCN20(_MASK) 601 }; 602 603 static const struct dcn30_mpc_registers mpc_regs = { 604 MPC_REG_LIST_DCN3_0(0), 605 MPC_REG_LIST_DCN3_0(1), 606 MPC_REG_LIST_DCN3_0(2), 607 MPC_REG_LIST_DCN3_0(3), 608 MPC_OUT_MUX_REG_LIST_DCN3_0(0), 609 MPC_OUT_MUX_REG_LIST_DCN3_0(1), 610 MPC_OUT_MUX_REG_LIST_DCN3_0(2), 611 MPC_OUT_MUX_REG_LIST_DCN3_0(3), 612 MPC_RMU_GLOBAL_REG_LIST_DCN3AG, 613 MPC_RMU_REG_LIST_DCN3AG(0), 614 MPC_RMU_REG_LIST_DCN3AG(1), 615 //MPC_RMU_REG_LIST_DCN3AG(2), 616 MPC_DWB_MUX_REG_LIST_DCN3_0(0), 617 }; 618 619 static const struct dcn30_mpc_shift mpc_shift = { 620 MPC_COMMON_MASK_SH_LIST_DCN30(__SHIFT) 621 }; 622 623 static const struct dcn30_mpc_mask mpc_mask = { 624 MPC_COMMON_MASK_SH_LIST_DCN30(_MASK) 625 }; 626 627 #define optc_regs(id)\ 628 [id] = {OPTC_COMMON_REG_LIST_DCN3_14(id)} 629 630 static const struct dcn_optc_registers optc_regs[] = { 631 optc_regs(0), 632 optc_regs(1), 633 optc_regs(2), 634 optc_regs(3) 635 }; 636 637 static const struct dcn_optc_shift optc_shift = { 638 OPTC_COMMON_MASK_SH_LIST_DCN3_14(__SHIFT) 639 }; 640 641 static const struct dcn_optc_mask optc_mask = { 642 OPTC_COMMON_MASK_SH_LIST_DCN3_14(_MASK) 643 }; 644 645 #define hubp_regs(id)\ 646 [id] = {\ 647 HUBP_REG_LIST_DCN30(id)\ 648 } 649 650 static const struct dcn_hubp2_registers hubp_regs[] = { 651 hubp_regs(0), 652 hubp_regs(1), 653 hubp_regs(2), 654 hubp_regs(3) 655 }; 656 657 658 static const struct dcn_hubp2_shift hubp_shift = { 659 HUBP_MASK_SH_LIST_DCN31(__SHIFT) 660 }; 661 662 static const struct dcn_hubp2_mask hubp_mask = { 663 HUBP_MASK_SH_LIST_DCN31(_MASK) 664 }; 665 static const struct dcn_hubbub_registers hubbub_reg = { 666 HUBBUB_REG_LIST_DCN31(0) 667 }; 668 669 static const struct dcn_hubbub_shift hubbub_shift = { 670 HUBBUB_MASK_SH_LIST_DCN31(__SHIFT) 671 }; 672 673 static const struct dcn_hubbub_mask hubbub_mask = { 674 HUBBUB_MASK_SH_LIST_DCN31(_MASK) 675 }; 676 677 static const struct dccg_registers dccg_regs = { 678 DCCG_REG_LIST_DCN314() 679 }; 680 681 static const struct dccg_shift dccg_shift = { 682 DCCG_MASK_SH_LIST_DCN314(__SHIFT) 683 }; 684 685 static const struct dccg_mask dccg_mask = { 686 DCCG_MASK_SH_LIST_DCN314(_MASK) 687 }; 688 689 690 #define SRII2(reg_name_pre, reg_name_post, id)\ 691 .reg_name_pre ## _ ## reg_name_post[id] = BASE(reg ## reg_name_pre \ 692 ## id ## _ ## reg_name_post ## _BASE_IDX) + \ 693 reg ## reg_name_pre ## id ## _ ## reg_name_post 694 695 696 #define HWSEQ_DCN31_REG_LIST()\ 697 SR(DCHUBBUB_GLOBAL_TIMER_CNTL), \ 698 SR(DCHUBBUB_ARB_HOSTVM_CNTL), \ 699 SR(DIO_MEM_PWR_CTRL), \ 700 SR(ODM_MEM_PWR_CTRL3), \ 701 SR(DMU_MEM_PWR_CNTL), \ 702 SR(MMHUBBUB_MEM_PWR_CNTL), \ 703 SR(DCCG_GATE_DISABLE_CNTL), \ 704 SR(DCCG_GATE_DISABLE_CNTL2), \ 705 SR(DCFCLK_CNTL),\ 706 SR(DC_MEM_GLOBAL_PWR_REQ_CNTL), \ 707 SRII(PIXEL_RATE_CNTL, OTG, 0), \ 708 SRII(PIXEL_RATE_CNTL, OTG, 1),\ 709 SRII(PIXEL_RATE_CNTL, OTG, 2),\ 710 SRII(PIXEL_RATE_CNTL, OTG, 3),\ 711 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 0),\ 712 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 1),\ 713 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 2),\ 714 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 3),\ 715 SR(MICROSECOND_TIME_BASE_DIV), \ 716 SR(MILLISECOND_TIME_BASE_DIV), \ 717 SR(DISPCLK_FREQ_CHANGE_CNTL), \ 718 SR(RBBMIF_TIMEOUT_DIS), \ 719 SR(RBBMIF_TIMEOUT_DIS_2), \ 720 SR(DCHUBBUB_CRC_CTRL), \ 721 SR(DPP_TOP0_DPP_CRC_CTRL), \ 722 SR(DPP_TOP0_DPP_CRC_VAL_B_A), \ 723 SR(DPP_TOP0_DPP_CRC_VAL_R_G), \ 724 SR(MPC_CRC_CTRL), \ 725 SR(MPC_CRC_RESULT_GB), \ 726 SR(MPC_CRC_RESULT_C), \ 727 SR(MPC_CRC_RESULT_AR), \ 728 SR(DOMAIN0_PG_CONFIG), \ 729 SR(DOMAIN1_PG_CONFIG), \ 730 SR(DOMAIN2_PG_CONFIG), \ 731 SR(DOMAIN3_PG_CONFIG), \ 732 SR(DOMAIN16_PG_CONFIG), \ 733 SR(DOMAIN17_PG_CONFIG), \ 734 SR(DOMAIN18_PG_CONFIG), \ 735 SR(DOMAIN19_PG_CONFIG), \ 736 SR(DOMAIN0_PG_STATUS), \ 737 SR(DOMAIN1_PG_STATUS), \ 738 SR(DOMAIN2_PG_STATUS), \ 739 SR(DOMAIN3_PG_STATUS), \ 740 SR(DOMAIN16_PG_STATUS), \ 741 SR(DOMAIN17_PG_STATUS), \ 742 SR(DOMAIN18_PG_STATUS), \ 743 SR(DOMAIN19_PG_STATUS), \ 744 SR(D1VGA_CONTROL), \ 745 SR(D2VGA_CONTROL), \ 746 SR(D3VGA_CONTROL), \ 747 SR(D4VGA_CONTROL), \ 748 SR(D5VGA_CONTROL), \ 749 SR(D6VGA_CONTROL), \ 750 SR(DC_IP_REQUEST_CNTL), \ 751 SR(AZALIA_AUDIO_DTO), \ 752 SR(AZALIA_CONTROLLER_CLOCK_GATING), \ 753 SR(HPO_TOP_HW_CONTROL) 754 755 static const struct dce_hwseq_registers hwseq_reg = { 756 HWSEQ_DCN31_REG_LIST() 757 }; 758 759 #define HWSEQ_DCN31_MASK_SH_LIST(mask_sh)\ 760 HWSEQ_DCN_MASK_SH_LIST(mask_sh), \ 761 HWS_SF(, DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_REFDIV, mask_sh), \ 762 HWS_SF(, DCHUBBUB_ARB_HOSTVM_CNTL, DISABLE_HOSTVM_FORCE_ALLOW_PSTATE, mask_sh), \ 763 HWS_SF(, DOMAIN0_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ 764 HWS_SF(, DOMAIN0_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ 765 HWS_SF(, DOMAIN1_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ 766 HWS_SF(, DOMAIN1_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ 767 HWS_SF(, DOMAIN2_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ 768 HWS_SF(, DOMAIN2_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ 769 HWS_SF(, DOMAIN3_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ 770 HWS_SF(, DOMAIN3_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ 771 HWS_SF(, DOMAIN16_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ 772 HWS_SF(, DOMAIN16_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ 773 HWS_SF(, DOMAIN17_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ 774 HWS_SF(, DOMAIN17_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ 775 HWS_SF(, DOMAIN18_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ 776 HWS_SF(, DOMAIN18_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ 777 HWS_SF(, DOMAIN19_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ 778 HWS_SF(, DOMAIN19_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ 779 HWS_SF(, DOMAIN0_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ 780 HWS_SF(, DOMAIN1_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ 781 HWS_SF(, DOMAIN2_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ 782 HWS_SF(, DOMAIN3_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ 783 HWS_SF(, DOMAIN16_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ 784 HWS_SF(, DOMAIN17_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ 785 HWS_SF(, DOMAIN18_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ 786 HWS_SF(, DOMAIN19_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ 787 HWS_SF(, DC_IP_REQUEST_CNTL, IP_REQUEST_EN, mask_sh), \ 788 HWS_SF(, AZALIA_AUDIO_DTO, AZALIA_AUDIO_DTO_MODULE, mask_sh), \ 789 HWS_SF(, HPO_TOP_CLOCK_CONTROL, HPO_HDMISTREAMCLK_G_GATE_DIS, mask_sh), \ 790 HWS_SF(, DMU_MEM_PWR_CNTL, DMCU_ERAM_MEM_PWR_FORCE, mask_sh), \ 791 HWS_SF(, ODM_MEM_PWR_CTRL3, ODM_MEM_UNASSIGNED_PWR_MODE, mask_sh), \ 792 HWS_SF(, ODM_MEM_PWR_CTRL3, ODM_MEM_VBLANK_PWR_MODE, mask_sh), \ 793 HWS_SF(, MMHUBBUB_MEM_PWR_CNTL, VGA_MEM_PWR_FORCE, mask_sh), \ 794 HWS_SF(, DIO_MEM_PWR_CTRL, I2C_LIGHT_SLEEP_FORCE, mask_sh), \ 795 HWS_SF(, HPO_TOP_HW_CONTROL, HPO_IO_EN, mask_sh) 796 797 static const struct dce_hwseq_shift hwseq_shift = { 798 HWSEQ_DCN31_MASK_SH_LIST(__SHIFT) 799 }; 800 801 static const struct dce_hwseq_mask hwseq_mask = { 802 HWSEQ_DCN31_MASK_SH_LIST(_MASK) 803 }; 804 #define vmid_regs(id)\ 805 [id] = {\ 806 DCN20_VMID_REG_LIST(id)\ 807 } 808 809 static const struct dcn_vmid_registers vmid_regs[] = { 810 vmid_regs(0), 811 vmid_regs(1), 812 vmid_regs(2), 813 vmid_regs(3), 814 vmid_regs(4), 815 vmid_regs(5), 816 vmid_regs(6), 817 vmid_regs(7), 818 vmid_regs(8), 819 vmid_regs(9), 820 vmid_regs(10), 821 vmid_regs(11), 822 vmid_regs(12), 823 vmid_regs(13), 824 vmid_regs(14), 825 vmid_regs(15) 826 }; 827 828 static const struct dcn20_vmid_shift vmid_shifts = { 829 DCN20_VMID_MASK_SH_LIST(__SHIFT) 830 }; 831 832 static const struct dcn20_vmid_mask vmid_masks = { 833 DCN20_VMID_MASK_SH_LIST(_MASK) 834 }; 835 836 static const struct resource_caps res_cap_dcn314 = { 837 .num_timing_generator = 4, 838 .num_opp = 4, 839 .num_video_plane = 4, 840 .num_audio = 5, 841 .num_stream_encoder = 5, 842 .num_dig_link_enc = 5, 843 .num_hpo_dp_stream_encoder = 4, 844 .num_hpo_dp_link_encoder = 2, 845 .num_pll = 5, 846 .num_dwb = 1, 847 .num_ddc = 5, 848 .num_vmid = 16, 849 .num_mpc_3dlut = 2, 850 .num_dsc = 4, 851 }; 852 853 static const struct dc_plane_cap plane_cap = { 854 .type = DC_PLANE_TYPE_DCN_UNIVERSAL, 855 .blends_with_above = true, 856 .blends_with_below = true, 857 .per_pixel_alpha = true, 858 859 .pixel_format_support = { 860 .argb8888 = true, 861 .nv12 = true, 862 .fp16 = true, 863 .p010 = true, 864 .ayuv = false, 865 }, 866 867 .max_upscale_factor = { 868 .argb8888 = 16000, 869 .nv12 = 16000, 870 .fp16 = 16000 871 }, 872 873 // 6:1 downscaling ratio: 1000/6 = 166.666 874 .max_downscale_factor = { 875 .argb8888 = 167, 876 .nv12 = 167, 877 .fp16 = 167 878 }, 879 64, 880 64 881 }; 882 883 static const struct dc_debug_options debug_defaults_drv = { 884 .disable_z10 = false, 885 .enable_z9_disable_interface = true, 886 .disable_dmcu = true, 887 .force_abm_enable = false, 888 .timing_trace = false, 889 .clock_trace = true, 890 .disable_pplib_clock_request = false, 891 .pipe_split_policy = MPC_SPLIT_DYNAMIC, 892 .force_single_disp_pipe_split = false, 893 .disable_dcc = DCC_ENABLE, 894 .vsr_support = true, 895 .performance_trace = false, 896 .max_downscale_src_width = 4096,/*upto true 4k*/ 897 .disable_pplib_wm_range = false, 898 .scl_reset_length10 = true, 899 .sanity_checks = false, 900 .underflow_assert_delay_us = 0xFFFFFFFF, 901 .dwb_fi_phase = -1, // -1 = disable, 902 .dmub_command_table = true, 903 .pstate_enabled = true, 904 .use_max_lb = true, 905 .enable_mem_low_power = { 906 .bits = { 907 .vga = true, 908 .i2c = true, 909 .dmcu = false, // This is previously known to cause hang on S3 cycles if enabled 910 .dscl = true, 911 .cm = true, 912 .mpc = true, 913 .optc = true, 914 .vpg = true, 915 .afmt = true, 916 } 917 }, 918 .seamless_boot_odm_combine = true 919 }; 920 921 static const struct dc_debug_options debug_defaults_diags = { 922 .disable_dmcu = true, 923 .force_abm_enable = false, 924 .timing_trace = true, 925 .clock_trace = true, 926 .disable_dpp_power_gate = true, 927 .disable_hubp_power_gate = true, 928 .disable_clock_gate = true, 929 .disable_pplib_clock_request = true, 930 .disable_pplib_wm_range = true, 931 .disable_stutter = false, 932 .scl_reset_length10 = true, 933 .dwb_fi_phase = -1, // -1 = disable 934 .dmub_command_table = true, 935 .enable_tri_buf = true, 936 .use_max_lb = true 937 }; 938 939 static const struct dc_panel_config panel_config_defaults = { 940 .ilr = { 941 .optimize_edp_link_rate = true, 942 }, 943 }; 944 945 static void dcn31_dpp_destroy(struct dpp **dpp) 946 { 947 kfree(TO_DCN20_DPP(*dpp)); 948 *dpp = NULL; 949 } 950 951 static struct dpp *dcn31_dpp_create( 952 struct dc_context *ctx, 953 uint32_t inst) 954 { 955 struct dcn3_dpp *dpp = 956 kzalloc(sizeof(struct dcn3_dpp), GFP_KERNEL); 957 958 if (!dpp) 959 return NULL; 960 961 if (dpp3_construct(dpp, ctx, inst, 962 &dpp_regs[inst], &tf_shift, &tf_mask)) 963 return &dpp->base; 964 965 BREAK_TO_DEBUGGER(); 966 kfree(dpp); 967 return NULL; 968 } 969 970 static struct output_pixel_processor *dcn31_opp_create( 971 struct dc_context *ctx, uint32_t inst) 972 { 973 struct dcn20_opp *opp = 974 kzalloc(sizeof(struct dcn20_opp), GFP_KERNEL); 975 976 if (!opp) { 977 BREAK_TO_DEBUGGER(); 978 return NULL; 979 } 980 981 dcn20_opp_construct(opp, ctx, inst, 982 &opp_regs[inst], &opp_shift, &opp_mask); 983 return &opp->base; 984 } 985 986 static struct dce_aux *dcn31_aux_engine_create( 987 struct dc_context *ctx, 988 uint32_t inst) 989 { 990 struct aux_engine_dce110 *aux_engine = 991 kzalloc(sizeof(struct aux_engine_dce110), GFP_KERNEL); 992 993 if (!aux_engine) 994 return NULL; 995 996 dce110_aux_engine_construct(aux_engine, ctx, inst, 997 SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD, 998 &aux_engine_regs[inst], 999 &aux_mask, 1000 &aux_shift, 1001 ctx->dc->caps.extended_aux_timeout_support); 1002 1003 return &aux_engine->base; 1004 } 1005 #define i2c_inst_regs(id) { I2C_HW_ENGINE_COMMON_REG_LIST_DCN30(id) } 1006 1007 static const struct dce_i2c_registers i2c_hw_regs[] = { 1008 i2c_inst_regs(1), 1009 i2c_inst_regs(2), 1010 i2c_inst_regs(3), 1011 i2c_inst_regs(4), 1012 i2c_inst_regs(5), 1013 }; 1014 1015 static const struct dce_i2c_shift i2c_shifts = { 1016 I2C_COMMON_MASK_SH_LIST_DCN30(__SHIFT) 1017 }; 1018 1019 static const struct dce_i2c_mask i2c_masks = { 1020 I2C_COMMON_MASK_SH_LIST_DCN30(_MASK) 1021 }; 1022 1023 static struct dce_i2c_hw *dcn31_i2c_hw_create( 1024 struct dc_context *ctx, 1025 uint32_t inst) 1026 { 1027 struct dce_i2c_hw *dce_i2c_hw = 1028 kzalloc(sizeof(struct dce_i2c_hw), GFP_KERNEL); 1029 1030 if (!dce_i2c_hw) 1031 return NULL; 1032 1033 dcn2_i2c_hw_construct(dce_i2c_hw, ctx, inst, 1034 &i2c_hw_regs[inst], &i2c_shifts, &i2c_masks); 1035 1036 return dce_i2c_hw; 1037 } 1038 static struct mpc *dcn31_mpc_create( 1039 struct dc_context *ctx, 1040 int num_mpcc, 1041 int num_rmu) 1042 { 1043 struct dcn30_mpc *mpc30 = kzalloc(sizeof(struct dcn30_mpc), 1044 GFP_KERNEL); 1045 1046 if (!mpc30) 1047 return NULL; 1048 1049 dcn30_mpc_construct(mpc30, ctx, 1050 &mpc_regs, 1051 &mpc_shift, 1052 &mpc_mask, 1053 num_mpcc, 1054 num_rmu); 1055 1056 return &mpc30->base; 1057 } 1058 1059 static struct hubbub *dcn31_hubbub_create(struct dc_context *ctx) 1060 { 1061 int i; 1062 1063 struct dcn20_hubbub *hubbub3 = kzalloc(sizeof(struct dcn20_hubbub), 1064 GFP_KERNEL); 1065 1066 if (!hubbub3) 1067 return NULL; 1068 1069 hubbub31_construct(hubbub3, ctx, 1070 &hubbub_reg, 1071 &hubbub_shift, 1072 &hubbub_mask, 1073 dcn3_14_ip.det_buffer_size_kbytes, 1074 dcn3_14_ip.pixel_chunk_size_kbytes, 1075 dcn3_14_ip.config_return_buffer_size_in_kbytes); 1076 1077 1078 for (i = 0; i < res_cap_dcn314.num_vmid; i++) { 1079 struct dcn20_vmid *vmid = &hubbub3->vmid[i]; 1080 1081 vmid->ctx = ctx; 1082 1083 vmid->regs = &vmid_regs[i]; 1084 vmid->shifts = &vmid_shifts; 1085 vmid->masks = &vmid_masks; 1086 } 1087 1088 return &hubbub3->base; 1089 } 1090 1091 static struct timing_generator *dcn31_timing_generator_create( 1092 struct dc_context *ctx, 1093 uint32_t instance) 1094 { 1095 struct optc *tgn10 = 1096 kzalloc(sizeof(struct optc), GFP_KERNEL); 1097 1098 if (!tgn10) 1099 return NULL; 1100 1101 tgn10->base.inst = instance; 1102 tgn10->base.ctx = ctx; 1103 1104 tgn10->tg_regs = &optc_regs[instance]; 1105 tgn10->tg_shift = &optc_shift; 1106 tgn10->tg_mask = &optc_mask; 1107 1108 dcn314_timing_generator_init(tgn10); 1109 1110 return &tgn10->base; 1111 } 1112 1113 static const struct encoder_feature_support link_enc_feature = { 1114 .max_hdmi_deep_color = COLOR_DEPTH_121212, 1115 .max_hdmi_pixel_clock = 600000, 1116 .hdmi_ycbcr420_supported = true, 1117 .dp_ycbcr420_supported = true, 1118 .fec_supported = true, 1119 .flags.bits.IS_HBR2_CAPABLE = true, 1120 .flags.bits.IS_HBR3_CAPABLE = true, 1121 .flags.bits.IS_TPS3_CAPABLE = true, 1122 .flags.bits.IS_TPS4_CAPABLE = true 1123 }; 1124 1125 static struct link_encoder *dcn31_link_encoder_create( 1126 struct dc_context *ctx, 1127 const struct encoder_init_data *enc_init_data) 1128 { 1129 struct dcn20_link_encoder *enc20 = 1130 kzalloc(sizeof(struct dcn20_link_encoder), GFP_KERNEL); 1131 1132 if (!enc20) 1133 return NULL; 1134 1135 dcn31_link_encoder_construct(enc20, 1136 enc_init_data, 1137 &link_enc_feature, 1138 &link_enc_regs[enc_init_data->transmitter], 1139 &link_enc_aux_regs[enc_init_data->channel - 1], 1140 &link_enc_hpd_regs[enc_init_data->hpd_source], 1141 &le_shift, 1142 &le_mask); 1143 1144 return &enc20->enc10.base; 1145 } 1146 1147 /* Create a minimal link encoder object not associated with a particular 1148 * physical connector. 1149 * resource_funcs.link_enc_create_minimal 1150 */ 1151 static struct link_encoder *dcn31_link_enc_create_minimal( 1152 struct dc_context *ctx, enum engine_id eng_id) 1153 { 1154 struct dcn20_link_encoder *enc20; 1155 1156 if ((eng_id - ENGINE_ID_DIGA) > ctx->dc->res_pool->res_cap->num_dig_link_enc) 1157 return NULL; 1158 1159 enc20 = kzalloc(sizeof(struct dcn20_link_encoder), GFP_KERNEL); 1160 if (!enc20) 1161 return NULL; 1162 1163 dcn31_link_encoder_construct_minimal( 1164 enc20, 1165 ctx, 1166 &link_enc_feature, 1167 &link_enc_regs[eng_id - ENGINE_ID_DIGA], 1168 eng_id); 1169 1170 return &enc20->enc10.base; 1171 } 1172 1173 static struct panel_cntl *dcn31_panel_cntl_create(const struct panel_cntl_init_data *init_data) 1174 { 1175 struct dcn31_panel_cntl *panel_cntl = 1176 kzalloc(sizeof(struct dcn31_panel_cntl), GFP_KERNEL); 1177 1178 if (!panel_cntl) 1179 return NULL; 1180 1181 dcn31_panel_cntl_construct(panel_cntl, init_data); 1182 1183 return &panel_cntl->base; 1184 } 1185 1186 static void read_dce_straps( 1187 struct dc_context *ctx, 1188 struct resource_straps *straps) 1189 { 1190 generic_reg_get(ctx, regDC_PINSTRAPS + BASE(regDC_PINSTRAPS_BASE_IDX), 1191 FN(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO), &straps->dc_pinstraps_audio); 1192 1193 } 1194 1195 static struct audio *dcn31_create_audio( 1196 struct dc_context *ctx, unsigned int inst) 1197 { 1198 return dce_audio_create(ctx, inst, 1199 &audio_regs[inst], &audio_shift, &audio_mask); 1200 } 1201 1202 static struct vpg *dcn31_vpg_create( 1203 struct dc_context *ctx, 1204 uint32_t inst) 1205 { 1206 struct dcn31_vpg *vpg31 = kzalloc(sizeof(struct dcn31_vpg), GFP_KERNEL); 1207 1208 if (!vpg31) 1209 return NULL; 1210 1211 vpg31_construct(vpg31, ctx, inst, 1212 &vpg_regs[inst], 1213 &vpg_shift, 1214 &vpg_mask); 1215 1216 return &vpg31->base; 1217 } 1218 1219 static struct afmt *dcn31_afmt_create( 1220 struct dc_context *ctx, 1221 uint32_t inst) 1222 { 1223 struct dcn31_afmt *afmt31 = kzalloc(sizeof(struct dcn31_afmt), GFP_KERNEL); 1224 1225 if (!afmt31) 1226 return NULL; 1227 1228 afmt31_construct(afmt31, ctx, inst, 1229 &afmt_regs[inst], 1230 &afmt_shift, 1231 &afmt_mask); 1232 1233 // Light sleep by default, no need to power down here 1234 1235 return &afmt31->base; 1236 } 1237 1238 static struct apg *dcn31_apg_create( 1239 struct dc_context *ctx, 1240 uint32_t inst) 1241 { 1242 struct dcn31_apg *apg31 = kzalloc(sizeof(struct dcn31_apg), GFP_KERNEL); 1243 1244 if (!apg31) 1245 return NULL; 1246 1247 apg31_construct(apg31, ctx, inst, 1248 &apg_regs[inst], 1249 &apg_shift, 1250 &apg_mask); 1251 1252 return &apg31->base; 1253 } 1254 1255 static struct stream_encoder *dcn314_stream_encoder_create( 1256 enum engine_id eng_id, 1257 struct dc_context *ctx) 1258 { 1259 struct dcn10_stream_encoder *enc1; 1260 struct vpg *vpg; 1261 struct afmt *afmt; 1262 int vpg_inst; 1263 int afmt_inst; 1264 1265 /* Mapping of VPG, AFMT, DME register blocks to DIO block instance */ 1266 if (eng_id < ENGINE_ID_DIGF) { 1267 vpg_inst = eng_id; 1268 afmt_inst = eng_id; 1269 } else 1270 return NULL; 1271 1272 enc1 = kzalloc(sizeof(struct dcn10_stream_encoder), GFP_KERNEL); 1273 vpg = dcn31_vpg_create(ctx, vpg_inst); 1274 afmt = dcn31_afmt_create(ctx, afmt_inst); 1275 1276 if (!enc1 || !vpg || !afmt) { 1277 kfree(enc1); 1278 kfree(vpg); 1279 kfree(afmt); 1280 return NULL; 1281 } 1282 1283 dcn314_dio_stream_encoder_construct(enc1, ctx, ctx->dc_bios, 1284 eng_id, vpg, afmt, 1285 &stream_enc_regs[eng_id], 1286 &se_shift, &se_mask); 1287 1288 return &enc1->base; 1289 } 1290 1291 static struct hpo_dp_stream_encoder *dcn31_hpo_dp_stream_encoder_create( 1292 enum engine_id eng_id, 1293 struct dc_context *ctx) 1294 { 1295 struct dcn31_hpo_dp_stream_encoder *hpo_dp_enc31; 1296 struct vpg *vpg; 1297 struct apg *apg; 1298 uint32_t hpo_dp_inst; 1299 uint32_t vpg_inst; 1300 uint32_t apg_inst; 1301 1302 ASSERT((eng_id >= ENGINE_ID_HPO_DP_0) && (eng_id <= ENGINE_ID_HPO_DP_3)); 1303 hpo_dp_inst = eng_id - ENGINE_ID_HPO_DP_0; 1304 1305 /* Mapping of VPG register blocks to HPO DP block instance: 1306 * VPG[6] -> HPO_DP[0] 1307 * VPG[7] -> HPO_DP[1] 1308 * VPG[8] -> HPO_DP[2] 1309 * VPG[9] -> HPO_DP[3] 1310 */ 1311 //Uses offset index 5-8, but actually maps to vpg_inst 6-9 1312 vpg_inst = hpo_dp_inst + 5; 1313 1314 /* Mapping of APG register blocks to HPO DP block instance: 1315 * APG[0] -> HPO_DP[0] 1316 * APG[1] -> HPO_DP[1] 1317 * APG[2] -> HPO_DP[2] 1318 * APG[3] -> HPO_DP[3] 1319 */ 1320 apg_inst = hpo_dp_inst; 1321 1322 /* allocate HPO stream encoder and create VPG sub-block */ 1323 hpo_dp_enc31 = kzalloc(sizeof(struct dcn31_hpo_dp_stream_encoder), GFP_KERNEL); 1324 vpg = dcn31_vpg_create(ctx, vpg_inst); 1325 apg = dcn31_apg_create(ctx, apg_inst); 1326 1327 if (!hpo_dp_enc31 || !vpg || !apg) { 1328 kfree(hpo_dp_enc31); 1329 kfree(vpg); 1330 kfree(apg); 1331 return NULL; 1332 } 1333 1334 dcn31_hpo_dp_stream_encoder_construct(hpo_dp_enc31, ctx, ctx->dc_bios, 1335 hpo_dp_inst, eng_id, vpg, apg, 1336 &hpo_dp_stream_enc_regs[hpo_dp_inst], 1337 &hpo_dp_se_shift, &hpo_dp_se_mask); 1338 1339 return &hpo_dp_enc31->base; 1340 } 1341 1342 static struct hpo_dp_link_encoder *dcn31_hpo_dp_link_encoder_create( 1343 uint8_t inst, 1344 struct dc_context *ctx) 1345 { 1346 struct dcn31_hpo_dp_link_encoder *hpo_dp_enc31; 1347 1348 /* allocate HPO link encoder */ 1349 hpo_dp_enc31 = kzalloc(sizeof(struct dcn31_hpo_dp_link_encoder), GFP_KERNEL); 1350 1351 hpo_dp_link_encoder31_construct(hpo_dp_enc31, ctx, inst, 1352 &hpo_dp_link_enc_regs[inst], 1353 &hpo_dp_le_shift, &hpo_dp_le_mask); 1354 1355 return &hpo_dp_enc31->base; 1356 } 1357 1358 static struct dce_hwseq *dcn314_hwseq_create( 1359 struct dc_context *ctx) 1360 { 1361 struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_KERNEL); 1362 1363 if (hws) { 1364 hws->ctx = ctx; 1365 hws->regs = &hwseq_reg; 1366 hws->shifts = &hwseq_shift; 1367 hws->masks = &hwseq_mask; 1368 /* DCN3.1 FPGA Workaround 1369 * Need to enable HPO DP Stream Encoder before setting OTG master enable. 1370 * To do so, move calling function enable_stream_timing to only be done AFTER calling 1371 * function core_link_enable_stream 1372 */ 1373 if (IS_FPGA_MAXIMUS_DC(ctx->dce_environment)) 1374 hws->wa.dp_hpo_and_otg_sequence = true; 1375 } 1376 return hws; 1377 } 1378 static const struct resource_create_funcs res_create_funcs = { 1379 .read_dce_straps = read_dce_straps, 1380 .create_audio = dcn31_create_audio, 1381 .create_stream_encoder = dcn314_stream_encoder_create, 1382 .create_hpo_dp_stream_encoder = dcn31_hpo_dp_stream_encoder_create, 1383 .create_hpo_dp_link_encoder = dcn31_hpo_dp_link_encoder_create, 1384 .create_hwseq = dcn314_hwseq_create, 1385 }; 1386 1387 static const struct resource_create_funcs res_create_maximus_funcs = { 1388 .read_dce_straps = NULL, 1389 .create_audio = NULL, 1390 .create_stream_encoder = NULL, 1391 .create_hpo_dp_stream_encoder = dcn31_hpo_dp_stream_encoder_create, 1392 .create_hpo_dp_link_encoder = dcn31_hpo_dp_link_encoder_create, 1393 .create_hwseq = dcn314_hwseq_create, 1394 }; 1395 1396 static void dcn314_resource_destruct(struct dcn314_resource_pool *pool) 1397 { 1398 unsigned int i; 1399 1400 for (i = 0; i < pool->base.stream_enc_count; i++) { 1401 if (pool->base.stream_enc[i] != NULL) { 1402 if (pool->base.stream_enc[i]->vpg != NULL) { 1403 kfree(DCN30_VPG_FROM_VPG(pool->base.stream_enc[i]->vpg)); 1404 pool->base.stream_enc[i]->vpg = NULL; 1405 } 1406 if (pool->base.stream_enc[i]->afmt != NULL) { 1407 kfree(DCN30_AFMT_FROM_AFMT(pool->base.stream_enc[i]->afmt)); 1408 pool->base.stream_enc[i]->afmt = NULL; 1409 } 1410 kfree(DCN10STRENC_FROM_STRENC(pool->base.stream_enc[i])); 1411 pool->base.stream_enc[i] = NULL; 1412 } 1413 } 1414 1415 for (i = 0; i < pool->base.hpo_dp_stream_enc_count; i++) { 1416 if (pool->base.hpo_dp_stream_enc[i] != NULL) { 1417 if (pool->base.hpo_dp_stream_enc[i]->vpg != NULL) { 1418 kfree(DCN30_VPG_FROM_VPG(pool->base.hpo_dp_stream_enc[i]->vpg)); 1419 pool->base.hpo_dp_stream_enc[i]->vpg = NULL; 1420 } 1421 if (pool->base.hpo_dp_stream_enc[i]->apg != NULL) { 1422 kfree(DCN31_APG_FROM_APG(pool->base.hpo_dp_stream_enc[i]->apg)); 1423 pool->base.hpo_dp_stream_enc[i]->apg = NULL; 1424 } 1425 kfree(DCN3_1_HPO_DP_STREAM_ENC_FROM_HPO_STREAM_ENC(pool->base.hpo_dp_stream_enc[i])); 1426 pool->base.hpo_dp_stream_enc[i] = NULL; 1427 } 1428 } 1429 1430 for (i = 0; i < pool->base.hpo_dp_link_enc_count; i++) { 1431 if (pool->base.hpo_dp_link_enc[i] != NULL) { 1432 kfree(DCN3_1_HPO_DP_LINK_ENC_FROM_HPO_LINK_ENC(pool->base.hpo_dp_link_enc[i])); 1433 pool->base.hpo_dp_link_enc[i] = NULL; 1434 } 1435 } 1436 1437 for (i = 0; i < pool->base.res_cap->num_dsc; i++) { 1438 if (pool->base.dscs[i] != NULL) 1439 dcn20_dsc_destroy(&pool->base.dscs[i]); 1440 } 1441 1442 if (pool->base.mpc != NULL) { 1443 kfree(TO_DCN20_MPC(pool->base.mpc)); 1444 pool->base.mpc = NULL; 1445 } 1446 if (pool->base.hubbub != NULL) { 1447 kfree(pool->base.hubbub); 1448 pool->base.hubbub = NULL; 1449 } 1450 for (i = 0; i < pool->base.pipe_count; i++) { 1451 if (pool->base.dpps[i] != NULL) 1452 dcn31_dpp_destroy(&pool->base.dpps[i]); 1453 1454 if (pool->base.ipps[i] != NULL) 1455 pool->base.ipps[i]->funcs->ipp_destroy(&pool->base.ipps[i]); 1456 1457 if (pool->base.hubps[i] != NULL) { 1458 kfree(TO_DCN20_HUBP(pool->base.hubps[i])); 1459 pool->base.hubps[i] = NULL; 1460 } 1461 1462 if (pool->base.irqs != NULL) 1463 dal_irq_service_destroy(&pool->base.irqs); 1464 } 1465 1466 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { 1467 if (pool->base.engines[i] != NULL) 1468 dce110_engine_destroy(&pool->base.engines[i]); 1469 if (pool->base.hw_i2cs[i] != NULL) { 1470 kfree(pool->base.hw_i2cs[i]); 1471 pool->base.hw_i2cs[i] = NULL; 1472 } 1473 if (pool->base.sw_i2cs[i] != NULL) { 1474 kfree(pool->base.sw_i2cs[i]); 1475 pool->base.sw_i2cs[i] = NULL; 1476 } 1477 } 1478 1479 for (i = 0; i < pool->base.res_cap->num_opp; i++) { 1480 if (pool->base.opps[i] != NULL) 1481 pool->base.opps[i]->funcs->opp_destroy(&pool->base.opps[i]); 1482 } 1483 1484 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { 1485 if (pool->base.timing_generators[i] != NULL) { 1486 kfree(DCN10TG_FROM_TG(pool->base.timing_generators[i])); 1487 pool->base.timing_generators[i] = NULL; 1488 } 1489 } 1490 1491 for (i = 0; i < pool->base.res_cap->num_dwb; i++) { 1492 if (pool->base.dwbc[i] != NULL) { 1493 kfree(TO_DCN30_DWBC(pool->base.dwbc[i])); 1494 pool->base.dwbc[i] = NULL; 1495 } 1496 if (pool->base.mcif_wb[i] != NULL) { 1497 kfree(TO_DCN30_MMHUBBUB(pool->base.mcif_wb[i])); 1498 pool->base.mcif_wb[i] = NULL; 1499 } 1500 } 1501 1502 for (i = 0; i < pool->base.audio_count; i++) { 1503 if (pool->base.audios[i]) 1504 dce_aud_destroy(&pool->base.audios[i]); 1505 } 1506 1507 for (i = 0; i < pool->base.clk_src_count; i++) { 1508 if (pool->base.clock_sources[i] != NULL) { 1509 dcn20_clock_source_destroy(&pool->base.clock_sources[i]); 1510 pool->base.clock_sources[i] = NULL; 1511 } 1512 } 1513 1514 for (i = 0; i < pool->base.res_cap->num_mpc_3dlut; i++) { 1515 if (pool->base.mpc_lut[i] != NULL) { 1516 dc_3dlut_func_release(pool->base.mpc_lut[i]); 1517 pool->base.mpc_lut[i] = NULL; 1518 } 1519 if (pool->base.mpc_shaper[i] != NULL) { 1520 dc_transfer_func_release(pool->base.mpc_shaper[i]); 1521 pool->base.mpc_shaper[i] = NULL; 1522 } 1523 } 1524 1525 if (pool->base.dp_clock_source != NULL) { 1526 dcn20_clock_source_destroy(&pool->base.dp_clock_source); 1527 pool->base.dp_clock_source = NULL; 1528 } 1529 1530 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { 1531 if (pool->base.multiple_abms[i] != NULL) 1532 dce_abm_destroy(&pool->base.multiple_abms[i]); 1533 } 1534 1535 if (pool->base.psr != NULL) 1536 dmub_psr_destroy(&pool->base.psr); 1537 1538 if (pool->base.dccg != NULL) 1539 dcn_dccg_destroy(&pool->base.dccg); 1540 } 1541 1542 static struct hubp *dcn31_hubp_create( 1543 struct dc_context *ctx, 1544 uint32_t inst) 1545 { 1546 struct dcn20_hubp *hubp2 = 1547 kzalloc(sizeof(struct dcn20_hubp), GFP_KERNEL); 1548 1549 if (!hubp2) 1550 return NULL; 1551 1552 if (hubp31_construct(hubp2, ctx, inst, 1553 &hubp_regs[inst], &hubp_shift, &hubp_mask)) 1554 return &hubp2->base; 1555 1556 BREAK_TO_DEBUGGER(); 1557 kfree(hubp2); 1558 return NULL; 1559 } 1560 1561 static bool dcn31_dwbc_create(struct dc_context *ctx, struct resource_pool *pool) 1562 { 1563 int i; 1564 uint32_t pipe_count = pool->res_cap->num_dwb; 1565 1566 for (i = 0; i < pipe_count; i++) { 1567 struct dcn30_dwbc *dwbc30 = kzalloc(sizeof(struct dcn30_dwbc), 1568 GFP_KERNEL); 1569 1570 if (!dwbc30) { 1571 dm_error("DC: failed to create dwbc30!\n"); 1572 return false; 1573 } 1574 1575 dcn30_dwbc_construct(dwbc30, ctx, 1576 &dwbc30_regs[i], 1577 &dwbc30_shift, 1578 &dwbc30_mask, 1579 i); 1580 1581 pool->dwbc[i] = &dwbc30->base; 1582 } 1583 return true; 1584 } 1585 1586 static bool dcn31_mmhubbub_create(struct dc_context *ctx, struct resource_pool *pool) 1587 { 1588 int i; 1589 uint32_t pipe_count = pool->res_cap->num_dwb; 1590 1591 for (i = 0; i < pipe_count; i++) { 1592 struct dcn30_mmhubbub *mcif_wb30 = kzalloc(sizeof(struct dcn30_mmhubbub), 1593 GFP_KERNEL); 1594 1595 if (!mcif_wb30) { 1596 dm_error("DC: failed to create mcif_wb30!\n"); 1597 return false; 1598 } 1599 1600 dcn30_mmhubbub_construct(mcif_wb30, ctx, 1601 &mcif_wb30_regs[i], 1602 &mcif_wb30_shift, 1603 &mcif_wb30_mask, 1604 i); 1605 1606 pool->mcif_wb[i] = &mcif_wb30->base; 1607 } 1608 return true; 1609 } 1610 1611 static struct display_stream_compressor *dcn314_dsc_create( 1612 struct dc_context *ctx, uint32_t inst) 1613 { 1614 struct dcn20_dsc *dsc = 1615 kzalloc(sizeof(struct dcn20_dsc), GFP_KERNEL); 1616 1617 if (!dsc) { 1618 BREAK_TO_DEBUGGER(); 1619 return NULL; 1620 } 1621 1622 dsc2_construct(dsc, ctx, inst, &dsc_regs[inst], &dsc_shift, &dsc_mask); 1623 return &dsc->base; 1624 } 1625 1626 static void dcn314_destroy_resource_pool(struct resource_pool **pool) 1627 { 1628 struct dcn314_resource_pool *dcn314_pool = TO_DCN314_RES_POOL(*pool); 1629 1630 dcn314_resource_destruct(dcn314_pool); 1631 kfree(dcn314_pool); 1632 *pool = NULL; 1633 } 1634 1635 static struct clock_source *dcn31_clock_source_create( 1636 struct dc_context *ctx, 1637 struct dc_bios *bios, 1638 enum clock_source_id id, 1639 const struct dce110_clk_src_regs *regs, 1640 bool dp_clk_src) 1641 { 1642 struct dce110_clk_src *clk_src = 1643 kzalloc(sizeof(struct dce110_clk_src), GFP_KERNEL); 1644 1645 if (!clk_src) 1646 return NULL; 1647 1648 if (dcn31_clk_src_construct(clk_src, ctx, bios, id, 1649 regs, &cs_shift, &cs_mask)) { 1650 clk_src->base.dp_clk_src = dp_clk_src; 1651 return &clk_src->base; 1652 } 1653 1654 BREAK_TO_DEBUGGER(); 1655 kfree(clk_src); 1656 return NULL; 1657 } 1658 1659 static int dcn314_populate_dml_pipes_from_context( 1660 struct dc *dc, struct dc_state *context, 1661 display_e2e_pipe_params_st *pipes, 1662 bool fast_validate) 1663 { 1664 int pipe_cnt; 1665 1666 DC_FP_START(); 1667 pipe_cnt = dcn314_populate_dml_pipes_from_context_fpu(dc, context, pipes, fast_validate); 1668 DC_FP_END(); 1669 1670 return pipe_cnt; 1671 } 1672 1673 static struct dc_cap_funcs cap_funcs = { 1674 .get_dcc_compression_cap = dcn20_get_dcc_compression_cap 1675 }; 1676 1677 static void dcn314_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params) 1678 { 1679 DC_FP_START(); 1680 dcn314_update_bw_bounding_box_fpu(dc, bw_params); 1681 DC_FP_END(); 1682 } 1683 1684 static void dcn314_get_panel_config_defaults(struct dc_panel_config *panel_config) 1685 { 1686 *panel_config = panel_config_defaults; 1687 } 1688 1689 static struct resource_funcs dcn314_res_pool_funcs = { 1690 .destroy = dcn314_destroy_resource_pool, 1691 .link_enc_create = dcn31_link_encoder_create, 1692 .link_enc_create_minimal = dcn31_link_enc_create_minimal, 1693 .link_encs_assign = link_enc_cfg_link_encs_assign, 1694 .link_enc_unassign = link_enc_cfg_link_enc_unassign, 1695 .panel_cntl_create = dcn31_panel_cntl_create, 1696 .validate_bandwidth = dcn31_validate_bandwidth, 1697 .calculate_wm_and_dlg = dcn31_calculate_wm_and_dlg, 1698 .update_soc_for_wm_a = dcn31_update_soc_for_wm_a, 1699 .populate_dml_pipes = dcn314_populate_dml_pipes_from_context, 1700 .acquire_idle_pipe_for_layer = dcn20_acquire_idle_pipe_for_layer, 1701 .add_stream_to_ctx = dcn30_add_stream_to_ctx, 1702 .add_dsc_to_stream_resource = dcn20_add_dsc_to_stream_resource, 1703 .remove_stream_from_ctx = dcn20_remove_stream_from_ctx, 1704 .populate_dml_writeback_from_context = dcn30_populate_dml_writeback_from_context, 1705 .set_mcif_arb_params = dcn30_set_mcif_arb_params, 1706 .find_first_free_match_stream_enc_for_link = dcn10_find_first_free_match_stream_enc_for_link, 1707 .acquire_post_bldn_3dlut = dcn30_acquire_post_bldn_3dlut, 1708 .release_post_bldn_3dlut = dcn30_release_post_bldn_3dlut, 1709 .update_bw_bounding_box = dcn314_update_bw_bounding_box, 1710 .patch_unknown_plane_state = dcn20_patch_unknown_plane_state, 1711 .get_panel_config_defaults = dcn314_get_panel_config_defaults, 1712 }; 1713 1714 static struct clock_source *dcn30_clock_source_create( 1715 struct dc_context *ctx, 1716 struct dc_bios *bios, 1717 enum clock_source_id id, 1718 const struct dce110_clk_src_regs *regs, 1719 bool dp_clk_src) 1720 { 1721 struct dce110_clk_src *clk_src = 1722 kzalloc(sizeof(struct dce110_clk_src), GFP_KERNEL); 1723 1724 if (!clk_src) 1725 return NULL; 1726 1727 if (dcn31_clk_src_construct(clk_src, ctx, bios, id, 1728 regs, &cs_shift, &cs_mask)) { 1729 clk_src->base.dp_clk_src = dp_clk_src; 1730 return &clk_src->base; 1731 } 1732 1733 BREAK_TO_DEBUGGER(); 1734 kfree(clk_src); 1735 return NULL; 1736 } 1737 1738 static bool dcn314_resource_construct( 1739 uint8_t num_virtual_links, 1740 struct dc *dc, 1741 struct dcn314_resource_pool *pool) 1742 { 1743 int i; 1744 struct dc_context *ctx = dc->ctx; 1745 struct irq_service_init_data init_data; 1746 1747 ctx->dc_bios->regs = &bios_regs; 1748 1749 pool->base.res_cap = &res_cap_dcn314; 1750 pool->base.funcs = &dcn314_res_pool_funcs; 1751 1752 /************************************************* 1753 * Resource + asic cap harcoding * 1754 *************************************************/ 1755 pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE; 1756 pool->base.pipe_count = pool->base.res_cap->num_timing_generator; 1757 pool->base.mpcc_count = pool->base.res_cap->num_timing_generator; 1758 dc->caps.max_downscale_ratio = 600; 1759 dc->caps.i2c_speed_in_khz = 100; 1760 dc->caps.i2c_speed_in_khz_hdcp = 100; 1761 dc->caps.max_cursor_size = 256; 1762 dc->caps.min_horizontal_blanking_period = 80; 1763 dc->caps.dmdata_alloc_size = 2048; 1764 dc->caps.max_slave_planes = 2; 1765 dc->caps.max_slave_yuv_planes = 2; 1766 dc->caps.max_slave_rgb_planes = 2; 1767 dc->caps.post_blend_color_processing = true; 1768 dc->caps.force_dp_tps4_for_cp2520 = true; 1769 dc->caps.dp_hpo = true; 1770 dc->caps.dp_hdmi21_pcon_support = true; 1771 dc->caps.edp_dsc_support = true; 1772 dc->caps.extended_aux_timeout_support = true; 1773 dc->caps.dmcub_support = true; 1774 dc->caps.is_apu = true; 1775 dc->caps.seamless_odm = true; 1776 1777 dc->caps.zstate_support = true; 1778 1779 /* Color pipeline capabilities */ 1780 dc->caps.color.dpp.dcn_arch = 1; 1781 dc->caps.color.dpp.input_lut_shared = 0; 1782 dc->caps.color.dpp.icsc = 1; 1783 dc->caps.color.dpp.dgam_ram = 0; // must use gamma_corr 1784 dc->caps.color.dpp.dgam_rom_caps.srgb = 1; 1785 dc->caps.color.dpp.dgam_rom_caps.bt2020 = 1; 1786 dc->caps.color.dpp.dgam_rom_caps.gamma2_2 = 1; 1787 dc->caps.color.dpp.dgam_rom_caps.pq = 1; 1788 dc->caps.color.dpp.dgam_rom_caps.hlg = 1; 1789 dc->caps.color.dpp.post_csc = 1; 1790 dc->caps.color.dpp.gamma_corr = 1; 1791 dc->caps.color.dpp.dgam_rom_for_yuv = 0; 1792 1793 dc->caps.color.dpp.hw_3d_lut = 1; 1794 dc->caps.color.dpp.ogam_ram = 1; 1795 // no OGAM ROM on DCN301 1796 dc->caps.color.dpp.ogam_rom_caps.srgb = 0; 1797 dc->caps.color.dpp.ogam_rom_caps.bt2020 = 0; 1798 dc->caps.color.dpp.ogam_rom_caps.gamma2_2 = 0; 1799 dc->caps.color.dpp.ogam_rom_caps.pq = 0; 1800 dc->caps.color.dpp.ogam_rom_caps.hlg = 0; 1801 dc->caps.color.dpp.ocsc = 0; 1802 1803 dc->caps.color.mpc.gamut_remap = 1; 1804 dc->caps.color.mpc.num_3dluts = pool->base.res_cap->num_mpc_3dlut; //2 1805 dc->caps.color.mpc.ogam_ram = 1; 1806 dc->caps.color.mpc.ogam_rom_caps.srgb = 0; 1807 dc->caps.color.mpc.ogam_rom_caps.bt2020 = 0; 1808 dc->caps.color.mpc.ogam_rom_caps.gamma2_2 = 0; 1809 dc->caps.color.mpc.ogam_rom_caps.pq = 0; 1810 dc->caps.color.mpc.ogam_rom_caps.hlg = 0; 1811 dc->caps.color.mpc.ocsc = 1; 1812 1813 /* Use pipe context based otg sync logic */ 1814 dc->config.use_pipe_ctx_sync_logic = true; 1815 1816 /* read VBIOS LTTPR caps */ 1817 { 1818 if (ctx->dc_bios->funcs->get_lttpr_caps) { 1819 enum bp_result bp_query_result; 1820 uint8_t is_vbios_lttpr_enable = 0; 1821 1822 bp_query_result = ctx->dc_bios->funcs->get_lttpr_caps(ctx->dc_bios, &is_vbios_lttpr_enable); 1823 dc->caps.vbios_lttpr_enable = (bp_query_result == BP_RESULT_OK) && !!is_vbios_lttpr_enable; 1824 } 1825 1826 /* interop bit is implicit */ 1827 { 1828 dc->caps.vbios_lttpr_aware = true; 1829 } 1830 } 1831 1832 if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV) 1833 dc->debug = debug_defaults_drv; 1834 else 1835 dc->debug = debug_defaults_diags; 1836 // Init the vm_helper 1837 if (dc->vm_helper) 1838 vm_helper_init(dc->vm_helper, 16); 1839 1840 /************************************************* 1841 * Create resources * 1842 *************************************************/ 1843 1844 /* Clock Sources for Pixel Clock*/ 1845 pool->base.clock_sources[DCN31_CLK_SRC_PLL0] = 1846 dcn30_clock_source_create(ctx, ctx->dc_bios, 1847 CLOCK_SOURCE_COMBO_PHY_PLL0, 1848 &clk_src_regs[0], false); 1849 pool->base.clock_sources[DCN31_CLK_SRC_PLL1] = 1850 dcn30_clock_source_create(ctx, ctx->dc_bios, 1851 CLOCK_SOURCE_COMBO_PHY_PLL1, 1852 &clk_src_regs[1], false); 1853 pool->base.clock_sources[DCN31_CLK_SRC_PLL2] = 1854 dcn30_clock_source_create(ctx, ctx->dc_bios, 1855 CLOCK_SOURCE_COMBO_PHY_PLL2, 1856 &clk_src_regs[2], false); 1857 pool->base.clock_sources[DCN31_CLK_SRC_PLL3] = 1858 dcn30_clock_source_create(ctx, ctx->dc_bios, 1859 CLOCK_SOURCE_COMBO_PHY_PLL3, 1860 &clk_src_regs[3], false); 1861 pool->base.clock_sources[DCN31_CLK_SRC_PLL4] = 1862 dcn30_clock_source_create(ctx, ctx->dc_bios, 1863 CLOCK_SOURCE_COMBO_PHY_PLL4, 1864 &clk_src_regs[4], false); 1865 1866 pool->base.clk_src_count = DCN30_CLK_SRC_TOTAL; 1867 1868 /* todo: not reuse phy_pll registers */ 1869 pool->base.dp_clock_source = 1870 dcn31_clock_source_create(ctx, ctx->dc_bios, 1871 CLOCK_SOURCE_ID_DP_DTO, 1872 &clk_src_regs[0], true); 1873 1874 for (i = 0; i < pool->base.clk_src_count; i++) { 1875 if (pool->base.clock_sources[i] == NULL) { 1876 dm_error("DC: failed to create clock sources!\n"); 1877 BREAK_TO_DEBUGGER(); 1878 goto create_fail; 1879 } 1880 } 1881 1882 pool->base.dccg = dccg314_create(ctx, &dccg_regs, &dccg_shift, &dccg_mask); 1883 if (pool->base.dccg == NULL) { 1884 dm_error("DC: failed to create dccg!\n"); 1885 BREAK_TO_DEBUGGER(); 1886 goto create_fail; 1887 } 1888 1889 init_data.ctx = dc->ctx; 1890 pool->base.irqs = dal_irq_service_dcn314_create(&init_data); 1891 if (!pool->base.irqs) 1892 goto create_fail; 1893 1894 /* HUBBUB */ 1895 pool->base.hubbub = dcn31_hubbub_create(ctx); 1896 if (pool->base.hubbub == NULL) { 1897 BREAK_TO_DEBUGGER(); 1898 dm_error("DC: failed to create hubbub!\n"); 1899 goto create_fail; 1900 } 1901 1902 /* HUBPs, DPPs, OPPs and TGs */ 1903 for (i = 0; i < pool->base.pipe_count; i++) { 1904 pool->base.hubps[i] = dcn31_hubp_create(ctx, i); 1905 if (pool->base.hubps[i] == NULL) { 1906 BREAK_TO_DEBUGGER(); 1907 dm_error( 1908 "DC: failed to create hubps!\n"); 1909 goto create_fail; 1910 } 1911 1912 pool->base.dpps[i] = dcn31_dpp_create(ctx, i); 1913 if (pool->base.dpps[i] == NULL) { 1914 BREAK_TO_DEBUGGER(); 1915 dm_error( 1916 "DC: failed to create dpps!\n"); 1917 goto create_fail; 1918 } 1919 } 1920 1921 for (i = 0; i < pool->base.res_cap->num_opp; i++) { 1922 pool->base.opps[i] = dcn31_opp_create(ctx, i); 1923 if (pool->base.opps[i] == NULL) { 1924 BREAK_TO_DEBUGGER(); 1925 dm_error( 1926 "DC: failed to create output pixel processor!\n"); 1927 goto create_fail; 1928 } 1929 } 1930 1931 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { 1932 pool->base.timing_generators[i] = dcn31_timing_generator_create( 1933 ctx, i); 1934 if (pool->base.timing_generators[i] == NULL) { 1935 BREAK_TO_DEBUGGER(); 1936 dm_error("DC: failed to create tg!\n"); 1937 goto create_fail; 1938 } 1939 } 1940 pool->base.timing_generator_count = i; 1941 1942 /* PSR */ 1943 pool->base.psr = dmub_psr_create(ctx); 1944 if (pool->base.psr == NULL) { 1945 dm_error("DC: failed to create psr obj!\n"); 1946 BREAK_TO_DEBUGGER(); 1947 goto create_fail; 1948 } 1949 1950 /* ABM */ 1951 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { 1952 pool->base.multiple_abms[i] = dmub_abm_create(ctx, 1953 &abm_regs[i], 1954 &abm_shift, 1955 &abm_mask); 1956 if (pool->base.multiple_abms[i] == NULL) { 1957 dm_error("DC: failed to create abm for pipe %d!\n", i); 1958 BREAK_TO_DEBUGGER(); 1959 goto create_fail; 1960 } 1961 } 1962 1963 /* MPC and DSC */ 1964 pool->base.mpc = dcn31_mpc_create(ctx, pool->base.mpcc_count, pool->base.res_cap->num_mpc_3dlut); 1965 if (pool->base.mpc == NULL) { 1966 BREAK_TO_DEBUGGER(); 1967 dm_error("DC: failed to create mpc!\n"); 1968 goto create_fail; 1969 } 1970 1971 for (i = 0; i < pool->base.res_cap->num_dsc; i++) { 1972 pool->base.dscs[i] = dcn314_dsc_create(ctx, i); 1973 if (pool->base.dscs[i] == NULL) { 1974 BREAK_TO_DEBUGGER(); 1975 dm_error("DC: failed to create display stream compressor %d!\n", i); 1976 goto create_fail; 1977 } 1978 } 1979 1980 /* DWB and MMHUBBUB */ 1981 if (!dcn31_dwbc_create(ctx, &pool->base)) { 1982 BREAK_TO_DEBUGGER(); 1983 dm_error("DC: failed to create dwbc!\n"); 1984 goto create_fail; 1985 } 1986 1987 if (!dcn31_mmhubbub_create(ctx, &pool->base)) { 1988 BREAK_TO_DEBUGGER(); 1989 dm_error("DC: failed to create mcif_wb!\n"); 1990 goto create_fail; 1991 } 1992 1993 /* AUX and I2C */ 1994 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { 1995 pool->base.engines[i] = dcn31_aux_engine_create(ctx, i); 1996 if (pool->base.engines[i] == NULL) { 1997 BREAK_TO_DEBUGGER(); 1998 dm_error( 1999 "DC:failed to create aux engine!!\n"); 2000 goto create_fail; 2001 } 2002 pool->base.hw_i2cs[i] = dcn31_i2c_hw_create(ctx, i); 2003 if (pool->base.hw_i2cs[i] == NULL) { 2004 BREAK_TO_DEBUGGER(); 2005 dm_error( 2006 "DC:failed to create hw i2c!!\n"); 2007 goto create_fail; 2008 } 2009 pool->base.sw_i2cs[i] = NULL; 2010 } 2011 2012 /* DCN314 has 4 DPIA */ 2013 pool->base.usb4_dpia_count = 4; 2014 2015 /* Audio, Stream Encoders including HPO and virtual, MPC 3D LUTs */ 2016 if (!resource_construct(num_virtual_links, dc, &pool->base, 2017 (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment) ? 2018 &res_create_funcs : &res_create_maximus_funcs))) 2019 goto create_fail; 2020 2021 /* HW Sequencer and Plane caps */ 2022 dcn314_hw_sequencer_construct(dc); 2023 2024 dc->caps.max_planes = pool->base.pipe_count; 2025 2026 for (i = 0; i < dc->caps.max_planes; ++i) 2027 dc->caps.planes[i] = plane_cap; 2028 2029 dc->cap_funcs = cap_funcs; 2030 2031 dc->dcn_ip->max_num_dpp = dcn3_14_ip.max_num_dpp; 2032 2033 return true; 2034 2035 create_fail: 2036 2037 dcn314_resource_destruct(pool); 2038 2039 return false; 2040 } 2041 2042 struct resource_pool *dcn314_create_resource_pool( 2043 const struct dc_init_data *init_data, 2044 struct dc *dc) 2045 { 2046 struct dcn314_resource_pool *pool = 2047 kzalloc(sizeof(struct dcn314_resource_pool), GFP_KERNEL); 2048 2049 if (!pool) 2050 return NULL; 2051 2052 if (dcn314_resource_construct(init_data->num_virtual_links, dc, pool)) 2053 return &pool->base; 2054 2055 BREAK_TO_DEBUGGER(); 2056 kfree(pool); 2057 return NULL; 2058 } 2059