1 // SPDX-License-Identifier: MIT 2 /* 3 * Copyright 2022 Advanced Micro Devices, Inc. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 * 23 * Authors: AMD 24 * 25 */ 26 27 28 #include "dm_services.h" 29 #include "dc.h" 30 31 #include "dcn31/dcn31_init.h" 32 #include "dcn314/dcn314_init.h" 33 34 #include "resource.h" 35 #include "include/irq_service_interface.h" 36 #include "dcn314_resource.h" 37 38 #include "dcn20/dcn20_resource.h" 39 #include "dcn30/dcn30_resource.h" 40 #include "dcn31/dcn31_resource.h" 41 42 #include "dcn10/dcn10_ipp.h" 43 #include "dcn30/dcn30_hubbub.h" 44 #include "dcn31/dcn31_hubbub.h" 45 #include "dcn30/dcn30_mpc.h" 46 #include "dcn31/dcn31_hubp.h" 47 #include "irq/dcn31/irq_service_dcn31.h" 48 #include "irq/dcn314/irq_service_dcn314.h" 49 #include "dcn30/dcn30_dpp.h" 50 #include "dcn314/dcn314_optc.h" 51 #include "dcn20/dcn20_hwseq.h" 52 #include "dcn30/dcn30_hwseq.h" 53 #include "dce110/dce110_hw_sequencer.h" 54 #include "dcn30/dcn30_opp.h" 55 #include "dcn20/dcn20_dsc.h" 56 #include "dcn30/dcn30_vpg.h" 57 #include "dcn30/dcn30_afmt.h" 58 #include "dcn31/dcn31_dio_link_encoder.h" 59 #include "dcn314/dcn314_dio_stream_encoder.h" 60 #include "dcn31/dcn31_hpo_dp_stream_encoder.h" 61 #include "dcn31/dcn31_hpo_dp_link_encoder.h" 62 #include "dcn31/dcn31_apg.h" 63 #include "dcn31/dcn31_vpg.h" 64 #include "dcn31/dcn31_afmt.h" 65 #include "dce/dce_clock_source.h" 66 #include "dce/dce_audio.h" 67 #include "dce/dce_hwseq.h" 68 #include "clk_mgr.h" 69 #include "virtual/virtual_stream_encoder.h" 70 #include "dce110/dce110_resource.h" 71 #include "dml/display_mode_vba.h" 72 #include "dml/dcn31/dcn31_fpu.h" 73 #include "dcn314/dcn314_dccg.h" 74 #include "dcn10/dcn10_resource.h" 75 #include "dcn31/dcn31_panel_cntl.h" 76 #include "dcn314/dcn314_hwseq.h" 77 78 #include "dcn30/dcn30_dwb.h" 79 #include "dcn30/dcn30_mmhubbub.h" 80 81 #include "dcn/dcn_3_1_4_offset.h" 82 #include "dcn/dcn_3_1_4_sh_mask.h" 83 #include "dpcs/dpcs_3_1_4_offset.h" 84 #include "dpcs/dpcs_3_1_4_sh_mask.h" 85 86 #define DCHUBBUB_DEBUG_CTRL_0__DET_DEPTH__SHIFT 0x10 87 #define DCHUBBUB_DEBUG_CTRL_0__DET_DEPTH_MASK 0x01FF0000L 88 89 #include "reg_helper.h" 90 #include "dce/dmub_abm.h" 91 #include "dce/dmub_psr.h" 92 #include "dce/dce_aux.h" 93 #include "dce/dce_i2c.h" 94 #include "dml/dcn314/display_mode_vba_314.h" 95 #include "vm_helper.h" 96 #include "dcn20/dcn20_vmid.h" 97 98 #include "link_enc_cfg.h" 99 100 #define DCN_BASE__INST0_SEG1 0x000000C0 101 #define DCN_BASE__INST0_SEG2 0x000034C0 102 #define DCN_BASE__INST0_SEG3 0x00009000 103 104 #define NBIO_BASE__INST0_SEG1 0x00000014 105 106 #define MAX_INSTANCE 7 107 #define MAX_SEGMENT 8 108 109 #define regBIF_BX2_BIOS_SCRATCH_2 0x003a 110 #define regBIF_BX2_BIOS_SCRATCH_2_BASE_IDX 1 111 #define regBIF_BX2_BIOS_SCRATCH_3 0x003b 112 #define regBIF_BX2_BIOS_SCRATCH_3_BASE_IDX 1 113 #define regBIF_BX2_BIOS_SCRATCH_6 0x003e 114 #define regBIF_BX2_BIOS_SCRATCH_6_BASE_IDX 1 115 116 struct IP_BASE_INSTANCE { 117 unsigned int segment[MAX_SEGMENT]; 118 }; 119 120 struct IP_BASE { 121 struct IP_BASE_INSTANCE instance[MAX_INSTANCE]; 122 }; 123 124 static const struct IP_BASE DCN_BASE = { { { { 0x00000012, 0x000000C0, 0x000034C0, 0x00009000, 0x02403C00, 0, 0, 0 } }, 125 { { 0, 0, 0, 0, 0, 0, 0, 0 } }, 126 { { 0, 0, 0, 0, 0, 0, 0, 0 } }, 127 { { 0, 0, 0, 0, 0, 0, 0, 0 } }, 128 { { 0, 0, 0, 0, 0, 0, 0, 0 } }, 129 { { 0, 0, 0, 0, 0, 0, 0, 0 } }, 130 { { 0, 0, 0, 0, 0, 0, 0, 0 } } } }; 131 132 133 #define DC_LOGGER_INIT(logger) 134 135 #define DCN3_14_DEFAULT_DET_SIZE 384 136 #define DCN3_14_MAX_DET_SIZE 384 137 #define DCN3_14_MIN_COMPBUF_SIZE_KB 128 138 #define DCN3_14_CRB_SEGMENT_SIZE_KB 64 139 struct _vcs_dpi_ip_params_st dcn3_14_ip = { 140 .VBlankNomDefaultUS = 668, 141 .gpuvm_enable = 1, 142 .gpuvm_max_page_table_levels = 1, 143 .hostvm_enable = 1, 144 .hostvm_max_page_table_levels = 2, 145 .rob_buffer_size_kbytes = 64, 146 .det_buffer_size_kbytes = DCN3_14_DEFAULT_DET_SIZE, 147 .config_return_buffer_size_in_kbytes = 1792, 148 .compressed_buffer_segment_size_in_kbytes = 64, 149 .meta_fifo_size_in_kentries = 32, 150 .zero_size_buffer_entries = 512, 151 .compbuf_reserved_space_64b = 256, 152 .compbuf_reserved_space_zs = 64, 153 .dpp_output_buffer_pixels = 2560, 154 .opp_output_buffer_lines = 1, 155 .pixel_chunk_size_kbytes = 8, 156 .meta_chunk_size_kbytes = 2, 157 .min_meta_chunk_size_bytes = 256, 158 .writeback_chunk_size_kbytes = 8, 159 .ptoi_supported = false, 160 .num_dsc = 4, 161 .maximum_dsc_bits_per_component = 10, 162 .dsc422_native_support = false, 163 .is_line_buffer_bpp_fixed = true, 164 .line_buffer_fixed_bpp = 48, 165 .line_buffer_size_bits = 789504, 166 .max_line_buffer_lines = 12, 167 .writeback_interface_buffer_size_kbytes = 90, 168 .max_num_dpp = 4, 169 .max_num_otg = 4, 170 .max_num_hdmi_frl_outputs = 1, 171 .max_num_wb = 1, 172 .max_dchub_pscl_bw_pix_per_clk = 4, 173 .max_pscl_lb_bw_pix_per_clk = 2, 174 .max_lb_vscl_bw_pix_per_clk = 4, 175 .max_vscl_hscl_bw_pix_per_clk = 4, 176 .max_hscl_ratio = 6, 177 .max_vscl_ratio = 6, 178 .max_hscl_taps = 8, 179 .max_vscl_taps = 8, 180 .dpte_buffer_size_in_pte_reqs_luma = 64, 181 .dpte_buffer_size_in_pte_reqs_chroma = 34, 182 .dispclk_ramp_margin_percent = 1, 183 .max_inter_dcn_tile_repeaters = 8, 184 .cursor_buffer_size = 16, 185 .cursor_chunk_size = 2, 186 .writeback_line_buffer_buffer_size = 0, 187 .writeback_min_hscl_ratio = 1, 188 .writeback_min_vscl_ratio = 1, 189 .writeback_max_hscl_ratio = 1, 190 .writeback_max_vscl_ratio = 1, 191 .writeback_max_hscl_taps = 1, 192 .writeback_max_vscl_taps = 1, 193 .dppclk_delay_subtotal = 46, 194 .dppclk_delay_scl = 50, 195 .dppclk_delay_scl_lb_only = 16, 196 .dppclk_delay_cnvc_formatter = 27, 197 .dppclk_delay_cnvc_cursor = 6, 198 .dispclk_delay_subtotal = 119, 199 .dynamic_metadata_vm_enabled = false, 200 .odm_combine_4to1_supported = false, 201 .dcc_supported = true, 202 }; 203 204 struct _vcs_dpi_soc_bounding_box_st dcn3_14_soc = { 205 /*TODO: correct dispclk/dppclk voltage level determination*/ 206 .clock_limits = { 207 { 208 .state = 0, 209 .dispclk_mhz = 1200.0, 210 .dppclk_mhz = 1200.0, 211 .phyclk_mhz = 600.0, 212 .phyclk_d18_mhz = 667.0, 213 .dscclk_mhz = 186.0, 214 .dtbclk_mhz = 625.0, 215 }, 216 { 217 .state = 1, 218 .dispclk_mhz = 1200.0, 219 .dppclk_mhz = 1200.0, 220 .phyclk_mhz = 810.0, 221 .phyclk_d18_mhz = 667.0, 222 .dscclk_mhz = 209.0, 223 .dtbclk_mhz = 625.0, 224 }, 225 { 226 .state = 2, 227 .dispclk_mhz = 1200.0, 228 .dppclk_mhz = 1200.0, 229 .phyclk_mhz = 810.0, 230 .phyclk_d18_mhz = 667.0, 231 .dscclk_mhz = 209.0, 232 .dtbclk_mhz = 625.0, 233 }, 234 { 235 .state = 3, 236 .dispclk_mhz = 1200.0, 237 .dppclk_mhz = 1200.0, 238 .phyclk_mhz = 810.0, 239 .phyclk_d18_mhz = 667.0, 240 .dscclk_mhz = 371.0, 241 .dtbclk_mhz = 625.0, 242 }, 243 { 244 .state = 4, 245 .dispclk_mhz = 1200.0, 246 .dppclk_mhz = 1200.0, 247 .phyclk_mhz = 810.0, 248 .phyclk_d18_mhz = 667.0, 249 .dscclk_mhz = 417.0, 250 .dtbclk_mhz = 625.0, 251 }, 252 }, 253 .num_states = 5, 254 .sr_exit_time_us = 9.0, 255 .sr_enter_plus_exit_time_us = 11.0, 256 .sr_exit_z8_time_us = 442.0, 257 .sr_enter_plus_exit_z8_time_us = 560.0, 258 .writeback_latency_us = 12.0, 259 .dram_channel_width_bytes = 4, 260 .round_trip_ping_latency_dcfclk_cycles = 106, 261 .urgent_latency_pixel_data_only_us = 4.0, 262 .urgent_latency_pixel_mixed_with_vm_data_us = 4.0, 263 .urgent_latency_vm_data_only_us = 4.0, 264 .urgent_out_of_order_return_per_channel_pixel_only_bytes = 4096, 265 .urgent_out_of_order_return_per_channel_pixel_and_vm_bytes = 4096, 266 .urgent_out_of_order_return_per_channel_vm_only_bytes = 4096, 267 .pct_ideal_sdp_bw_after_urgent = 80.0, 268 .pct_ideal_dram_sdp_bw_after_urgent_pixel_only = 65.0, 269 .pct_ideal_dram_sdp_bw_after_urgent_pixel_and_vm = 60.0, 270 .pct_ideal_dram_sdp_bw_after_urgent_vm_only = 30.0, 271 .max_avg_sdp_bw_use_normal_percent = 60.0, 272 .max_avg_dram_bw_use_normal_percent = 60.0, 273 .fabric_datapath_to_dcn_data_return_bytes = 32, 274 .return_bus_width_bytes = 64, 275 .downspread_percent = 0.38, 276 .dcn_downspread_percent = 0.5, 277 .gpuvm_min_page_size_bytes = 4096, 278 .hostvm_min_page_size_bytes = 4096, 279 .do_urgent_latency_adjustment = false, 280 .urgent_latency_adjustment_fabric_clock_component_us = 0, 281 .urgent_latency_adjustment_fabric_clock_reference_mhz = 0, 282 }; 283 284 enum dcn31_clk_src_array_id { 285 DCN31_CLK_SRC_PLL0, 286 DCN31_CLK_SRC_PLL1, 287 DCN31_CLK_SRC_PLL2, 288 DCN31_CLK_SRC_PLL3, 289 DCN31_CLK_SRC_PLL4, 290 DCN30_CLK_SRC_TOTAL 291 }; 292 293 /* begin ********************* 294 * macros to expend register list macro defined in HW object header file 295 */ 296 297 /* DCN */ 298 /* TODO awful hack. fixup dcn20_dwb.h */ 299 #undef BASE_INNER 300 #define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg 301 302 #define BASE(seg) BASE_INNER(seg) 303 304 #define SR(reg_name)\ 305 .reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \ 306 reg ## reg_name 307 308 #define SRI(reg_name, block, id)\ 309 .reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 310 reg ## block ## id ## _ ## reg_name 311 312 #define SRI2(reg_name, block, id)\ 313 .reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \ 314 reg ## reg_name 315 316 #define SRIR(var_name, reg_name, block, id)\ 317 .var_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 318 reg ## block ## id ## _ ## reg_name 319 320 #define SRII(reg_name, block, id)\ 321 .reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 322 reg ## block ## id ## _ ## reg_name 323 324 #define SRII_MPC_RMU(reg_name, block, id)\ 325 .RMU##_##reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 326 reg ## block ## id ## _ ## reg_name 327 328 #define SRII_DWB(reg_name, temp_name, block, id)\ 329 .reg_name[id] = BASE(reg ## block ## id ## _ ## temp_name ## _BASE_IDX) + \ 330 reg ## block ## id ## _ ## temp_name 331 332 #define DCCG_SRII(reg_name, block, id)\ 333 .block ## _ ## reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 334 reg ## block ## id ## _ ## reg_name 335 336 #define VUPDATE_SRII(reg_name, block, id)\ 337 .reg_name[id] = BASE(reg ## reg_name ## _ ## block ## id ## _BASE_IDX) + \ 338 reg ## reg_name ## _ ## block ## id 339 340 /* NBIO */ 341 #define NBIO_BASE_INNER(seg) \ 342 NBIO_BASE__INST0_SEG ## seg 343 344 #define NBIO_BASE(seg) \ 345 NBIO_BASE_INNER(seg) 346 347 #define NBIO_SR(reg_name)\ 348 .reg_name = NBIO_BASE(regBIF_BX2_ ## reg_name ## _BASE_IDX) + \ 349 regBIF_BX2_ ## reg_name 350 351 /* MMHUB */ 352 #define MMHUB_BASE_INNER(seg) \ 353 MMHUB_BASE__INST0_SEG ## seg 354 355 #define MMHUB_BASE(seg) \ 356 MMHUB_BASE_INNER(seg) 357 358 #define MMHUB_SR(reg_name)\ 359 .reg_name = MMHUB_BASE(reg ## reg_name ## _BASE_IDX) + \ 360 reg ## reg_name 361 362 /* CLOCK */ 363 #define CLK_BASE_INNER(seg) \ 364 CLK_BASE__INST0_SEG ## seg 365 366 #define CLK_BASE(seg) \ 367 CLK_BASE_INNER(seg) 368 369 #define CLK_SRI(reg_name, block, inst)\ 370 .reg_name = CLK_BASE(reg ## block ## _ ## inst ## _ ## reg_name ## _BASE_IDX) + \ 371 reg ## block ## _ ## inst ## _ ## reg_name 372 373 374 static const struct bios_registers bios_regs = { 375 NBIO_SR(BIOS_SCRATCH_3), 376 NBIO_SR(BIOS_SCRATCH_6) 377 }; 378 379 #define clk_src_regs(index, pllid)\ 380 [index] = {\ 381 CS_COMMON_REG_LIST_DCN3_0(index, pllid),\ 382 } 383 384 static const struct dce110_clk_src_regs clk_src_regs[] = { 385 clk_src_regs(0, A), 386 clk_src_regs(1, B), 387 clk_src_regs(2, C), 388 clk_src_regs(3, D), 389 clk_src_regs(4, E) 390 }; 391 392 static const struct dce110_clk_src_shift cs_shift = { 393 CS_COMMON_MASK_SH_LIST_DCN3_1_4(__SHIFT) 394 }; 395 396 static const struct dce110_clk_src_mask cs_mask = { 397 CS_COMMON_MASK_SH_LIST_DCN3_1_4(_MASK) 398 }; 399 400 #define abm_regs(id)\ 401 [id] = {\ 402 ABM_DCN302_REG_LIST(id)\ 403 } 404 405 static const struct dce_abm_registers abm_regs[] = { 406 abm_regs(0), 407 abm_regs(1), 408 abm_regs(2), 409 abm_regs(3), 410 }; 411 412 static const struct dce_abm_shift abm_shift = { 413 ABM_MASK_SH_LIST_DCN30(__SHIFT) 414 }; 415 416 static const struct dce_abm_mask abm_mask = { 417 ABM_MASK_SH_LIST_DCN30(_MASK) 418 }; 419 420 #define audio_regs(id)\ 421 [id] = {\ 422 AUD_COMMON_REG_LIST(id)\ 423 } 424 425 static const struct dce_audio_registers audio_regs[] = { 426 audio_regs(0), 427 audio_regs(1), 428 audio_regs(2), 429 audio_regs(3), 430 audio_regs(4), 431 audio_regs(5), 432 audio_regs(6) 433 }; 434 435 #define DCE120_AUD_COMMON_MASK_SH_LIST(mask_sh)\ 436 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX, AZALIA_ENDPOINT_REG_INDEX, mask_sh),\ 437 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA, AZALIA_ENDPOINT_REG_DATA, mask_sh),\ 438 AUD_COMMON_MASK_SH_LIST_BASE(mask_sh) 439 440 static const struct dce_audio_shift audio_shift = { 441 DCE120_AUD_COMMON_MASK_SH_LIST(__SHIFT) 442 }; 443 444 static const struct dce_audio_mask audio_mask = { 445 DCE120_AUD_COMMON_MASK_SH_LIST(_MASK) 446 }; 447 448 #define vpg_regs(id)\ 449 [id] = {\ 450 VPG_DCN31_REG_LIST(id)\ 451 } 452 453 static const struct dcn31_vpg_registers vpg_regs[] = { 454 vpg_regs(0), 455 vpg_regs(1), 456 vpg_regs(2), 457 vpg_regs(3), 458 vpg_regs(4), 459 vpg_regs(5), 460 vpg_regs(6), 461 vpg_regs(7), 462 vpg_regs(8), 463 vpg_regs(9), 464 }; 465 466 static const struct dcn31_vpg_shift vpg_shift = { 467 DCN31_VPG_MASK_SH_LIST(__SHIFT) 468 }; 469 470 static const struct dcn31_vpg_mask vpg_mask = { 471 DCN31_VPG_MASK_SH_LIST(_MASK) 472 }; 473 474 #define afmt_regs(id)\ 475 [id] = {\ 476 AFMT_DCN31_REG_LIST(id)\ 477 } 478 479 static const struct dcn31_afmt_registers afmt_regs[] = { 480 afmt_regs(0), 481 afmt_regs(1), 482 afmt_regs(2), 483 afmt_regs(3), 484 afmt_regs(4), 485 afmt_regs(5) 486 }; 487 488 static const struct dcn31_afmt_shift afmt_shift = { 489 DCN31_AFMT_MASK_SH_LIST(__SHIFT) 490 }; 491 492 static const struct dcn31_afmt_mask afmt_mask = { 493 DCN31_AFMT_MASK_SH_LIST(_MASK) 494 }; 495 496 #define apg_regs(id)\ 497 [id] = {\ 498 APG_DCN31_REG_LIST(id)\ 499 } 500 501 static const struct dcn31_apg_registers apg_regs[] = { 502 apg_regs(0), 503 apg_regs(1), 504 apg_regs(2), 505 apg_regs(3) 506 }; 507 508 static const struct dcn31_apg_shift apg_shift = { 509 DCN31_APG_MASK_SH_LIST(__SHIFT) 510 }; 511 512 static const struct dcn31_apg_mask apg_mask = { 513 DCN31_APG_MASK_SH_LIST(_MASK) 514 }; 515 516 #define stream_enc_regs(id)\ 517 [id] = {\ 518 SE_DCN314_REG_LIST(id)\ 519 } 520 521 static const struct dcn10_stream_enc_registers stream_enc_regs[] = { 522 stream_enc_regs(0), 523 stream_enc_regs(1), 524 stream_enc_regs(2), 525 stream_enc_regs(3), 526 stream_enc_regs(4) 527 }; 528 529 static const struct dcn10_stream_encoder_shift se_shift = { 530 SE_COMMON_MASK_SH_LIST_DCN314(__SHIFT) 531 }; 532 533 static const struct dcn10_stream_encoder_mask se_mask = { 534 SE_COMMON_MASK_SH_LIST_DCN314(_MASK) 535 }; 536 537 538 #define aux_regs(id)\ 539 [id] = {\ 540 DCN2_AUX_REG_LIST(id)\ 541 } 542 543 static const struct dcn10_link_enc_aux_registers link_enc_aux_regs[] = { 544 aux_regs(0), 545 aux_regs(1), 546 aux_regs(2), 547 aux_regs(3), 548 aux_regs(4) 549 }; 550 551 #define hpd_regs(id)\ 552 [id] = {\ 553 HPD_REG_LIST(id)\ 554 } 555 556 static const struct dcn10_link_enc_hpd_registers link_enc_hpd_regs[] = { 557 hpd_regs(0), 558 hpd_regs(1), 559 hpd_regs(2), 560 hpd_regs(3), 561 hpd_regs(4) 562 }; 563 564 #define link_regs(id, phyid)\ 565 [id] = {\ 566 LE_DCN31_REG_LIST(id), \ 567 UNIPHY_DCN2_REG_LIST(phyid), \ 568 } 569 570 static const struct dce110_aux_registers_shift aux_shift = { 571 DCN_AUX_MASK_SH_LIST(__SHIFT) 572 }; 573 574 static const struct dce110_aux_registers_mask aux_mask = { 575 DCN_AUX_MASK_SH_LIST(_MASK) 576 }; 577 578 static const struct dcn10_link_enc_registers link_enc_regs[] = { 579 link_regs(0, A), 580 link_regs(1, B), 581 link_regs(2, C), 582 link_regs(3, D), 583 link_regs(4, E) 584 }; 585 586 static const struct dcn10_link_enc_shift le_shift = { 587 LINK_ENCODER_MASK_SH_LIST_DCN31(__SHIFT), 588 DPCS_DCN31_MASK_SH_LIST(__SHIFT) 589 }; 590 591 static const struct dcn10_link_enc_mask le_mask = { 592 LINK_ENCODER_MASK_SH_LIST_DCN31(_MASK), 593 DPCS_DCN31_MASK_SH_LIST(_MASK) 594 }; 595 596 #define hpo_dp_stream_encoder_reg_list(id)\ 597 [id] = {\ 598 DCN3_1_HPO_DP_STREAM_ENC_REG_LIST(id)\ 599 } 600 601 static const struct dcn31_hpo_dp_stream_encoder_registers hpo_dp_stream_enc_regs[] = { 602 hpo_dp_stream_encoder_reg_list(0), 603 hpo_dp_stream_encoder_reg_list(1), 604 hpo_dp_stream_encoder_reg_list(2), 605 }; 606 607 static const struct dcn31_hpo_dp_stream_encoder_shift hpo_dp_se_shift = { 608 DCN3_1_HPO_DP_STREAM_ENC_MASK_SH_LIST(__SHIFT) 609 }; 610 611 static const struct dcn31_hpo_dp_stream_encoder_mask hpo_dp_se_mask = { 612 DCN3_1_HPO_DP_STREAM_ENC_MASK_SH_LIST(_MASK) 613 }; 614 615 616 #define hpo_dp_link_encoder_reg_list(id)\ 617 [id] = {\ 618 DCN3_1_HPO_DP_LINK_ENC_REG_LIST(id),\ 619 DCN3_1_RDPCSTX_REG_LIST(0),\ 620 DCN3_1_RDPCSTX_REG_LIST(1),\ 621 DCN3_1_RDPCSTX_REG_LIST(2),\ 622 } 623 624 static const struct dcn31_hpo_dp_link_encoder_registers hpo_dp_link_enc_regs[] = { 625 hpo_dp_link_encoder_reg_list(0), 626 hpo_dp_link_encoder_reg_list(1), 627 }; 628 629 static const struct dcn31_hpo_dp_link_encoder_shift hpo_dp_le_shift = { 630 DCN3_1_HPO_DP_LINK_ENC_MASK_SH_LIST(__SHIFT) 631 }; 632 633 static const struct dcn31_hpo_dp_link_encoder_mask hpo_dp_le_mask = { 634 DCN3_1_HPO_DP_LINK_ENC_MASK_SH_LIST(_MASK) 635 }; 636 637 #define dpp_regs(id)\ 638 [id] = {\ 639 DPP_REG_LIST_DCN30(id),\ 640 } 641 642 static const struct dcn3_dpp_registers dpp_regs[] = { 643 dpp_regs(0), 644 dpp_regs(1), 645 dpp_regs(2), 646 dpp_regs(3) 647 }; 648 649 static const struct dcn3_dpp_shift tf_shift = { 650 DPP_REG_LIST_SH_MASK_DCN30(__SHIFT) 651 }; 652 653 static const struct dcn3_dpp_mask tf_mask = { 654 DPP_REG_LIST_SH_MASK_DCN30(_MASK) 655 }; 656 657 #define opp_regs(id)\ 658 [id] = {\ 659 OPP_REG_LIST_DCN30(id),\ 660 } 661 662 static const struct dcn20_opp_registers opp_regs[] = { 663 opp_regs(0), 664 opp_regs(1), 665 opp_regs(2), 666 opp_regs(3) 667 }; 668 669 static const struct dcn20_opp_shift opp_shift = { 670 OPP_MASK_SH_LIST_DCN20(__SHIFT) 671 }; 672 673 static const struct dcn20_opp_mask opp_mask = { 674 OPP_MASK_SH_LIST_DCN20(_MASK) 675 }; 676 677 #define aux_engine_regs(id)\ 678 [id] = {\ 679 AUX_COMMON_REG_LIST0(id), \ 680 .AUXN_IMPCAL = 0, \ 681 .AUXP_IMPCAL = 0, \ 682 .AUX_RESET_MASK = DP_AUX0_AUX_CONTROL__AUX_RESET_MASK, \ 683 } 684 685 static const struct dce110_aux_registers aux_engine_regs[] = { 686 aux_engine_regs(0), 687 aux_engine_regs(1), 688 aux_engine_regs(2), 689 aux_engine_regs(3), 690 aux_engine_regs(4) 691 }; 692 693 #define dwbc_regs_dcn3(id)\ 694 [id] = {\ 695 DWBC_COMMON_REG_LIST_DCN30(id),\ 696 } 697 698 static const struct dcn30_dwbc_registers dwbc30_regs[] = { 699 dwbc_regs_dcn3(0), 700 }; 701 702 static const struct dcn30_dwbc_shift dwbc30_shift = { 703 DWBC_COMMON_MASK_SH_LIST_DCN30(__SHIFT) 704 }; 705 706 static const struct dcn30_dwbc_mask dwbc30_mask = { 707 DWBC_COMMON_MASK_SH_LIST_DCN30(_MASK) 708 }; 709 710 #define mcif_wb_regs_dcn3(id)\ 711 [id] = {\ 712 MCIF_WB_COMMON_REG_LIST_DCN30(id),\ 713 } 714 715 static const struct dcn30_mmhubbub_registers mcif_wb30_regs[] = { 716 mcif_wb_regs_dcn3(0) 717 }; 718 719 static const struct dcn30_mmhubbub_shift mcif_wb30_shift = { 720 MCIF_WB_COMMON_MASK_SH_LIST_DCN30(__SHIFT) 721 }; 722 723 static const struct dcn30_mmhubbub_mask mcif_wb30_mask = { 724 MCIF_WB_COMMON_MASK_SH_LIST_DCN30(_MASK) 725 }; 726 727 #define dsc_regsDCN314(id)\ 728 [id] = {\ 729 DSC_REG_LIST_DCN314(id)\ 730 } 731 732 static const struct dcn20_dsc_registers dsc_regs[] = { 733 dsc_regsDCN314(0), 734 dsc_regsDCN314(1), 735 dsc_regsDCN314(2), 736 dsc_regsDCN314(3) 737 }; 738 739 static const struct dcn20_dsc_shift dsc_shift = { 740 DSC_REG_LIST_SH_MASK_DCN314(__SHIFT) 741 }; 742 743 static const struct dcn20_dsc_mask dsc_mask = { 744 DSC_REG_LIST_SH_MASK_DCN314(_MASK) 745 }; 746 747 static const struct dcn30_mpc_registers mpc_regs = { 748 MPC_REG_LIST_DCN3_0(0), 749 MPC_REG_LIST_DCN3_0(1), 750 MPC_REG_LIST_DCN3_0(2), 751 MPC_REG_LIST_DCN3_0(3), 752 MPC_OUT_MUX_REG_LIST_DCN3_0(0), 753 MPC_OUT_MUX_REG_LIST_DCN3_0(1), 754 MPC_OUT_MUX_REG_LIST_DCN3_0(2), 755 MPC_OUT_MUX_REG_LIST_DCN3_0(3), 756 MPC_RMU_GLOBAL_REG_LIST_DCN3AG, 757 MPC_RMU_REG_LIST_DCN3AG(0), 758 MPC_RMU_REG_LIST_DCN3AG(1), 759 //MPC_RMU_REG_LIST_DCN3AG(2), 760 MPC_DWB_MUX_REG_LIST_DCN3_0(0), 761 }; 762 763 static const struct dcn30_mpc_shift mpc_shift = { 764 MPC_COMMON_MASK_SH_LIST_DCN30(__SHIFT) 765 }; 766 767 static const struct dcn30_mpc_mask mpc_mask = { 768 MPC_COMMON_MASK_SH_LIST_DCN30(_MASK) 769 }; 770 771 #define optc_regs(id)\ 772 [id] = {OPTC_COMMON_REG_LIST_DCN3_14(id)} 773 774 static const struct dcn_optc_registers optc_regs[] = { 775 optc_regs(0), 776 optc_regs(1), 777 optc_regs(2), 778 optc_regs(3) 779 }; 780 781 static const struct dcn_optc_shift optc_shift = { 782 OPTC_COMMON_MASK_SH_LIST_DCN3_14(__SHIFT) 783 }; 784 785 static const struct dcn_optc_mask optc_mask = { 786 OPTC_COMMON_MASK_SH_LIST_DCN3_14(_MASK) 787 }; 788 789 #define hubp_regs(id)\ 790 [id] = {\ 791 HUBP_REG_LIST_DCN30(id)\ 792 } 793 794 static const struct dcn_hubp2_registers hubp_regs[] = { 795 hubp_regs(0), 796 hubp_regs(1), 797 hubp_regs(2), 798 hubp_regs(3) 799 }; 800 801 802 static const struct dcn_hubp2_shift hubp_shift = { 803 HUBP_MASK_SH_LIST_DCN31(__SHIFT) 804 }; 805 806 static const struct dcn_hubp2_mask hubp_mask = { 807 HUBP_MASK_SH_LIST_DCN31(_MASK) 808 }; 809 static const struct dcn_hubbub_registers hubbub_reg = { 810 HUBBUB_REG_LIST_DCN31(0) 811 }; 812 813 static const struct dcn_hubbub_shift hubbub_shift = { 814 HUBBUB_MASK_SH_LIST_DCN31(__SHIFT) 815 }; 816 817 static const struct dcn_hubbub_mask hubbub_mask = { 818 HUBBUB_MASK_SH_LIST_DCN31(_MASK) 819 }; 820 821 static const struct dccg_registers dccg_regs = { 822 DCCG_REG_LIST_DCN314() 823 }; 824 825 static const struct dccg_shift dccg_shift = { 826 DCCG_MASK_SH_LIST_DCN314(__SHIFT) 827 }; 828 829 static const struct dccg_mask dccg_mask = { 830 DCCG_MASK_SH_LIST_DCN314(_MASK) 831 }; 832 833 834 #define SRII2(reg_name_pre, reg_name_post, id)\ 835 .reg_name_pre ## _ ## reg_name_post[id] = BASE(reg ## reg_name_pre \ 836 ## id ## _ ## reg_name_post ## _BASE_IDX) + \ 837 reg ## reg_name_pre ## id ## _ ## reg_name_post 838 839 840 #define HWSEQ_DCN31_REG_LIST()\ 841 SR(DCHUBBUB_GLOBAL_TIMER_CNTL), \ 842 SR(DCHUBBUB_ARB_HOSTVM_CNTL), \ 843 SR(DIO_MEM_PWR_CTRL), \ 844 SR(ODM_MEM_PWR_CTRL3), \ 845 SR(DMU_MEM_PWR_CNTL), \ 846 SR(MMHUBBUB_MEM_PWR_CNTL), \ 847 SR(DCCG_GATE_DISABLE_CNTL), \ 848 SR(DCCG_GATE_DISABLE_CNTL2), \ 849 SR(DCFCLK_CNTL),\ 850 SR(DC_MEM_GLOBAL_PWR_REQ_CNTL), \ 851 SRII(PIXEL_RATE_CNTL, OTG, 0), \ 852 SRII(PIXEL_RATE_CNTL, OTG, 1),\ 853 SRII(PIXEL_RATE_CNTL, OTG, 2),\ 854 SRII(PIXEL_RATE_CNTL, OTG, 3),\ 855 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 0),\ 856 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 1),\ 857 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 2),\ 858 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 3),\ 859 SR(MICROSECOND_TIME_BASE_DIV), \ 860 SR(MILLISECOND_TIME_BASE_DIV), \ 861 SR(DISPCLK_FREQ_CHANGE_CNTL), \ 862 SR(RBBMIF_TIMEOUT_DIS), \ 863 SR(RBBMIF_TIMEOUT_DIS_2), \ 864 SR(DCHUBBUB_CRC_CTRL), \ 865 SR(DPP_TOP0_DPP_CRC_CTRL), \ 866 SR(DPP_TOP0_DPP_CRC_VAL_B_A), \ 867 SR(DPP_TOP0_DPP_CRC_VAL_R_G), \ 868 SR(MPC_CRC_CTRL), \ 869 SR(MPC_CRC_RESULT_GB), \ 870 SR(MPC_CRC_RESULT_C), \ 871 SR(MPC_CRC_RESULT_AR), \ 872 SR(DOMAIN0_PG_CONFIG), \ 873 SR(DOMAIN1_PG_CONFIG), \ 874 SR(DOMAIN2_PG_CONFIG), \ 875 SR(DOMAIN3_PG_CONFIG), \ 876 SR(DOMAIN16_PG_CONFIG), \ 877 SR(DOMAIN17_PG_CONFIG), \ 878 SR(DOMAIN18_PG_CONFIG), \ 879 SR(DOMAIN19_PG_CONFIG), \ 880 SR(DOMAIN0_PG_STATUS), \ 881 SR(DOMAIN1_PG_STATUS), \ 882 SR(DOMAIN2_PG_STATUS), \ 883 SR(DOMAIN3_PG_STATUS), \ 884 SR(DOMAIN16_PG_STATUS), \ 885 SR(DOMAIN17_PG_STATUS), \ 886 SR(DOMAIN18_PG_STATUS), \ 887 SR(DOMAIN19_PG_STATUS), \ 888 SR(D1VGA_CONTROL), \ 889 SR(D2VGA_CONTROL), \ 890 SR(D3VGA_CONTROL), \ 891 SR(D4VGA_CONTROL), \ 892 SR(D5VGA_CONTROL), \ 893 SR(D6VGA_CONTROL), \ 894 SR(DC_IP_REQUEST_CNTL), \ 895 SR(AZALIA_AUDIO_DTO), \ 896 SR(AZALIA_CONTROLLER_CLOCK_GATING), \ 897 SR(HPO_TOP_HW_CONTROL) 898 899 static const struct dce_hwseq_registers hwseq_reg = { 900 HWSEQ_DCN31_REG_LIST() 901 }; 902 903 #define HWSEQ_DCN31_MASK_SH_LIST(mask_sh)\ 904 HWSEQ_DCN_MASK_SH_LIST(mask_sh), \ 905 HWS_SF(, DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_REFDIV, mask_sh), \ 906 HWS_SF(, DCHUBBUB_ARB_HOSTVM_CNTL, DISABLE_HOSTVM_FORCE_ALLOW_PSTATE, mask_sh), \ 907 HWS_SF(, DOMAIN0_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ 908 HWS_SF(, DOMAIN0_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ 909 HWS_SF(, DOMAIN1_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ 910 HWS_SF(, DOMAIN1_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ 911 HWS_SF(, DOMAIN2_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ 912 HWS_SF(, DOMAIN2_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ 913 HWS_SF(, DOMAIN3_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ 914 HWS_SF(, DOMAIN3_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ 915 HWS_SF(, DOMAIN16_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ 916 HWS_SF(, DOMAIN16_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ 917 HWS_SF(, DOMAIN17_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ 918 HWS_SF(, DOMAIN17_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ 919 HWS_SF(, DOMAIN18_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ 920 HWS_SF(, DOMAIN18_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ 921 HWS_SF(, DOMAIN19_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ 922 HWS_SF(, DOMAIN19_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ 923 HWS_SF(, DOMAIN0_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ 924 HWS_SF(, DOMAIN1_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ 925 HWS_SF(, DOMAIN2_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ 926 HWS_SF(, DOMAIN3_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ 927 HWS_SF(, DOMAIN16_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ 928 HWS_SF(, DOMAIN17_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ 929 HWS_SF(, DOMAIN18_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ 930 HWS_SF(, DOMAIN19_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ 931 HWS_SF(, DC_IP_REQUEST_CNTL, IP_REQUEST_EN, mask_sh), \ 932 HWS_SF(, AZALIA_AUDIO_DTO, AZALIA_AUDIO_DTO_MODULE, mask_sh), \ 933 HWS_SF(, HPO_TOP_CLOCK_CONTROL, HPO_HDMISTREAMCLK_G_GATE_DIS, mask_sh), \ 934 HWS_SF(, DMU_MEM_PWR_CNTL, DMCU_ERAM_MEM_PWR_FORCE, mask_sh), \ 935 HWS_SF(, ODM_MEM_PWR_CTRL3, ODM_MEM_UNASSIGNED_PWR_MODE, mask_sh), \ 936 HWS_SF(, ODM_MEM_PWR_CTRL3, ODM_MEM_VBLANK_PWR_MODE, mask_sh), \ 937 HWS_SF(, MMHUBBUB_MEM_PWR_CNTL, VGA_MEM_PWR_FORCE, mask_sh), \ 938 HWS_SF(, DIO_MEM_PWR_CTRL, I2C_LIGHT_SLEEP_FORCE, mask_sh), \ 939 HWS_SF(, HPO_TOP_HW_CONTROL, HPO_IO_EN, mask_sh) 940 941 static const struct dce_hwseq_shift hwseq_shift = { 942 HWSEQ_DCN31_MASK_SH_LIST(__SHIFT) 943 }; 944 945 static const struct dce_hwseq_mask hwseq_mask = { 946 HWSEQ_DCN31_MASK_SH_LIST(_MASK) 947 }; 948 #define vmid_regs(id)\ 949 [id] = {\ 950 DCN20_VMID_REG_LIST(id)\ 951 } 952 953 static const struct dcn_vmid_registers vmid_regs[] = { 954 vmid_regs(0), 955 vmid_regs(1), 956 vmid_regs(2), 957 vmid_regs(3), 958 vmid_regs(4), 959 vmid_regs(5), 960 vmid_regs(6), 961 vmid_regs(7), 962 vmid_regs(8), 963 vmid_regs(9), 964 vmid_regs(10), 965 vmid_regs(11), 966 vmid_regs(12), 967 vmid_regs(13), 968 vmid_regs(14), 969 vmid_regs(15) 970 }; 971 972 static const struct dcn20_vmid_shift vmid_shifts = { 973 DCN20_VMID_MASK_SH_LIST(__SHIFT) 974 }; 975 976 static const struct dcn20_vmid_mask vmid_masks = { 977 DCN20_VMID_MASK_SH_LIST(_MASK) 978 }; 979 980 static const struct resource_caps res_cap_dcn314 = { 981 .num_timing_generator = 4, 982 .num_opp = 4, 983 .num_video_plane = 4, 984 .num_audio = 5, 985 .num_stream_encoder = 5, 986 .num_dig_link_enc = 5, 987 .num_hpo_dp_stream_encoder = 4, 988 .num_hpo_dp_link_encoder = 2, 989 .num_pll = 5, 990 .num_dwb = 1, 991 .num_ddc = 5, 992 .num_vmid = 16, 993 .num_mpc_3dlut = 2, 994 .num_dsc = 4, 995 }; 996 997 static const struct dc_plane_cap plane_cap = { 998 .type = DC_PLANE_TYPE_DCN_UNIVERSAL, 999 .blends_with_above = true, 1000 .blends_with_below = true, 1001 .per_pixel_alpha = true, 1002 1003 .pixel_format_support = { 1004 .argb8888 = true, 1005 .nv12 = true, 1006 .fp16 = true, 1007 .p010 = true, 1008 .ayuv = false, 1009 }, 1010 1011 .max_upscale_factor = { 1012 .argb8888 = 16000, 1013 .nv12 = 16000, 1014 .fp16 = 16000 1015 }, 1016 1017 // 6:1 downscaling ratio: 1000/6 = 166.666 1018 .max_downscale_factor = { 1019 .argb8888 = 167, 1020 .nv12 = 167, 1021 .fp16 = 167 1022 }, 1023 64, 1024 64 1025 }; 1026 1027 static const struct dc_debug_options debug_defaults_drv = { 1028 .disable_z10 = true, /*hw not support it*/ 1029 .disable_dmcu = true, 1030 .force_abm_enable = false, 1031 .timing_trace = false, 1032 .clock_trace = true, 1033 .disable_pplib_clock_request = false, 1034 .pipe_split_policy = MPC_SPLIT_DYNAMIC, 1035 .force_single_disp_pipe_split = false, 1036 .disable_dcc = DCC_ENABLE, 1037 .vsr_support = true, 1038 .performance_trace = false, 1039 .max_downscale_src_width = 4096,/*upto true 4k*/ 1040 .disable_pplib_wm_range = false, 1041 .scl_reset_length10 = true, 1042 .sanity_checks = false, 1043 .underflow_assert_delay_us = 0xFFFFFFFF, 1044 .dwb_fi_phase = -1, // -1 = disable, 1045 .dmub_command_table = true, 1046 .pstate_enabled = true, 1047 .use_max_lb = true, 1048 .enable_mem_low_power = { 1049 .bits = { 1050 .vga = true, 1051 .i2c = true, 1052 .dmcu = false, // This is previously known to cause hang on S3 cycles if enabled 1053 .dscl = true, 1054 .cm = true, 1055 .mpc = true, 1056 .optc = true, 1057 .vpg = true, 1058 .afmt = true, 1059 } 1060 }, 1061 .optimize_edp_link_rate = true, 1062 .enable_sw_cntl_psr = true, 1063 .seamless_boot_odm_combine = true 1064 }; 1065 1066 static const struct dc_debug_options debug_defaults_diags = { 1067 .disable_dmcu = true, 1068 .force_abm_enable = false, 1069 .timing_trace = true, 1070 .clock_trace = true, 1071 .disable_dpp_power_gate = true, 1072 .disable_hubp_power_gate = true, 1073 .disable_clock_gate = true, 1074 .disable_pplib_clock_request = true, 1075 .disable_pplib_wm_range = true, 1076 .disable_stutter = false, 1077 .scl_reset_length10 = true, 1078 .dwb_fi_phase = -1, // -1 = disable 1079 .dmub_command_table = true, 1080 .enable_tri_buf = true, 1081 .use_max_lb = true 1082 }; 1083 1084 static void dcn31_dpp_destroy(struct dpp **dpp) 1085 { 1086 kfree(TO_DCN20_DPP(*dpp)); 1087 *dpp = NULL; 1088 } 1089 1090 static struct dpp *dcn31_dpp_create( 1091 struct dc_context *ctx, 1092 uint32_t inst) 1093 { 1094 struct dcn3_dpp *dpp = 1095 kzalloc(sizeof(struct dcn3_dpp), GFP_KERNEL); 1096 1097 if (!dpp) 1098 return NULL; 1099 1100 if (dpp3_construct(dpp, ctx, inst, 1101 &dpp_regs[inst], &tf_shift, &tf_mask)) 1102 return &dpp->base; 1103 1104 BREAK_TO_DEBUGGER(); 1105 kfree(dpp); 1106 return NULL; 1107 } 1108 1109 static struct output_pixel_processor *dcn31_opp_create( 1110 struct dc_context *ctx, uint32_t inst) 1111 { 1112 struct dcn20_opp *opp = 1113 kzalloc(sizeof(struct dcn20_opp), GFP_KERNEL); 1114 1115 if (!opp) { 1116 BREAK_TO_DEBUGGER(); 1117 return NULL; 1118 } 1119 1120 dcn20_opp_construct(opp, ctx, inst, 1121 &opp_regs[inst], &opp_shift, &opp_mask); 1122 return &opp->base; 1123 } 1124 1125 static struct dce_aux *dcn31_aux_engine_create( 1126 struct dc_context *ctx, 1127 uint32_t inst) 1128 { 1129 struct aux_engine_dce110 *aux_engine = 1130 kzalloc(sizeof(struct aux_engine_dce110), GFP_KERNEL); 1131 1132 if (!aux_engine) 1133 return NULL; 1134 1135 dce110_aux_engine_construct(aux_engine, ctx, inst, 1136 SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD, 1137 &aux_engine_regs[inst], 1138 &aux_mask, 1139 &aux_shift, 1140 ctx->dc->caps.extended_aux_timeout_support); 1141 1142 return &aux_engine->base; 1143 } 1144 #define i2c_inst_regs(id) { I2C_HW_ENGINE_COMMON_REG_LIST_DCN30(id) } 1145 1146 static const struct dce_i2c_registers i2c_hw_regs[] = { 1147 i2c_inst_regs(1), 1148 i2c_inst_regs(2), 1149 i2c_inst_regs(3), 1150 i2c_inst_regs(4), 1151 i2c_inst_regs(5), 1152 }; 1153 1154 static const struct dce_i2c_shift i2c_shifts = { 1155 I2C_COMMON_MASK_SH_LIST_DCN30(__SHIFT) 1156 }; 1157 1158 static const struct dce_i2c_mask i2c_masks = { 1159 I2C_COMMON_MASK_SH_LIST_DCN30(_MASK) 1160 }; 1161 1162 static struct dce_i2c_hw *dcn31_i2c_hw_create( 1163 struct dc_context *ctx, 1164 uint32_t inst) 1165 { 1166 struct dce_i2c_hw *dce_i2c_hw = 1167 kzalloc(sizeof(struct dce_i2c_hw), GFP_KERNEL); 1168 1169 if (!dce_i2c_hw) 1170 return NULL; 1171 1172 dcn2_i2c_hw_construct(dce_i2c_hw, ctx, inst, 1173 &i2c_hw_regs[inst], &i2c_shifts, &i2c_masks); 1174 1175 return dce_i2c_hw; 1176 } 1177 static struct mpc *dcn31_mpc_create( 1178 struct dc_context *ctx, 1179 int num_mpcc, 1180 int num_rmu) 1181 { 1182 struct dcn30_mpc *mpc30 = kzalloc(sizeof(struct dcn30_mpc), 1183 GFP_KERNEL); 1184 1185 if (!mpc30) 1186 return NULL; 1187 1188 dcn30_mpc_construct(mpc30, ctx, 1189 &mpc_regs, 1190 &mpc_shift, 1191 &mpc_mask, 1192 num_mpcc, 1193 num_rmu); 1194 1195 return &mpc30->base; 1196 } 1197 1198 static struct hubbub *dcn31_hubbub_create(struct dc_context *ctx) 1199 { 1200 int i; 1201 1202 struct dcn20_hubbub *hubbub3 = kzalloc(sizeof(struct dcn20_hubbub), 1203 GFP_KERNEL); 1204 1205 if (!hubbub3) 1206 return NULL; 1207 1208 hubbub31_construct(hubbub3, ctx, 1209 &hubbub_reg, 1210 &hubbub_shift, 1211 &hubbub_mask, 1212 dcn3_14_ip.det_buffer_size_kbytes, 1213 dcn3_14_ip.pixel_chunk_size_kbytes, 1214 dcn3_14_ip.config_return_buffer_size_in_kbytes); 1215 1216 1217 for (i = 0; i < res_cap_dcn314.num_vmid; i++) { 1218 struct dcn20_vmid *vmid = &hubbub3->vmid[i]; 1219 1220 vmid->ctx = ctx; 1221 1222 vmid->regs = &vmid_regs[i]; 1223 vmid->shifts = &vmid_shifts; 1224 vmid->masks = &vmid_masks; 1225 } 1226 1227 return &hubbub3->base; 1228 } 1229 1230 static struct timing_generator *dcn31_timing_generator_create( 1231 struct dc_context *ctx, 1232 uint32_t instance) 1233 { 1234 struct optc *tgn10 = 1235 kzalloc(sizeof(struct optc), GFP_KERNEL); 1236 1237 if (!tgn10) 1238 return NULL; 1239 1240 tgn10->base.inst = instance; 1241 tgn10->base.ctx = ctx; 1242 1243 tgn10->tg_regs = &optc_regs[instance]; 1244 tgn10->tg_shift = &optc_shift; 1245 tgn10->tg_mask = &optc_mask; 1246 1247 dcn314_timing_generator_init(tgn10); 1248 1249 return &tgn10->base; 1250 } 1251 1252 static const struct encoder_feature_support link_enc_feature = { 1253 .max_hdmi_deep_color = COLOR_DEPTH_121212, 1254 .max_hdmi_pixel_clock = 600000, 1255 .hdmi_ycbcr420_supported = true, 1256 .dp_ycbcr420_supported = true, 1257 .fec_supported = true, 1258 .flags.bits.IS_HBR2_CAPABLE = true, 1259 .flags.bits.IS_HBR3_CAPABLE = true, 1260 .flags.bits.IS_TPS3_CAPABLE = true, 1261 .flags.bits.IS_TPS4_CAPABLE = true 1262 }; 1263 1264 static struct link_encoder *dcn31_link_encoder_create( 1265 const struct encoder_init_data *enc_init_data) 1266 { 1267 struct dcn20_link_encoder *enc20 = 1268 kzalloc(sizeof(struct dcn20_link_encoder), GFP_KERNEL); 1269 1270 if (!enc20) 1271 return NULL; 1272 1273 dcn31_link_encoder_construct(enc20, 1274 enc_init_data, 1275 &link_enc_feature, 1276 &link_enc_regs[enc_init_data->transmitter], 1277 &link_enc_aux_regs[enc_init_data->channel - 1], 1278 &link_enc_hpd_regs[enc_init_data->hpd_source], 1279 &le_shift, 1280 &le_mask); 1281 1282 return &enc20->enc10.base; 1283 } 1284 1285 /* Create a minimal link encoder object not associated with a particular 1286 * physical connector. 1287 * resource_funcs.link_enc_create_minimal 1288 */ 1289 static struct link_encoder *dcn31_link_enc_create_minimal( 1290 struct dc_context *ctx, enum engine_id eng_id) 1291 { 1292 struct dcn20_link_encoder *enc20; 1293 1294 if ((eng_id - ENGINE_ID_DIGA) > ctx->dc->res_pool->res_cap->num_dig_link_enc) 1295 return NULL; 1296 1297 enc20 = kzalloc(sizeof(struct dcn20_link_encoder), GFP_KERNEL); 1298 if (!enc20) 1299 return NULL; 1300 1301 dcn31_link_encoder_construct_minimal( 1302 enc20, 1303 ctx, 1304 &link_enc_feature, 1305 &link_enc_regs[eng_id - ENGINE_ID_DIGA], 1306 eng_id); 1307 1308 return &enc20->enc10.base; 1309 } 1310 1311 static struct panel_cntl *dcn31_panel_cntl_create(const struct panel_cntl_init_data *init_data) 1312 { 1313 struct dcn31_panel_cntl *panel_cntl = 1314 kzalloc(sizeof(struct dcn31_panel_cntl), GFP_KERNEL); 1315 1316 if (!panel_cntl) 1317 return NULL; 1318 1319 dcn31_panel_cntl_construct(panel_cntl, init_data); 1320 1321 return &panel_cntl->base; 1322 } 1323 1324 static void read_dce_straps( 1325 struct dc_context *ctx, 1326 struct resource_straps *straps) 1327 { 1328 generic_reg_get(ctx, regDC_PINSTRAPS + BASE(regDC_PINSTRAPS_BASE_IDX), 1329 FN(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO), &straps->dc_pinstraps_audio); 1330 1331 } 1332 1333 static struct audio *dcn31_create_audio( 1334 struct dc_context *ctx, unsigned int inst) 1335 { 1336 return dce_audio_create(ctx, inst, 1337 &audio_regs[inst], &audio_shift, &audio_mask); 1338 } 1339 1340 static struct vpg *dcn31_vpg_create( 1341 struct dc_context *ctx, 1342 uint32_t inst) 1343 { 1344 struct dcn31_vpg *vpg31 = kzalloc(sizeof(struct dcn31_vpg), GFP_KERNEL); 1345 1346 if (!vpg31) 1347 return NULL; 1348 1349 vpg31_construct(vpg31, ctx, inst, 1350 &vpg_regs[inst], 1351 &vpg_shift, 1352 &vpg_mask); 1353 1354 return &vpg31->base; 1355 } 1356 1357 static struct afmt *dcn31_afmt_create( 1358 struct dc_context *ctx, 1359 uint32_t inst) 1360 { 1361 struct dcn31_afmt *afmt31 = kzalloc(sizeof(struct dcn31_afmt), GFP_KERNEL); 1362 1363 if (!afmt31) 1364 return NULL; 1365 1366 afmt31_construct(afmt31, ctx, inst, 1367 &afmt_regs[inst], 1368 &afmt_shift, 1369 &afmt_mask); 1370 1371 // Light sleep by default, no need to power down here 1372 1373 return &afmt31->base; 1374 } 1375 1376 static struct apg *dcn31_apg_create( 1377 struct dc_context *ctx, 1378 uint32_t inst) 1379 { 1380 struct dcn31_apg *apg31 = kzalloc(sizeof(struct dcn31_apg), GFP_KERNEL); 1381 1382 if (!apg31) 1383 return NULL; 1384 1385 apg31_construct(apg31, ctx, inst, 1386 &apg_regs[inst], 1387 &apg_shift, 1388 &apg_mask); 1389 1390 return &apg31->base; 1391 } 1392 1393 static struct stream_encoder *dcn314_stream_encoder_create( 1394 enum engine_id eng_id, 1395 struct dc_context *ctx) 1396 { 1397 struct dcn10_stream_encoder *enc1; 1398 struct vpg *vpg; 1399 struct afmt *afmt; 1400 int vpg_inst; 1401 int afmt_inst; 1402 1403 /* Mapping of VPG, AFMT, DME register blocks to DIO block instance */ 1404 if (eng_id <= ENGINE_ID_DIGF) { 1405 vpg_inst = eng_id; 1406 afmt_inst = eng_id; 1407 } else 1408 return NULL; 1409 1410 enc1 = kzalloc(sizeof(struct dcn10_stream_encoder), GFP_KERNEL); 1411 vpg = dcn31_vpg_create(ctx, vpg_inst); 1412 afmt = dcn31_afmt_create(ctx, afmt_inst); 1413 1414 if (!enc1 || !vpg || !afmt) { 1415 kfree(enc1); 1416 kfree(vpg); 1417 kfree(afmt); 1418 return NULL; 1419 } 1420 1421 dcn314_dio_stream_encoder_construct(enc1, ctx, ctx->dc_bios, 1422 eng_id, vpg, afmt, 1423 &stream_enc_regs[eng_id], 1424 &se_shift, &se_mask); 1425 1426 return &enc1->base; 1427 } 1428 1429 static struct hpo_dp_stream_encoder *dcn31_hpo_dp_stream_encoder_create( 1430 enum engine_id eng_id, 1431 struct dc_context *ctx) 1432 { 1433 struct dcn31_hpo_dp_stream_encoder *hpo_dp_enc31; 1434 struct vpg *vpg; 1435 struct apg *apg; 1436 uint32_t hpo_dp_inst; 1437 uint32_t vpg_inst; 1438 uint32_t apg_inst; 1439 1440 ASSERT((eng_id >= ENGINE_ID_HPO_DP_0) && (eng_id <= ENGINE_ID_HPO_DP_3)); 1441 hpo_dp_inst = eng_id - ENGINE_ID_HPO_DP_0; 1442 1443 /* Mapping of VPG register blocks to HPO DP block instance: 1444 * VPG[6] -> HPO_DP[0] 1445 * VPG[7] -> HPO_DP[1] 1446 * VPG[8] -> HPO_DP[2] 1447 * VPG[9] -> HPO_DP[3] 1448 */ 1449 vpg_inst = hpo_dp_inst + 6; 1450 1451 /* Mapping of APG register blocks to HPO DP block instance: 1452 * APG[0] -> HPO_DP[0] 1453 * APG[1] -> HPO_DP[1] 1454 * APG[2] -> HPO_DP[2] 1455 * APG[3] -> HPO_DP[3] 1456 */ 1457 apg_inst = hpo_dp_inst; 1458 1459 /* allocate HPO stream encoder and create VPG sub-block */ 1460 hpo_dp_enc31 = kzalloc(sizeof(struct dcn31_hpo_dp_stream_encoder), GFP_KERNEL); 1461 vpg = dcn31_vpg_create(ctx, vpg_inst); 1462 apg = dcn31_apg_create(ctx, apg_inst); 1463 1464 if (!hpo_dp_enc31 || !vpg || !apg) { 1465 kfree(hpo_dp_enc31); 1466 kfree(vpg); 1467 kfree(apg); 1468 return NULL; 1469 } 1470 1471 dcn31_hpo_dp_stream_encoder_construct(hpo_dp_enc31, ctx, ctx->dc_bios, 1472 hpo_dp_inst, eng_id, vpg, apg, 1473 &hpo_dp_stream_enc_regs[hpo_dp_inst], 1474 &hpo_dp_se_shift, &hpo_dp_se_mask); 1475 1476 return &hpo_dp_enc31->base; 1477 } 1478 1479 static struct hpo_dp_link_encoder *dcn31_hpo_dp_link_encoder_create( 1480 uint8_t inst, 1481 struct dc_context *ctx) 1482 { 1483 struct dcn31_hpo_dp_link_encoder *hpo_dp_enc31; 1484 1485 /* allocate HPO link encoder */ 1486 hpo_dp_enc31 = kzalloc(sizeof(struct dcn31_hpo_dp_link_encoder), GFP_KERNEL); 1487 1488 hpo_dp_link_encoder31_construct(hpo_dp_enc31, ctx, inst, 1489 &hpo_dp_link_enc_regs[inst], 1490 &hpo_dp_le_shift, &hpo_dp_le_mask); 1491 1492 return &hpo_dp_enc31->base; 1493 } 1494 1495 static struct dce_hwseq *dcn314_hwseq_create( 1496 struct dc_context *ctx) 1497 { 1498 struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_KERNEL); 1499 1500 if (hws) { 1501 hws->ctx = ctx; 1502 hws->regs = &hwseq_reg; 1503 hws->shifts = &hwseq_shift; 1504 hws->masks = &hwseq_mask; 1505 /* DCN3.1 FPGA Workaround 1506 * Need to enable HPO DP Stream Encoder before setting OTG master enable. 1507 * To do so, move calling function enable_stream_timing to only be done AFTER calling 1508 * function core_link_enable_stream 1509 */ 1510 if (IS_FPGA_MAXIMUS_DC(ctx->dce_environment)) 1511 hws->wa.dp_hpo_and_otg_sequence = true; 1512 } 1513 return hws; 1514 } 1515 static const struct resource_create_funcs res_create_funcs = { 1516 .read_dce_straps = read_dce_straps, 1517 .create_audio = dcn31_create_audio, 1518 .create_stream_encoder = dcn314_stream_encoder_create, 1519 .create_hpo_dp_stream_encoder = dcn31_hpo_dp_stream_encoder_create, 1520 .create_hpo_dp_link_encoder = dcn31_hpo_dp_link_encoder_create, 1521 .create_hwseq = dcn314_hwseq_create, 1522 }; 1523 1524 static const struct resource_create_funcs res_create_maximus_funcs = { 1525 .read_dce_straps = NULL, 1526 .create_audio = NULL, 1527 .create_stream_encoder = NULL, 1528 .create_hpo_dp_stream_encoder = dcn31_hpo_dp_stream_encoder_create, 1529 .create_hpo_dp_link_encoder = dcn31_hpo_dp_link_encoder_create, 1530 .create_hwseq = dcn314_hwseq_create, 1531 }; 1532 1533 static void dcn314_resource_destruct(struct dcn314_resource_pool *pool) 1534 { 1535 unsigned int i; 1536 1537 for (i = 0; i < pool->base.stream_enc_count; i++) { 1538 if (pool->base.stream_enc[i] != NULL) { 1539 if (pool->base.stream_enc[i]->vpg != NULL) { 1540 kfree(DCN30_VPG_FROM_VPG(pool->base.stream_enc[i]->vpg)); 1541 pool->base.stream_enc[i]->vpg = NULL; 1542 } 1543 if (pool->base.stream_enc[i]->afmt != NULL) { 1544 kfree(DCN30_AFMT_FROM_AFMT(pool->base.stream_enc[i]->afmt)); 1545 pool->base.stream_enc[i]->afmt = NULL; 1546 } 1547 kfree(DCN10STRENC_FROM_STRENC(pool->base.stream_enc[i])); 1548 pool->base.stream_enc[i] = NULL; 1549 } 1550 } 1551 1552 for (i = 0; i < pool->base.hpo_dp_stream_enc_count; i++) { 1553 if (pool->base.hpo_dp_stream_enc[i] != NULL) { 1554 if (pool->base.hpo_dp_stream_enc[i]->vpg != NULL) { 1555 kfree(DCN30_VPG_FROM_VPG(pool->base.hpo_dp_stream_enc[i]->vpg)); 1556 pool->base.hpo_dp_stream_enc[i]->vpg = NULL; 1557 } 1558 if (pool->base.hpo_dp_stream_enc[i]->apg != NULL) { 1559 kfree(DCN31_APG_FROM_APG(pool->base.hpo_dp_stream_enc[i]->apg)); 1560 pool->base.hpo_dp_stream_enc[i]->apg = NULL; 1561 } 1562 kfree(DCN3_1_HPO_DP_STREAM_ENC_FROM_HPO_STREAM_ENC(pool->base.hpo_dp_stream_enc[i])); 1563 pool->base.hpo_dp_stream_enc[i] = NULL; 1564 } 1565 } 1566 1567 for (i = 0; i < pool->base.hpo_dp_link_enc_count; i++) { 1568 if (pool->base.hpo_dp_link_enc[i] != NULL) { 1569 kfree(DCN3_1_HPO_DP_LINK_ENC_FROM_HPO_LINK_ENC(pool->base.hpo_dp_link_enc[i])); 1570 pool->base.hpo_dp_link_enc[i] = NULL; 1571 } 1572 } 1573 1574 for (i = 0; i < pool->base.res_cap->num_dsc; i++) { 1575 if (pool->base.dscs[i] != NULL) 1576 dcn20_dsc_destroy(&pool->base.dscs[i]); 1577 } 1578 1579 if (pool->base.mpc != NULL) { 1580 kfree(TO_DCN20_MPC(pool->base.mpc)); 1581 pool->base.mpc = NULL; 1582 } 1583 if (pool->base.hubbub != NULL) { 1584 kfree(pool->base.hubbub); 1585 pool->base.hubbub = NULL; 1586 } 1587 for (i = 0; i < pool->base.pipe_count; i++) { 1588 if (pool->base.dpps[i] != NULL) 1589 dcn31_dpp_destroy(&pool->base.dpps[i]); 1590 1591 if (pool->base.ipps[i] != NULL) 1592 pool->base.ipps[i]->funcs->ipp_destroy(&pool->base.ipps[i]); 1593 1594 if (pool->base.hubps[i] != NULL) { 1595 kfree(TO_DCN20_HUBP(pool->base.hubps[i])); 1596 pool->base.hubps[i] = NULL; 1597 } 1598 1599 if (pool->base.irqs != NULL) 1600 dal_irq_service_destroy(&pool->base.irqs); 1601 } 1602 1603 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { 1604 if (pool->base.engines[i] != NULL) 1605 dce110_engine_destroy(&pool->base.engines[i]); 1606 if (pool->base.hw_i2cs[i] != NULL) { 1607 kfree(pool->base.hw_i2cs[i]); 1608 pool->base.hw_i2cs[i] = NULL; 1609 } 1610 if (pool->base.sw_i2cs[i] != NULL) { 1611 kfree(pool->base.sw_i2cs[i]); 1612 pool->base.sw_i2cs[i] = NULL; 1613 } 1614 } 1615 1616 for (i = 0; i < pool->base.res_cap->num_opp; i++) { 1617 if (pool->base.opps[i] != NULL) 1618 pool->base.opps[i]->funcs->opp_destroy(&pool->base.opps[i]); 1619 } 1620 1621 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { 1622 if (pool->base.timing_generators[i] != NULL) { 1623 kfree(DCN10TG_FROM_TG(pool->base.timing_generators[i])); 1624 pool->base.timing_generators[i] = NULL; 1625 } 1626 } 1627 1628 for (i = 0; i < pool->base.res_cap->num_dwb; i++) { 1629 if (pool->base.dwbc[i] != NULL) { 1630 kfree(TO_DCN30_DWBC(pool->base.dwbc[i])); 1631 pool->base.dwbc[i] = NULL; 1632 } 1633 if (pool->base.mcif_wb[i] != NULL) { 1634 kfree(TO_DCN30_MMHUBBUB(pool->base.mcif_wb[i])); 1635 pool->base.mcif_wb[i] = NULL; 1636 } 1637 } 1638 1639 for (i = 0; i < pool->base.audio_count; i++) { 1640 if (pool->base.audios[i]) 1641 dce_aud_destroy(&pool->base.audios[i]); 1642 } 1643 1644 for (i = 0; i < pool->base.clk_src_count; i++) { 1645 if (pool->base.clock_sources[i] != NULL) { 1646 dcn20_clock_source_destroy(&pool->base.clock_sources[i]); 1647 pool->base.clock_sources[i] = NULL; 1648 } 1649 } 1650 1651 for (i = 0; i < pool->base.res_cap->num_mpc_3dlut; i++) { 1652 if (pool->base.mpc_lut[i] != NULL) { 1653 dc_3dlut_func_release(pool->base.mpc_lut[i]); 1654 pool->base.mpc_lut[i] = NULL; 1655 } 1656 if (pool->base.mpc_shaper[i] != NULL) { 1657 dc_transfer_func_release(pool->base.mpc_shaper[i]); 1658 pool->base.mpc_shaper[i] = NULL; 1659 } 1660 } 1661 1662 if (pool->base.dp_clock_source != NULL) { 1663 dcn20_clock_source_destroy(&pool->base.dp_clock_source); 1664 pool->base.dp_clock_source = NULL; 1665 } 1666 1667 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { 1668 if (pool->base.multiple_abms[i] != NULL) 1669 dce_abm_destroy(&pool->base.multiple_abms[i]); 1670 } 1671 1672 if (pool->base.psr != NULL) 1673 dmub_psr_destroy(&pool->base.psr); 1674 1675 if (pool->base.dccg != NULL) 1676 dcn_dccg_destroy(&pool->base.dccg); 1677 } 1678 1679 static struct hubp *dcn31_hubp_create( 1680 struct dc_context *ctx, 1681 uint32_t inst) 1682 { 1683 struct dcn20_hubp *hubp2 = 1684 kzalloc(sizeof(struct dcn20_hubp), GFP_KERNEL); 1685 1686 if (!hubp2) 1687 return NULL; 1688 1689 if (hubp31_construct(hubp2, ctx, inst, 1690 &hubp_regs[inst], &hubp_shift, &hubp_mask)) 1691 return &hubp2->base; 1692 1693 BREAK_TO_DEBUGGER(); 1694 kfree(hubp2); 1695 return NULL; 1696 } 1697 1698 static bool dcn31_dwbc_create(struct dc_context *ctx, struct resource_pool *pool) 1699 { 1700 int i; 1701 uint32_t pipe_count = pool->res_cap->num_dwb; 1702 1703 for (i = 0; i < pipe_count; i++) { 1704 struct dcn30_dwbc *dwbc30 = kzalloc(sizeof(struct dcn30_dwbc), 1705 GFP_KERNEL); 1706 1707 if (!dwbc30) { 1708 dm_error("DC: failed to create dwbc30!\n"); 1709 return false; 1710 } 1711 1712 dcn30_dwbc_construct(dwbc30, ctx, 1713 &dwbc30_regs[i], 1714 &dwbc30_shift, 1715 &dwbc30_mask, 1716 i); 1717 1718 pool->dwbc[i] = &dwbc30->base; 1719 } 1720 return true; 1721 } 1722 1723 static bool dcn31_mmhubbub_create(struct dc_context *ctx, struct resource_pool *pool) 1724 { 1725 int i; 1726 uint32_t pipe_count = pool->res_cap->num_dwb; 1727 1728 for (i = 0; i < pipe_count; i++) { 1729 struct dcn30_mmhubbub *mcif_wb30 = kzalloc(sizeof(struct dcn30_mmhubbub), 1730 GFP_KERNEL); 1731 1732 if (!mcif_wb30) { 1733 dm_error("DC: failed to create mcif_wb30!\n"); 1734 return false; 1735 } 1736 1737 dcn30_mmhubbub_construct(mcif_wb30, ctx, 1738 &mcif_wb30_regs[i], 1739 &mcif_wb30_shift, 1740 &mcif_wb30_mask, 1741 i); 1742 1743 pool->mcif_wb[i] = &mcif_wb30->base; 1744 } 1745 return true; 1746 } 1747 1748 static struct display_stream_compressor *dcn314_dsc_create( 1749 struct dc_context *ctx, uint32_t inst) 1750 { 1751 struct dcn20_dsc *dsc = 1752 kzalloc(sizeof(struct dcn20_dsc), GFP_KERNEL); 1753 1754 if (!dsc) { 1755 BREAK_TO_DEBUGGER(); 1756 return NULL; 1757 } 1758 1759 dsc2_construct(dsc, ctx, inst, &dsc_regs[inst], &dsc_shift, &dsc_mask); 1760 return &dsc->base; 1761 } 1762 1763 static void dcn314_destroy_resource_pool(struct resource_pool **pool) 1764 { 1765 struct dcn314_resource_pool *dcn314_pool = TO_DCN314_RES_POOL(*pool); 1766 1767 dcn314_resource_destruct(dcn314_pool); 1768 kfree(dcn314_pool); 1769 *pool = NULL; 1770 } 1771 1772 static struct clock_source *dcn31_clock_source_create( 1773 struct dc_context *ctx, 1774 struct dc_bios *bios, 1775 enum clock_source_id id, 1776 const struct dce110_clk_src_regs *regs, 1777 bool dp_clk_src) 1778 { 1779 struct dce110_clk_src *clk_src = 1780 kzalloc(sizeof(struct dce110_clk_src), GFP_KERNEL); 1781 1782 if (!clk_src) 1783 return NULL; 1784 1785 if (dcn3_clk_src_construct(clk_src, ctx, bios, id, 1786 regs, &cs_shift, &cs_mask)) { 1787 clk_src->base.dp_clk_src = dp_clk_src; 1788 return &clk_src->base; 1789 } 1790 1791 BREAK_TO_DEBUGGER(); 1792 return NULL; 1793 } 1794 1795 static bool is_dual_plane(enum surface_pixel_format format) 1796 { 1797 return format >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN || format == SURFACE_PIXEL_FORMAT_GRPH_RGBE_ALPHA; 1798 } 1799 1800 static int dcn314_populate_dml_pipes_from_context( 1801 struct dc *dc, struct dc_state *context, 1802 display_e2e_pipe_params_st *pipes, 1803 bool fast_validate) 1804 { 1805 int i, pipe_cnt; 1806 struct resource_context *res_ctx = &context->res_ctx; 1807 struct pipe_ctx *pipe; 1808 bool upscaled = false; 1809 1810 dcn20_populate_dml_pipes_from_context(dc, context, pipes, fast_validate); 1811 1812 for (i = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) { 1813 struct dc_crtc_timing *timing; 1814 1815 if (!res_ctx->pipe_ctx[i].stream) 1816 continue; 1817 pipe = &res_ctx->pipe_ctx[i]; 1818 timing = &pipe->stream->timing; 1819 1820 if (dc_extended_blank_supported(dc) && pipe->stream->adjust.v_total_max == pipe->stream->adjust.v_total_min 1821 && pipe->stream->adjust.v_total_min > timing->v_total) 1822 pipes[pipe_cnt].pipe.dest.vtotal = pipe->stream->adjust.v_total_min; 1823 1824 if (pipe->plane_state && 1825 (pipe->plane_state->src_rect.height < pipe->plane_state->dst_rect.height || 1826 pipe->plane_state->src_rect.width < pipe->plane_state->dst_rect.width)) 1827 upscaled = true; 1828 1829 /* 1830 * Immediate flip can be set dynamically after enabling the plane. 1831 * We need to require support for immediate flip or underflow can be 1832 * intermittently experienced depending on peak b/w requirements. 1833 */ 1834 pipes[pipe_cnt].pipe.src.immediate_flip = true; 1835 1836 pipes[pipe_cnt].pipe.src.unbounded_req_mode = false; 1837 pipes[pipe_cnt].pipe.src.hostvm = dc->res_pool->hubbub->riommu_active; 1838 pipes[pipe_cnt].pipe.src.gpuvm = true; 1839 pipes[pipe_cnt].pipe.src.dcc_fraction_of_zs_req_luma = 0; 1840 pipes[pipe_cnt].pipe.src.dcc_fraction_of_zs_req_chroma = 0; 1841 pipes[pipe_cnt].pipe.dest.vfront_porch = timing->v_front_porch; 1842 pipes[pipe_cnt].pipe.src.dcc_rate = 3; 1843 pipes[pipe_cnt].dout.dsc_input_bpc = 0; 1844 1845 if (pipes[pipe_cnt].dout.dsc_enable) { 1846 switch (timing->display_color_depth) { 1847 case COLOR_DEPTH_888: 1848 pipes[pipe_cnt].dout.dsc_input_bpc = 8; 1849 break; 1850 case COLOR_DEPTH_101010: 1851 pipes[pipe_cnt].dout.dsc_input_bpc = 10; 1852 break; 1853 case COLOR_DEPTH_121212: 1854 pipes[pipe_cnt].dout.dsc_input_bpc = 12; 1855 break; 1856 default: 1857 ASSERT(0); 1858 break; 1859 } 1860 } 1861 1862 pipe_cnt++; 1863 } 1864 context->bw_ctx.dml.ip.det_buffer_size_kbytes = DCN3_14_DEFAULT_DET_SIZE; 1865 1866 dc->config.enable_4to1MPC = false; 1867 if (pipe_cnt == 1 && pipe->plane_state && !dc->debug.disable_z9_mpc) { 1868 if (is_dual_plane(pipe->plane_state->format) 1869 && pipe->plane_state->src_rect.width <= 1920 && pipe->plane_state->src_rect.height <= 1080) { 1870 dc->config.enable_4to1MPC = true; 1871 } else if (!is_dual_plane(pipe->plane_state->format) && pipe->plane_state->src_rect.width <= 5120) { 1872 /* Limit to 5k max to avoid forced pipe split when there is not enough detile for swath */ 1873 context->bw_ctx.dml.ip.det_buffer_size_kbytes = 192; 1874 pipes[0].pipe.src.unbounded_req_mode = true; 1875 } 1876 } else if (context->stream_count >= dc->debug.crb_alloc_policy_min_disp_count 1877 && dc->debug.crb_alloc_policy > DET_SIZE_DEFAULT) { 1878 context->bw_ctx.dml.ip.det_buffer_size_kbytes = dc->debug.crb_alloc_policy * 64; 1879 } else if (context->stream_count >= 3 && upscaled) { 1880 context->bw_ctx.dml.ip.det_buffer_size_kbytes = 192; 1881 } 1882 1883 for (i = 0; i < dc->res_pool->pipe_count; i++) { 1884 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; 1885 1886 if (!pipe->stream) 1887 continue; 1888 1889 if (pipe->stream->signal == SIGNAL_TYPE_EDP && dc->debug.seamless_boot_odm_combine && 1890 pipe->stream->apply_seamless_boot_optimization) { 1891 1892 if (pipe->stream->apply_boot_odm_mode == dm_odm_combine_policy_2to1) { 1893 context->bw_ctx.dml.vba.ODMCombinePolicy = dm_odm_combine_policy_2to1; 1894 break; 1895 } 1896 } 1897 } 1898 1899 return pipe_cnt; 1900 } 1901 1902 static struct dc_cap_funcs cap_funcs = { 1903 .get_dcc_compression_cap = dcn20_get_dcc_compression_cap 1904 }; 1905 1906 static void dcn314_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params) 1907 { 1908 struct clk_limit_table *clk_table = &bw_params->clk_table; 1909 struct _vcs_dpi_voltage_scaling_st *clock_tmp = dcn3_14_soc._clock_tmp; 1910 unsigned int i, closest_clk_lvl; 1911 int max_dispclk_mhz = 0, max_dppclk_mhz = 0; 1912 int j; 1913 1914 // Default clock levels are used for diags, which may lead to overclocking. 1915 if (!IS_DIAG_DC(dc->ctx->dce_environment)) { 1916 1917 dcn3_14_ip.max_num_otg = dc->res_pool->res_cap->num_timing_generator; 1918 dcn3_14_ip.max_num_dpp = dc->res_pool->pipe_count; 1919 dcn3_14_soc.num_chans = bw_params->num_channels; 1920 1921 ASSERT(clk_table->num_entries); 1922 1923 /* Prepass to find max clocks independent of voltage level. */ 1924 for (i = 0; i < clk_table->num_entries; ++i) { 1925 if (clk_table->entries[i].dispclk_mhz > max_dispclk_mhz) 1926 max_dispclk_mhz = clk_table->entries[i].dispclk_mhz; 1927 if (clk_table->entries[i].dppclk_mhz > max_dppclk_mhz) 1928 max_dppclk_mhz = clk_table->entries[i].dppclk_mhz; 1929 } 1930 1931 for (i = 0; i < clk_table->num_entries; i++) { 1932 /* loop backwards*/ 1933 for (closest_clk_lvl = 0, j = dcn3_14_soc.num_states - 1; j >= 0; j--) { 1934 if ((unsigned int) dcn3_14_soc.clock_limits[j].dcfclk_mhz <= clk_table->entries[i].dcfclk_mhz) { 1935 closest_clk_lvl = j; 1936 break; 1937 } 1938 } 1939 if (clk_table->num_entries == 1) { 1940 /*smu gives one DPM level, let's take the highest one*/ 1941 closest_clk_lvl = dcn3_14_soc.num_states - 1; 1942 } 1943 1944 clock_tmp[i].state = i; 1945 1946 /* Clocks dependent on voltage level. */ 1947 clock_tmp[i].dcfclk_mhz = clk_table->entries[i].dcfclk_mhz; 1948 if (clk_table->num_entries == 1 && 1949 clock_tmp[i].dcfclk_mhz < dcn3_14_soc.clock_limits[closest_clk_lvl].dcfclk_mhz) { 1950 /*SMU fix not released yet*/ 1951 clock_tmp[i].dcfclk_mhz = dcn3_14_soc.clock_limits[closest_clk_lvl].dcfclk_mhz; 1952 } 1953 clock_tmp[i].fabricclk_mhz = clk_table->entries[i].fclk_mhz; 1954 clock_tmp[i].socclk_mhz = clk_table->entries[i].socclk_mhz; 1955 1956 if (clk_table->entries[i].memclk_mhz && clk_table->entries[i].wck_ratio) 1957 clock_tmp[i].dram_speed_mts = clk_table->entries[i].memclk_mhz * 2 * clk_table->entries[i].wck_ratio; 1958 1959 /* Clocks independent of voltage level. */ 1960 clock_tmp[i].dispclk_mhz = max_dispclk_mhz ? max_dispclk_mhz : 1961 dcn3_14_soc.clock_limits[closest_clk_lvl].dispclk_mhz; 1962 1963 clock_tmp[i].dppclk_mhz = max_dppclk_mhz ? max_dppclk_mhz : 1964 dcn3_14_soc.clock_limits[closest_clk_lvl].dppclk_mhz; 1965 1966 clock_tmp[i].dram_bw_per_chan_gbps = dcn3_14_soc.clock_limits[closest_clk_lvl].dram_bw_per_chan_gbps; 1967 clock_tmp[i].dscclk_mhz = dcn3_14_soc.clock_limits[closest_clk_lvl].dscclk_mhz; 1968 clock_tmp[i].dtbclk_mhz = dcn3_14_soc.clock_limits[closest_clk_lvl].dtbclk_mhz; 1969 clock_tmp[i].phyclk_d18_mhz = dcn3_14_soc.clock_limits[closest_clk_lvl].phyclk_d18_mhz; 1970 clock_tmp[i].phyclk_mhz = dcn3_14_soc.clock_limits[closest_clk_lvl].phyclk_mhz; 1971 } 1972 for (i = 0; i < clk_table->num_entries; i++) 1973 dcn3_14_soc.clock_limits[i] = clock_tmp[i]; 1974 if (clk_table->num_entries) 1975 dcn3_14_soc.num_states = clk_table->num_entries; 1976 } 1977 1978 if (max_dispclk_mhz) { 1979 dcn3_14_soc.dispclk_dppclk_vco_speed_mhz = max_dispclk_mhz * 2; 1980 dc->dml.soc.dispclk_dppclk_vco_speed_mhz = max_dispclk_mhz * 2; 1981 } 1982 1983 if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) 1984 dml_init_instance(&dc->dml, &dcn3_14_soc, &dcn3_14_ip, DML_PROJECT_DCN31); 1985 else 1986 dml_init_instance(&dc->dml, &dcn3_14_soc, &dcn3_14_ip, DML_PROJECT_DCN31_FPGA); 1987 } 1988 1989 static struct resource_funcs dcn314_res_pool_funcs = { 1990 .destroy = dcn314_destroy_resource_pool, 1991 .link_enc_create = dcn31_link_encoder_create, 1992 .link_enc_create_minimal = dcn31_link_enc_create_minimal, 1993 .link_encs_assign = link_enc_cfg_link_encs_assign, 1994 .link_enc_unassign = link_enc_cfg_link_enc_unassign, 1995 .panel_cntl_create = dcn31_panel_cntl_create, 1996 .validate_bandwidth = dcn31_validate_bandwidth, 1997 .calculate_wm_and_dlg = dcn31_calculate_wm_and_dlg, 1998 .update_soc_for_wm_a = dcn31_update_soc_for_wm_a, 1999 .populate_dml_pipes = dcn314_populate_dml_pipes_from_context, 2000 .acquire_idle_pipe_for_layer = dcn20_acquire_idle_pipe_for_layer, 2001 .add_stream_to_ctx = dcn30_add_stream_to_ctx, 2002 .add_dsc_to_stream_resource = dcn20_add_dsc_to_stream_resource, 2003 .remove_stream_from_ctx = dcn20_remove_stream_from_ctx, 2004 .populate_dml_writeback_from_context = dcn30_populate_dml_writeback_from_context, 2005 .set_mcif_arb_params = dcn30_set_mcif_arb_params, 2006 .find_first_free_match_stream_enc_for_link = dcn10_find_first_free_match_stream_enc_for_link, 2007 .acquire_post_bldn_3dlut = dcn30_acquire_post_bldn_3dlut, 2008 .release_post_bldn_3dlut = dcn30_release_post_bldn_3dlut, 2009 .update_bw_bounding_box = dcn314_update_bw_bounding_box, 2010 .patch_unknown_plane_state = dcn20_patch_unknown_plane_state, 2011 }; 2012 2013 static struct clock_source *dcn30_clock_source_create( 2014 struct dc_context *ctx, 2015 struct dc_bios *bios, 2016 enum clock_source_id id, 2017 const struct dce110_clk_src_regs *regs, 2018 bool dp_clk_src) 2019 { 2020 struct dce110_clk_src *clk_src = 2021 kzalloc(sizeof(struct dce110_clk_src), GFP_KERNEL); 2022 2023 if (!clk_src) 2024 return NULL; 2025 2026 if (dcn31_clk_src_construct(clk_src, ctx, bios, id, 2027 regs, &cs_shift, &cs_mask)) { 2028 clk_src->base.dp_clk_src = dp_clk_src; 2029 return &clk_src->base; 2030 } 2031 2032 BREAK_TO_DEBUGGER(); 2033 return NULL; 2034 } 2035 2036 static bool dcn314_resource_construct( 2037 uint8_t num_virtual_links, 2038 struct dc *dc, 2039 struct dcn314_resource_pool *pool) 2040 { 2041 int i; 2042 struct dc_context *ctx = dc->ctx; 2043 struct irq_service_init_data init_data; 2044 2045 ctx->dc_bios->regs = &bios_regs; 2046 2047 pool->base.res_cap = &res_cap_dcn314; 2048 pool->base.funcs = &dcn314_res_pool_funcs; 2049 2050 /************************************************* 2051 * Resource + asic cap harcoding * 2052 *************************************************/ 2053 pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE; 2054 pool->base.pipe_count = pool->base.res_cap->num_timing_generator; 2055 pool->base.mpcc_count = pool->base.res_cap->num_timing_generator; 2056 dc->caps.max_downscale_ratio = 600; 2057 dc->caps.i2c_speed_in_khz = 100; 2058 dc->caps.i2c_speed_in_khz_hdcp = 100; 2059 dc->caps.max_cursor_size = 256; 2060 dc->caps.min_horizontal_blanking_period = 80; 2061 dc->caps.dmdata_alloc_size = 2048; 2062 dc->caps.max_slave_planes = 2; 2063 dc->caps.max_slave_yuv_planes = 2; 2064 dc->caps.max_slave_rgb_planes = 2; 2065 dc->caps.post_blend_color_processing = true; 2066 dc->caps.force_dp_tps4_for_cp2520 = true; 2067 dc->caps.dp_hpo = true; 2068 dc->caps.edp_dsc_support = true; 2069 dc->caps.extended_aux_timeout_support = true; 2070 dc->caps.dmcub_support = true; 2071 dc->caps.is_apu = true; 2072 dc->caps.seamless_odm = true; 2073 2074 dc->caps.zstate_support = true; 2075 2076 /* Color pipeline capabilities */ 2077 dc->caps.color.dpp.dcn_arch = 1; 2078 dc->caps.color.dpp.input_lut_shared = 0; 2079 dc->caps.color.dpp.icsc = 1; 2080 dc->caps.color.dpp.dgam_ram = 0; // must use gamma_corr 2081 dc->caps.color.dpp.dgam_rom_caps.srgb = 1; 2082 dc->caps.color.dpp.dgam_rom_caps.bt2020 = 1; 2083 dc->caps.color.dpp.dgam_rom_caps.gamma2_2 = 1; 2084 dc->caps.color.dpp.dgam_rom_caps.pq = 1; 2085 dc->caps.color.dpp.dgam_rom_caps.hlg = 1; 2086 dc->caps.color.dpp.post_csc = 1; 2087 dc->caps.color.dpp.gamma_corr = 1; 2088 dc->caps.color.dpp.dgam_rom_for_yuv = 0; 2089 2090 dc->caps.color.dpp.hw_3d_lut = 1; 2091 dc->caps.color.dpp.ogam_ram = 1; 2092 // no OGAM ROM on DCN301 2093 dc->caps.color.dpp.ogam_rom_caps.srgb = 0; 2094 dc->caps.color.dpp.ogam_rom_caps.bt2020 = 0; 2095 dc->caps.color.dpp.ogam_rom_caps.gamma2_2 = 0; 2096 dc->caps.color.dpp.ogam_rom_caps.pq = 0; 2097 dc->caps.color.dpp.ogam_rom_caps.hlg = 0; 2098 dc->caps.color.dpp.ocsc = 0; 2099 2100 dc->caps.color.mpc.gamut_remap = 1; 2101 dc->caps.color.mpc.num_3dluts = pool->base.res_cap->num_mpc_3dlut; //2 2102 dc->caps.color.mpc.ogam_ram = 1; 2103 dc->caps.color.mpc.ogam_rom_caps.srgb = 0; 2104 dc->caps.color.mpc.ogam_rom_caps.bt2020 = 0; 2105 dc->caps.color.mpc.ogam_rom_caps.gamma2_2 = 0; 2106 dc->caps.color.mpc.ogam_rom_caps.pq = 0; 2107 dc->caps.color.mpc.ogam_rom_caps.hlg = 0; 2108 dc->caps.color.mpc.ocsc = 1; 2109 2110 /* Use pipe context based otg sync logic */ 2111 dc->config.use_pipe_ctx_sync_logic = true; 2112 2113 /* read VBIOS LTTPR caps */ 2114 { 2115 if (ctx->dc_bios->funcs->get_lttpr_caps) { 2116 enum bp_result bp_query_result; 2117 uint8_t is_vbios_lttpr_enable = 0; 2118 2119 bp_query_result = ctx->dc_bios->funcs->get_lttpr_caps(ctx->dc_bios, &is_vbios_lttpr_enable); 2120 dc->caps.vbios_lttpr_enable = (bp_query_result == BP_RESULT_OK) && !!is_vbios_lttpr_enable; 2121 } 2122 2123 /* interop bit is implicit */ 2124 { 2125 dc->caps.vbios_lttpr_aware = true; 2126 } 2127 } 2128 2129 if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV) 2130 dc->debug = debug_defaults_drv; 2131 else if (dc->ctx->dce_environment == DCE_ENV_FPGA_MAXIMUS) 2132 dc->debug = debug_defaults_diags; 2133 else 2134 dc->debug = debug_defaults_diags; 2135 // Init the vm_helper 2136 if (dc->vm_helper) 2137 vm_helper_init(dc->vm_helper, 16); 2138 2139 /************************************************* 2140 * Create resources * 2141 *************************************************/ 2142 2143 /* Clock Sources for Pixel Clock*/ 2144 pool->base.clock_sources[DCN31_CLK_SRC_PLL0] = 2145 dcn30_clock_source_create(ctx, ctx->dc_bios, 2146 CLOCK_SOURCE_COMBO_PHY_PLL0, 2147 &clk_src_regs[0], false); 2148 pool->base.clock_sources[DCN31_CLK_SRC_PLL1] = 2149 dcn30_clock_source_create(ctx, ctx->dc_bios, 2150 CLOCK_SOURCE_COMBO_PHY_PLL1, 2151 &clk_src_regs[1], false); 2152 pool->base.clock_sources[DCN31_CLK_SRC_PLL2] = 2153 dcn30_clock_source_create(ctx, ctx->dc_bios, 2154 CLOCK_SOURCE_COMBO_PHY_PLL2, 2155 &clk_src_regs[2], false); 2156 pool->base.clock_sources[DCN31_CLK_SRC_PLL3] = 2157 dcn30_clock_source_create(ctx, ctx->dc_bios, 2158 CLOCK_SOURCE_COMBO_PHY_PLL3, 2159 &clk_src_regs[3], false); 2160 pool->base.clock_sources[DCN31_CLK_SRC_PLL4] = 2161 dcn30_clock_source_create(ctx, ctx->dc_bios, 2162 CLOCK_SOURCE_COMBO_PHY_PLL4, 2163 &clk_src_regs[4], false); 2164 2165 pool->base.clk_src_count = DCN30_CLK_SRC_TOTAL; 2166 2167 /* todo: not reuse phy_pll registers */ 2168 pool->base.dp_clock_source = 2169 dcn31_clock_source_create(ctx, ctx->dc_bios, 2170 CLOCK_SOURCE_ID_DP_DTO, 2171 &clk_src_regs[0], true); 2172 2173 for (i = 0; i < pool->base.clk_src_count; i++) { 2174 if (pool->base.clock_sources[i] == NULL) { 2175 dm_error("DC: failed to create clock sources!\n"); 2176 BREAK_TO_DEBUGGER(); 2177 goto create_fail; 2178 } 2179 } 2180 2181 pool->base.dccg = dccg314_create(ctx, &dccg_regs, &dccg_shift, &dccg_mask); 2182 if (pool->base.dccg == NULL) { 2183 dm_error("DC: failed to create dccg!\n"); 2184 BREAK_TO_DEBUGGER(); 2185 goto create_fail; 2186 } 2187 2188 init_data.ctx = dc->ctx; 2189 pool->base.irqs = dal_irq_service_dcn314_create(&init_data); 2190 if (!pool->base.irqs) 2191 goto create_fail; 2192 2193 /* HUBBUB */ 2194 pool->base.hubbub = dcn31_hubbub_create(ctx); 2195 if (pool->base.hubbub == NULL) { 2196 BREAK_TO_DEBUGGER(); 2197 dm_error("DC: failed to create hubbub!\n"); 2198 goto create_fail; 2199 } 2200 2201 /* HUBPs, DPPs, OPPs and TGs */ 2202 for (i = 0; i < pool->base.pipe_count; i++) { 2203 pool->base.hubps[i] = dcn31_hubp_create(ctx, i); 2204 if (pool->base.hubps[i] == NULL) { 2205 BREAK_TO_DEBUGGER(); 2206 dm_error( 2207 "DC: failed to create hubps!\n"); 2208 goto create_fail; 2209 } 2210 2211 pool->base.dpps[i] = dcn31_dpp_create(ctx, i); 2212 if (pool->base.dpps[i] == NULL) { 2213 BREAK_TO_DEBUGGER(); 2214 dm_error( 2215 "DC: failed to create dpps!\n"); 2216 goto create_fail; 2217 } 2218 } 2219 2220 for (i = 0; i < pool->base.res_cap->num_opp; i++) { 2221 pool->base.opps[i] = dcn31_opp_create(ctx, i); 2222 if (pool->base.opps[i] == NULL) { 2223 BREAK_TO_DEBUGGER(); 2224 dm_error( 2225 "DC: failed to create output pixel processor!\n"); 2226 goto create_fail; 2227 } 2228 } 2229 2230 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { 2231 pool->base.timing_generators[i] = dcn31_timing_generator_create( 2232 ctx, i); 2233 if (pool->base.timing_generators[i] == NULL) { 2234 BREAK_TO_DEBUGGER(); 2235 dm_error("DC: failed to create tg!\n"); 2236 goto create_fail; 2237 } 2238 } 2239 pool->base.timing_generator_count = i; 2240 2241 /* PSR */ 2242 pool->base.psr = dmub_psr_create(ctx); 2243 if (pool->base.psr == NULL) { 2244 dm_error("DC: failed to create psr obj!\n"); 2245 BREAK_TO_DEBUGGER(); 2246 goto create_fail; 2247 } 2248 2249 /* ABM */ 2250 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { 2251 pool->base.multiple_abms[i] = dmub_abm_create(ctx, 2252 &abm_regs[i], 2253 &abm_shift, 2254 &abm_mask); 2255 if (pool->base.multiple_abms[i] == NULL) { 2256 dm_error("DC: failed to create abm for pipe %d!\n", i); 2257 BREAK_TO_DEBUGGER(); 2258 goto create_fail; 2259 } 2260 } 2261 2262 /* MPC and DSC */ 2263 pool->base.mpc = dcn31_mpc_create(ctx, pool->base.mpcc_count, pool->base.res_cap->num_mpc_3dlut); 2264 if (pool->base.mpc == NULL) { 2265 BREAK_TO_DEBUGGER(); 2266 dm_error("DC: failed to create mpc!\n"); 2267 goto create_fail; 2268 } 2269 2270 for (i = 0; i < pool->base.res_cap->num_dsc; i++) { 2271 pool->base.dscs[i] = dcn314_dsc_create(ctx, i); 2272 if (pool->base.dscs[i] == NULL) { 2273 BREAK_TO_DEBUGGER(); 2274 dm_error("DC: failed to create display stream compressor %d!\n", i); 2275 goto create_fail; 2276 } 2277 } 2278 2279 /* DWB and MMHUBBUB */ 2280 if (!dcn31_dwbc_create(ctx, &pool->base)) { 2281 BREAK_TO_DEBUGGER(); 2282 dm_error("DC: failed to create dwbc!\n"); 2283 goto create_fail; 2284 } 2285 2286 if (!dcn31_mmhubbub_create(ctx, &pool->base)) { 2287 BREAK_TO_DEBUGGER(); 2288 dm_error("DC: failed to create mcif_wb!\n"); 2289 goto create_fail; 2290 } 2291 2292 /* AUX and I2C */ 2293 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { 2294 pool->base.engines[i] = dcn31_aux_engine_create(ctx, i); 2295 if (pool->base.engines[i] == NULL) { 2296 BREAK_TO_DEBUGGER(); 2297 dm_error( 2298 "DC:failed to create aux engine!!\n"); 2299 goto create_fail; 2300 } 2301 pool->base.hw_i2cs[i] = dcn31_i2c_hw_create(ctx, i); 2302 if (pool->base.hw_i2cs[i] == NULL) { 2303 BREAK_TO_DEBUGGER(); 2304 dm_error( 2305 "DC:failed to create hw i2c!!\n"); 2306 goto create_fail; 2307 } 2308 pool->base.sw_i2cs[i] = NULL; 2309 } 2310 2311 /* DCN314 has 4 DPIA */ 2312 pool->base.usb4_dpia_count = 4; 2313 2314 /* Audio, Stream Encoders including HPO and virtual, MPC 3D LUTs */ 2315 if (!resource_construct(num_virtual_links, dc, &pool->base, 2316 (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment) ? 2317 &res_create_funcs : &res_create_maximus_funcs))) 2318 goto create_fail; 2319 2320 /* HW Sequencer and Plane caps */ 2321 dcn314_hw_sequencer_construct(dc); 2322 2323 dc->caps.max_planes = pool->base.pipe_count; 2324 2325 for (i = 0; i < dc->caps.max_planes; ++i) 2326 dc->caps.planes[i] = plane_cap; 2327 2328 dc->cap_funcs = cap_funcs; 2329 2330 dc->dcn_ip->max_num_dpp = dcn3_14_ip.max_num_dpp; 2331 2332 return true; 2333 2334 create_fail: 2335 2336 dcn314_resource_destruct(pool); 2337 2338 return false; 2339 } 2340 2341 struct resource_pool *dcn314_create_resource_pool( 2342 const struct dc_init_data *init_data, 2343 struct dc *dc) 2344 { 2345 struct dcn314_resource_pool *pool = 2346 kzalloc(sizeof(struct dcn314_resource_pool), GFP_KERNEL); 2347 2348 if (!pool) 2349 return NULL; 2350 2351 if (dcn314_resource_construct(init_data->num_virtual_links, dc, pool)) 2352 return &pool->base; 2353 2354 BREAK_TO_DEBUGGER(); 2355 kfree(pool); 2356 return NULL; 2357 } 2358