1 // SPDX-License-Identifier: MIT 2 /* 3 * Copyright 2022 Advanced Micro Devices, Inc. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 * 23 * Authors: AMD 24 * 25 */ 26 27 28 #include "dm_services.h" 29 #include "dc.h" 30 31 #include "dcn31/dcn31_init.h" 32 #include "dcn314/dcn314_init.h" 33 34 #include "resource.h" 35 #include "include/irq_service_interface.h" 36 #include "dcn314_resource.h" 37 38 #include "dcn20/dcn20_resource.h" 39 #include "dcn30/dcn30_resource.h" 40 #include "dcn31/dcn31_resource.h" 41 42 #include "dcn10/dcn10_ipp.h" 43 #include "dcn30/dcn30_hubbub.h" 44 #include "dcn31/dcn31_hubbub.h" 45 #include "dcn30/dcn30_mpc.h" 46 #include "dcn31/dcn31_hubp.h" 47 #include "irq/dcn31/irq_service_dcn31.h" 48 #include "irq/dcn314/irq_service_dcn314.h" 49 #include "dcn30/dcn30_dpp.h" 50 #include "dcn314/dcn314_optc.h" 51 #include "dcn20/dcn20_hwseq.h" 52 #include "dcn30/dcn30_hwseq.h" 53 #include "dce110/dce110_hw_sequencer.h" 54 #include "dcn30/dcn30_opp.h" 55 #include "dcn20/dcn20_dsc.h" 56 #include "dcn30/dcn30_vpg.h" 57 #include "dcn30/dcn30_afmt.h" 58 #include "dcn31/dcn31_dio_link_encoder.h" 59 #include "dcn314/dcn314_dio_stream_encoder.h" 60 #include "dcn31/dcn31_hpo_dp_stream_encoder.h" 61 #include "dcn31/dcn31_hpo_dp_link_encoder.h" 62 #include "dcn31/dcn31_apg.h" 63 #include "dcn31/dcn31_vpg.h" 64 #include "dcn31/dcn31_afmt.h" 65 #include "dce/dce_clock_source.h" 66 #include "dce/dce_audio.h" 67 #include "dce/dce_hwseq.h" 68 #include "clk_mgr.h" 69 #include "virtual/virtual_stream_encoder.h" 70 #include "dce110/dce110_resource.h" 71 #include "dml/display_mode_vba.h" 72 #include "dml/dcn31/dcn31_fpu.h" 73 #include "dml/dcn314/dcn314_fpu.h" 74 #include "dcn314/dcn314_dccg.h" 75 #include "dcn10/dcn10_resource.h" 76 #include "dcn31/dcn31_panel_cntl.h" 77 #include "dcn314/dcn314_hwseq.h" 78 79 #include "dcn30/dcn30_dwb.h" 80 #include "dcn30/dcn30_mmhubbub.h" 81 82 #include "dcn/dcn_3_1_4_offset.h" 83 #include "dcn/dcn_3_1_4_sh_mask.h" 84 #include "dpcs/dpcs_3_1_4_offset.h" 85 #include "dpcs/dpcs_3_1_4_sh_mask.h" 86 87 #define DCHUBBUB_DEBUG_CTRL_0__DET_DEPTH__SHIFT 0x10 88 #define DCHUBBUB_DEBUG_CTRL_0__DET_DEPTH_MASK 0x01FF0000L 89 90 #include "reg_helper.h" 91 #include "dce/dmub_abm.h" 92 #include "dce/dmub_psr.h" 93 #include "dce/dce_aux.h" 94 #include "dce/dce_i2c.h" 95 #include "dml/dcn314/display_mode_vba_314.h" 96 #include "vm_helper.h" 97 #include "dcn20/dcn20_vmid.h" 98 99 #include "link_enc_cfg.h" 100 101 #define DCN_BASE__INST0_SEG1 0x000000C0 102 #define DCN_BASE__INST0_SEG2 0x000034C0 103 #define DCN_BASE__INST0_SEG3 0x00009000 104 105 #define NBIO_BASE__INST0_SEG1 0x00000014 106 107 #define MAX_INSTANCE 7 108 #define MAX_SEGMENT 8 109 110 #define regBIF_BX2_BIOS_SCRATCH_2 0x003a 111 #define regBIF_BX2_BIOS_SCRATCH_2_BASE_IDX 1 112 #define regBIF_BX2_BIOS_SCRATCH_3 0x003b 113 #define regBIF_BX2_BIOS_SCRATCH_3_BASE_IDX 1 114 #define regBIF_BX2_BIOS_SCRATCH_6 0x003e 115 #define regBIF_BX2_BIOS_SCRATCH_6_BASE_IDX 1 116 117 struct IP_BASE_INSTANCE { 118 unsigned int segment[MAX_SEGMENT]; 119 }; 120 121 struct IP_BASE { 122 struct IP_BASE_INSTANCE instance[MAX_INSTANCE]; 123 }; 124 125 static const struct IP_BASE DCN_BASE = { { { { 0x00000012, 0x000000C0, 0x000034C0, 0x00009000, 0x02403C00, 0, 0, 0 } }, 126 { { 0, 0, 0, 0, 0, 0, 0, 0 } }, 127 { { 0, 0, 0, 0, 0, 0, 0, 0 } }, 128 { { 0, 0, 0, 0, 0, 0, 0, 0 } }, 129 { { 0, 0, 0, 0, 0, 0, 0, 0 } }, 130 { { 0, 0, 0, 0, 0, 0, 0, 0 } }, 131 { { 0, 0, 0, 0, 0, 0, 0, 0 } } } }; 132 133 134 #define DC_LOGGER_INIT(logger) 135 136 enum dcn31_clk_src_array_id { 137 DCN31_CLK_SRC_PLL0, 138 DCN31_CLK_SRC_PLL1, 139 DCN31_CLK_SRC_PLL2, 140 DCN31_CLK_SRC_PLL3, 141 DCN31_CLK_SRC_PLL4, 142 DCN30_CLK_SRC_TOTAL 143 }; 144 145 /* begin ********************* 146 * macros to expend register list macro defined in HW object header file 147 */ 148 149 /* DCN */ 150 /* TODO awful hack. fixup dcn20_dwb.h */ 151 #undef BASE_INNER 152 #define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg 153 154 #define BASE(seg) BASE_INNER(seg) 155 156 #define SR(reg_name)\ 157 .reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \ 158 reg ## reg_name 159 160 #define SRI(reg_name, block, id)\ 161 .reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 162 reg ## block ## id ## _ ## reg_name 163 164 #define SRI2(reg_name, block, id)\ 165 .reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \ 166 reg ## reg_name 167 168 #define SRIR(var_name, reg_name, block, id)\ 169 .var_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 170 reg ## block ## id ## _ ## reg_name 171 172 #define SRII(reg_name, block, id)\ 173 .reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 174 reg ## block ## id ## _ ## reg_name 175 176 #define SRII_MPC_RMU(reg_name, block, id)\ 177 .RMU##_##reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 178 reg ## block ## id ## _ ## reg_name 179 180 #define SRII_DWB(reg_name, temp_name, block, id)\ 181 .reg_name[id] = BASE(reg ## block ## id ## _ ## temp_name ## _BASE_IDX) + \ 182 reg ## block ## id ## _ ## temp_name 183 184 #define DCCG_SRII(reg_name, block, id)\ 185 .block ## _ ## reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 186 reg ## block ## id ## _ ## reg_name 187 188 #define VUPDATE_SRII(reg_name, block, id)\ 189 .reg_name[id] = BASE(reg ## reg_name ## _ ## block ## id ## _BASE_IDX) + \ 190 reg ## reg_name ## _ ## block ## id 191 192 /* NBIO */ 193 #define NBIO_BASE_INNER(seg) \ 194 NBIO_BASE__INST0_SEG ## seg 195 196 #define NBIO_BASE(seg) \ 197 NBIO_BASE_INNER(seg) 198 199 #define NBIO_SR(reg_name)\ 200 .reg_name = NBIO_BASE(regBIF_BX2_ ## reg_name ## _BASE_IDX) + \ 201 regBIF_BX2_ ## reg_name 202 203 /* MMHUB */ 204 #define MMHUB_BASE_INNER(seg) \ 205 MMHUB_BASE__INST0_SEG ## seg 206 207 #define MMHUB_BASE(seg) \ 208 MMHUB_BASE_INNER(seg) 209 210 #define MMHUB_SR(reg_name)\ 211 .reg_name = MMHUB_BASE(reg ## reg_name ## _BASE_IDX) + \ 212 reg ## reg_name 213 214 /* CLOCK */ 215 #define CLK_BASE_INNER(seg) \ 216 CLK_BASE__INST0_SEG ## seg 217 218 #define CLK_BASE(seg) \ 219 CLK_BASE_INNER(seg) 220 221 #define CLK_SRI(reg_name, block, inst)\ 222 .reg_name = CLK_BASE(reg ## block ## _ ## inst ## _ ## reg_name ## _BASE_IDX) + \ 223 reg ## block ## _ ## inst ## _ ## reg_name 224 225 226 static const struct bios_registers bios_regs = { 227 NBIO_SR(BIOS_SCRATCH_3), 228 NBIO_SR(BIOS_SCRATCH_6) 229 }; 230 231 #define clk_src_regs(index, pllid)\ 232 [index] = {\ 233 CS_COMMON_REG_LIST_DCN3_0(index, pllid),\ 234 } 235 236 static const struct dce110_clk_src_regs clk_src_regs[] = { 237 clk_src_regs(0, A), 238 clk_src_regs(1, B), 239 clk_src_regs(2, C), 240 clk_src_regs(3, D), 241 clk_src_regs(4, E) 242 }; 243 244 static const struct dce110_clk_src_shift cs_shift = { 245 CS_COMMON_MASK_SH_LIST_DCN3_1_4(__SHIFT) 246 }; 247 248 static const struct dce110_clk_src_mask cs_mask = { 249 CS_COMMON_MASK_SH_LIST_DCN3_1_4(_MASK) 250 }; 251 252 #define abm_regs(id)\ 253 [id] = {\ 254 ABM_DCN302_REG_LIST(id)\ 255 } 256 257 static const struct dce_abm_registers abm_regs[] = { 258 abm_regs(0), 259 abm_regs(1), 260 abm_regs(2), 261 abm_regs(3), 262 }; 263 264 static const struct dce_abm_shift abm_shift = { 265 ABM_MASK_SH_LIST_DCN30(__SHIFT) 266 }; 267 268 static const struct dce_abm_mask abm_mask = { 269 ABM_MASK_SH_LIST_DCN30(_MASK) 270 }; 271 272 #define audio_regs(id)\ 273 [id] = {\ 274 AUD_COMMON_REG_LIST(id)\ 275 } 276 277 static const struct dce_audio_registers audio_regs[] = { 278 audio_regs(0), 279 audio_regs(1), 280 audio_regs(2), 281 audio_regs(3), 282 audio_regs(4), 283 audio_regs(5), 284 audio_regs(6) 285 }; 286 287 #define DCE120_AUD_COMMON_MASK_SH_LIST(mask_sh)\ 288 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX, AZALIA_ENDPOINT_REG_INDEX, mask_sh),\ 289 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA, AZALIA_ENDPOINT_REG_DATA, mask_sh),\ 290 AUD_COMMON_MASK_SH_LIST_BASE(mask_sh) 291 292 static const struct dce_audio_shift audio_shift = { 293 DCE120_AUD_COMMON_MASK_SH_LIST(__SHIFT) 294 }; 295 296 static const struct dce_audio_mask audio_mask = { 297 DCE120_AUD_COMMON_MASK_SH_LIST(_MASK) 298 }; 299 300 #define vpg_regs(id)\ 301 [id] = {\ 302 VPG_DCN31_REG_LIST(id)\ 303 } 304 305 static const struct dcn31_vpg_registers vpg_regs[] = { 306 vpg_regs(0), 307 vpg_regs(1), 308 vpg_regs(2), 309 vpg_regs(3), 310 vpg_regs(4), 311 vpg_regs(5), 312 vpg_regs(6), 313 vpg_regs(7), 314 vpg_regs(8), 315 vpg_regs(9), 316 }; 317 318 static const struct dcn31_vpg_shift vpg_shift = { 319 DCN31_VPG_MASK_SH_LIST(__SHIFT) 320 }; 321 322 static const struct dcn31_vpg_mask vpg_mask = { 323 DCN31_VPG_MASK_SH_LIST(_MASK) 324 }; 325 326 #define afmt_regs(id)\ 327 [id] = {\ 328 AFMT_DCN31_REG_LIST(id)\ 329 } 330 331 static const struct dcn31_afmt_registers afmt_regs[] = { 332 afmt_regs(0), 333 afmt_regs(1), 334 afmt_regs(2), 335 afmt_regs(3), 336 afmt_regs(4), 337 afmt_regs(5) 338 }; 339 340 static const struct dcn31_afmt_shift afmt_shift = { 341 DCN31_AFMT_MASK_SH_LIST(__SHIFT) 342 }; 343 344 static const struct dcn31_afmt_mask afmt_mask = { 345 DCN31_AFMT_MASK_SH_LIST(_MASK) 346 }; 347 348 #define apg_regs(id)\ 349 [id] = {\ 350 APG_DCN31_REG_LIST(id)\ 351 } 352 353 static const struct dcn31_apg_registers apg_regs[] = { 354 apg_regs(0), 355 apg_regs(1), 356 apg_regs(2), 357 apg_regs(3) 358 }; 359 360 static const struct dcn31_apg_shift apg_shift = { 361 DCN31_APG_MASK_SH_LIST(__SHIFT) 362 }; 363 364 static const struct dcn31_apg_mask apg_mask = { 365 DCN31_APG_MASK_SH_LIST(_MASK) 366 }; 367 368 #define stream_enc_regs(id)\ 369 [id] = {\ 370 SE_DCN314_REG_LIST(id)\ 371 } 372 373 static const struct dcn10_stream_enc_registers stream_enc_regs[] = { 374 stream_enc_regs(0), 375 stream_enc_regs(1), 376 stream_enc_regs(2), 377 stream_enc_regs(3), 378 stream_enc_regs(4) 379 }; 380 381 static const struct dcn10_stream_encoder_shift se_shift = { 382 SE_COMMON_MASK_SH_LIST_DCN314(__SHIFT) 383 }; 384 385 static const struct dcn10_stream_encoder_mask se_mask = { 386 SE_COMMON_MASK_SH_LIST_DCN314(_MASK) 387 }; 388 389 390 #define aux_regs(id)\ 391 [id] = {\ 392 DCN2_AUX_REG_LIST(id)\ 393 } 394 395 static const struct dcn10_link_enc_aux_registers link_enc_aux_regs[] = { 396 aux_regs(0), 397 aux_regs(1), 398 aux_regs(2), 399 aux_regs(3), 400 aux_regs(4) 401 }; 402 403 #define hpd_regs(id)\ 404 [id] = {\ 405 HPD_REG_LIST(id)\ 406 } 407 408 static const struct dcn10_link_enc_hpd_registers link_enc_hpd_regs[] = { 409 hpd_regs(0), 410 hpd_regs(1), 411 hpd_regs(2), 412 hpd_regs(3), 413 hpd_regs(4) 414 }; 415 416 #define link_regs(id, phyid)\ 417 [id] = {\ 418 LE_DCN31_REG_LIST(id), \ 419 UNIPHY_DCN2_REG_LIST(phyid), \ 420 } 421 422 static const struct dce110_aux_registers_shift aux_shift = { 423 DCN_AUX_MASK_SH_LIST(__SHIFT) 424 }; 425 426 static const struct dce110_aux_registers_mask aux_mask = { 427 DCN_AUX_MASK_SH_LIST(_MASK) 428 }; 429 430 static const struct dcn10_link_enc_registers link_enc_regs[] = { 431 link_regs(0, A), 432 link_regs(1, B), 433 link_regs(2, C), 434 link_regs(3, D), 435 link_regs(4, E) 436 }; 437 438 static const struct dcn10_link_enc_shift le_shift = { 439 LINK_ENCODER_MASK_SH_LIST_DCN31(__SHIFT), 440 DPCS_DCN31_MASK_SH_LIST(__SHIFT) 441 }; 442 443 static const struct dcn10_link_enc_mask le_mask = { 444 LINK_ENCODER_MASK_SH_LIST_DCN31(_MASK), 445 DPCS_DCN31_MASK_SH_LIST(_MASK) 446 }; 447 448 #define hpo_dp_stream_encoder_reg_list(id)\ 449 [id] = {\ 450 DCN3_1_HPO_DP_STREAM_ENC_REG_LIST(id)\ 451 } 452 453 static const struct dcn31_hpo_dp_stream_encoder_registers hpo_dp_stream_enc_regs[] = { 454 hpo_dp_stream_encoder_reg_list(0), 455 hpo_dp_stream_encoder_reg_list(1), 456 hpo_dp_stream_encoder_reg_list(2), 457 hpo_dp_stream_encoder_reg_list(3) 458 }; 459 460 static const struct dcn31_hpo_dp_stream_encoder_shift hpo_dp_se_shift = { 461 DCN3_1_HPO_DP_STREAM_ENC_MASK_SH_LIST(__SHIFT) 462 }; 463 464 static const struct dcn31_hpo_dp_stream_encoder_mask hpo_dp_se_mask = { 465 DCN3_1_HPO_DP_STREAM_ENC_MASK_SH_LIST(_MASK) 466 }; 467 468 469 #define hpo_dp_link_encoder_reg_list(id)\ 470 [id] = {\ 471 DCN3_1_HPO_DP_LINK_ENC_REG_LIST(id),\ 472 DCN3_1_RDPCSTX_REG_LIST(0),\ 473 DCN3_1_RDPCSTX_REG_LIST(1),\ 474 DCN3_1_RDPCSTX_REG_LIST(2),\ 475 } 476 477 static const struct dcn31_hpo_dp_link_encoder_registers hpo_dp_link_enc_regs[] = { 478 hpo_dp_link_encoder_reg_list(0), 479 hpo_dp_link_encoder_reg_list(1), 480 }; 481 482 static const struct dcn31_hpo_dp_link_encoder_shift hpo_dp_le_shift = { 483 DCN3_1_HPO_DP_LINK_ENC_MASK_SH_LIST(__SHIFT) 484 }; 485 486 static const struct dcn31_hpo_dp_link_encoder_mask hpo_dp_le_mask = { 487 DCN3_1_HPO_DP_LINK_ENC_MASK_SH_LIST(_MASK) 488 }; 489 490 #define dpp_regs(id)\ 491 [id] = {\ 492 DPP_REG_LIST_DCN30(id),\ 493 } 494 495 static const struct dcn3_dpp_registers dpp_regs[] = { 496 dpp_regs(0), 497 dpp_regs(1), 498 dpp_regs(2), 499 dpp_regs(3) 500 }; 501 502 static const struct dcn3_dpp_shift tf_shift = { 503 DPP_REG_LIST_SH_MASK_DCN30(__SHIFT) 504 }; 505 506 static const struct dcn3_dpp_mask tf_mask = { 507 DPP_REG_LIST_SH_MASK_DCN30(_MASK) 508 }; 509 510 #define opp_regs(id)\ 511 [id] = {\ 512 OPP_REG_LIST_DCN30(id),\ 513 } 514 515 static const struct dcn20_opp_registers opp_regs[] = { 516 opp_regs(0), 517 opp_regs(1), 518 opp_regs(2), 519 opp_regs(3) 520 }; 521 522 static const struct dcn20_opp_shift opp_shift = { 523 OPP_MASK_SH_LIST_DCN20(__SHIFT) 524 }; 525 526 static const struct dcn20_opp_mask opp_mask = { 527 OPP_MASK_SH_LIST_DCN20(_MASK) 528 }; 529 530 #define aux_engine_regs(id)\ 531 [id] = {\ 532 AUX_COMMON_REG_LIST0(id), \ 533 .AUXN_IMPCAL = 0, \ 534 .AUXP_IMPCAL = 0, \ 535 .AUX_RESET_MASK = DP_AUX0_AUX_CONTROL__AUX_RESET_MASK, \ 536 } 537 538 static const struct dce110_aux_registers aux_engine_regs[] = { 539 aux_engine_regs(0), 540 aux_engine_regs(1), 541 aux_engine_regs(2), 542 aux_engine_regs(3), 543 aux_engine_regs(4) 544 }; 545 546 #define dwbc_regs_dcn3(id)\ 547 [id] = {\ 548 DWBC_COMMON_REG_LIST_DCN30(id),\ 549 } 550 551 static const struct dcn30_dwbc_registers dwbc30_regs[] = { 552 dwbc_regs_dcn3(0), 553 }; 554 555 static const struct dcn30_dwbc_shift dwbc30_shift = { 556 DWBC_COMMON_MASK_SH_LIST_DCN30(__SHIFT) 557 }; 558 559 static const struct dcn30_dwbc_mask dwbc30_mask = { 560 DWBC_COMMON_MASK_SH_LIST_DCN30(_MASK) 561 }; 562 563 #define mcif_wb_regs_dcn3(id)\ 564 [id] = {\ 565 MCIF_WB_COMMON_REG_LIST_DCN30(id),\ 566 } 567 568 static const struct dcn30_mmhubbub_registers mcif_wb30_regs[] = { 569 mcif_wb_regs_dcn3(0) 570 }; 571 572 static const struct dcn30_mmhubbub_shift mcif_wb30_shift = { 573 MCIF_WB_COMMON_MASK_SH_LIST_DCN30(__SHIFT) 574 }; 575 576 static const struct dcn30_mmhubbub_mask mcif_wb30_mask = { 577 MCIF_WB_COMMON_MASK_SH_LIST_DCN30(_MASK) 578 }; 579 580 #define dsc_regsDCN314(id)\ 581 [id] = {\ 582 DSC_REG_LIST_DCN314(id)\ 583 } 584 585 static const struct dcn20_dsc_registers dsc_regs[] = { 586 dsc_regsDCN314(0), 587 dsc_regsDCN314(1), 588 dsc_regsDCN314(2), 589 dsc_regsDCN314(3) 590 }; 591 592 static const struct dcn20_dsc_shift dsc_shift = { 593 DSC_REG_LIST_SH_MASK_DCN314(__SHIFT) 594 }; 595 596 static const struct dcn20_dsc_mask dsc_mask = { 597 DSC_REG_LIST_SH_MASK_DCN314(_MASK) 598 }; 599 600 static const struct dcn30_mpc_registers mpc_regs = { 601 MPC_REG_LIST_DCN3_0(0), 602 MPC_REG_LIST_DCN3_0(1), 603 MPC_REG_LIST_DCN3_0(2), 604 MPC_REG_LIST_DCN3_0(3), 605 MPC_OUT_MUX_REG_LIST_DCN3_0(0), 606 MPC_OUT_MUX_REG_LIST_DCN3_0(1), 607 MPC_OUT_MUX_REG_LIST_DCN3_0(2), 608 MPC_OUT_MUX_REG_LIST_DCN3_0(3), 609 MPC_RMU_GLOBAL_REG_LIST_DCN3AG, 610 MPC_RMU_REG_LIST_DCN3AG(0), 611 MPC_RMU_REG_LIST_DCN3AG(1), 612 //MPC_RMU_REG_LIST_DCN3AG(2), 613 MPC_DWB_MUX_REG_LIST_DCN3_0(0), 614 }; 615 616 static const struct dcn30_mpc_shift mpc_shift = { 617 MPC_COMMON_MASK_SH_LIST_DCN30(__SHIFT) 618 }; 619 620 static const struct dcn30_mpc_mask mpc_mask = { 621 MPC_COMMON_MASK_SH_LIST_DCN30(_MASK) 622 }; 623 624 #define optc_regs(id)\ 625 [id] = {OPTC_COMMON_REG_LIST_DCN3_14(id)} 626 627 static const struct dcn_optc_registers optc_regs[] = { 628 optc_regs(0), 629 optc_regs(1), 630 optc_regs(2), 631 optc_regs(3) 632 }; 633 634 static const struct dcn_optc_shift optc_shift = { 635 OPTC_COMMON_MASK_SH_LIST_DCN3_14(__SHIFT) 636 }; 637 638 static const struct dcn_optc_mask optc_mask = { 639 OPTC_COMMON_MASK_SH_LIST_DCN3_14(_MASK) 640 }; 641 642 #define hubp_regs(id)\ 643 [id] = {\ 644 HUBP_REG_LIST_DCN30(id)\ 645 } 646 647 static const struct dcn_hubp2_registers hubp_regs[] = { 648 hubp_regs(0), 649 hubp_regs(1), 650 hubp_regs(2), 651 hubp_regs(3) 652 }; 653 654 655 static const struct dcn_hubp2_shift hubp_shift = { 656 HUBP_MASK_SH_LIST_DCN31(__SHIFT) 657 }; 658 659 static const struct dcn_hubp2_mask hubp_mask = { 660 HUBP_MASK_SH_LIST_DCN31(_MASK) 661 }; 662 static const struct dcn_hubbub_registers hubbub_reg = { 663 HUBBUB_REG_LIST_DCN31(0) 664 }; 665 666 static const struct dcn_hubbub_shift hubbub_shift = { 667 HUBBUB_MASK_SH_LIST_DCN31(__SHIFT) 668 }; 669 670 static const struct dcn_hubbub_mask hubbub_mask = { 671 HUBBUB_MASK_SH_LIST_DCN31(_MASK) 672 }; 673 674 static const struct dccg_registers dccg_regs = { 675 DCCG_REG_LIST_DCN314() 676 }; 677 678 static const struct dccg_shift dccg_shift = { 679 DCCG_MASK_SH_LIST_DCN314(__SHIFT) 680 }; 681 682 static const struct dccg_mask dccg_mask = { 683 DCCG_MASK_SH_LIST_DCN314(_MASK) 684 }; 685 686 687 #define SRII2(reg_name_pre, reg_name_post, id)\ 688 .reg_name_pre ## _ ## reg_name_post[id] = BASE(reg ## reg_name_pre \ 689 ## id ## _ ## reg_name_post ## _BASE_IDX) + \ 690 reg ## reg_name_pre ## id ## _ ## reg_name_post 691 692 693 #define HWSEQ_DCN31_REG_LIST()\ 694 SR(DCHUBBUB_GLOBAL_TIMER_CNTL), \ 695 SR(DCHUBBUB_ARB_HOSTVM_CNTL), \ 696 SR(DIO_MEM_PWR_CTRL), \ 697 SR(ODM_MEM_PWR_CTRL3), \ 698 SR(DMU_MEM_PWR_CNTL), \ 699 SR(MMHUBBUB_MEM_PWR_CNTL), \ 700 SR(DCCG_GATE_DISABLE_CNTL), \ 701 SR(DCCG_GATE_DISABLE_CNTL2), \ 702 SR(DCFCLK_CNTL),\ 703 SR(DC_MEM_GLOBAL_PWR_REQ_CNTL), \ 704 SRII(PIXEL_RATE_CNTL, OTG, 0), \ 705 SRII(PIXEL_RATE_CNTL, OTG, 1),\ 706 SRII(PIXEL_RATE_CNTL, OTG, 2),\ 707 SRII(PIXEL_RATE_CNTL, OTG, 3),\ 708 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 0),\ 709 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 1),\ 710 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 2),\ 711 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 3),\ 712 SR(MICROSECOND_TIME_BASE_DIV), \ 713 SR(MILLISECOND_TIME_BASE_DIV), \ 714 SR(DISPCLK_FREQ_CHANGE_CNTL), \ 715 SR(RBBMIF_TIMEOUT_DIS), \ 716 SR(RBBMIF_TIMEOUT_DIS_2), \ 717 SR(DCHUBBUB_CRC_CTRL), \ 718 SR(DPP_TOP0_DPP_CRC_CTRL), \ 719 SR(DPP_TOP0_DPP_CRC_VAL_B_A), \ 720 SR(DPP_TOP0_DPP_CRC_VAL_R_G), \ 721 SR(MPC_CRC_CTRL), \ 722 SR(MPC_CRC_RESULT_GB), \ 723 SR(MPC_CRC_RESULT_C), \ 724 SR(MPC_CRC_RESULT_AR), \ 725 SR(DOMAIN0_PG_CONFIG), \ 726 SR(DOMAIN1_PG_CONFIG), \ 727 SR(DOMAIN2_PG_CONFIG), \ 728 SR(DOMAIN3_PG_CONFIG), \ 729 SR(DOMAIN16_PG_CONFIG), \ 730 SR(DOMAIN17_PG_CONFIG), \ 731 SR(DOMAIN18_PG_CONFIG), \ 732 SR(DOMAIN19_PG_CONFIG), \ 733 SR(DOMAIN0_PG_STATUS), \ 734 SR(DOMAIN1_PG_STATUS), \ 735 SR(DOMAIN2_PG_STATUS), \ 736 SR(DOMAIN3_PG_STATUS), \ 737 SR(DOMAIN16_PG_STATUS), \ 738 SR(DOMAIN17_PG_STATUS), \ 739 SR(DOMAIN18_PG_STATUS), \ 740 SR(DOMAIN19_PG_STATUS), \ 741 SR(D1VGA_CONTROL), \ 742 SR(D2VGA_CONTROL), \ 743 SR(D3VGA_CONTROL), \ 744 SR(D4VGA_CONTROL), \ 745 SR(D5VGA_CONTROL), \ 746 SR(D6VGA_CONTROL), \ 747 SR(DC_IP_REQUEST_CNTL), \ 748 SR(AZALIA_AUDIO_DTO), \ 749 SR(AZALIA_CONTROLLER_CLOCK_GATING), \ 750 SR(HPO_TOP_HW_CONTROL) 751 752 static const struct dce_hwseq_registers hwseq_reg = { 753 HWSEQ_DCN31_REG_LIST() 754 }; 755 756 #define HWSEQ_DCN31_MASK_SH_LIST(mask_sh)\ 757 HWSEQ_DCN_MASK_SH_LIST(mask_sh), \ 758 HWS_SF(, DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_REFDIV, mask_sh), \ 759 HWS_SF(, DCHUBBUB_ARB_HOSTVM_CNTL, DISABLE_HOSTVM_FORCE_ALLOW_PSTATE, mask_sh), \ 760 HWS_SF(, DOMAIN0_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ 761 HWS_SF(, DOMAIN0_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ 762 HWS_SF(, DOMAIN1_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ 763 HWS_SF(, DOMAIN1_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ 764 HWS_SF(, DOMAIN2_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ 765 HWS_SF(, DOMAIN2_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ 766 HWS_SF(, DOMAIN3_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ 767 HWS_SF(, DOMAIN3_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ 768 HWS_SF(, DOMAIN16_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ 769 HWS_SF(, DOMAIN16_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ 770 HWS_SF(, DOMAIN17_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ 771 HWS_SF(, DOMAIN17_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ 772 HWS_SF(, DOMAIN18_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ 773 HWS_SF(, DOMAIN18_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ 774 HWS_SF(, DOMAIN19_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ 775 HWS_SF(, DOMAIN19_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ 776 HWS_SF(, DOMAIN0_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ 777 HWS_SF(, DOMAIN1_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ 778 HWS_SF(, DOMAIN2_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ 779 HWS_SF(, DOMAIN3_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ 780 HWS_SF(, DOMAIN16_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ 781 HWS_SF(, DOMAIN17_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ 782 HWS_SF(, DOMAIN18_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ 783 HWS_SF(, DOMAIN19_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ 784 HWS_SF(, DC_IP_REQUEST_CNTL, IP_REQUEST_EN, mask_sh), \ 785 HWS_SF(, AZALIA_AUDIO_DTO, AZALIA_AUDIO_DTO_MODULE, mask_sh), \ 786 HWS_SF(, HPO_TOP_CLOCK_CONTROL, HPO_HDMISTREAMCLK_G_GATE_DIS, mask_sh), \ 787 HWS_SF(, DMU_MEM_PWR_CNTL, DMCU_ERAM_MEM_PWR_FORCE, mask_sh), \ 788 HWS_SF(, ODM_MEM_PWR_CTRL3, ODM_MEM_UNASSIGNED_PWR_MODE, mask_sh), \ 789 HWS_SF(, ODM_MEM_PWR_CTRL3, ODM_MEM_VBLANK_PWR_MODE, mask_sh), \ 790 HWS_SF(, MMHUBBUB_MEM_PWR_CNTL, VGA_MEM_PWR_FORCE, mask_sh), \ 791 HWS_SF(, DIO_MEM_PWR_CTRL, I2C_LIGHT_SLEEP_FORCE, mask_sh), \ 792 HWS_SF(, HPO_TOP_HW_CONTROL, HPO_IO_EN, mask_sh) 793 794 static const struct dce_hwseq_shift hwseq_shift = { 795 HWSEQ_DCN31_MASK_SH_LIST(__SHIFT) 796 }; 797 798 static const struct dce_hwseq_mask hwseq_mask = { 799 HWSEQ_DCN31_MASK_SH_LIST(_MASK) 800 }; 801 #define vmid_regs(id)\ 802 [id] = {\ 803 DCN20_VMID_REG_LIST(id)\ 804 } 805 806 static const struct dcn_vmid_registers vmid_regs[] = { 807 vmid_regs(0), 808 vmid_regs(1), 809 vmid_regs(2), 810 vmid_regs(3), 811 vmid_regs(4), 812 vmid_regs(5), 813 vmid_regs(6), 814 vmid_regs(7), 815 vmid_regs(8), 816 vmid_regs(9), 817 vmid_regs(10), 818 vmid_regs(11), 819 vmid_regs(12), 820 vmid_regs(13), 821 vmid_regs(14), 822 vmid_regs(15) 823 }; 824 825 static const struct dcn20_vmid_shift vmid_shifts = { 826 DCN20_VMID_MASK_SH_LIST(__SHIFT) 827 }; 828 829 static const struct dcn20_vmid_mask vmid_masks = { 830 DCN20_VMID_MASK_SH_LIST(_MASK) 831 }; 832 833 static const struct resource_caps res_cap_dcn314 = { 834 .num_timing_generator = 4, 835 .num_opp = 4, 836 .num_video_plane = 4, 837 .num_audio = 5, 838 .num_stream_encoder = 5, 839 .num_dig_link_enc = 5, 840 .num_hpo_dp_stream_encoder = 4, 841 .num_hpo_dp_link_encoder = 2, 842 .num_pll = 5, 843 .num_dwb = 1, 844 .num_ddc = 5, 845 .num_vmid = 16, 846 .num_mpc_3dlut = 2, 847 .num_dsc = 4, 848 }; 849 850 static const struct dc_plane_cap plane_cap = { 851 .type = DC_PLANE_TYPE_DCN_UNIVERSAL, 852 .blends_with_above = true, 853 .blends_with_below = true, 854 .per_pixel_alpha = true, 855 856 .pixel_format_support = { 857 .argb8888 = true, 858 .nv12 = true, 859 .fp16 = true, 860 .p010 = true, 861 .ayuv = false, 862 }, 863 864 .max_upscale_factor = { 865 .argb8888 = 16000, 866 .nv12 = 16000, 867 .fp16 = 16000 868 }, 869 870 // 6:1 downscaling ratio: 1000/6 = 166.666 871 .max_downscale_factor = { 872 .argb8888 = 167, 873 .nv12 = 167, 874 .fp16 = 167 875 }, 876 64, 877 64 878 }; 879 880 static const struct dc_debug_options debug_defaults_drv = { 881 .disable_z10 = true, /*hw not support it*/ 882 .disable_dmcu = true, 883 .force_abm_enable = false, 884 .timing_trace = false, 885 .clock_trace = true, 886 .disable_pplib_clock_request = false, 887 .pipe_split_policy = MPC_SPLIT_DYNAMIC, 888 .force_single_disp_pipe_split = false, 889 .disable_dcc = DCC_ENABLE, 890 .vsr_support = true, 891 .performance_trace = false, 892 .max_downscale_src_width = 4096,/*upto true 4k*/ 893 .disable_pplib_wm_range = false, 894 .scl_reset_length10 = true, 895 .sanity_checks = false, 896 .underflow_assert_delay_us = 0xFFFFFFFF, 897 .dwb_fi_phase = -1, // -1 = disable, 898 .dmub_command_table = true, 899 .pstate_enabled = true, 900 .use_max_lb = true, 901 .enable_mem_low_power = { 902 .bits = { 903 .vga = true, 904 .i2c = true, 905 .dmcu = false, // This is previously known to cause hang on S3 cycles if enabled 906 .dscl = true, 907 .cm = true, 908 .mpc = true, 909 .optc = true, 910 .vpg = true, 911 .afmt = true, 912 } 913 }, 914 .optimize_edp_link_rate = true, 915 .enable_sw_cntl_psr = true, 916 .seamless_boot_odm_combine = true 917 }; 918 919 static const struct dc_debug_options debug_defaults_diags = { 920 .disable_dmcu = true, 921 .force_abm_enable = false, 922 .timing_trace = true, 923 .clock_trace = true, 924 .disable_dpp_power_gate = true, 925 .disable_hubp_power_gate = true, 926 .disable_clock_gate = true, 927 .disable_pplib_clock_request = true, 928 .disable_pplib_wm_range = true, 929 .disable_stutter = false, 930 .scl_reset_length10 = true, 931 .dwb_fi_phase = -1, // -1 = disable 932 .dmub_command_table = true, 933 .enable_tri_buf = true, 934 .use_max_lb = true 935 }; 936 937 static void dcn31_dpp_destroy(struct dpp **dpp) 938 { 939 kfree(TO_DCN20_DPP(*dpp)); 940 *dpp = NULL; 941 } 942 943 static struct dpp *dcn31_dpp_create( 944 struct dc_context *ctx, 945 uint32_t inst) 946 { 947 struct dcn3_dpp *dpp = 948 kzalloc(sizeof(struct dcn3_dpp), GFP_KERNEL); 949 950 if (!dpp) 951 return NULL; 952 953 if (dpp3_construct(dpp, ctx, inst, 954 &dpp_regs[inst], &tf_shift, &tf_mask)) 955 return &dpp->base; 956 957 BREAK_TO_DEBUGGER(); 958 kfree(dpp); 959 return NULL; 960 } 961 962 static struct output_pixel_processor *dcn31_opp_create( 963 struct dc_context *ctx, uint32_t inst) 964 { 965 struct dcn20_opp *opp = 966 kzalloc(sizeof(struct dcn20_opp), GFP_KERNEL); 967 968 if (!opp) { 969 BREAK_TO_DEBUGGER(); 970 return NULL; 971 } 972 973 dcn20_opp_construct(opp, ctx, inst, 974 &opp_regs[inst], &opp_shift, &opp_mask); 975 return &opp->base; 976 } 977 978 static struct dce_aux *dcn31_aux_engine_create( 979 struct dc_context *ctx, 980 uint32_t inst) 981 { 982 struct aux_engine_dce110 *aux_engine = 983 kzalloc(sizeof(struct aux_engine_dce110), GFP_KERNEL); 984 985 if (!aux_engine) 986 return NULL; 987 988 dce110_aux_engine_construct(aux_engine, ctx, inst, 989 SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD, 990 &aux_engine_regs[inst], 991 &aux_mask, 992 &aux_shift, 993 ctx->dc->caps.extended_aux_timeout_support); 994 995 return &aux_engine->base; 996 } 997 #define i2c_inst_regs(id) { I2C_HW_ENGINE_COMMON_REG_LIST_DCN30(id) } 998 999 static const struct dce_i2c_registers i2c_hw_regs[] = { 1000 i2c_inst_regs(1), 1001 i2c_inst_regs(2), 1002 i2c_inst_regs(3), 1003 i2c_inst_regs(4), 1004 i2c_inst_regs(5), 1005 }; 1006 1007 static const struct dce_i2c_shift i2c_shifts = { 1008 I2C_COMMON_MASK_SH_LIST_DCN30(__SHIFT) 1009 }; 1010 1011 static const struct dce_i2c_mask i2c_masks = { 1012 I2C_COMMON_MASK_SH_LIST_DCN30(_MASK) 1013 }; 1014 1015 static struct dce_i2c_hw *dcn31_i2c_hw_create( 1016 struct dc_context *ctx, 1017 uint32_t inst) 1018 { 1019 struct dce_i2c_hw *dce_i2c_hw = 1020 kzalloc(sizeof(struct dce_i2c_hw), GFP_KERNEL); 1021 1022 if (!dce_i2c_hw) 1023 return NULL; 1024 1025 dcn2_i2c_hw_construct(dce_i2c_hw, ctx, inst, 1026 &i2c_hw_regs[inst], &i2c_shifts, &i2c_masks); 1027 1028 return dce_i2c_hw; 1029 } 1030 static struct mpc *dcn31_mpc_create( 1031 struct dc_context *ctx, 1032 int num_mpcc, 1033 int num_rmu) 1034 { 1035 struct dcn30_mpc *mpc30 = kzalloc(sizeof(struct dcn30_mpc), 1036 GFP_KERNEL); 1037 1038 if (!mpc30) 1039 return NULL; 1040 1041 dcn30_mpc_construct(mpc30, ctx, 1042 &mpc_regs, 1043 &mpc_shift, 1044 &mpc_mask, 1045 num_mpcc, 1046 num_rmu); 1047 1048 return &mpc30->base; 1049 } 1050 1051 static struct hubbub *dcn31_hubbub_create(struct dc_context *ctx) 1052 { 1053 int i; 1054 1055 struct dcn20_hubbub *hubbub3 = kzalloc(sizeof(struct dcn20_hubbub), 1056 GFP_KERNEL); 1057 1058 if (!hubbub3) 1059 return NULL; 1060 1061 hubbub31_construct(hubbub3, ctx, 1062 &hubbub_reg, 1063 &hubbub_shift, 1064 &hubbub_mask, 1065 dcn3_14_ip.det_buffer_size_kbytes, 1066 dcn3_14_ip.pixel_chunk_size_kbytes, 1067 dcn3_14_ip.config_return_buffer_size_in_kbytes); 1068 1069 1070 for (i = 0; i < res_cap_dcn314.num_vmid; i++) { 1071 struct dcn20_vmid *vmid = &hubbub3->vmid[i]; 1072 1073 vmid->ctx = ctx; 1074 1075 vmid->regs = &vmid_regs[i]; 1076 vmid->shifts = &vmid_shifts; 1077 vmid->masks = &vmid_masks; 1078 } 1079 1080 return &hubbub3->base; 1081 } 1082 1083 static struct timing_generator *dcn31_timing_generator_create( 1084 struct dc_context *ctx, 1085 uint32_t instance) 1086 { 1087 struct optc *tgn10 = 1088 kzalloc(sizeof(struct optc), GFP_KERNEL); 1089 1090 if (!tgn10) 1091 return NULL; 1092 1093 tgn10->base.inst = instance; 1094 tgn10->base.ctx = ctx; 1095 1096 tgn10->tg_regs = &optc_regs[instance]; 1097 tgn10->tg_shift = &optc_shift; 1098 tgn10->tg_mask = &optc_mask; 1099 1100 dcn314_timing_generator_init(tgn10); 1101 1102 return &tgn10->base; 1103 } 1104 1105 static const struct encoder_feature_support link_enc_feature = { 1106 .max_hdmi_deep_color = COLOR_DEPTH_121212, 1107 .max_hdmi_pixel_clock = 600000, 1108 .hdmi_ycbcr420_supported = true, 1109 .dp_ycbcr420_supported = true, 1110 .fec_supported = true, 1111 .flags.bits.IS_HBR2_CAPABLE = true, 1112 .flags.bits.IS_HBR3_CAPABLE = true, 1113 .flags.bits.IS_TPS3_CAPABLE = true, 1114 .flags.bits.IS_TPS4_CAPABLE = true 1115 }; 1116 1117 static struct link_encoder *dcn31_link_encoder_create( 1118 struct dc_context *ctx, 1119 const struct encoder_init_data *enc_init_data) 1120 { 1121 struct dcn20_link_encoder *enc20 = 1122 kzalloc(sizeof(struct dcn20_link_encoder), GFP_KERNEL); 1123 1124 if (!enc20) 1125 return NULL; 1126 1127 dcn31_link_encoder_construct(enc20, 1128 enc_init_data, 1129 &link_enc_feature, 1130 &link_enc_regs[enc_init_data->transmitter], 1131 &link_enc_aux_regs[enc_init_data->channel - 1], 1132 &link_enc_hpd_regs[enc_init_data->hpd_source], 1133 &le_shift, 1134 &le_mask); 1135 1136 return &enc20->enc10.base; 1137 } 1138 1139 /* Create a minimal link encoder object not associated with a particular 1140 * physical connector. 1141 * resource_funcs.link_enc_create_minimal 1142 */ 1143 static struct link_encoder *dcn31_link_enc_create_minimal( 1144 struct dc_context *ctx, enum engine_id eng_id) 1145 { 1146 struct dcn20_link_encoder *enc20; 1147 1148 if ((eng_id - ENGINE_ID_DIGA) > ctx->dc->res_pool->res_cap->num_dig_link_enc) 1149 return NULL; 1150 1151 enc20 = kzalloc(sizeof(struct dcn20_link_encoder), GFP_KERNEL); 1152 if (!enc20) 1153 return NULL; 1154 1155 dcn31_link_encoder_construct_minimal( 1156 enc20, 1157 ctx, 1158 &link_enc_feature, 1159 &link_enc_regs[eng_id - ENGINE_ID_DIGA], 1160 eng_id); 1161 1162 return &enc20->enc10.base; 1163 } 1164 1165 static struct panel_cntl *dcn31_panel_cntl_create(const struct panel_cntl_init_data *init_data) 1166 { 1167 struct dcn31_panel_cntl *panel_cntl = 1168 kzalloc(sizeof(struct dcn31_panel_cntl), GFP_KERNEL); 1169 1170 if (!panel_cntl) 1171 return NULL; 1172 1173 dcn31_panel_cntl_construct(panel_cntl, init_data); 1174 1175 return &panel_cntl->base; 1176 } 1177 1178 static void read_dce_straps( 1179 struct dc_context *ctx, 1180 struct resource_straps *straps) 1181 { 1182 generic_reg_get(ctx, regDC_PINSTRAPS + BASE(regDC_PINSTRAPS_BASE_IDX), 1183 FN(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO), &straps->dc_pinstraps_audio); 1184 1185 } 1186 1187 static struct audio *dcn31_create_audio( 1188 struct dc_context *ctx, unsigned int inst) 1189 { 1190 return dce_audio_create(ctx, inst, 1191 &audio_regs[inst], &audio_shift, &audio_mask); 1192 } 1193 1194 static struct vpg *dcn31_vpg_create( 1195 struct dc_context *ctx, 1196 uint32_t inst) 1197 { 1198 struct dcn31_vpg *vpg31 = kzalloc(sizeof(struct dcn31_vpg), GFP_KERNEL); 1199 1200 if (!vpg31) 1201 return NULL; 1202 1203 vpg31_construct(vpg31, ctx, inst, 1204 &vpg_regs[inst], 1205 &vpg_shift, 1206 &vpg_mask); 1207 1208 return &vpg31->base; 1209 } 1210 1211 static struct afmt *dcn31_afmt_create( 1212 struct dc_context *ctx, 1213 uint32_t inst) 1214 { 1215 struct dcn31_afmt *afmt31 = kzalloc(sizeof(struct dcn31_afmt), GFP_KERNEL); 1216 1217 if (!afmt31) 1218 return NULL; 1219 1220 afmt31_construct(afmt31, ctx, inst, 1221 &afmt_regs[inst], 1222 &afmt_shift, 1223 &afmt_mask); 1224 1225 // Light sleep by default, no need to power down here 1226 1227 return &afmt31->base; 1228 } 1229 1230 static struct apg *dcn31_apg_create( 1231 struct dc_context *ctx, 1232 uint32_t inst) 1233 { 1234 struct dcn31_apg *apg31 = kzalloc(sizeof(struct dcn31_apg), GFP_KERNEL); 1235 1236 if (!apg31) 1237 return NULL; 1238 1239 apg31_construct(apg31, ctx, inst, 1240 &apg_regs[inst], 1241 &apg_shift, 1242 &apg_mask); 1243 1244 return &apg31->base; 1245 } 1246 1247 static struct stream_encoder *dcn314_stream_encoder_create( 1248 enum engine_id eng_id, 1249 struct dc_context *ctx) 1250 { 1251 struct dcn10_stream_encoder *enc1; 1252 struct vpg *vpg; 1253 struct afmt *afmt; 1254 int vpg_inst; 1255 int afmt_inst; 1256 1257 /* Mapping of VPG, AFMT, DME register blocks to DIO block instance */ 1258 if (eng_id < ENGINE_ID_DIGF) { 1259 vpg_inst = eng_id; 1260 afmt_inst = eng_id; 1261 } else 1262 return NULL; 1263 1264 enc1 = kzalloc(sizeof(struct dcn10_stream_encoder), GFP_KERNEL); 1265 vpg = dcn31_vpg_create(ctx, vpg_inst); 1266 afmt = dcn31_afmt_create(ctx, afmt_inst); 1267 1268 if (!enc1 || !vpg || !afmt) { 1269 kfree(enc1); 1270 kfree(vpg); 1271 kfree(afmt); 1272 return NULL; 1273 } 1274 1275 dcn314_dio_stream_encoder_construct(enc1, ctx, ctx->dc_bios, 1276 eng_id, vpg, afmt, 1277 &stream_enc_regs[eng_id], 1278 &se_shift, &se_mask); 1279 1280 return &enc1->base; 1281 } 1282 1283 static struct hpo_dp_stream_encoder *dcn31_hpo_dp_stream_encoder_create( 1284 enum engine_id eng_id, 1285 struct dc_context *ctx) 1286 { 1287 struct dcn31_hpo_dp_stream_encoder *hpo_dp_enc31; 1288 struct vpg *vpg; 1289 struct apg *apg; 1290 uint32_t hpo_dp_inst; 1291 uint32_t vpg_inst; 1292 uint32_t apg_inst; 1293 1294 ASSERT((eng_id >= ENGINE_ID_HPO_DP_0) && (eng_id <= ENGINE_ID_HPO_DP_3)); 1295 hpo_dp_inst = eng_id - ENGINE_ID_HPO_DP_0; 1296 1297 /* Mapping of VPG register blocks to HPO DP block instance: 1298 * VPG[6] -> HPO_DP[0] 1299 * VPG[7] -> HPO_DP[1] 1300 * VPG[8] -> HPO_DP[2] 1301 * VPG[9] -> HPO_DP[3] 1302 */ 1303 //Uses offset index 5-8, but actually maps to vpg_inst 6-9 1304 vpg_inst = hpo_dp_inst + 5; 1305 1306 /* Mapping of APG register blocks to HPO DP block instance: 1307 * APG[0] -> HPO_DP[0] 1308 * APG[1] -> HPO_DP[1] 1309 * APG[2] -> HPO_DP[2] 1310 * APG[3] -> HPO_DP[3] 1311 */ 1312 apg_inst = hpo_dp_inst; 1313 1314 /* allocate HPO stream encoder and create VPG sub-block */ 1315 hpo_dp_enc31 = kzalloc(sizeof(struct dcn31_hpo_dp_stream_encoder), GFP_KERNEL); 1316 vpg = dcn31_vpg_create(ctx, vpg_inst); 1317 apg = dcn31_apg_create(ctx, apg_inst); 1318 1319 if (!hpo_dp_enc31 || !vpg || !apg) { 1320 kfree(hpo_dp_enc31); 1321 kfree(vpg); 1322 kfree(apg); 1323 return NULL; 1324 } 1325 1326 dcn31_hpo_dp_stream_encoder_construct(hpo_dp_enc31, ctx, ctx->dc_bios, 1327 hpo_dp_inst, eng_id, vpg, apg, 1328 &hpo_dp_stream_enc_regs[hpo_dp_inst], 1329 &hpo_dp_se_shift, &hpo_dp_se_mask); 1330 1331 return &hpo_dp_enc31->base; 1332 } 1333 1334 static struct hpo_dp_link_encoder *dcn31_hpo_dp_link_encoder_create( 1335 uint8_t inst, 1336 struct dc_context *ctx) 1337 { 1338 struct dcn31_hpo_dp_link_encoder *hpo_dp_enc31; 1339 1340 /* allocate HPO link encoder */ 1341 hpo_dp_enc31 = kzalloc(sizeof(struct dcn31_hpo_dp_link_encoder), GFP_KERNEL); 1342 1343 hpo_dp_link_encoder31_construct(hpo_dp_enc31, ctx, inst, 1344 &hpo_dp_link_enc_regs[inst], 1345 &hpo_dp_le_shift, &hpo_dp_le_mask); 1346 1347 return &hpo_dp_enc31->base; 1348 } 1349 1350 static struct dce_hwseq *dcn314_hwseq_create( 1351 struct dc_context *ctx) 1352 { 1353 struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_KERNEL); 1354 1355 if (hws) { 1356 hws->ctx = ctx; 1357 hws->regs = &hwseq_reg; 1358 hws->shifts = &hwseq_shift; 1359 hws->masks = &hwseq_mask; 1360 /* DCN3.1 FPGA Workaround 1361 * Need to enable HPO DP Stream Encoder before setting OTG master enable. 1362 * To do so, move calling function enable_stream_timing to only be done AFTER calling 1363 * function core_link_enable_stream 1364 */ 1365 if (IS_FPGA_MAXIMUS_DC(ctx->dce_environment)) 1366 hws->wa.dp_hpo_and_otg_sequence = true; 1367 } 1368 return hws; 1369 } 1370 static const struct resource_create_funcs res_create_funcs = { 1371 .read_dce_straps = read_dce_straps, 1372 .create_audio = dcn31_create_audio, 1373 .create_stream_encoder = dcn314_stream_encoder_create, 1374 .create_hpo_dp_stream_encoder = dcn31_hpo_dp_stream_encoder_create, 1375 .create_hpo_dp_link_encoder = dcn31_hpo_dp_link_encoder_create, 1376 .create_hwseq = dcn314_hwseq_create, 1377 }; 1378 1379 static const struct resource_create_funcs res_create_maximus_funcs = { 1380 .read_dce_straps = NULL, 1381 .create_audio = NULL, 1382 .create_stream_encoder = NULL, 1383 .create_hpo_dp_stream_encoder = dcn31_hpo_dp_stream_encoder_create, 1384 .create_hpo_dp_link_encoder = dcn31_hpo_dp_link_encoder_create, 1385 .create_hwseq = dcn314_hwseq_create, 1386 }; 1387 1388 static void dcn314_resource_destruct(struct dcn314_resource_pool *pool) 1389 { 1390 unsigned int i; 1391 1392 for (i = 0; i < pool->base.stream_enc_count; i++) { 1393 if (pool->base.stream_enc[i] != NULL) { 1394 if (pool->base.stream_enc[i]->vpg != NULL) { 1395 kfree(DCN30_VPG_FROM_VPG(pool->base.stream_enc[i]->vpg)); 1396 pool->base.stream_enc[i]->vpg = NULL; 1397 } 1398 if (pool->base.stream_enc[i]->afmt != NULL) { 1399 kfree(DCN30_AFMT_FROM_AFMT(pool->base.stream_enc[i]->afmt)); 1400 pool->base.stream_enc[i]->afmt = NULL; 1401 } 1402 kfree(DCN10STRENC_FROM_STRENC(pool->base.stream_enc[i])); 1403 pool->base.stream_enc[i] = NULL; 1404 } 1405 } 1406 1407 for (i = 0; i < pool->base.hpo_dp_stream_enc_count; i++) { 1408 if (pool->base.hpo_dp_stream_enc[i] != NULL) { 1409 if (pool->base.hpo_dp_stream_enc[i]->vpg != NULL) { 1410 kfree(DCN30_VPG_FROM_VPG(pool->base.hpo_dp_stream_enc[i]->vpg)); 1411 pool->base.hpo_dp_stream_enc[i]->vpg = NULL; 1412 } 1413 if (pool->base.hpo_dp_stream_enc[i]->apg != NULL) { 1414 kfree(DCN31_APG_FROM_APG(pool->base.hpo_dp_stream_enc[i]->apg)); 1415 pool->base.hpo_dp_stream_enc[i]->apg = NULL; 1416 } 1417 kfree(DCN3_1_HPO_DP_STREAM_ENC_FROM_HPO_STREAM_ENC(pool->base.hpo_dp_stream_enc[i])); 1418 pool->base.hpo_dp_stream_enc[i] = NULL; 1419 } 1420 } 1421 1422 for (i = 0; i < pool->base.hpo_dp_link_enc_count; i++) { 1423 if (pool->base.hpo_dp_link_enc[i] != NULL) { 1424 kfree(DCN3_1_HPO_DP_LINK_ENC_FROM_HPO_LINK_ENC(pool->base.hpo_dp_link_enc[i])); 1425 pool->base.hpo_dp_link_enc[i] = NULL; 1426 } 1427 } 1428 1429 for (i = 0; i < pool->base.res_cap->num_dsc; i++) { 1430 if (pool->base.dscs[i] != NULL) 1431 dcn20_dsc_destroy(&pool->base.dscs[i]); 1432 } 1433 1434 if (pool->base.mpc != NULL) { 1435 kfree(TO_DCN20_MPC(pool->base.mpc)); 1436 pool->base.mpc = NULL; 1437 } 1438 if (pool->base.hubbub != NULL) { 1439 kfree(pool->base.hubbub); 1440 pool->base.hubbub = NULL; 1441 } 1442 for (i = 0; i < pool->base.pipe_count; i++) { 1443 if (pool->base.dpps[i] != NULL) 1444 dcn31_dpp_destroy(&pool->base.dpps[i]); 1445 1446 if (pool->base.ipps[i] != NULL) 1447 pool->base.ipps[i]->funcs->ipp_destroy(&pool->base.ipps[i]); 1448 1449 if (pool->base.hubps[i] != NULL) { 1450 kfree(TO_DCN20_HUBP(pool->base.hubps[i])); 1451 pool->base.hubps[i] = NULL; 1452 } 1453 1454 if (pool->base.irqs != NULL) 1455 dal_irq_service_destroy(&pool->base.irqs); 1456 } 1457 1458 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { 1459 if (pool->base.engines[i] != NULL) 1460 dce110_engine_destroy(&pool->base.engines[i]); 1461 if (pool->base.hw_i2cs[i] != NULL) { 1462 kfree(pool->base.hw_i2cs[i]); 1463 pool->base.hw_i2cs[i] = NULL; 1464 } 1465 if (pool->base.sw_i2cs[i] != NULL) { 1466 kfree(pool->base.sw_i2cs[i]); 1467 pool->base.sw_i2cs[i] = NULL; 1468 } 1469 } 1470 1471 for (i = 0; i < pool->base.res_cap->num_opp; i++) { 1472 if (pool->base.opps[i] != NULL) 1473 pool->base.opps[i]->funcs->opp_destroy(&pool->base.opps[i]); 1474 } 1475 1476 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { 1477 if (pool->base.timing_generators[i] != NULL) { 1478 kfree(DCN10TG_FROM_TG(pool->base.timing_generators[i])); 1479 pool->base.timing_generators[i] = NULL; 1480 } 1481 } 1482 1483 for (i = 0; i < pool->base.res_cap->num_dwb; i++) { 1484 if (pool->base.dwbc[i] != NULL) { 1485 kfree(TO_DCN30_DWBC(pool->base.dwbc[i])); 1486 pool->base.dwbc[i] = NULL; 1487 } 1488 if (pool->base.mcif_wb[i] != NULL) { 1489 kfree(TO_DCN30_MMHUBBUB(pool->base.mcif_wb[i])); 1490 pool->base.mcif_wb[i] = NULL; 1491 } 1492 } 1493 1494 for (i = 0; i < pool->base.audio_count; i++) { 1495 if (pool->base.audios[i]) 1496 dce_aud_destroy(&pool->base.audios[i]); 1497 } 1498 1499 for (i = 0; i < pool->base.clk_src_count; i++) { 1500 if (pool->base.clock_sources[i] != NULL) { 1501 dcn20_clock_source_destroy(&pool->base.clock_sources[i]); 1502 pool->base.clock_sources[i] = NULL; 1503 } 1504 } 1505 1506 for (i = 0; i < pool->base.res_cap->num_mpc_3dlut; i++) { 1507 if (pool->base.mpc_lut[i] != NULL) { 1508 dc_3dlut_func_release(pool->base.mpc_lut[i]); 1509 pool->base.mpc_lut[i] = NULL; 1510 } 1511 if (pool->base.mpc_shaper[i] != NULL) { 1512 dc_transfer_func_release(pool->base.mpc_shaper[i]); 1513 pool->base.mpc_shaper[i] = NULL; 1514 } 1515 } 1516 1517 if (pool->base.dp_clock_source != NULL) { 1518 dcn20_clock_source_destroy(&pool->base.dp_clock_source); 1519 pool->base.dp_clock_source = NULL; 1520 } 1521 1522 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { 1523 if (pool->base.multiple_abms[i] != NULL) 1524 dce_abm_destroy(&pool->base.multiple_abms[i]); 1525 } 1526 1527 if (pool->base.psr != NULL) 1528 dmub_psr_destroy(&pool->base.psr); 1529 1530 if (pool->base.dccg != NULL) 1531 dcn_dccg_destroy(&pool->base.dccg); 1532 } 1533 1534 static struct hubp *dcn31_hubp_create( 1535 struct dc_context *ctx, 1536 uint32_t inst) 1537 { 1538 struct dcn20_hubp *hubp2 = 1539 kzalloc(sizeof(struct dcn20_hubp), GFP_KERNEL); 1540 1541 if (!hubp2) 1542 return NULL; 1543 1544 if (hubp31_construct(hubp2, ctx, inst, 1545 &hubp_regs[inst], &hubp_shift, &hubp_mask)) 1546 return &hubp2->base; 1547 1548 BREAK_TO_DEBUGGER(); 1549 kfree(hubp2); 1550 return NULL; 1551 } 1552 1553 static bool dcn31_dwbc_create(struct dc_context *ctx, struct resource_pool *pool) 1554 { 1555 int i; 1556 uint32_t pipe_count = pool->res_cap->num_dwb; 1557 1558 for (i = 0; i < pipe_count; i++) { 1559 struct dcn30_dwbc *dwbc30 = kzalloc(sizeof(struct dcn30_dwbc), 1560 GFP_KERNEL); 1561 1562 if (!dwbc30) { 1563 dm_error("DC: failed to create dwbc30!\n"); 1564 return false; 1565 } 1566 1567 dcn30_dwbc_construct(dwbc30, ctx, 1568 &dwbc30_regs[i], 1569 &dwbc30_shift, 1570 &dwbc30_mask, 1571 i); 1572 1573 pool->dwbc[i] = &dwbc30->base; 1574 } 1575 return true; 1576 } 1577 1578 static bool dcn31_mmhubbub_create(struct dc_context *ctx, struct resource_pool *pool) 1579 { 1580 int i; 1581 uint32_t pipe_count = pool->res_cap->num_dwb; 1582 1583 for (i = 0; i < pipe_count; i++) { 1584 struct dcn30_mmhubbub *mcif_wb30 = kzalloc(sizeof(struct dcn30_mmhubbub), 1585 GFP_KERNEL); 1586 1587 if (!mcif_wb30) { 1588 dm_error("DC: failed to create mcif_wb30!\n"); 1589 return false; 1590 } 1591 1592 dcn30_mmhubbub_construct(mcif_wb30, ctx, 1593 &mcif_wb30_regs[i], 1594 &mcif_wb30_shift, 1595 &mcif_wb30_mask, 1596 i); 1597 1598 pool->mcif_wb[i] = &mcif_wb30->base; 1599 } 1600 return true; 1601 } 1602 1603 static struct display_stream_compressor *dcn314_dsc_create( 1604 struct dc_context *ctx, uint32_t inst) 1605 { 1606 struct dcn20_dsc *dsc = 1607 kzalloc(sizeof(struct dcn20_dsc), GFP_KERNEL); 1608 1609 if (!dsc) { 1610 BREAK_TO_DEBUGGER(); 1611 return NULL; 1612 } 1613 1614 dsc2_construct(dsc, ctx, inst, &dsc_regs[inst], &dsc_shift, &dsc_mask); 1615 return &dsc->base; 1616 } 1617 1618 static void dcn314_destroy_resource_pool(struct resource_pool **pool) 1619 { 1620 struct dcn314_resource_pool *dcn314_pool = TO_DCN314_RES_POOL(*pool); 1621 1622 dcn314_resource_destruct(dcn314_pool); 1623 kfree(dcn314_pool); 1624 *pool = NULL; 1625 } 1626 1627 static struct clock_source *dcn31_clock_source_create( 1628 struct dc_context *ctx, 1629 struct dc_bios *bios, 1630 enum clock_source_id id, 1631 const struct dce110_clk_src_regs *regs, 1632 bool dp_clk_src) 1633 { 1634 struct dce110_clk_src *clk_src = 1635 kzalloc(sizeof(struct dce110_clk_src), GFP_KERNEL); 1636 1637 if (!clk_src) 1638 return NULL; 1639 1640 if (dcn31_clk_src_construct(clk_src, ctx, bios, id, 1641 regs, &cs_shift, &cs_mask)) { 1642 clk_src->base.dp_clk_src = dp_clk_src; 1643 return &clk_src->base; 1644 } 1645 1646 BREAK_TO_DEBUGGER(); 1647 return NULL; 1648 } 1649 1650 static int dcn314_populate_dml_pipes_from_context( 1651 struct dc *dc, struct dc_state *context, 1652 display_e2e_pipe_params_st *pipes, 1653 bool fast_validate) 1654 { 1655 int pipe_cnt; 1656 1657 DC_FP_START(); 1658 pipe_cnt = dcn314_populate_dml_pipes_from_context_fpu(dc, context, pipes, fast_validate); 1659 DC_FP_END(); 1660 1661 return pipe_cnt; 1662 } 1663 1664 static struct dc_cap_funcs cap_funcs = { 1665 .get_dcc_compression_cap = dcn20_get_dcc_compression_cap 1666 }; 1667 1668 static void dcn314_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params) 1669 { 1670 DC_FP_START(); 1671 dcn314_update_bw_bounding_box_fpu(dc, bw_params); 1672 DC_FP_END(); 1673 } 1674 1675 static struct resource_funcs dcn314_res_pool_funcs = { 1676 .destroy = dcn314_destroy_resource_pool, 1677 .link_enc_create = dcn31_link_encoder_create, 1678 .link_enc_create_minimal = dcn31_link_enc_create_minimal, 1679 .link_encs_assign = link_enc_cfg_link_encs_assign, 1680 .link_enc_unassign = link_enc_cfg_link_enc_unassign, 1681 .panel_cntl_create = dcn31_panel_cntl_create, 1682 .validate_bandwidth = dcn31_validate_bandwidth, 1683 .calculate_wm_and_dlg = dcn31_calculate_wm_and_dlg, 1684 .update_soc_for_wm_a = dcn31_update_soc_for_wm_a, 1685 .populate_dml_pipes = dcn314_populate_dml_pipes_from_context, 1686 .acquire_idle_pipe_for_layer = dcn20_acquire_idle_pipe_for_layer, 1687 .add_stream_to_ctx = dcn30_add_stream_to_ctx, 1688 .add_dsc_to_stream_resource = dcn20_add_dsc_to_stream_resource, 1689 .remove_stream_from_ctx = dcn20_remove_stream_from_ctx, 1690 .populate_dml_writeback_from_context = dcn30_populate_dml_writeback_from_context, 1691 .set_mcif_arb_params = dcn30_set_mcif_arb_params, 1692 .find_first_free_match_stream_enc_for_link = dcn10_find_first_free_match_stream_enc_for_link, 1693 .acquire_post_bldn_3dlut = dcn30_acquire_post_bldn_3dlut, 1694 .release_post_bldn_3dlut = dcn30_release_post_bldn_3dlut, 1695 .update_bw_bounding_box = dcn314_update_bw_bounding_box, 1696 .patch_unknown_plane_state = dcn20_patch_unknown_plane_state, 1697 }; 1698 1699 static struct clock_source *dcn30_clock_source_create( 1700 struct dc_context *ctx, 1701 struct dc_bios *bios, 1702 enum clock_source_id id, 1703 const struct dce110_clk_src_regs *regs, 1704 bool dp_clk_src) 1705 { 1706 struct dce110_clk_src *clk_src = 1707 kzalloc(sizeof(struct dce110_clk_src), GFP_KERNEL); 1708 1709 if (!clk_src) 1710 return NULL; 1711 1712 if (dcn31_clk_src_construct(clk_src, ctx, bios, id, 1713 regs, &cs_shift, &cs_mask)) { 1714 clk_src->base.dp_clk_src = dp_clk_src; 1715 return &clk_src->base; 1716 } 1717 1718 BREAK_TO_DEBUGGER(); 1719 return NULL; 1720 } 1721 1722 static bool dcn314_resource_construct( 1723 uint8_t num_virtual_links, 1724 struct dc *dc, 1725 struct dcn314_resource_pool *pool) 1726 { 1727 int i; 1728 struct dc_context *ctx = dc->ctx; 1729 struct irq_service_init_data init_data; 1730 1731 ctx->dc_bios->regs = &bios_regs; 1732 1733 pool->base.res_cap = &res_cap_dcn314; 1734 pool->base.funcs = &dcn314_res_pool_funcs; 1735 1736 /************************************************* 1737 * Resource + asic cap harcoding * 1738 *************************************************/ 1739 pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE; 1740 pool->base.pipe_count = pool->base.res_cap->num_timing_generator; 1741 pool->base.mpcc_count = pool->base.res_cap->num_timing_generator; 1742 dc->caps.max_downscale_ratio = 600; 1743 dc->caps.i2c_speed_in_khz = 100; 1744 dc->caps.i2c_speed_in_khz_hdcp = 100; 1745 dc->caps.max_cursor_size = 256; 1746 dc->caps.min_horizontal_blanking_period = 80; 1747 dc->caps.dmdata_alloc_size = 2048; 1748 dc->caps.max_slave_planes = 2; 1749 dc->caps.max_slave_yuv_planes = 2; 1750 dc->caps.max_slave_rgb_planes = 2; 1751 dc->caps.post_blend_color_processing = true; 1752 dc->caps.force_dp_tps4_for_cp2520 = true; 1753 dc->caps.dp_hpo = true; 1754 dc->caps.dp_hdmi21_pcon_support = true; 1755 dc->caps.edp_dsc_support = true; 1756 dc->caps.extended_aux_timeout_support = true; 1757 dc->caps.dmcub_support = true; 1758 dc->caps.is_apu = true; 1759 dc->caps.seamless_odm = true; 1760 1761 dc->caps.zstate_support = true; 1762 1763 /* Color pipeline capabilities */ 1764 dc->caps.color.dpp.dcn_arch = 1; 1765 dc->caps.color.dpp.input_lut_shared = 0; 1766 dc->caps.color.dpp.icsc = 1; 1767 dc->caps.color.dpp.dgam_ram = 0; // must use gamma_corr 1768 dc->caps.color.dpp.dgam_rom_caps.srgb = 1; 1769 dc->caps.color.dpp.dgam_rom_caps.bt2020 = 1; 1770 dc->caps.color.dpp.dgam_rom_caps.gamma2_2 = 1; 1771 dc->caps.color.dpp.dgam_rom_caps.pq = 1; 1772 dc->caps.color.dpp.dgam_rom_caps.hlg = 1; 1773 dc->caps.color.dpp.post_csc = 1; 1774 dc->caps.color.dpp.gamma_corr = 1; 1775 dc->caps.color.dpp.dgam_rom_for_yuv = 0; 1776 1777 dc->caps.color.dpp.hw_3d_lut = 1; 1778 dc->caps.color.dpp.ogam_ram = 1; 1779 // no OGAM ROM on DCN301 1780 dc->caps.color.dpp.ogam_rom_caps.srgb = 0; 1781 dc->caps.color.dpp.ogam_rom_caps.bt2020 = 0; 1782 dc->caps.color.dpp.ogam_rom_caps.gamma2_2 = 0; 1783 dc->caps.color.dpp.ogam_rom_caps.pq = 0; 1784 dc->caps.color.dpp.ogam_rom_caps.hlg = 0; 1785 dc->caps.color.dpp.ocsc = 0; 1786 1787 dc->caps.color.mpc.gamut_remap = 1; 1788 dc->caps.color.mpc.num_3dluts = pool->base.res_cap->num_mpc_3dlut; //2 1789 dc->caps.color.mpc.ogam_ram = 1; 1790 dc->caps.color.mpc.ogam_rom_caps.srgb = 0; 1791 dc->caps.color.mpc.ogam_rom_caps.bt2020 = 0; 1792 dc->caps.color.mpc.ogam_rom_caps.gamma2_2 = 0; 1793 dc->caps.color.mpc.ogam_rom_caps.pq = 0; 1794 dc->caps.color.mpc.ogam_rom_caps.hlg = 0; 1795 dc->caps.color.mpc.ocsc = 1; 1796 1797 /* Use pipe context based otg sync logic */ 1798 dc->config.use_pipe_ctx_sync_logic = true; 1799 1800 /* read VBIOS LTTPR caps */ 1801 { 1802 if (ctx->dc_bios->funcs->get_lttpr_caps) { 1803 enum bp_result bp_query_result; 1804 uint8_t is_vbios_lttpr_enable = 0; 1805 1806 bp_query_result = ctx->dc_bios->funcs->get_lttpr_caps(ctx->dc_bios, &is_vbios_lttpr_enable); 1807 dc->caps.vbios_lttpr_enable = (bp_query_result == BP_RESULT_OK) && !!is_vbios_lttpr_enable; 1808 } 1809 1810 /* interop bit is implicit */ 1811 { 1812 dc->caps.vbios_lttpr_aware = true; 1813 } 1814 } 1815 1816 if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV) 1817 dc->debug = debug_defaults_drv; 1818 else if (dc->ctx->dce_environment == DCE_ENV_FPGA_MAXIMUS) 1819 dc->debug = debug_defaults_diags; 1820 else 1821 dc->debug = debug_defaults_diags; 1822 // Init the vm_helper 1823 if (dc->vm_helper) 1824 vm_helper_init(dc->vm_helper, 16); 1825 1826 /************************************************* 1827 * Create resources * 1828 *************************************************/ 1829 1830 /* Clock Sources for Pixel Clock*/ 1831 pool->base.clock_sources[DCN31_CLK_SRC_PLL0] = 1832 dcn30_clock_source_create(ctx, ctx->dc_bios, 1833 CLOCK_SOURCE_COMBO_PHY_PLL0, 1834 &clk_src_regs[0], false); 1835 pool->base.clock_sources[DCN31_CLK_SRC_PLL1] = 1836 dcn30_clock_source_create(ctx, ctx->dc_bios, 1837 CLOCK_SOURCE_COMBO_PHY_PLL1, 1838 &clk_src_regs[1], false); 1839 pool->base.clock_sources[DCN31_CLK_SRC_PLL2] = 1840 dcn30_clock_source_create(ctx, ctx->dc_bios, 1841 CLOCK_SOURCE_COMBO_PHY_PLL2, 1842 &clk_src_regs[2], false); 1843 pool->base.clock_sources[DCN31_CLK_SRC_PLL3] = 1844 dcn30_clock_source_create(ctx, ctx->dc_bios, 1845 CLOCK_SOURCE_COMBO_PHY_PLL3, 1846 &clk_src_regs[3], false); 1847 pool->base.clock_sources[DCN31_CLK_SRC_PLL4] = 1848 dcn30_clock_source_create(ctx, ctx->dc_bios, 1849 CLOCK_SOURCE_COMBO_PHY_PLL4, 1850 &clk_src_regs[4], false); 1851 1852 pool->base.clk_src_count = DCN30_CLK_SRC_TOTAL; 1853 1854 /* todo: not reuse phy_pll registers */ 1855 pool->base.dp_clock_source = 1856 dcn31_clock_source_create(ctx, ctx->dc_bios, 1857 CLOCK_SOURCE_ID_DP_DTO, 1858 &clk_src_regs[0], true); 1859 1860 for (i = 0; i < pool->base.clk_src_count; i++) { 1861 if (pool->base.clock_sources[i] == NULL) { 1862 dm_error("DC: failed to create clock sources!\n"); 1863 BREAK_TO_DEBUGGER(); 1864 goto create_fail; 1865 } 1866 } 1867 1868 pool->base.dccg = dccg314_create(ctx, &dccg_regs, &dccg_shift, &dccg_mask); 1869 if (pool->base.dccg == NULL) { 1870 dm_error("DC: failed to create dccg!\n"); 1871 BREAK_TO_DEBUGGER(); 1872 goto create_fail; 1873 } 1874 1875 init_data.ctx = dc->ctx; 1876 pool->base.irqs = dal_irq_service_dcn314_create(&init_data); 1877 if (!pool->base.irqs) 1878 goto create_fail; 1879 1880 /* HUBBUB */ 1881 pool->base.hubbub = dcn31_hubbub_create(ctx); 1882 if (pool->base.hubbub == NULL) { 1883 BREAK_TO_DEBUGGER(); 1884 dm_error("DC: failed to create hubbub!\n"); 1885 goto create_fail; 1886 } 1887 1888 /* HUBPs, DPPs, OPPs and TGs */ 1889 for (i = 0; i < pool->base.pipe_count; i++) { 1890 pool->base.hubps[i] = dcn31_hubp_create(ctx, i); 1891 if (pool->base.hubps[i] == NULL) { 1892 BREAK_TO_DEBUGGER(); 1893 dm_error( 1894 "DC: failed to create hubps!\n"); 1895 goto create_fail; 1896 } 1897 1898 pool->base.dpps[i] = dcn31_dpp_create(ctx, i); 1899 if (pool->base.dpps[i] == NULL) { 1900 BREAK_TO_DEBUGGER(); 1901 dm_error( 1902 "DC: failed to create dpps!\n"); 1903 goto create_fail; 1904 } 1905 } 1906 1907 for (i = 0; i < pool->base.res_cap->num_opp; i++) { 1908 pool->base.opps[i] = dcn31_opp_create(ctx, i); 1909 if (pool->base.opps[i] == NULL) { 1910 BREAK_TO_DEBUGGER(); 1911 dm_error( 1912 "DC: failed to create output pixel processor!\n"); 1913 goto create_fail; 1914 } 1915 } 1916 1917 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { 1918 pool->base.timing_generators[i] = dcn31_timing_generator_create( 1919 ctx, i); 1920 if (pool->base.timing_generators[i] == NULL) { 1921 BREAK_TO_DEBUGGER(); 1922 dm_error("DC: failed to create tg!\n"); 1923 goto create_fail; 1924 } 1925 } 1926 pool->base.timing_generator_count = i; 1927 1928 /* PSR */ 1929 pool->base.psr = dmub_psr_create(ctx); 1930 if (pool->base.psr == NULL) { 1931 dm_error("DC: failed to create psr obj!\n"); 1932 BREAK_TO_DEBUGGER(); 1933 goto create_fail; 1934 } 1935 1936 /* ABM */ 1937 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { 1938 pool->base.multiple_abms[i] = dmub_abm_create(ctx, 1939 &abm_regs[i], 1940 &abm_shift, 1941 &abm_mask); 1942 if (pool->base.multiple_abms[i] == NULL) { 1943 dm_error("DC: failed to create abm for pipe %d!\n", i); 1944 BREAK_TO_DEBUGGER(); 1945 goto create_fail; 1946 } 1947 } 1948 1949 /* MPC and DSC */ 1950 pool->base.mpc = dcn31_mpc_create(ctx, pool->base.mpcc_count, pool->base.res_cap->num_mpc_3dlut); 1951 if (pool->base.mpc == NULL) { 1952 BREAK_TO_DEBUGGER(); 1953 dm_error("DC: failed to create mpc!\n"); 1954 goto create_fail; 1955 } 1956 1957 for (i = 0; i < pool->base.res_cap->num_dsc; i++) { 1958 pool->base.dscs[i] = dcn314_dsc_create(ctx, i); 1959 if (pool->base.dscs[i] == NULL) { 1960 BREAK_TO_DEBUGGER(); 1961 dm_error("DC: failed to create display stream compressor %d!\n", i); 1962 goto create_fail; 1963 } 1964 } 1965 1966 /* DWB and MMHUBBUB */ 1967 if (!dcn31_dwbc_create(ctx, &pool->base)) { 1968 BREAK_TO_DEBUGGER(); 1969 dm_error("DC: failed to create dwbc!\n"); 1970 goto create_fail; 1971 } 1972 1973 if (!dcn31_mmhubbub_create(ctx, &pool->base)) { 1974 BREAK_TO_DEBUGGER(); 1975 dm_error("DC: failed to create mcif_wb!\n"); 1976 goto create_fail; 1977 } 1978 1979 /* AUX and I2C */ 1980 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { 1981 pool->base.engines[i] = dcn31_aux_engine_create(ctx, i); 1982 if (pool->base.engines[i] == NULL) { 1983 BREAK_TO_DEBUGGER(); 1984 dm_error( 1985 "DC:failed to create aux engine!!\n"); 1986 goto create_fail; 1987 } 1988 pool->base.hw_i2cs[i] = dcn31_i2c_hw_create(ctx, i); 1989 if (pool->base.hw_i2cs[i] == NULL) { 1990 BREAK_TO_DEBUGGER(); 1991 dm_error( 1992 "DC:failed to create hw i2c!!\n"); 1993 goto create_fail; 1994 } 1995 pool->base.sw_i2cs[i] = NULL; 1996 } 1997 1998 /* DCN314 has 4 DPIA */ 1999 pool->base.usb4_dpia_count = 4; 2000 2001 /* Audio, Stream Encoders including HPO and virtual, MPC 3D LUTs */ 2002 if (!resource_construct(num_virtual_links, dc, &pool->base, 2003 (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment) ? 2004 &res_create_funcs : &res_create_maximus_funcs))) 2005 goto create_fail; 2006 2007 /* HW Sequencer and Plane caps */ 2008 dcn314_hw_sequencer_construct(dc); 2009 2010 dc->caps.max_planes = pool->base.pipe_count; 2011 2012 for (i = 0; i < dc->caps.max_planes; ++i) 2013 dc->caps.planes[i] = plane_cap; 2014 2015 dc->cap_funcs = cap_funcs; 2016 2017 dc->dcn_ip->max_num_dpp = dcn3_14_ip.max_num_dpp; 2018 2019 return true; 2020 2021 create_fail: 2022 2023 dcn314_resource_destruct(pool); 2024 2025 return false; 2026 } 2027 2028 struct resource_pool *dcn314_create_resource_pool( 2029 const struct dc_init_data *init_data, 2030 struct dc *dc) 2031 { 2032 struct dcn314_resource_pool *pool = 2033 kzalloc(sizeof(struct dcn314_resource_pool), GFP_KERNEL); 2034 2035 if (!pool) 2036 return NULL; 2037 2038 if (dcn314_resource_construct(init_data->num_virtual_links, dc, pool)) 2039 return &pool->base; 2040 2041 BREAK_TO_DEBUGGER(); 2042 kfree(pool); 2043 return NULL; 2044 } 2045