1 // SPDX-License-Identifier: MIT 2 /* 3 * Copyright 2022 Advanced Micro Devices, Inc. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 * 23 * Authors: AMD 24 * 25 */ 26 27 28 #include "dm_services.h" 29 #include "dc.h" 30 31 #include "dcn31/dcn31_init.h" 32 #include "dcn314/dcn314_init.h" 33 34 #include "resource.h" 35 #include "include/irq_service_interface.h" 36 #include "dcn314_resource.h" 37 38 #include "dcn20/dcn20_resource.h" 39 #include "dcn30/dcn30_resource.h" 40 #include "dcn31/dcn31_resource.h" 41 42 #include "dcn10/dcn10_ipp.h" 43 #include "dcn30/dcn30_hubbub.h" 44 #include "dcn31/dcn31_hubbub.h" 45 #include "dcn30/dcn30_mpc.h" 46 #include "dcn31/dcn31_hubp.h" 47 #include "irq/dcn31/irq_service_dcn31.h" 48 #include "irq/dcn314/irq_service_dcn314.h" 49 #include "dcn30/dcn30_dpp.h" 50 #include "dcn314/dcn314_optc.h" 51 #include "dcn20/dcn20_hwseq.h" 52 #include "dcn30/dcn30_hwseq.h" 53 #include "dce110/dce110_hw_sequencer.h" 54 #include "dcn30/dcn30_opp.h" 55 #include "dcn20/dcn20_dsc.h" 56 #include "dcn30/dcn30_vpg.h" 57 #include "dcn30/dcn30_afmt.h" 58 #include "dcn31/dcn31_dio_link_encoder.h" 59 #include "dcn314/dcn314_dio_stream_encoder.h" 60 #include "dcn31/dcn31_hpo_dp_stream_encoder.h" 61 #include "dcn31/dcn31_hpo_dp_link_encoder.h" 62 #include "dcn31/dcn31_apg.h" 63 #include "dcn31/dcn31_vpg.h" 64 #include "dcn31/dcn31_afmt.h" 65 #include "dce/dce_clock_source.h" 66 #include "dce/dce_audio.h" 67 #include "dce/dce_hwseq.h" 68 #include "clk_mgr.h" 69 #include "virtual/virtual_stream_encoder.h" 70 #include "dce110/dce110_resource.h" 71 #include "dml/display_mode_vba.h" 72 #include "dml/dcn31/dcn31_fpu.h" 73 #include "dml/dcn314/dcn314_fpu.h" 74 #include "dcn314/dcn314_dccg.h" 75 #include "dcn10/dcn10_resource.h" 76 #include "dcn31/dcn31_panel_cntl.h" 77 #include "dcn314/dcn314_hwseq.h" 78 79 #include "dcn30/dcn30_dwb.h" 80 #include "dcn30/dcn30_mmhubbub.h" 81 82 #include "dcn/dcn_3_1_4_offset.h" 83 #include "dcn/dcn_3_1_4_sh_mask.h" 84 #include "dpcs/dpcs_3_1_4_offset.h" 85 #include "dpcs/dpcs_3_1_4_sh_mask.h" 86 87 #define DCHUBBUB_DEBUG_CTRL_0__DET_DEPTH__SHIFT 0x10 88 #define DCHUBBUB_DEBUG_CTRL_0__DET_DEPTH_MASK 0x01FF0000L 89 90 #define DSCC0_DSCC_CONFIG0__ICH_RESET_AT_END_OF_LINE__SHIFT 0x0 91 #define DSCC0_DSCC_CONFIG0__ICH_RESET_AT_END_OF_LINE_MASK 0x0000000FL 92 93 #include "reg_helper.h" 94 #include "dce/dmub_abm.h" 95 #include "dce/dmub_psr.h" 96 #include "dce/dce_aux.h" 97 #include "dce/dce_i2c.h" 98 #include "dml/dcn314/display_mode_vba_314.h" 99 #include "vm_helper.h" 100 #include "dcn20/dcn20_vmid.h" 101 102 #include "link_enc_cfg.h" 103 104 #define DCN_BASE__INST0_SEG1 0x000000C0 105 #define DCN_BASE__INST0_SEG2 0x000034C0 106 #define DCN_BASE__INST0_SEG3 0x00009000 107 108 #define NBIO_BASE__INST0_SEG1 0x00000014 109 110 #define MAX_INSTANCE 7 111 #define MAX_SEGMENT 8 112 113 #define regBIF_BX2_BIOS_SCRATCH_2 0x003a 114 #define regBIF_BX2_BIOS_SCRATCH_2_BASE_IDX 1 115 #define regBIF_BX2_BIOS_SCRATCH_3 0x003b 116 #define regBIF_BX2_BIOS_SCRATCH_3_BASE_IDX 1 117 #define regBIF_BX2_BIOS_SCRATCH_6 0x003e 118 #define regBIF_BX2_BIOS_SCRATCH_6_BASE_IDX 1 119 120 #define DC_LOGGER_INIT(logger) 121 122 enum dcn31_clk_src_array_id { 123 DCN31_CLK_SRC_PLL0, 124 DCN31_CLK_SRC_PLL1, 125 DCN31_CLK_SRC_PLL2, 126 DCN31_CLK_SRC_PLL3, 127 DCN31_CLK_SRC_PLL4, 128 DCN30_CLK_SRC_TOTAL 129 }; 130 131 /* begin ********************* 132 * macros to expend register list macro defined in HW object header file 133 */ 134 135 /* DCN */ 136 /* TODO awful hack. fixup dcn20_dwb.h */ 137 #undef BASE_INNER 138 #define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg 139 140 #define BASE(seg) BASE_INNER(seg) 141 142 #define SR(reg_name)\ 143 .reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \ 144 reg ## reg_name 145 146 #define SRI(reg_name, block, id)\ 147 .reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 148 reg ## block ## id ## _ ## reg_name 149 150 #define SRI2(reg_name, block, id)\ 151 .reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \ 152 reg ## reg_name 153 154 #define SRIR(var_name, reg_name, block, id)\ 155 .var_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 156 reg ## block ## id ## _ ## reg_name 157 158 #define SRII(reg_name, block, id)\ 159 .reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 160 reg ## block ## id ## _ ## reg_name 161 162 #define SRII_MPC_RMU(reg_name, block, id)\ 163 .RMU##_##reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 164 reg ## block ## id ## _ ## reg_name 165 166 #define SRII_DWB(reg_name, temp_name, block, id)\ 167 .reg_name[id] = BASE(reg ## block ## id ## _ ## temp_name ## _BASE_IDX) + \ 168 reg ## block ## id ## _ ## temp_name 169 170 #define SF_DWB2(reg_name, block, id, field_name, post_fix) \ 171 .field_name = reg_name ## __ ## field_name ## post_fix 172 173 #define DCCG_SRII(reg_name, block, id)\ 174 .block ## _ ## reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 175 reg ## block ## id ## _ ## reg_name 176 177 #define VUPDATE_SRII(reg_name, block, id)\ 178 .reg_name[id] = BASE(reg ## reg_name ## _ ## block ## id ## _BASE_IDX) + \ 179 reg ## reg_name ## _ ## block ## id 180 181 /* NBIO */ 182 #define NBIO_BASE_INNER(seg) \ 183 NBIO_BASE__INST0_SEG ## seg 184 185 #define NBIO_BASE(seg) \ 186 NBIO_BASE_INNER(seg) 187 188 #define NBIO_SR(reg_name)\ 189 .reg_name = NBIO_BASE(regBIF_BX2_ ## reg_name ## _BASE_IDX) + \ 190 regBIF_BX2_ ## reg_name 191 192 /* MMHUB */ 193 #define MMHUB_BASE_INNER(seg) \ 194 MMHUB_BASE__INST0_SEG ## seg 195 196 #define MMHUB_BASE(seg) \ 197 MMHUB_BASE_INNER(seg) 198 199 #define MMHUB_SR(reg_name)\ 200 .reg_name = MMHUB_BASE(reg ## reg_name ## _BASE_IDX) + \ 201 reg ## reg_name 202 203 /* CLOCK */ 204 #define CLK_BASE_INNER(seg) \ 205 CLK_BASE__INST0_SEG ## seg 206 207 #define CLK_BASE(seg) \ 208 CLK_BASE_INNER(seg) 209 210 #define CLK_SRI(reg_name, block, inst)\ 211 .reg_name = CLK_BASE(reg ## block ## _ ## inst ## _ ## reg_name ## _BASE_IDX) + \ 212 reg ## block ## _ ## inst ## _ ## reg_name 213 214 215 static const struct bios_registers bios_regs = { 216 NBIO_SR(BIOS_SCRATCH_3), 217 NBIO_SR(BIOS_SCRATCH_6) 218 }; 219 220 #define clk_src_regs(index, pllid)\ 221 [index] = {\ 222 CS_COMMON_REG_LIST_DCN3_0(index, pllid),\ 223 } 224 225 static const struct dce110_clk_src_regs clk_src_regs[] = { 226 clk_src_regs(0, A), 227 clk_src_regs(1, B), 228 clk_src_regs(2, C), 229 clk_src_regs(3, D), 230 clk_src_regs(4, E) 231 }; 232 233 static const struct dce110_clk_src_shift cs_shift = { 234 CS_COMMON_MASK_SH_LIST_DCN3_1_4(__SHIFT) 235 }; 236 237 static const struct dce110_clk_src_mask cs_mask = { 238 CS_COMMON_MASK_SH_LIST_DCN3_1_4(_MASK) 239 }; 240 241 #define abm_regs(id)\ 242 [id] = {\ 243 ABM_DCN302_REG_LIST(id)\ 244 } 245 246 static const struct dce_abm_registers abm_regs[] = { 247 abm_regs(0), 248 abm_regs(1), 249 abm_regs(2), 250 abm_regs(3), 251 }; 252 253 static const struct dce_abm_shift abm_shift = { 254 ABM_MASK_SH_LIST_DCN30(__SHIFT) 255 }; 256 257 static const struct dce_abm_mask abm_mask = { 258 ABM_MASK_SH_LIST_DCN30(_MASK) 259 }; 260 261 #define audio_regs(id)\ 262 [id] = {\ 263 AUD_COMMON_REG_LIST(id)\ 264 } 265 266 static const struct dce_audio_registers audio_regs[] = { 267 audio_regs(0), 268 audio_regs(1), 269 audio_regs(2), 270 audio_regs(3), 271 audio_regs(4), 272 audio_regs(5), 273 audio_regs(6) 274 }; 275 276 #define DCE120_AUD_COMMON_MASK_SH_LIST(mask_sh)\ 277 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX, AZALIA_ENDPOINT_REG_INDEX, mask_sh),\ 278 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA, AZALIA_ENDPOINT_REG_DATA, mask_sh),\ 279 AUD_COMMON_MASK_SH_LIST_BASE(mask_sh) 280 281 static const struct dce_audio_shift audio_shift = { 282 DCE120_AUD_COMMON_MASK_SH_LIST(__SHIFT) 283 }; 284 285 static const struct dce_audio_mask audio_mask = { 286 DCE120_AUD_COMMON_MASK_SH_LIST(_MASK) 287 }; 288 289 #define vpg_regs(id)\ 290 [id] = {\ 291 VPG_DCN31_REG_LIST(id)\ 292 } 293 294 static const struct dcn31_vpg_registers vpg_regs[] = { 295 vpg_regs(0), 296 vpg_regs(1), 297 vpg_regs(2), 298 vpg_regs(3), 299 vpg_regs(4), 300 vpg_regs(5), 301 vpg_regs(6), 302 vpg_regs(7), 303 vpg_regs(8), 304 vpg_regs(9), 305 }; 306 307 static const struct dcn31_vpg_shift vpg_shift = { 308 DCN31_VPG_MASK_SH_LIST(__SHIFT) 309 }; 310 311 static const struct dcn31_vpg_mask vpg_mask = { 312 DCN31_VPG_MASK_SH_LIST(_MASK) 313 }; 314 315 #define afmt_regs(id)\ 316 [id] = {\ 317 AFMT_DCN31_REG_LIST(id)\ 318 } 319 320 static const struct dcn31_afmt_registers afmt_regs[] = { 321 afmt_regs(0), 322 afmt_regs(1), 323 afmt_regs(2), 324 afmt_regs(3), 325 afmt_regs(4), 326 afmt_regs(5) 327 }; 328 329 static const struct dcn31_afmt_shift afmt_shift = { 330 DCN31_AFMT_MASK_SH_LIST(__SHIFT) 331 }; 332 333 static const struct dcn31_afmt_mask afmt_mask = { 334 DCN31_AFMT_MASK_SH_LIST(_MASK) 335 }; 336 337 #define apg_regs(id)\ 338 [id] = {\ 339 APG_DCN31_REG_LIST(id)\ 340 } 341 342 static const struct dcn31_apg_registers apg_regs[] = { 343 apg_regs(0), 344 apg_regs(1), 345 apg_regs(2), 346 apg_regs(3) 347 }; 348 349 static const struct dcn31_apg_shift apg_shift = { 350 DCN31_APG_MASK_SH_LIST(__SHIFT) 351 }; 352 353 static const struct dcn31_apg_mask apg_mask = { 354 DCN31_APG_MASK_SH_LIST(_MASK) 355 }; 356 357 #define stream_enc_regs(id)\ 358 [id] = {\ 359 SE_DCN314_REG_LIST(id)\ 360 } 361 362 static const struct dcn10_stream_enc_registers stream_enc_regs[] = { 363 stream_enc_regs(0), 364 stream_enc_regs(1), 365 stream_enc_regs(2), 366 stream_enc_regs(3), 367 stream_enc_regs(4) 368 }; 369 370 static const struct dcn10_stream_encoder_shift se_shift = { 371 SE_COMMON_MASK_SH_LIST_DCN314(__SHIFT) 372 }; 373 374 static const struct dcn10_stream_encoder_mask se_mask = { 375 SE_COMMON_MASK_SH_LIST_DCN314(_MASK) 376 }; 377 378 379 #define aux_regs(id)\ 380 [id] = {\ 381 DCN2_AUX_REG_LIST(id)\ 382 } 383 384 static const struct dcn10_link_enc_aux_registers link_enc_aux_regs[] = { 385 aux_regs(0), 386 aux_regs(1), 387 aux_regs(2), 388 aux_regs(3), 389 aux_regs(4) 390 }; 391 392 #define hpd_regs(id)\ 393 [id] = {\ 394 HPD_REG_LIST(id)\ 395 } 396 397 static const struct dcn10_link_enc_hpd_registers link_enc_hpd_regs[] = { 398 hpd_regs(0), 399 hpd_regs(1), 400 hpd_regs(2), 401 hpd_regs(3), 402 hpd_regs(4) 403 }; 404 405 #define link_regs(id, phyid)\ 406 [id] = {\ 407 LE_DCN31_REG_LIST(id), \ 408 UNIPHY_DCN2_REG_LIST(phyid), \ 409 } 410 411 static const struct dce110_aux_registers_shift aux_shift = { 412 DCN_AUX_MASK_SH_LIST(__SHIFT) 413 }; 414 415 static const struct dce110_aux_registers_mask aux_mask = { 416 DCN_AUX_MASK_SH_LIST(_MASK) 417 }; 418 419 static const struct dcn10_link_enc_registers link_enc_regs[] = { 420 link_regs(0, A), 421 link_regs(1, B), 422 link_regs(2, C), 423 link_regs(3, D), 424 link_regs(4, E) 425 }; 426 427 static const struct dcn10_link_enc_shift le_shift = { 428 LINK_ENCODER_MASK_SH_LIST_DCN31(__SHIFT), 429 DPCS_DCN31_MASK_SH_LIST(__SHIFT) 430 }; 431 432 static const struct dcn10_link_enc_mask le_mask = { 433 LINK_ENCODER_MASK_SH_LIST_DCN31(_MASK), 434 DPCS_DCN31_MASK_SH_LIST(_MASK) 435 }; 436 437 #define hpo_dp_stream_encoder_reg_list(id)\ 438 [id] = {\ 439 DCN3_1_HPO_DP_STREAM_ENC_REG_LIST(id)\ 440 } 441 442 static const struct dcn31_hpo_dp_stream_encoder_registers hpo_dp_stream_enc_regs[] = { 443 hpo_dp_stream_encoder_reg_list(0), 444 hpo_dp_stream_encoder_reg_list(1), 445 hpo_dp_stream_encoder_reg_list(2), 446 hpo_dp_stream_encoder_reg_list(3) 447 }; 448 449 static const struct dcn31_hpo_dp_stream_encoder_shift hpo_dp_se_shift = { 450 DCN3_1_HPO_DP_STREAM_ENC_MASK_SH_LIST(__SHIFT) 451 }; 452 453 static const struct dcn31_hpo_dp_stream_encoder_mask hpo_dp_se_mask = { 454 DCN3_1_HPO_DP_STREAM_ENC_MASK_SH_LIST(_MASK) 455 }; 456 457 458 #define hpo_dp_link_encoder_reg_list(id)\ 459 [id] = {\ 460 DCN3_1_HPO_DP_LINK_ENC_REG_LIST(id),\ 461 DCN3_1_RDPCSTX_REG_LIST(0),\ 462 DCN3_1_RDPCSTX_REG_LIST(1),\ 463 DCN3_1_RDPCSTX_REG_LIST(2),\ 464 } 465 466 static const struct dcn31_hpo_dp_link_encoder_registers hpo_dp_link_enc_regs[] = { 467 hpo_dp_link_encoder_reg_list(0), 468 hpo_dp_link_encoder_reg_list(1), 469 }; 470 471 static const struct dcn31_hpo_dp_link_encoder_shift hpo_dp_le_shift = { 472 DCN3_1_HPO_DP_LINK_ENC_MASK_SH_LIST(__SHIFT) 473 }; 474 475 static const struct dcn31_hpo_dp_link_encoder_mask hpo_dp_le_mask = { 476 DCN3_1_HPO_DP_LINK_ENC_MASK_SH_LIST(_MASK) 477 }; 478 479 #define dpp_regs(id)\ 480 [id] = {\ 481 DPP_REG_LIST_DCN30(id),\ 482 } 483 484 static const struct dcn3_dpp_registers dpp_regs[] = { 485 dpp_regs(0), 486 dpp_regs(1), 487 dpp_regs(2), 488 dpp_regs(3) 489 }; 490 491 static const struct dcn3_dpp_shift tf_shift = { 492 DPP_REG_LIST_SH_MASK_DCN30(__SHIFT) 493 }; 494 495 static const struct dcn3_dpp_mask tf_mask = { 496 DPP_REG_LIST_SH_MASK_DCN30(_MASK) 497 }; 498 499 #define opp_regs(id)\ 500 [id] = {\ 501 OPP_REG_LIST_DCN30(id),\ 502 } 503 504 static const struct dcn20_opp_registers opp_regs[] = { 505 opp_regs(0), 506 opp_regs(1), 507 opp_regs(2), 508 opp_regs(3) 509 }; 510 511 static const struct dcn20_opp_shift opp_shift = { 512 OPP_MASK_SH_LIST_DCN20(__SHIFT) 513 }; 514 515 static const struct dcn20_opp_mask opp_mask = { 516 OPP_MASK_SH_LIST_DCN20(_MASK) 517 }; 518 519 #define aux_engine_regs(id)\ 520 [id] = {\ 521 AUX_COMMON_REG_LIST0(id), \ 522 .AUXN_IMPCAL = 0, \ 523 .AUXP_IMPCAL = 0, \ 524 .AUX_RESET_MASK = DP_AUX0_AUX_CONTROL__AUX_RESET_MASK, \ 525 } 526 527 static const struct dce110_aux_registers aux_engine_regs[] = { 528 aux_engine_regs(0), 529 aux_engine_regs(1), 530 aux_engine_regs(2), 531 aux_engine_regs(3), 532 aux_engine_regs(4) 533 }; 534 535 #define dwbc_regs_dcn3(id)\ 536 [id] = {\ 537 DWBC_COMMON_REG_LIST_DCN30(id),\ 538 } 539 540 static const struct dcn30_dwbc_registers dwbc30_regs[] = { 541 dwbc_regs_dcn3(0), 542 }; 543 544 static const struct dcn30_dwbc_shift dwbc30_shift = { 545 DWBC_COMMON_MASK_SH_LIST_DCN30(__SHIFT) 546 }; 547 548 static const struct dcn30_dwbc_mask dwbc30_mask = { 549 DWBC_COMMON_MASK_SH_LIST_DCN30(_MASK) 550 }; 551 552 #define mcif_wb_regs_dcn3(id)\ 553 [id] = {\ 554 MCIF_WB_COMMON_REG_LIST_DCN30(id),\ 555 } 556 557 static const struct dcn30_mmhubbub_registers mcif_wb30_regs[] = { 558 mcif_wb_regs_dcn3(0) 559 }; 560 561 static const struct dcn30_mmhubbub_shift mcif_wb30_shift = { 562 MCIF_WB_COMMON_MASK_SH_LIST_DCN30(__SHIFT) 563 }; 564 565 static const struct dcn30_mmhubbub_mask mcif_wb30_mask = { 566 MCIF_WB_COMMON_MASK_SH_LIST_DCN30(_MASK) 567 }; 568 569 #define dsc_regsDCN314(id)\ 570 [id] = {\ 571 DSC_REG_LIST_DCN20(id)\ 572 } 573 574 static const struct dcn20_dsc_registers dsc_regs[] = { 575 dsc_regsDCN314(0), 576 dsc_regsDCN314(1), 577 dsc_regsDCN314(2), 578 dsc_regsDCN314(3) 579 }; 580 581 static const struct dcn20_dsc_shift dsc_shift = { 582 DSC_REG_LIST_SH_MASK_DCN20(__SHIFT) 583 }; 584 585 static const struct dcn20_dsc_mask dsc_mask = { 586 DSC_REG_LIST_SH_MASK_DCN20(_MASK) 587 }; 588 589 static const struct dcn30_mpc_registers mpc_regs = { 590 MPC_REG_LIST_DCN3_0(0), 591 MPC_REG_LIST_DCN3_0(1), 592 MPC_REG_LIST_DCN3_0(2), 593 MPC_REG_LIST_DCN3_0(3), 594 MPC_OUT_MUX_REG_LIST_DCN3_0(0), 595 MPC_OUT_MUX_REG_LIST_DCN3_0(1), 596 MPC_OUT_MUX_REG_LIST_DCN3_0(2), 597 MPC_OUT_MUX_REG_LIST_DCN3_0(3), 598 MPC_RMU_GLOBAL_REG_LIST_DCN3AG, 599 MPC_RMU_REG_LIST_DCN3AG(0), 600 MPC_RMU_REG_LIST_DCN3AG(1), 601 //MPC_RMU_REG_LIST_DCN3AG(2), 602 MPC_DWB_MUX_REG_LIST_DCN3_0(0), 603 }; 604 605 static const struct dcn30_mpc_shift mpc_shift = { 606 MPC_COMMON_MASK_SH_LIST_DCN30(__SHIFT) 607 }; 608 609 static const struct dcn30_mpc_mask mpc_mask = { 610 MPC_COMMON_MASK_SH_LIST_DCN30(_MASK) 611 }; 612 613 #define optc_regs(id)\ 614 [id] = {OPTC_COMMON_REG_LIST_DCN3_14(id)} 615 616 static const struct dcn_optc_registers optc_regs[] = { 617 optc_regs(0), 618 optc_regs(1), 619 optc_regs(2), 620 optc_regs(3) 621 }; 622 623 static const struct dcn_optc_shift optc_shift = { 624 OPTC_COMMON_MASK_SH_LIST_DCN3_14(__SHIFT) 625 }; 626 627 static const struct dcn_optc_mask optc_mask = { 628 OPTC_COMMON_MASK_SH_LIST_DCN3_14(_MASK) 629 }; 630 631 #define hubp_regs(id)\ 632 [id] = {\ 633 HUBP_REG_LIST_DCN30(id)\ 634 } 635 636 static const struct dcn_hubp2_registers hubp_regs[] = { 637 hubp_regs(0), 638 hubp_regs(1), 639 hubp_regs(2), 640 hubp_regs(3) 641 }; 642 643 644 static const struct dcn_hubp2_shift hubp_shift = { 645 HUBP_MASK_SH_LIST_DCN31(__SHIFT) 646 }; 647 648 static const struct dcn_hubp2_mask hubp_mask = { 649 HUBP_MASK_SH_LIST_DCN31(_MASK) 650 }; 651 static const struct dcn_hubbub_registers hubbub_reg = { 652 HUBBUB_REG_LIST_DCN31(0) 653 }; 654 655 static const struct dcn_hubbub_shift hubbub_shift = { 656 HUBBUB_MASK_SH_LIST_DCN31(__SHIFT) 657 }; 658 659 static const struct dcn_hubbub_mask hubbub_mask = { 660 HUBBUB_MASK_SH_LIST_DCN31(_MASK) 661 }; 662 663 static const struct dccg_registers dccg_regs = { 664 DCCG_REG_LIST_DCN314() 665 }; 666 667 static const struct dccg_shift dccg_shift = { 668 DCCG_MASK_SH_LIST_DCN314(__SHIFT) 669 }; 670 671 static const struct dccg_mask dccg_mask = { 672 DCCG_MASK_SH_LIST_DCN314(_MASK) 673 }; 674 675 676 #define SRII2(reg_name_pre, reg_name_post, id)\ 677 .reg_name_pre ## _ ## reg_name_post[id] = BASE(reg ## reg_name_pre \ 678 ## id ## _ ## reg_name_post ## _BASE_IDX) + \ 679 reg ## reg_name_pre ## id ## _ ## reg_name_post 680 681 682 #define HWSEQ_DCN31_REG_LIST()\ 683 SR(DCHUBBUB_GLOBAL_TIMER_CNTL), \ 684 SR(DCHUBBUB_ARB_HOSTVM_CNTL), \ 685 SR(DIO_MEM_PWR_CTRL), \ 686 SR(ODM_MEM_PWR_CTRL3), \ 687 SR(DMU_MEM_PWR_CNTL), \ 688 SR(MMHUBBUB_MEM_PWR_CNTL), \ 689 SR(DCCG_GATE_DISABLE_CNTL), \ 690 SR(DCCG_GATE_DISABLE_CNTL2), \ 691 SR(DCFCLK_CNTL),\ 692 SR(DC_MEM_GLOBAL_PWR_REQ_CNTL), \ 693 SRII(PIXEL_RATE_CNTL, OTG, 0), \ 694 SRII(PIXEL_RATE_CNTL, OTG, 1),\ 695 SRII(PIXEL_RATE_CNTL, OTG, 2),\ 696 SRII(PIXEL_RATE_CNTL, OTG, 3),\ 697 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 0),\ 698 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 1),\ 699 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 2),\ 700 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 3),\ 701 SR(MICROSECOND_TIME_BASE_DIV), \ 702 SR(MILLISECOND_TIME_BASE_DIV), \ 703 SR(DISPCLK_FREQ_CHANGE_CNTL), \ 704 SR(RBBMIF_TIMEOUT_DIS), \ 705 SR(RBBMIF_TIMEOUT_DIS_2), \ 706 SR(DCHUBBUB_CRC_CTRL), \ 707 SR(DPP_TOP0_DPP_CRC_CTRL), \ 708 SR(DPP_TOP0_DPP_CRC_VAL_B_A), \ 709 SR(DPP_TOP0_DPP_CRC_VAL_R_G), \ 710 SR(MPC_CRC_CTRL), \ 711 SR(MPC_CRC_RESULT_GB), \ 712 SR(MPC_CRC_RESULT_C), \ 713 SR(MPC_CRC_RESULT_AR), \ 714 SR(DOMAIN0_PG_CONFIG), \ 715 SR(DOMAIN1_PG_CONFIG), \ 716 SR(DOMAIN2_PG_CONFIG), \ 717 SR(DOMAIN3_PG_CONFIG), \ 718 SR(DOMAIN16_PG_CONFIG), \ 719 SR(DOMAIN17_PG_CONFIG), \ 720 SR(DOMAIN18_PG_CONFIG), \ 721 SR(DOMAIN19_PG_CONFIG), \ 722 SR(DOMAIN0_PG_STATUS), \ 723 SR(DOMAIN1_PG_STATUS), \ 724 SR(DOMAIN2_PG_STATUS), \ 725 SR(DOMAIN3_PG_STATUS), \ 726 SR(DOMAIN16_PG_STATUS), \ 727 SR(DOMAIN17_PG_STATUS), \ 728 SR(DOMAIN18_PG_STATUS), \ 729 SR(DOMAIN19_PG_STATUS), \ 730 SR(D1VGA_CONTROL), \ 731 SR(D2VGA_CONTROL), \ 732 SR(D3VGA_CONTROL), \ 733 SR(D4VGA_CONTROL), \ 734 SR(D5VGA_CONTROL), \ 735 SR(D6VGA_CONTROL), \ 736 SR(DC_IP_REQUEST_CNTL), \ 737 SR(AZALIA_AUDIO_DTO), \ 738 SR(AZALIA_CONTROLLER_CLOCK_GATING), \ 739 SR(HPO_TOP_HW_CONTROL) 740 741 static const struct dce_hwseq_registers hwseq_reg = { 742 HWSEQ_DCN31_REG_LIST() 743 }; 744 745 #define HWSEQ_DCN31_MASK_SH_LIST(mask_sh)\ 746 HWSEQ_DCN_MASK_SH_LIST(mask_sh), \ 747 HWS_SF(, DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_REFDIV, mask_sh), \ 748 HWS_SF(, DCHUBBUB_ARB_HOSTVM_CNTL, DISABLE_HOSTVM_FORCE_ALLOW_PSTATE, mask_sh), \ 749 HWS_SF(, DOMAIN0_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ 750 HWS_SF(, DOMAIN0_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ 751 HWS_SF(, DOMAIN1_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ 752 HWS_SF(, DOMAIN1_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ 753 HWS_SF(, DOMAIN2_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ 754 HWS_SF(, DOMAIN2_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ 755 HWS_SF(, DOMAIN3_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ 756 HWS_SF(, DOMAIN3_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ 757 HWS_SF(, DOMAIN16_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ 758 HWS_SF(, DOMAIN16_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ 759 HWS_SF(, DOMAIN17_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ 760 HWS_SF(, DOMAIN17_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ 761 HWS_SF(, DOMAIN18_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ 762 HWS_SF(, DOMAIN18_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ 763 HWS_SF(, DOMAIN19_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ 764 HWS_SF(, DOMAIN19_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ 765 HWS_SF(, DOMAIN0_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ 766 HWS_SF(, DOMAIN1_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ 767 HWS_SF(, DOMAIN2_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ 768 HWS_SF(, DOMAIN3_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ 769 HWS_SF(, DOMAIN16_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ 770 HWS_SF(, DOMAIN17_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ 771 HWS_SF(, DOMAIN18_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ 772 HWS_SF(, DOMAIN19_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ 773 HWS_SF(, DC_IP_REQUEST_CNTL, IP_REQUEST_EN, mask_sh), \ 774 HWS_SF(, AZALIA_AUDIO_DTO, AZALIA_AUDIO_DTO_MODULE, mask_sh), \ 775 HWS_SF(, HPO_TOP_CLOCK_CONTROL, HPO_HDMISTREAMCLK_G_GATE_DIS, mask_sh), \ 776 HWS_SF(, DMU_MEM_PWR_CNTL, DMCU_ERAM_MEM_PWR_FORCE, mask_sh), \ 777 HWS_SF(, ODM_MEM_PWR_CTRL3, ODM_MEM_UNASSIGNED_PWR_MODE, mask_sh), \ 778 HWS_SF(, ODM_MEM_PWR_CTRL3, ODM_MEM_VBLANK_PWR_MODE, mask_sh), \ 779 HWS_SF(, MMHUBBUB_MEM_PWR_CNTL, VGA_MEM_PWR_FORCE, mask_sh), \ 780 HWS_SF(, DIO_MEM_PWR_CTRL, I2C_LIGHT_SLEEP_FORCE, mask_sh), \ 781 HWS_SF(, HPO_TOP_HW_CONTROL, HPO_IO_EN, mask_sh) 782 783 static const struct dce_hwseq_shift hwseq_shift = { 784 HWSEQ_DCN31_MASK_SH_LIST(__SHIFT) 785 }; 786 787 static const struct dce_hwseq_mask hwseq_mask = { 788 HWSEQ_DCN31_MASK_SH_LIST(_MASK) 789 }; 790 #define vmid_regs(id)\ 791 [id] = {\ 792 DCN20_VMID_REG_LIST(id)\ 793 } 794 795 static const struct dcn_vmid_registers vmid_regs[] = { 796 vmid_regs(0), 797 vmid_regs(1), 798 vmid_regs(2), 799 vmid_regs(3), 800 vmid_regs(4), 801 vmid_regs(5), 802 vmid_regs(6), 803 vmid_regs(7), 804 vmid_regs(8), 805 vmid_regs(9), 806 vmid_regs(10), 807 vmid_regs(11), 808 vmid_regs(12), 809 vmid_regs(13), 810 vmid_regs(14), 811 vmid_regs(15) 812 }; 813 814 static const struct dcn20_vmid_shift vmid_shifts = { 815 DCN20_VMID_MASK_SH_LIST(__SHIFT) 816 }; 817 818 static const struct dcn20_vmid_mask vmid_masks = { 819 DCN20_VMID_MASK_SH_LIST(_MASK) 820 }; 821 822 static const struct resource_caps res_cap_dcn314 = { 823 .num_timing_generator = 4, 824 .num_opp = 4, 825 .num_video_plane = 4, 826 .num_audio = 5, 827 .num_stream_encoder = 5, 828 .num_dig_link_enc = 5, 829 .num_hpo_dp_stream_encoder = 4, 830 .num_hpo_dp_link_encoder = 2, 831 .num_pll = 5, 832 .num_dwb = 1, 833 .num_ddc = 5, 834 .num_vmid = 16, 835 .num_mpc_3dlut = 2, 836 .num_dsc = 4, 837 }; 838 839 static const struct dc_plane_cap plane_cap = { 840 .type = DC_PLANE_TYPE_DCN_UNIVERSAL, 841 .per_pixel_alpha = true, 842 843 .pixel_format_support = { 844 .argb8888 = true, 845 .nv12 = true, 846 .fp16 = true, 847 .p010 = true, 848 .ayuv = false, 849 }, 850 851 .max_upscale_factor = { 852 .argb8888 = 16000, 853 .nv12 = 16000, 854 .fp16 = 16000 855 }, 856 857 // 6:1 downscaling ratio: 1000/6 = 166.666 858 // 4:1 downscaling ratio for ARGB888 to prevent underflow during P010 playback: 1000/4 = 250 859 .max_downscale_factor = { 860 .argb8888 = 250, 861 .nv12 = 167, 862 .fp16 = 167 863 }, 864 64, 865 64 866 }; 867 868 static const struct dc_debug_options debug_defaults_drv = { 869 .disable_z10 = false, 870 .enable_z9_disable_interface = true, 871 .minimum_z8_residency_time = 2000, 872 .psr_skip_crtc_disable = true, 873 .disable_dmcu = true, 874 .force_abm_enable = false, 875 .timing_trace = false, 876 .clock_trace = true, 877 .disable_dpp_power_gate = true, 878 .disable_hubp_power_gate = true, 879 .disable_pplib_clock_request = false, 880 .pipe_split_policy = MPC_SPLIT_DYNAMIC, 881 .force_single_disp_pipe_split = false, 882 .disable_dcc = DCC_ENABLE, 883 .vsr_support = true, 884 .performance_trace = false, 885 .max_downscale_src_width = 4096,/*upto true 4k*/ 886 .disable_pplib_wm_range = false, 887 .scl_reset_length10 = true, 888 .sanity_checks = true, 889 .underflow_assert_delay_us = 0xFFFFFFFF, 890 .dwb_fi_phase = -1, // -1 = disable, 891 .dmub_command_table = true, 892 .pstate_enabled = true, 893 .use_max_lb = true, 894 .enable_mem_low_power = { 895 .bits = { 896 .vga = true, 897 .i2c = true, 898 .dmcu = false, // This is previously known to cause hang on S3 cycles if enabled 899 .dscl = true, 900 .cm = true, 901 .mpc = true, 902 .optc = true, 903 .vpg = true, 904 .afmt = true, 905 } 906 }, 907 .seamless_boot_odm_combine = true 908 }; 909 910 static const struct dc_debug_options debug_defaults_diags = { 911 .disable_dmcu = true, 912 .force_abm_enable = false, 913 .timing_trace = true, 914 .clock_trace = true, 915 .disable_dpp_power_gate = true, 916 .disable_hubp_power_gate = true, 917 .disable_clock_gate = true, 918 .disable_pplib_clock_request = true, 919 .disable_pplib_wm_range = true, 920 .disable_stutter = false, 921 .scl_reset_length10 = true, 922 .dwb_fi_phase = -1, // -1 = disable 923 .dmub_command_table = true, 924 .enable_tri_buf = true, 925 .use_max_lb = true 926 }; 927 928 static const struct dc_panel_config panel_config_defaults = { 929 .psr = { 930 .disable_psr = false, 931 .disallow_psrsu = false, 932 }, 933 .ilr = { 934 .optimize_edp_link_rate = true, 935 }, 936 }; 937 938 static void dcn31_dpp_destroy(struct dpp **dpp) 939 { 940 kfree(TO_DCN20_DPP(*dpp)); 941 *dpp = NULL; 942 } 943 944 static struct dpp *dcn31_dpp_create( 945 struct dc_context *ctx, 946 uint32_t inst) 947 { 948 struct dcn3_dpp *dpp = 949 kzalloc(sizeof(struct dcn3_dpp), GFP_KERNEL); 950 951 if (!dpp) 952 return NULL; 953 954 if (dpp3_construct(dpp, ctx, inst, 955 &dpp_regs[inst], &tf_shift, &tf_mask)) 956 return &dpp->base; 957 958 BREAK_TO_DEBUGGER(); 959 kfree(dpp); 960 return NULL; 961 } 962 963 static struct output_pixel_processor *dcn31_opp_create( 964 struct dc_context *ctx, uint32_t inst) 965 { 966 struct dcn20_opp *opp = 967 kzalloc(sizeof(struct dcn20_opp), GFP_KERNEL); 968 969 if (!opp) { 970 BREAK_TO_DEBUGGER(); 971 return NULL; 972 } 973 974 dcn20_opp_construct(opp, ctx, inst, 975 &opp_regs[inst], &opp_shift, &opp_mask); 976 return &opp->base; 977 } 978 979 static struct dce_aux *dcn31_aux_engine_create( 980 struct dc_context *ctx, 981 uint32_t inst) 982 { 983 struct aux_engine_dce110 *aux_engine = 984 kzalloc(sizeof(struct aux_engine_dce110), GFP_KERNEL); 985 986 if (!aux_engine) 987 return NULL; 988 989 dce110_aux_engine_construct(aux_engine, ctx, inst, 990 SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD, 991 &aux_engine_regs[inst], 992 &aux_mask, 993 &aux_shift, 994 ctx->dc->caps.extended_aux_timeout_support); 995 996 return &aux_engine->base; 997 } 998 #define i2c_inst_regs(id) { I2C_HW_ENGINE_COMMON_REG_LIST_DCN30(id) } 999 1000 static const struct dce_i2c_registers i2c_hw_regs[] = { 1001 i2c_inst_regs(1), 1002 i2c_inst_regs(2), 1003 i2c_inst_regs(3), 1004 i2c_inst_regs(4), 1005 i2c_inst_regs(5), 1006 }; 1007 1008 static const struct dce_i2c_shift i2c_shifts = { 1009 I2C_COMMON_MASK_SH_LIST_DCN30(__SHIFT) 1010 }; 1011 1012 static const struct dce_i2c_mask i2c_masks = { 1013 I2C_COMMON_MASK_SH_LIST_DCN30(_MASK) 1014 }; 1015 1016 static struct dce_i2c_hw *dcn31_i2c_hw_create( 1017 struct dc_context *ctx, 1018 uint32_t inst) 1019 { 1020 struct dce_i2c_hw *dce_i2c_hw = 1021 kzalloc(sizeof(struct dce_i2c_hw), GFP_KERNEL); 1022 1023 if (!dce_i2c_hw) 1024 return NULL; 1025 1026 dcn2_i2c_hw_construct(dce_i2c_hw, ctx, inst, 1027 &i2c_hw_regs[inst], &i2c_shifts, &i2c_masks); 1028 1029 return dce_i2c_hw; 1030 } 1031 static struct mpc *dcn31_mpc_create( 1032 struct dc_context *ctx, 1033 int num_mpcc, 1034 int num_rmu) 1035 { 1036 struct dcn30_mpc *mpc30 = kzalloc(sizeof(struct dcn30_mpc), 1037 GFP_KERNEL); 1038 1039 if (!mpc30) 1040 return NULL; 1041 1042 dcn30_mpc_construct(mpc30, ctx, 1043 &mpc_regs, 1044 &mpc_shift, 1045 &mpc_mask, 1046 num_mpcc, 1047 num_rmu); 1048 1049 return &mpc30->base; 1050 } 1051 1052 static struct hubbub *dcn31_hubbub_create(struct dc_context *ctx) 1053 { 1054 int i; 1055 1056 struct dcn20_hubbub *hubbub3 = kzalloc(sizeof(struct dcn20_hubbub), 1057 GFP_KERNEL); 1058 1059 if (!hubbub3) 1060 return NULL; 1061 1062 hubbub31_construct(hubbub3, ctx, 1063 &hubbub_reg, 1064 &hubbub_shift, 1065 &hubbub_mask, 1066 dcn3_14_ip.det_buffer_size_kbytes, 1067 dcn3_14_ip.pixel_chunk_size_kbytes, 1068 dcn3_14_ip.config_return_buffer_size_in_kbytes); 1069 1070 1071 for (i = 0; i < res_cap_dcn314.num_vmid; i++) { 1072 struct dcn20_vmid *vmid = &hubbub3->vmid[i]; 1073 1074 vmid->ctx = ctx; 1075 1076 vmid->regs = &vmid_regs[i]; 1077 vmid->shifts = &vmid_shifts; 1078 vmid->masks = &vmid_masks; 1079 } 1080 1081 return &hubbub3->base; 1082 } 1083 1084 static struct timing_generator *dcn31_timing_generator_create( 1085 struct dc_context *ctx, 1086 uint32_t instance) 1087 { 1088 struct optc *tgn10 = 1089 kzalloc(sizeof(struct optc), GFP_KERNEL); 1090 1091 if (!tgn10) 1092 return NULL; 1093 1094 tgn10->base.inst = instance; 1095 tgn10->base.ctx = ctx; 1096 1097 tgn10->tg_regs = &optc_regs[instance]; 1098 tgn10->tg_shift = &optc_shift; 1099 tgn10->tg_mask = &optc_mask; 1100 1101 dcn314_timing_generator_init(tgn10); 1102 1103 return &tgn10->base; 1104 } 1105 1106 static const struct encoder_feature_support link_enc_feature = { 1107 .max_hdmi_deep_color = COLOR_DEPTH_121212, 1108 .max_hdmi_pixel_clock = 600000, 1109 .hdmi_ycbcr420_supported = true, 1110 .dp_ycbcr420_supported = true, 1111 .fec_supported = true, 1112 .flags.bits.IS_HBR2_CAPABLE = true, 1113 .flags.bits.IS_HBR3_CAPABLE = true, 1114 .flags.bits.IS_TPS3_CAPABLE = true, 1115 .flags.bits.IS_TPS4_CAPABLE = true 1116 }; 1117 1118 static struct link_encoder *dcn31_link_encoder_create( 1119 struct dc_context *ctx, 1120 const struct encoder_init_data *enc_init_data) 1121 { 1122 struct dcn20_link_encoder *enc20 = 1123 kzalloc(sizeof(struct dcn20_link_encoder), GFP_KERNEL); 1124 1125 if (!enc20) 1126 return NULL; 1127 1128 dcn31_link_encoder_construct(enc20, 1129 enc_init_data, 1130 &link_enc_feature, 1131 &link_enc_regs[enc_init_data->transmitter], 1132 &link_enc_aux_regs[enc_init_data->channel - 1], 1133 &link_enc_hpd_regs[enc_init_data->hpd_source], 1134 &le_shift, 1135 &le_mask); 1136 1137 return &enc20->enc10.base; 1138 } 1139 1140 /* Create a minimal link encoder object not associated with a particular 1141 * physical connector. 1142 * resource_funcs.link_enc_create_minimal 1143 */ 1144 static struct link_encoder *dcn31_link_enc_create_minimal( 1145 struct dc_context *ctx, enum engine_id eng_id) 1146 { 1147 struct dcn20_link_encoder *enc20; 1148 1149 if ((eng_id - ENGINE_ID_DIGA) > ctx->dc->res_pool->res_cap->num_dig_link_enc) 1150 return NULL; 1151 1152 enc20 = kzalloc(sizeof(struct dcn20_link_encoder), GFP_KERNEL); 1153 if (!enc20) 1154 return NULL; 1155 1156 dcn31_link_encoder_construct_minimal( 1157 enc20, 1158 ctx, 1159 &link_enc_feature, 1160 &link_enc_regs[eng_id - ENGINE_ID_DIGA], 1161 eng_id); 1162 1163 return &enc20->enc10.base; 1164 } 1165 1166 static struct panel_cntl *dcn31_panel_cntl_create(const struct panel_cntl_init_data *init_data) 1167 { 1168 struct dcn31_panel_cntl *panel_cntl = 1169 kzalloc(sizeof(struct dcn31_panel_cntl), GFP_KERNEL); 1170 1171 if (!panel_cntl) 1172 return NULL; 1173 1174 dcn31_panel_cntl_construct(panel_cntl, init_data); 1175 1176 return &panel_cntl->base; 1177 } 1178 1179 static void read_dce_straps( 1180 struct dc_context *ctx, 1181 struct resource_straps *straps) 1182 { 1183 generic_reg_get(ctx, regDC_PINSTRAPS + BASE(regDC_PINSTRAPS_BASE_IDX), 1184 FN(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO), &straps->dc_pinstraps_audio); 1185 1186 } 1187 1188 static struct audio *dcn31_create_audio( 1189 struct dc_context *ctx, unsigned int inst) 1190 { 1191 return dce_audio_create(ctx, inst, 1192 &audio_regs[inst], &audio_shift, &audio_mask); 1193 } 1194 1195 static struct vpg *dcn31_vpg_create( 1196 struct dc_context *ctx, 1197 uint32_t inst) 1198 { 1199 struct dcn31_vpg *vpg31 = kzalloc(sizeof(struct dcn31_vpg), GFP_KERNEL); 1200 1201 if (!vpg31) 1202 return NULL; 1203 1204 vpg31_construct(vpg31, ctx, inst, 1205 &vpg_regs[inst], 1206 &vpg_shift, 1207 &vpg_mask); 1208 1209 return &vpg31->base; 1210 } 1211 1212 static struct afmt *dcn31_afmt_create( 1213 struct dc_context *ctx, 1214 uint32_t inst) 1215 { 1216 struct dcn31_afmt *afmt31 = kzalloc(sizeof(struct dcn31_afmt), GFP_KERNEL); 1217 1218 if (!afmt31) 1219 return NULL; 1220 1221 afmt31_construct(afmt31, ctx, inst, 1222 &afmt_regs[inst], 1223 &afmt_shift, 1224 &afmt_mask); 1225 1226 // Light sleep by default, no need to power down here 1227 1228 return &afmt31->base; 1229 } 1230 1231 static struct apg *dcn31_apg_create( 1232 struct dc_context *ctx, 1233 uint32_t inst) 1234 { 1235 struct dcn31_apg *apg31 = kzalloc(sizeof(struct dcn31_apg), GFP_KERNEL); 1236 1237 if (!apg31) 1238 return NULL; 1239 1240 apg31_construct(apg31, ctx, inst, 1241 &apg_regs[inst], 1242 &apg_shift, 1243 &apg_mask); 1244 1245 return &apg31->base; 1246 } 1247 1248 static struct stream_encoder *dcn314_stream_encoder_create( 1249 enum engine_id eng_id, 1250 struct dc_context *ctx) 1251 { 1252 struct dcn10_stream_encoder *enc1; 1253 struct vpg *vpg; 1254 struct afmt *afmt; 1255 int vpg_inst; 1256 int afmt_inst; 1257 1258 /* Mapping of VPG, AFMT, DME register blocks to DIO block instance */ 1259 if (eng_id < ENGINE_ID_DIGF) { 1260 vpg_inst = eng_id; 1261 afmt_inst = eng_id; 1262 } else 1263 return NULL; 1264 1265 enc1 = kzalloc(sizeof(struct dcn10_stream_encoder), GFP_KERNEL); 1266 vpg = dcn31_vpg_create(ctx, vpg_inst); 1267 afmt = dcn31_afmt_create(ctx, afmt_inst); 1268 1269 if (!enc1 || !vpg || !afmt) { 1270 kfree(enc1); 1271 kfree(vpg); 1272 kfree(afmt); 1273 return NULL; 1274 } 1275 1276 dcn314_dio_stream_encoder_construct(enc1, ctx, ctx->dc_bios, 1277 eng_id, vpg, afmt, 1278 &stream_enc_regs[eng_id], 1279 &se_shift, &se_mask); 1280 1281 return &enc1->base; 1282 } 1283 1284 static struct hpo_dp_stream_encoder *dcn31_hpo_dp_stream_encoder_create( 1285 enum engine_id eng_id, 1286 struct dc_context *ctx) 1287 { 1288 struct dcn31_hpo_dp_stream_encoder *hpo_dp_enc31; 1289 struct vpg *vpg; 1290 struct apg *apg; 1291 uint32_t hpo_dp_inst; 1292 uint32_t vpg_inst; 1293 uint32_t apg_inst; 1294 1295 ASSERT((eng_id >= ENGINE_ID_HPO_DP_0) && (eng_id <= ENGINE_ID_HPO_DP_3)); 1296 hpo_dp_inst = eng_id - ENGINE_ID_HPO_DP_0; 1297 1298 /* Mapping of VPG register blocks to HPO DP block instance: 1299 * VPG[6] -> HPO_DP[0] 1300 * VPG[7] -> HPO_DP[1] 1301 * VPG[8] -> HPO_DP[2] 1302 * VPG[9] -> HPO_DP[3] 1303 */ 1304 //Uses offset index 5-8, but actually maps to vpg_inst 6-9 1305 vpg_inst = hpo_dp_inst + 5; 1306 1307 /* Mapping of APG register blocks to HPO DP block instance: 1308 * APG[0] -> HPO_DP[0] 1309 * APG[1] -> HPO_DP[1] 1310 * APG[2] -> HPO_DP[2] 1311 * APG[3] -> HPO_DP[3] 1312 */ 1313 apg_inst = hpo_dp_inst; 1314 1315 /* allocate HPO stream encoder and create VPG sub-block */ 1316 hpo_dp_enc31 = kzalloc(sizeof(struct dcn31_hpo_dp_stream_encoder), GFP_KERNEL); 1317 vpg = dcn31_vpg_create(ctx, vpg_inst); 1318 apg = dcn31_apg_create(ctx, apg_inst); 1319 1320 if (!hpo_dp_enc31 || !vpg || !apg) { 1321 kfree(hpo_dp_enc31); 1322 kfree(vpg); 1323 kfree(apg); 1324 return NULL; 1325 } 1326 1327 dcn31_hpo_dp_stream_encoder_construct(hpo_dp_enc31, ctx, ctx->dc_bios, 1328 hpo_dp_inst, eng_id, vpg, apg, 1329 &hpo_dp_stream_enc_regs[hpo_dp_inst], 1330 &hpo_dp_se_shift, &hpo_dp_se_mask); 1331 1332 return &hpo_dp_enc31->base; 1333 } 1334 1335 static struct hpo_dp_link_encoder *dcn31_hpo_dp_link_encoder_create( 1336 uint8_t inst, 1337 struct dc_context *ctx) 1338 { 1339 struct dcn31_hpo_dp_link_encoder *hpo_dp_enc31; 1340 1341 /* allocate HPO link encoder */ 1342 hpo_dp_enc31 = kzalloc(sizeof(struct dcn31_hpo_dp_link_encoder), GFP_KERNEL); 1343 1344 hpo_dp_link_encoder31_construct(hpo_dp_enc31, ctx, inst, 1345 &hpo_dp_link_enc_regs[inst], 1346 &hpo_dp_le_shift, &hpo_dp_le_mask); 1347 1348 return &hpo_dp_enc31->base; 1349 } 1350 1351 static struct dce_hwseq *dcn314_hwseq_create( 1352 struct dc_context *ctx) 1353 { 1354 struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_KERNEL); 1355 1356 if (hws) { 1357 hws->ctx = ctx; 1358 hws->regs = &hwseq_reg; 1359 hws->shifts = &hwseq_shift; 1360 hws->masks = &hwseq_mask; 1361 } 1362 return hws; 1363 } 1364 static const struct resource_create_funcs res_create_funcs = { 1365 .read_dce_straps = read_dce_straps, 1366 .create_audio = dcn31_create_audio, 1367 .create_stream_encoder = dcn314_stream_encoder_create, 1368 .create_hpo_dp_stream_encoder = dcn31_hpo_dp_stream_encoder_create, 1369 .create_hpo_dp_link_encoder = dcn31_hpo_dp_link_encoder_create, 1370 .create_hwseq = dcn314_hwseq_create, 1371 }; 1372 1373 static void dcn314_resource_destruct(struct dcn314_resource_pool *pool) 1374 { 1375 unsigned int i; 1376 1377 for (i = 0; i < pool->base.stream_enc_count; i++) { 1378 if (pool->base.stream_enc[i] != NULL) { 1379 if (pool->base.stream_enc[i]->vpg != NULL) { 1380 kfree(DCN30_VPG_FROM_VPG(pool->base.stream_enc[i]->vpg)); 1381 pool->base.stream_enc[i]->vpg = NULL; 1382 } 1383 if (pool->base.stream_enc[i]->afmt != NULL) { 1384 kfree(DCN30_AFMT_FROM_AFMT(pool->base.stream_enc[i]->afmt)); 1385 pool->base.stream_enc[i]->afmt = NULL; 1386 } 1387 kfree(DCN10STRENC_FROM_STRENC(pool->base.stream_enc[i])); 1388 pool->base.stream_enc[i] = NULL; 1389 } 1390 } 1391 1392 for (i = 0; i < pool->base.hpo_dp_stream_enc_count; i++) { 1393 if (pool->base.hpo_dp_stream_enc[i] != NULL) { 1394 if (pool->base.hpo_dp_stream_enc[i]->vpg != NULL) { 1395 kfree(DCN30_VPG_FROM_VPG(pool->base.hpo_dp_stream_enc[i]->vpg)); 1396 pool->base.hpo_dp_stream_enc[i]->vpg = NULL; 1397 } 1398 if (pool->base.hpo_dp_stream_enc[i]->apg != NULL) { 1399 kfree(DCN31_APG_FROM_APG(pool->base.hpo_dp_stream_enc[i]->apg)); 1400 pool->base.hpo_dp_stream_enc[i]->apg = NULL; 1401 } 1402 kfree(DCN3_1_HPO_DP_STREAM_ENC_FROM_HPO_STREAM_ENC(pool->base.hpo_dp_stream_enc[i])); 1403 pool->base.hpo_dp_stream_enc[i] = NULL; 1404 } 1405 } 1406 1407 for (i = 0; i < pool->base.hpo_dp_link_enc_count; i++) { 1408 if (pool->base.hpo_dp_link_enc[i] != NULL) { 1409 kfree(DCN3_1_HPO_DP_LINK_ENC_FROM_HPO_LINK_ENC(pool->base.hpo_dp_link_enc[i])); 1410 pool->base.hpo_dp_link_enc[i] = NULL; 1411 } 1412 } 1413 1414 for (i = 0; i < pool->base.res_cap->num_dsc; i++) { 1415 if (pool->base.dscs[i] != NULL) 1416 dcn20_dsc_destroy(&pool->base.dscs[i]); 1417 } 1418 1419 if (pool->base.mpc != NULL) { 1420 kfree(TO_DCN20_MPC(pool->base.mpc)); 1421 pool->base.mpc = NULL; 1422 } 1423 if (pool->base.hubbub != NULL) { 1424 kfree(pool->base.hubbub); 1425 pool->base.hubbub = NULL; 1426 } 1427 for (i = 0; i < pool->base.pipe_count; i++) { 1428 if (pool->base.dpps[i] != NULL) 1429 dcn31_dpp_destroy(&pool->base.dpps[i]); 1430 1431 if (pool->base.ipps[i] != NULL) 1432 pool->base.ipps[i]->funcs->ipp_destroy(&pool->base.ipps[i]); 1433 1434 if (pool->base.hubps[i] != NULL) { 1435 kfree(TO_DCN20_HUBP(pool->base.hubps[i])); 1436 pool->base.hubps[i] = NULL; 1437 } 1438 1439 if (pool->base.irqs != NULL) 1440 dal_irq_service_destroy(&pool->base.irqs); 1441 } 1442 1443 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { 1444 if (pool->base.engines[i] != NULL) 1445 dce110_engine_destroy(&pool->base.engines[i]); 1446 if (pool->base.hw_i2cs[i] != NULL) { 1447 kfree(pool->base.hw_i2cs[i]); 1448 pool->base.hw_i2cs[i] = NULL; 1449 } 1450 if (pool->base.sw_i2cs[i] != NULL) { 1451 kfree(pool->base.sw_i2cs[i]); 1452 pool->base.sw_i2cs[i] = NULL; 1453 } 1454 } 1455 1456 for (i = 0; i < pool->base.res_cap->num_opp; i++) { 1457 if (pool->base.opps[i] != NULL) 1458 pool->base.opps[i]->funcs->opp_destroy(&pool->base.opps[i]); 1459 } 1460 1461 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { 1462 if (pool->base.timing_generators[i] != NULL) { 1463 kfree(DCN10TG_FROM_TG(pool->base.timing_generators[i])); 1464 pool->base.timing_generators[i] = NULL; 1465 } 1466 } 1467 1468 for (i = 0; i < pool->base.res_cap->num_dwb; i++) { 1469 if (pool->base.dwbc[i] != NULL) { 1470 kfree(TO_DCN30_DWBC(pool->base.dwbc[i])); 1471 pool->base.dwbc[i] = NULL; 1472 } 1473 if (pool->base.mcif_wb[i] != NULL) { 1474 kfree(TO_DCN30_MMHUBBUB(pool->base.mcif_wb[i])); 1475 pool->base.mcif_wb[i] = NULL; 1476 } 1477 } 1478 1479 for (i = 0; i < pool->base.audio_count; i++) { 1480 if (pool->base.audios[i]) 1481 dce_aud_destroy(&pool->base.audios[i]); 1482 } 1483 1484 for (i = 0; i < pool->base.clk_src_count; i++) { 1485 if (pool->base.clock_sources[i] != NULL) { 1486 dcn20_clock_source_destroy(&pool->base.clock_sources[i]); 1487 pool->base.clock_sources[i] = NULL; 1488 } 1489 } 1490 1491 for (i = 0; i < pool->base.res_cap->num_mpc_3dlut; i++) { 1492 if (pool->base.mpc_lut[i] != NULL) { 1493 dc_3dlut_func_release(pool->base.mpc_lut[i]); 1494 pool->base.mpc_lut[i] = NULL; 1495 } 1496 if (pool->base.mpc_shaper[i] != NULL) { 1497 dc_transfer_func_release(pool->base.mpc_shaper[i]); 1498 pool->base.mpc_shaper[i] = NULL; 1499 } 1500 } 1501 1502 if (pool->base.dp_clock_source != NULL) { 1503 dcn20_clock_source_destroy(&pool->base.dp_clock_source); 1504 pool->base.dp_clock_source = NULL; 1505 } 1506 1507 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { 1508 if (pool->base.multiple_abms[i] != NULL) 1509 dce_abm_destroy(&pool->base.multiple_abms[i]); 1510 } 1511 1512 if (pool->base.psr != NULL) 1513 dmub_psr_destroy(&pool->base.psr); 1514 1515 if (pool->base.dccg != NULL) 1516 dcn_dccg_destroy(&pool->base.dccg); 1517 } 1518 1519 static struct hubp *dcn31_hubp_create( 1520 struct dc_context *ctx, 1521 uint32_t inst) 1522 { 1523 struct dcn20_hubp *hubp2 = 1524 kzalloc(sizeof(struct dcn20_hubp), GFP_KERNEL); 1525 1526 if (!hubp2) 1527 return NULL; 1528 1529 if (hubp31_construct(hubp2, ctx, inst, 1530 &hubp_regs[inst], &hubp_shift, &hubp_mask)) 1531 return &hubp2->base; 1532 1533 BREAK_TO_DEBUGGER(); 1534 kfree(hubp2); 1535 return NULL; 1536 } 1537 1538 static bool dcn31_dwbc_create(struct dc_context *ctx, struct resource_pool *pool) 1539 { 1540 int i; 1541 uint32_t pipe_count = pool->res_cap->num_dwb; 1542 1543 for (i = 0; i < pipe_count; i++) { 1544 struct dcn30_dwbc *dwbc30 = kzalloc(sizeof(struct dcn30_dwbc), 1545 GFP_KERNEL); 1546 1547 if (!dwbc30) { 1548 dm_error("DC: failed to create dwbc30!\n"); 1549 return false; 1550 } 1551 1552 dcn30_dwbc_construct(dwbc30, ctx, 1553 &dwbc30_regs[i], 1554 &dwbc30_shift, 1555 &dwbc30_mask, 1556 i); 1557 1558 pool->dwbc[i] = &dwbc30->base; 1559 } 1560 return true; 1561 } 1562 1563 static bool dcn31_mmhubbub_create(struct dc_context *ctx, struct resource_pool *pool) 1564 { 1565 int i; 1566 uint32_t pipe_count = pool->res_cap->num_dwb; 1567 1568 for (i = 0; i < pipe_count; i++) { 1569 struct dcn30_mmhubbub *mcif_wb30 = kzalloc(sizeof(struct dcn30_mmhubbub), 1570 GFP_KERNEL); 1571 1572 if (!mcif_wb30) { 1573 dm_error("DC: failed to create mcif_wb30!\n"); 1574 return false; 1575 } 1576 1577 dcn30_mmhubbub_construct(mcif_wb30, ctx, 1578 &mcif_wb30_regs[i], 1579 &mcif_wb30_shift, 1580 &mcif_wb30_mask, 1581 i); 1582 1583 pool->mcif_wb[i] = &mcif_wb30->base; 1584 } 1585 return true; 1586 } 1587 1588 static struct display_stream_compressor *dcn314_dsc_create( 1589 struct dc_context *ctx, uint32_t inst) 1590 { 1591 struct dcn20_dsc *dsc = 1592 kzalloc(sizeof(struct dcn20_dsc), GFP_KERNEL); 1593 1594 if (!dsc) { 1595 BREAK_TO_DEBUGGER(); 1596 return NULL; 1597 } 1598 1599 dsc2_construct(dsc, ctx, inst, &dsc_regs[inst], &dsc_shift, &dsc_mask); 1600 return &dsc->base; 1601 } 1602 1603 static void dcn314_destroy_resource_pool(struct resource_pool **pool) 1604 { 1605 struct dcn314_resource_pool *dcn314_pool = TO_DCN314_RES_POOL(*pool); 1606 1607 dcn314_resource_destruct(dcn314_pool); 1608 kfree(dcn314_pool); 1609 *pool = NULL; 1610 } 1611 1612 static struct clock_source *dcn31_clock_source_create( 1613 struct dc_context *ctx, 1614 struct dc_bios *bios, 1615 enum clock_source_id id, 1616 const struct dce110_clk_src_regs *regs, 1617 bool dp_clk_src) 1618 { 1619 struct dce110_clk_src *clk_src = 1620 kzalloc(sizeof(struct dce110_clk_src), GFP_KERNEL); 1621 1622 if (!clk_src) 1623 return NULL; 1624 1625 if (dcn31_clk_src_construct(clk_src, ctx, bios, id, 1626 regs, &cs_shift, &cs_mask)) { 1627 clk_src->base.dp_clk_src = dp_clk_src; 1628 return &clk_src->base; 1629 } 1630 1631 BREAK_TO_DEBUGGER(); 1632 kfree(clk_src); 1633 return NULL; 1634 } 1635 1636 static int dcn314_populate_dml_pipes_from_context( 1637 struct dc *dc, struct dc_state *context, 1638 display_e2e_pipe_params_st *pipes, 1639 bool fast_validate) 1640 { 1641 int pipe_cnt; 1642 1643 DC_FP_START(); 1644 pipe_cnt = dcn314_populate_dml_pipes_from_context_fpu(dc, context, pipes, fast_validate); 1645 DC_FP_END(); 1646 1647 return pipe_cnt; 1648 } 1649 1650 static struct dc_cap_funcs cap_funcs = { 1651 .get_dcc_compression_cap = dcn20_get_dcc_compression_cap 1652 }; 1653 1654 static void dcn314_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params) 1655 { 1656 DC_FP_START(); 1657 dcn314_update_bw_bounding_box_fpu(dc, bw_params); 1658 DC_FP_END(); 1659 } 1660 1661 static void dcn314_get_panel_config_defaults(struct dc_panel_config *panel_config) 1662 { 1663 *panel_config = panel_config_defaults; 1664 } 1665 1666 static bool filter_modes_for_single_channel_workaround(struct dc *dc, 1667 struct dc_state *context) 1668 { 1669 // Filter 2K@240Hz+8K@24fps above combination timing if memory only has single dimm LPDDR 1670 if (dc->clk_mgr->bw_params->vram_type == 34 && dc->clk_mgr->bw_params->num_channels < 2) { 1671 int total_phy_pix_clk = 0; 1672 1673 for (int i = 0; i < context->stream_count; i++) 1674 if (context->res_ctx.pipe_ctx[i].stream) 1675 total_phy_pix_clk += context->res_ctx.pipe_ctx[i].stream->phy_pix_clk; 1676 1677 if (total_phy_pix_clk >= (1148928+826260)) //2K@240Hz+8K@24fps 1678 return true; 1679 } 1680 return false; 1681 } 1682 1683 bool dcn314_validate_bandwidth(struct dc *dc, 1684 struct dc_state *context, 1685 bool fast_validate) 1686 { 1687 bool out = false; 1688 1689 BW_VAL_TRACE_SETUP(); 1690 1691 int vlevel = 0; 1692 int pipe_cnt = 0; 1693 display_e2e_pipe_params_st *pipes = kzalloc(dc->res_pool->pipe_count * sizeof(display_e2e_pipe_params_st), GFP_KERNEL); 1694 DC_LOGGER_INIT(dc->ctx->logger); 1695 1696 BW_VAL_TRACE_COUNT(); 1697 1698 if (filter_modes_for_single_channel_workaround(dc, context)) 1699 goto validate_fail; 1700 1701 DC_FP_START(); 1702 // do not support self refresh only 1703 out = dcn30_internal_validate_bw(dc, context, pipes, &pipe_cnt, &vlevel, fast_validate, false); 1704 DC_FP_END(); 1705 1706 // Disable fast_validate to set min dcfclk in calculate_wm_and_dlg 1707 if (pipe_cnt == 0) 1708 fast_validate = false; 1709 1710 if (!out) 1711 goto validate_fail; 1712 1713 BW_VAL_TRACE_END_VOLTAGE_LEVEL(); 1714 1715 if (fast_validate) { 1716 BW_VAL_TRACE_SKIP(fast); 1717 goto validate_out; 1718 } 1719 1720 dc->res_pool->funcs->calculate_wm_and_dlg(dc, context, pipes, pipe_cnt, vlevel); 1721 1722 BW_VAL_TRACE_END_WATERMARKS(); 1723 1724 goto validate_out; 1725 1726 validate_fail: 1727 DC_LOG_WARNING("Mode Validation Warning: %s failed validation.\n", 1728 dml_get_status_message(context->bw_ctx.dml.vba.ValidationStatus[context->bw_ctx.dml.vba.soc.num_states])); 1729 1730 BW_VAL_TRACE_SKIP(fail); 1731 out = false; 1732 1733 validate_out: 1734 kfree(pipes); 1735 1736 BW_VAL_TRACE_FINISH(); 1737 1738 return out; 1739 } 1740 1741 static struct resource_funcs dcn314_res_pool_funcs = { 1742 .destroy = dcn314_destroy_resource_pool, 1743 .link_enc_create = dcn31_link_encoder_create, 1744 .link_enc_create_minimal = dcn31_link_enc_create_minimal, 1745 .link_encs_assign = link_enc_cfg_link_encs_assign, 1746 .link_enc_unassign = link_enc_cfg_link_enc_unassign, 1747 .panel_cntl_create = dcn31_panel_cntl_create, 1748 .validate_bandwidth = dcn314_validate_bandwidth, 1749 .calculate_wm_and_dlg = dcn31_calculate_wm_and_dlg, 1750 .update_soc_for_wm_a = dcn31_update_soc_for_wm_a, 1751 .populate_dml_pipes = dcn314_populate_dml_pipes_from_context, 1752 .acquire_idle_pipe_for_layer = dcn20_acquire_idle_pipe_for_layer, 1753 .add_stream_to_ctx = dcn30_add_stream_to_ctx, 1754 .add_dsc_to_stream_resource = dcn20_add_dsc_to_stream_resource, 1755 .remove_stream_from_ctx = dcn20_remove_stream_from_ctx, 1756 .populate_dml_writeback_from_context = dcn30_populate_dml_writeback_from_context, 1757 .set_mcif_arb_params = dcn30_set_mcif_arb_params, 1758 .find_first_free_match_stream_enc_for_link = dcn10_find_first_free_match_stream_enc_for_link, 1759 .acquire_post_bldn_3dlut = dcn30_acquire_post_bldn_3dlut, 1760 .release_post_bldn_3dlut = dcn30_release_post_bldn_3dlut, 1761 .update_bw_bounding_box = dcn314_update_bw_bounding_box, 1762 .patch_unknown_plane_state = dcn20_patch_unknown_plane_state, 1763 .get_panel_config_defaults = dcn314_get_panel_config_defaults, 1764 }; 1765 1766 static struct clock_source *dcn30_clock_source_create( 1767 struct dc_context *ctx, 1768 struct dc_bios *bios, 1769 enum clock_source_id id, 1770 const struct dce110_clk_src_regs *regs, 1771 bool dp_clk_src) 1772 { 1773 struct dce110_clk_src *clk_src = 1774 kzalloc(sizeof(struct dce110_clk_src), GFP_KERNEL); 1775 1776 if (!clk_src) 1777 return NULL; 1778 1779 if (dcn31_clk_src_construct(clk_src, ctx, bios, id, 1780 regs, &cs_shift, &cs_mask)) { 1781 clk_src->base.dp_clk_src = dp_clk_src; 1782 return &clk_src->base; 1783 } 1784 1785 BREAK_TO_DEBUGGER(); 1786 kfree(clk_src); 1787 return NULL; 1788 } 1789 1790 static bool dcn314_resource_construct( 1791 uint8_t num_virtual_links, 1792 struct dc *dc, 1793 struct dcn314_resource_pool *pool) 1794 { 1795 int i; 1796 struct dc_context *ctx = dc->ctx; 1797 struct irq_service_init_data init_data; 1798 1799 ctx->dc_bios->regs = &bios_regs; 1800 1801 pool->base.res_cap = &res_cap_dcn314; 1802 pool->base.funcs = &dcn314_res_pool_funcs; 1803 1804 /************************************************* 1805 * Resource + asic cap harcoding * 1806 *************************************************/ 1807 pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE; 1808 pool->base.pipe_count = pool->base.res_cap->num_timing_generator; 1809 pool->base.mpcc_count = pool->base.res_cap->num_timing_generator; 1810 dc->caps.max_downscale_ratio = 400; 1811 dc->caps.i2c_speed_in_khz = 100; 1812 dc->caps.i2c_speed_in_khz_hdcp = 100; 1813 dc->caps.max_cursor_size = 256; 1814 dc->caps.min_horizontal_blanking_period = 80; 1815 dc->caps.dmdata_alloc_size = 2048; 1816 dc->caps.max_slave_planes = 2; 1817 dc->caps.max_slave_yuv_planes = 2; 1818 dc->caps.max_slave_rgb_planes = 2; 1819 dc->caps.post_blend_color_processing = true; 1820 dc->caps.force_dp_tps4_for_cp2520 = true; 1821 if (dc->config.forceHBR2CP2520) 1822 dc->caps.force_dp_tps4_for_cp2520 = false; 1823 dc->caps.dp_hpo = true; 1824 dc->caps.dp_hdmi21_pcon_support = true; 1825 dc->caps.edp_dsc_support = true; 1826 dc->caps.extended_aux_timeout_support = true; 1827 dc->caps.dmcub_support = true; 1828 dc->caps.is_apu = true; 1829 dc->caps.seamless_odm = true; 1830 1831 dc->caps.zstate_support = true; 1832 1833 /* Color pipeline capabilities */ 1834 dc->caps.color.dpp.dcn_arch = 1; 1835 dc->caps.color.dpp.input_lut_shared = 0; 1836 dc->caps.color.dpp.icsc = 1; 1837 dc->caps.color.dpp.dgam_ram = 0; // must use gamma_corr 1838 dc->caps.color.dpp.dgam_rom_caps.srgb = 1; 1839 dc->caps.color.dpp.dgam_rom_caps.bt2020 = 1; 1840 dc->caps.color.dpp.dgam_rom_caps.gamma2_2 = 1; 1841 dc->caps.color.dpp.dgam_rom_caps.pq = 1; 1842 dc->caps.color.dpp.dgam_rom_caps.hlg = 1; 1843 dc->caps.color.dpp.post_csc = 1; 1844 dc->caps.color.dpp.gamma_corr = 1; 1845 dc->caps.color.dpp.dgam_rom_for_yuv = 0; 1846 1847 dc->caps.color.dpp.hw_3d_lut = 1; 1848 dc->caps.color.dpp.ogam_ram = 1; 1849 // no OGAM ROM on DCN301 1850 dc->caps.color.dpp.ogam_rom_caps.srgb = 0; 1851 dc->caps.color.dpp.ogam_rom_caps.bt2020 = 0; 1852 dc->caps.color.dpp.ogam_rom_caps.gamma2_2 = 0; 1853 dc->caps.color.dpp.ogam_rom_caps.pq = 0; 1854 dc->caps.color.dpp.ogam_rom_caps.hlg = 0; 1855 dc->caps.color.dpp.ocsc = 0; 1856 1857 dc->caps.color.mpc.gamut_remap = 1; 1858 dc->caps.color.mpc.num_3dluts = pool->base.res_cap->num_mpc_3dlut; //2 1859 dc->caps.color.mpc.ogam_ram = 1; 1860 dc->caps.color.mpc.ogam_rom_caps.srgb = 0; 1861 dc->caps.color.mpc.ogam_rom_caps.bt2020 = 0; 1862 dc->caps.color.mpc.ogam_rom_caps.gamma2_2 = 0; 1863 dc->caps.color.mpc.ogam_rom_caps.pq = 0; 1864 dc->caps.color.mpc.ogam_rom_caps.hlg = 0; 1865 dc->caps.color.mpc.ocsc = 1; 1866 1867 /* Use pipe context based otg sync logic */ 1868 dc->config.use_pipe_ctx_sync_logic = true; 1869 1870 /* read VBIOS LTTPR caps */ 1871 { 1872 if (ctx->dc_bios->funcs->get_lttpr_caps) { 1873 enum bp_result bp_query_result; 1874 uint8_t is_vbios_lttpr_enable = 0; 1875 1876 bp_query_result = ctx->dc_bios->funcs->get_lttpr_caps(ctx->dc_bios, &is_vbios_lttpr_enable); 1877 dc->caps.vbios_lttpr_enable = (bp_query_result == BP_RESULT_OK) && !!is_vbios_lttpr_enable; 1878 } 1879 1880 /* interop bit is implicit */ 1881 { 1882 dc->caps.vbios_lttpr_aware = true; 1883 } 1884 } 1885 1886 if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV) 1887 dc->debug = debug_defaults_drv; 1888 else 1889 dc->debug = debug_defaults_diags; 1890 // Init the vm_helper 1891 if (dc->vm_helper) 1892 vm_helper_init(dc->vm_helper, 16); 1893 1894 /************************************************* 1895 * Create resources * 1896 *************************************************/ 1897 1898 /* Clock Sources for Pixel Clock*/ 1899 pool->base.clock_sources[DCN31_CLK_SRC_PLL0] = 1900 dcn30_clock_source_create(ctx, ctx->dc_bios, 1901 CLOCK_SOURCE_COMBO_PHY_PLL0, 1902 &clk_src_regs[0], false); 1903 pool->base.clock_sources[DCN31_CLK_SRC_PLL1] = 1904 dcn30_clock_source_create(ctx, ctx->dc_bios, 1905 CLOCK_SOURCE_COMBO_PHY_PLL1, 1906 &clk_src_regs[1], false); 1907 pool->base.clock_sources[DCN31_CLK_SRC_PLL2] = 1908 dcn30_clock_source_create(ctx, ctx->dc_bios, 1909 CLOCK_SOURCE_COMBO_PHY_PLL2, 1910 &clk_src_regs[2], false); 1911 pool->base.clock_sources[DCN31_CLK_SRC_PLL3] = 1912 dcn30_clock_source_create(ctx, ctx->dc_bios, 1913 CLOCK_SOURCE_COMBO_PHY_PLL3, 1914 &clk_src_regs[3], false); 1915 pool->base.clock_sources[DCN31_CLK_SRC_PLL4] = 1916 dcn30_clock_source_create(ctx, ctx->dc_bios, 1917 CLOCK_SOURCE_COMBO_PHY_PLL4, 1918 &clk_src_regs[4], false); 1919 1920 pool->base.clk_src_count = DCN30_CLK_SRC_TOTAL; 1921 1922 /* todo: not reuse phy_pll registers */ 1923 pool->base.dp_clock_source = 1924 dcn31_clock_source_create(ctx, ctx->dc_bios, 1925 CLOCK_SOURCE_ID_DP_DTO, 1926 &clk_src_regs[0], true); 1927 1928 for (i = 0; i < pool->base.clk_src_count; i++) { 1929 if (pool->base.clock_sources[i] == NULL) { 1930 dm_error("DC: failed to create clock sources!\n"); 1931 BREAK_TO_DEBUGGER(); 1932 goto create_fail; 1933 } 1934 } 1935 1936 pool->base.dccg = dccg314_create(ctx, &dccg_regs, &dccg_shift, &dccg_mask); 1937 if (pool->base.dccg == NULL) { 1938 dm_error("DC: failed to create dccg!\n"); 1939 BREAK_TO_DEBUGGER(); 1940 goto create_fail; 1941 } 1942 1943 init_data.ctx = dc->ctx; 1944 pool->base.irqs = dal_irq_service_dcn314_create(&init_data); 1945 if (!pool->base.irqs) 1946 goto create_fail; 1947 1948 /* HUBBUB */ 1949 pool->base.hubbub = dcn31_hubbub_create(ctx); 1950 if (pool->base.hubbub == NULL) { 1951 BREAK_TO_DEBUGGER(); 1952 dm_error("DC: failed to create hubbub!\n"); 1953 goto create_fail; 1954 } 1955 1956 /* HUBPs, DPPs, OPPs and TGs */ 1957 for (i = 0; i < pool->base.pipe_count; i++) { 1958 pool->base.hubps[i] = dcn31_hubp_create(ctx, i); 1959 if (pool->base.hubps[i] == NULL) { 1960 BREAK_TO_DEBUGGER(); 1961 dm_error( 1962 "DC: failed to create hubps!\n"); 1963 goto create_fail; 1964 } 1965 1966 pool->base.dpps[i] = dcn31_dpp_create(ctx, i); 1967 if (pool->base.dpps[i] == NULL) { 1968 BREAK_TO_DEBUGGER(); 1969 dm_error( 1970 "DC: failed to create dpps!\n"); 1971 goto create_fail; 1972 } 1973 } 1974 1975 for (i = 0; i < pool->base.res_cap->num_opp; i++) { 1976 pool->base.opps[i] = dcn31_opp_create(ctx, i); 1977 if (pool->base.opps[i] == NULL) { 1978 BREAK_TO_DEBUGGER(); 1979 dm_error( 1980 "DC: failed to create output pixel processor!\n"); 1981 goto create_fail; 1982 } 1983 } 1984 1985 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { 1986 pool->base.timing_generators[i] = dcn31_timing_generator_create( 1987 ctx, i); 1988 if (pool->base.timing_generators[i] == NULL) { 1989 BREAK_TO_DEBUGGER(); 1990 dm_error("DC: failed to create tg!\n"); 1991 goto create_fail; 1992 } 1993 } 1994 pool->base.timing_generator_count = i; 1995 1996 /* PSR */ 1997 pool->base.psr = dmub_psr_create(ctx); 1998 if (pool->base.psr == NULL) { 1999 dm_error("DC: failed to create psr obj!\n"); 2000 BREAK_TO_DEBUGGER(); 2001 goto create_fail; 2002 } 2003 2004 /* ABM */ 2005 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { 2006 pool->base.multiple_abms[i] = dmub_abm_create(ctx, 2007 &abm_regs[i], 2008 &abm_shift, 2009 &abm_mask); 2010 if (pool->base.multiple_abms[i] == NULL) { 2011 dm_error("DC: failed to create abm for pipe %d!\n", i); 2012 BREAK_TO_DEBUGGER(); 2013 goto create_fail; 2014 } 2015 } 2016 2017 /* MPC and DSC */ 2018 pool->base.mpc = dcn31_mpc_create(ctx, pool->base.mpcc_count, pool->base.res_cap->num_mpc_3dlut); 2019 if (pool->base.mpc == NULL) { 2020 BREAK_TO_DEBUGGER(); 2021 dm_error("DC: failed to create mpc!\n"); 2022 goto create_fail; 2023 } 2024 2025 for (i = 0; i < pool->base.res_cap->num_dsc; i++) { 2026 pool->base.dscs[i] = dcn314_dsc_create(ctx, i); 2027 if (pool->base.dscs[i] == NULL) { 2028 BREAK_TO_DEBUGGER(); 2029 dm_error("DC: failed to create display stream compressor %d!\n", i); 2030 goto create_fail; 2031 } 2032 } 2033 2034 /* DWB and MMHUBBUB */ 2035 if (!dcn31_dwbc_create(ctx, &pool->base)) { 2036 BREAK_TO_DEBUGGER(); 2037 dm_error("DC: failed to create dwbc!\n"); 2038 goto create_fail; 2039 } 2040 2041 if (!dcn31_mmhubbub_create(ctx, &pool->base)) { 2042 BREAK_TO_DEBUGGER(); 2043 dm_error("DC: failed to create mcif_wb!\n"); 2044 goto create_fail; 2045 } 2046 2047 /* AUX and I2C */ 2048 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { 2049 pool->base.engines[i] = dcn31_aux_engine_create(ctx, i); 2050 if (pool->base.engines[i] == NULL) { 2051 BREAK_TO_DEBUGGER(); 2052 dm_error( 2053 "DC:failed to create aux engine!!\n"); 2054 goto create_fail; 2055 } 2056 pool->base.hw_i2cs[i] = dcn31_i2c_hw_create(ctx, i); 2057 if (pool->base.hw_i2cs[i] == NULL) { 2058 BREAK_TO_DEBUGGER(); 2059 dm_error( 2060 "DC:failed to create hw i2c!!\n"); 2061 goto create_fail; 2062 } 2063 pool->base.sw_i2cs[i] = NULL; 2064 } 2065 2066 /* DCN314 has 4 DPIA */ 2067 pool->base.usb4_dpia_count = 4; 2068 2069 /* Audio, Stream Encoders including HPO and virtual, MPC 3D LUTs */ 2070 if (!resource_construct(num_virtual_links, dc, &pool->base, 2071 &res_create_funcs)) 2072 goto create_fail; 2073 2074 /* HW Sequencer and Plane caps */ 2075 dcn314_hw_sequencer_construct(dc); 2076 2077 dc->caps.max_planes = pool->base.pipe_count; 2078 2079 for (i = 0; i < dc->caps.max_planes; ++i) 2080 dc->caps.planes[i] = plane_cap; 2081 2082 dc->cap_funcs = cap_funcs; 2083 2084 dc->dcn_ip->max_num_dpp = dcn3_14_ip.max_num_dpp; 2085 2086 return true; 2087 2088 create_fail: 2089 2090 dcn314_resource_destruct(pool); 2091 2092 return false; 2093 } 2094 2095 struct resource_pool *dcn314_create_resource_pool( 2096 const struct dc_init_data *init_data, 2097 struct dc *dc) 2098 { 2099 struct dcn314_resource_pool *pool = 2100 kzalloc(sizeof(struct dcn314_resource_pool), GFP_KERNEL); 2101 2102 if (!pool) 2103 return NULL; 2104 2105 if (dcn314_resource_construct(init_data->num_virtual_links, dc, pool)) 2106 return &pool->base; 2107 2108 BREAK_TO_DEBUGGER(); 2109 kfree(pool); 2110 return NULL; 2111 } 2112