1 // SPDX-License-Identifier: MIT 2 /* 3 * Copyright 2022 Advanced Micro Devices, Inc. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 * 23 * Authors: AMD 24 * 25 */ 26 27 28 #include "dm_services.h" 29 #include "dm_helpers.h" 30 #include "core_types.h" 31 #include "resource.h" 32 #include "dccg.h" 33 #include "dce/dce_hwseq.h" 34 #include "clk_mgr.h" 35 #include "reg_helper.h" 36 #include "abm.h" 37 #include "hubp.h" 38 #include "dchubbub.h" 39 #include "timing_generator.h" 40 #include "opp.h" 41 #include "ipp.h" 42 #include "mpc.h" 43 #include "mcif_wb.h" 44 #include "dc_dmub_srv.h" 45 #include "dcn314_hwseq.h" 46 #include "link_hwss.h" 47 #include "dpcd_defs.h" 48 #include "dce/dmub_outbox.h" 49 #include "dc_link_dp.h" 50 #include "inc/dc_link_dp.h" 51 #include "inc/link_dpcd.h" 52 #include "dcn10/dcn10_hw_sequencer.h" 53 #include "inc/link_enc_cfg.h" 54 #include "dcn30/dcn30_vpg.h" 55 #include "dce/dce_i2c_hw.h" 56 #include "dsc.h" 57 #include "dcn20/dcn20_optc.h" 58 #include "dcn30/dcn30_cm_common.h" 59 60 #define DC_LOGGER_INIT(logger) 61 62 #define CTX \ 63 hws->ctx 64 #define REG(reg)\ 65 hws->regs->reg 66 #define DC_LOGGER \ 67 dc->ctx->logger 68 69 70 #undef FN 71 #define FN(reg_name, field_name) \ 72 hws->shifts->field_name, hws->masks->field_name 73 74 static int calc_mpc_flow_ctrl_cnt(const struct dc_stream_state *stream, 75 int opp_cnt) 76 { 77 bool hblank_halved = optc2_is_two_pixels_per_containter(&stream->timing); 78 int flow_ctrl_cnt; 79 80 if (opp_cnt >= 2) 81 hblank_halved = true; 82 83 flow_ctrl_cnt = stream->timing.h_total - stream->timing.h_addressable - 84 stream->timing.h_border_left - 85 stream->timing.h_border_right; 86 87 if (hblank_halved) 88 flow_ctrl_cnt /= 2; 89 90 /* ODM combine 4:1 case */ 91 if (opp_cnt == 4) 92 flow_ctrl_cnt /= 2; 93 94 return flow_ctrl_cnt; 95 } 96 97 static void update_dsc_on_stream(struct pipe_ctx *pipe_ctx, bool enable) 98 { 99 struct display_stream_compressor *dsc = pipe_ctx->stream_res.dsc; 100 struct dc_stream_state *stream = pipe_ctx->stream; 101 struct pipe_ctx *odm_pipe; 102 int opp_cnt = 1; 103 104 ASSERT(dsc); 105 for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) 106 opp_cnt++; 107 108 if (enable) { 109 struct dsc_config dsc_cfg; 110 struct dsc_optc_config dsc_optc_cfg; 111 enum optc_dsc_mode optc_dsc_mode; 112 113 /* Enable DSC hw block */ 114 dsc_cfg.pic_width = (stream->timing.h_addressable + stream->timing.h_border_left + stream->timing.h_border_right) / opp_cnt; 115 dsc_cfg.pic_height = stream->timing.v_addressable + stream->timing.v_border_top + stream->timing.v_border_bottom; 116 dsc_cfg.pixel_encoding = stream->timing.pixel_encoding; 117 dsc_cfg.color_depth = stream->timing.display_color_depth; 118 dsc_cfg.is_odm = pipe_ctx->next_odm_pipe ? true : false; 119 dsc_cfg.dc_dsc_cfg = stream->timing.dsc_cfg; 120 ASSERT(dsc_cfg.dc_dsc_cfg.num_slices_h % opp_cnt == 0); 121 dsc_cfg.dc_dsc_cfg.num_slices_h /= opp_cnt; 122 123 dsc->funcs->dsc_set_config(dsc, &dsc_cfg, &dsc_optc_cfg); 124 dsc->funcs->dsc_enable(dsc, pipe_ctx->stream_res.opp->inst); 125 for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) { 126 struct display_stream_compressor *odm_dsc = odm_pipe->stream_res.dsc; 127 128 ASSERT(odm_dsc); 129 odm_dsc->funcs->dsc_set_config(odm_dsc, &dsc_cfg, &dsc_optc_cfg); 130 odm_dsc->funcs->dsc_enable(odm_dsc, odm_pipe->stream_res.opp->inst); 131 } 132 dsc_cfg.dc_dsc_cfg.num_slices_h *= opp_cnt; 133 dsc_cfg.pic_width *= opp_cnt; 134 135 optc_dsc_mode = dsc_optc_cfg.is_pixel_format_444 ? OPTC_DSC_ENABLED_444 : OPTC_DSC_ENABLED_NATIVE_SUBSAMPLED; 136 137 /* Enable DSC in OPTC */ 138 DC_LOG_DSC("Setting optc DSC config for tg instance %d:", pipe_ctx->stream_res.tg->inst); 139 pipe_ctx->stream_res.tg->funcs->set_dsc_config(pipe_ctx->stream_res.tg, 140 optc_dsc_mode, 141 dsc_optc_cfg.bytes_per_pixel, 142 dsc_optc_cfg.slice_width); 143 } else { 144 /* disable DSC in OPTC */ 145 pipe_ctx->stream_res.tg->funcs->set_dsc_config( 146 pipe_ctx->stream_res.tg, 147 OPTC_DSC_DISABLED, 0, 0); 148 149 /* disable DSC block */ 150 dsc->funcs->dsc_disable(pipe_ctx->stream_res.dsc); 151 for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) { 152 ASSERT(odm_pipe->stream_res.dsc); 153 odm_pipe->stream_res.dsc->funcs->dsc_disable(odm_pipe->stream_res.dsc); 154 } 155 } 156 } 157 158 // Given any pipe_ctx, return the total ODM combine factor, and optionally return 159 // the OPPids which are used 160 static unsigned int get_odm_config(struct pipe_ctx *pipe_ctx, unsigned int *opp_instances) 161 { 162 unsigned int opp_count = 1; 163 struct pipe_ctx *odm_pipe; 164 165 // First get to the top pipe 166 for (odm_pipe = pipe_ctx; odm_pipe->prev_odm_pipe; odm_pipe = odm_pipe->prev_odm_pipe) 167 ; 168 169 // First pipe is always used 170 if (opp_instances) 171 opp_instances[0] = odm_pipe->stream_res.opp->inst; 172 173 // Find and count odm pipes, if any 174 for (odm_pipe = odm_pipe->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) { 175 if (opp_instances) 176 opp_instances[opp_count] = odm_pipe->stream_res.opp->inst; 177 opp_count++; 178 } 179 180 return opp_count; 181 } 182 183 void dcn314_update_odm(struct dc *dc, struct dc_state *context, struct pipe_ctx *pipe_ctx) 184 { 185 struct pipe_ctx *odm_pipe; 186 int opp_cnt = 0; 187 int opp_inst[MAX_PIPES] = {0}; 188 bool rate_control_2x_pclk = (pipe_ctx->stream->timing.flags.INTERLACE || optc2_is_two_pixels_per_containter(&pipe_ctx->stream->timing)); 189 struct mpc_dwb_flow_control flow_control; 190 struct mpc *mpc = dc->res_pool->mpc; 191 int i; 192 193 opp_cnt = get_odm_config(pipe_ctx, opp_inst); 194 195 if (opp_cnt > 1) 196 pipe_ctx->stream_res.tg->funcs->set_odm_combine( 197 pipe_ctx->stream_res.tg, 198 opp_inst, opp_cnt, 199 &pipe_ctx->stream->timing); 200 else 201 pipe_ctx->stream_res.tg->funcs->set_odm_bypass( 202 pipe_ctx->stream_res.tg, &pipe_ctx->stream->timing); 203 204 rate_control_2x_pclk = rate_control_2x_pclk || opp_cnt > 1; 205 flow_control.flow_ctrl_mode = 0; 206 flow_control.flow_ctrl_cnt0 = 0x80; 207 flow_control.flow_ctrl_cnt1 = calc_mpc_flow_ctrl_cnt(pipe_ctx->stream, opp_cnt); 208 if (mpc->funcs->set_out_rate_control) { 209 for (i = 0; i < opp_cnt; ++i) { 210 mpc->funcs->set_out_rate_control( 211 mpc, opp_inst[i], 212 true, 213 rate_control_2x_pclk, 214 &flow_control); 215 } 216 } 217 218 for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) { 219 odm_pipe->stream_res.opp->funcs->opp_pipe_clock_control( 220 odm_pipe->stream_res.opp, 221 true); 222 } 223 224 if (pipe_ctx->stream_res.dsc) { 225 struct pipe_ctx *current_pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[pipe_ctx->pipe_idx]; 226 227 update_dsc_on_stream(pipe_ctx, pipe_ctx->stream->timing.flags.DSC); 228 229 /* Check if no longer using pipe for ODM, then need to disconnect DSC for that pipe */ 230 if (!pipe_ctx->next_odm_pipe && current_pipe_ctx->next_odm_pipe && 231 current_pipe_ctx->next_odm_pipe->stream_res.dsc) { 232 struct display_stream_compressor *dsc = current_pipe_ctx->next_odm_pipe->stream_res.dsc; 233 /* disconnect DSC block from stream */ 234 dsc->funcs->dsc_disconnect(dsc); 235 } 236 } 237 } 238 239 void dcn314_dsc_pg_control( 240 struct dce_hwseq *hws, 241 unsigned int dsc_inst, 242 bool power_on) 243 { 244 uint32_t power_gate = power_on ? 0 : 1; 245 uint32_t pwr_status = power_on ? 0 : 2; 246 uint32_t org_ip_request_cntl = 0; 247 248 if (hws->ctx->dc->debug.disable_dsc_power_gate) 249 return; 250 251 if (hws->ctx->dc->debug.root_clock_optimization.bits.dsc && 252 hws->ctx->dc->res_pool->dccg->funcs->enable_dsc && 253 power_on) 254 hws->ctx->dc->res_pool->dccg->funcs->enable_dsc( 255 hws->ctx->dc->res_pool->dccg, dsc_inst); 256 257 REG_GET(DC_IP_REQUEST_CNTL, IP_REQUEST_EN, &org_ip_request_cntl); 258 if (org_ip_request_cntl == 0) 259 REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 1); 260 261 switch (dsc_inst) { 262 case 0: /* DSC0 */ 263 REG_UPDATE(DOMAIN16_PG_CONFIG, 264 DOMAIN_POWER_GATE, power_gate); 265 266 REG_WAIT(DOMAIN16_PG_STATUS, 267 DOMAIN_PGFSM_PWR_STATUS, pwr_status, 268 1, 1000); 269 break; 270 case 1: /* DSC1 */ 271 REG_UPDATE(DOMAIN17_PG_CONFIG, 272 DOMAIN_POWER_GATE, power_gate); 273 274 REG_WAIT(DOMAIN17_PG_STATUS, 275 DOMAIN_PGFSM_PWR_STATUS, pwr_status, 276 1, 1000); 277 break; 278 case 2: /* DSC2 */ 279 REG_UPDATE(DOMAIN18_PG_CONFIG, 280 DOMAIN_POWER_GATE, power_gate); 281 282 REG_WAIT(DOMAIN18_PG_STATUS, 283 DOMAIN_PGFSM_PWR_STATUS, pwr_status, 284 1, 1000); 285 break; 286 case 3: /* DSC3 */ 287 REG_UPDATE(DOMAIN19_PG_CONFIG, 288 DOMAIN_POWER_GATE, power_gate); 289 290 REG_WAIT(DOMAIN19_PG_STATUS, 291 DOMAIN_PGFSM_PWR_STATUS, pwr_status, 292 1, 1000); 293 break; 294 default: 295 BREAK_TO_DEBUGGER(); 296 break; 297 } 298 299 if (org_ip_request_cntl == 0) 300 REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 0); 301 302 if (hws->ctx->dc->debug.root_clock_optimization.bits.dsc) { 303 if (hws->ctx->dc->res_pool->dccg->funcs->disable_dsc && !power_on) 304 hws->ctx->dc->res_pool->dccg->funcs->disable_dsc( 305 hws->ctx->dc->res_pool->dccg, dsc_inst); 306 } 307 308 } 309 310 void dcn314_enable_power_gating_plane(struct dce_hwseq *hws, bool enable) 311 { 312 bool force_on = true; /* disable power gating */ 313 uint32_t org_ip_request_cntl = 0; 314 315 if (enable && !hws->ctx->dc->debug.disable_hubp_power_gate) 316 force_on = false; 317 318 REG_GET(DC_IP_REQUEST_CNTL, IP_REQUEST_EN, &org_ip_request_cntl); 319 if (org_ip_request_cntl == 0) 320 REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 1); 321 /* DCHUBP0/1/2/3/4/5 */ 322 REG_UPDATE(DOMAIN0_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on); 323 REG_UPDATE(DOMAIN2_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on); 324 /* DPP0/1/2/3/4/5 */ 325 REG_UPDATE(DOMAIN1_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on); 326 REG_UPDATE(DOMAIN3_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on); 327 328 force_on = true; /* disable power gating */ 329 if (enable && !hws->ctx->dc->debug.disable_dsc_power_gate) 330 force_on = false; 331 332 /* DCS0/1/2/3/4 */ 333 REG_UPDATE(DOMAIN16_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on); 334 REG_UPDATE(DOMAIN17_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on); 335 REG_UPDATE(DOMAIN18_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on); 336 REG_UPDATE(DOMAIN19_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on); 337 338 if (org_ip_request_cntl == 0) 339 REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 0); 340 } 341 342 unsigned int dcn314_calculate_dccg_k1_k2_values(struct pipe_ctx *pipe_ctx, unsigned int *k1_div, unsigned int *k2_div) 343 { 344 struct dc_stream_state *stream = pipe_ctx->stream; 345 unsigned int odm_combine_factor = 0; 346 bool two_pix_per_container = false; 347 348 two_pix_per_container = optc2_is_two_pixels_per_containter(&stream->timing); 349 odm_combine_factor = get_odm_config(pipe_ctx, NULL); 350 351 if (pipe_ctx->stream->signal == SIGNAL_TYPE_VIRTUAL) 352 return odm_combine_factor; 353 354 if (is_dp_128b_132b_signal(pipe_ctx)) { 355 *k2_div = PIXEL_RATE_DIV_BY_1; 356 } else if (dc_is_hdmi_tmds_signal(pipe_ctx->stream->signal) || dc_is_dvi_signal(pipe_ctx->stream->signal)) { 357 *k1_div = PIXEL_RATE_DIV_BY_1; 358 if (stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR420) 359 *k2_div = PIXEL_RATE_DIV_BY_2; 360 else 361 *k2_div = PIXEL_RATE_DIV_BY_4; 362 } else if (dc_is_dp_signal(pipe_ctx->stream->signal)) { 363 if (two_pix_per_container) { 364 *k1_div = PIXEL_RATE_DIV_BY_1; 365 *k2_div = PIXEL_RATE_DIV_BY_2; 366 } else { 367 *k1_div = PIXEL_RATE_DIV_BY_1; 368 *k2_div = PIXEL_RATE_DIV_BY_4; 369 if (odm_combine_factor == 2) 370 *k2_div = PIXEL_RATE_DIV_BY_2; 371 } 372 } 373 374 if ((*k1_div == PIXEL_RATE_DIV_NA) && (*k2_div == PIXEL_RATE_DIV_NA)) 375 ASSERT(false); 376 377 return odm_combine_factor; 378 } 379 380 void dcn314_set_pixels_per_cycle(struct pipe_ctx *pipe_ctx) 381 { 382 uint32_t pix_per_cycle = 1; 383 uint32_t odm_combine_factor = 1; 384 385 if (!pipe_ctx || !pipe_ctx->stream || !pipe_ctx->stream_res.stream_enc) 386 return; 387 388 odm_combine_factor = get_odm_config(pipe_ctx, NULL); 389 if (optc2_is_two_pixels_per_containter(&pipe_ctx->stream->timing) || odm_combine_factor > 1) 390 pix_per_cycle = 2; 391 392 if (pipe_ctx->stream_res.stream_enc->funcs->set_input_mode) 393 pipe_ctx->stream_res.stream_enc->funcs->set_input_mode(pipe_ctx->stream_res.stream_enc, 394 pix_per_cycle); 395 } 396