1 // SPDX-License-Identifier: MIT
2 /*
3  * Copyright 2022 Advanced Micro Devices, Inc.
4  *
5  * Permission is hereby granted, free of charge, to any person obtaining a
6  * copy of this software and associated documentation files (the "Software"),
7  * to deal in the Software without restriction, including without limitation
8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9  * and/or sell copies of the Software, and to permit persons to whom the
10  * Software is furnished to do so, subject to the following conditions:
11  *
12  * The above copyright notice and this permission notice shall be included in
13  * all copies or substantial portions of the Software.
14  *
15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
18  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21  * OTHER DEALINGS IN THE SOFTWARE.
22  *
23  * Authors: AMD
24  *
25  */
26 
27 
28 #include "dm_services.h"
29 #include "dm_helpers.h"
30 #include "core_types.h"
31 #include "resource.h"
32 #include "dccg.h"
33 #include "dce/dce_hwseq.h"
34 #include "clk_mgr.h"
35 #include "reg_helper.h"
36 #include "abm.h"
37 #include "hubp.h"
38 #include "dchubbub.h"
39 #include "timing_generator.h"
40 #include "opp.h"
41 #include "ipp.h"
42 #include "mpc.h"
43 #include "mcif_wb.h"
44 #include "dc_dmub_srv.h"
45 #include "dcn314_hwseq.h"
46 #include "link_hwss.h"
47 #include "dpcd_defs.h"
48 #include "dce/dmub_outbox.h"
49 #include "link.h"
50 #include "dcn10/dcn10_hw_sequencer.h"
51 #include "inc/link_enc_cfg.h"
52 #include "dcn30/dcn30_vpg.h"
53 #include "dce/dce_i2c_hw.h"
54 #include "dsc.h"
55 #include "dcn20/dcn20_optc.h"
56 #include "dcn30/dcn30_cm_common.h"
57 
58 #define DC_LOGGER_INIT(logger)
59 
60 #define CTX \
61 	hws->ctx
62 #define REG(reg)\
63 	hws->regs->reg
64 #define DC_LOGGER \
65 		dc->ctx->logger
66 
67 
68 #undef FN
69 #define FN(reg_name, field_name) \
70 	hws->shifts->field_name, hws->masks->field_name
71 
72 static int calc_mpc_flow_ctrl_cnt(const struct dc_stream_state *stream,
73 		int opp_cnt)
74 {
75 	bool hblank_halved = optc2_is_two_pixels_per_containter(&stream->timing);
76 	int flow_ctrl_cnt;
77 
78 	if (opp_cnt >= 2)
79 		hblank_halved = true;
80 
81 	flow_ctrl_cnt = stream->timing.h_total - stream->timing.h_addressable -
82 			stream->timing.h_border_left -
83 			stream->timing.h_border_right;
84 
85 	if (hblank_halved)
86 		flow_ctrl_cnt /= 2;
87 
88 	/* ODM combine 4:1 case */
89 	if (opp_cnt == 4)
90 		flow_ctrl_cnt /= 2;
91 
92 	return flow_ctrl_cnt;
93 }
94 
95 static void update_dsc_on_stream(struct pipe_ctx *pipe_ctx, bool enable)
96 {
97 	struct display_stream_compressor *dsc = pipe_ctx->stream_res.dsc;
98 	struct dc_stream_state *stream = pipe_ctx->stream;
99 	struct pipe_ctx *odm_pipe;
100 	int opp_cnt = 1;
101 
102 	ASSERT(dsc);
103 	for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe)
104 		opp_cnt++;
105 
106 	if (enable) {
107 		struct dsc_config dsc_cfg;
108 		struct dsc_optc_config dsc_optc_cfg;
109 		enum optc_dsc_mode optc_dsc_mode;
110 
111 		/* Enable DSC hw block */
112 		dsc_cfg.pic_width = (stream->timing.h_addressable + stream->timing.h_border_left + stream->timing.h_border_right) / opp_cnt;
113 		dsc_cfg.pic_height = stream->timing.v_addressable + stream->timing.v_border_top + stream->timing.v_border_bottom;
114 		dsc_cfg.pixel_encoding = stream->timing.pixel_encoding;
115 		dsc_cfg.color_depth = stream->timing.display_color_depth;
116 		dsc_cfg.is_odm = pipe_ctx->next_odm_pipe ? true : false;
117 		dsc_cfg.dc_dsc_cfg = stream->timing.dsc_cfg;
118 		ASSERT(dsc_cfg.dc_dsc_cfg.num_slices_h % opp_cnt == 0);
119 		dsc_cfg.dc_dsc_cfg.num_slices_h /= opp_cnt;
120 
121 		dsc->funcs->dsc_set_config(dsc, &dsc_cfg, &dsc_optc_cfg);
122 		dsc->funcs->dsc_enable(dsc, pipe_ctx->stream_res.opp->inst);
123 		for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) {
124 			struct display_stream_compressor *odm_dsc = odm_pipe->stream_res.dsc;
125 
126 			ASSERT(odm_dsc);
127 			odm_dsc->funcs->dsc_set_config(odm_dsc, &dsc_cfg, &dsc_optc_cfg);
128 			odm_dsc->funcs->dsc_enable(odm_dsc, odm_pipe->stream_res.opp->inst);
129 		}
130 		dsc_cfg.dc_dsc_cfg.num_slices_h *= opp_cnt;
131 		dsc_cfg.pic_width *= opp_cnt;
132 
133 		optc_dsc_mode = dsc_optc_cfg.is_pixel_format_444 ? OPTC_DSC_ENABLED_444 : OPTC_DSC_ENABLED_NATIVE_SUBSAMPLED;
134 
135 		/* Enable DSC in OPTC */
136 		DC_LOG_DSC("Setting optc DSC config for tg instance %d:", pipe_ctx->stream_res.tg->inst);
137 		pipe_ctx->stream_res.tg->funcs->set_dsc_config(pipe_ctx->stream_res.tg,
138 							optc_dsc_mode,
139 							dsc_optc_cfg.bytes_per_pixel,
140 							dsc_optc_cfg.slice_width);
141 	} else {
142 		/* disable DSC in OPTC */
143 		pipe_ctx->stream_res.tg->funcs->set_dsc_config(
144 				pipe_ctx->stream_res.tg,
145 				OPTC_DSC_DISABLED, 0, 0);
146 
147 		/* disable DSC block */
148 		dsc->funcs->dsc_disable(pipe_ctx->stream_res.dsc);
149 		for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) {
150 			ASSERT(odm_pipe->stream_res.dsc);
151 			odm_pipe->stream_res.dsc->funcs->dsc_disable(odm_pipe->stream_res.dsc);
152 		}
153 	}
154 }
155 
156 // Given any pipe_ctx, return the total ODM combine factor, and optionally return
157 // the OPPids which are used
158 static unsigned int get_odm_config(struct pipe_ctx *pipe_ctx, unsigned int *opp_instances)
159 {
160 	unsigned int opp_count = 1;
161 	struct pipe_ctx *odm_pipe;
162 
163 	// First get to the top pipe
164 	for (odm_pipe = pipe_ctx; odm_pipe->prev_odm_pipe; odm_pipe = odm_pipe->prev_odm_pipe)
165 		;
166 
167 	// First pipe is always used
168 	if (opp_instances)
169 		opp_instances[0] = odm_pipe->stream_res.opp->inst;
170 
171 	// Find and count odm pipes, if any
172 	for (odm_pipe = odm_pipe->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) {
173 		if (opp_instances)
174 			opp_instances[opp_count] = odm_pipe->stream_res.opp->inst;
175 		opp_count++;
176 	}
177 
178 	return opp_count;
179 }
180 
181 void dcn314_update_odm(struct dc *dc, struct dc_state *context, struct pipe_ctx *pipe_ctx)
182 {
183 	struct pipe_ctx *odm_pipe;
184 	int opp_cnt = 0;
185 	int opp_inst[MAX_PIPES] = {0};
186 	bool rate_control_2x_pclk = (pipe_ctx->stream->timing.flags.INTERLACE || optc2_is_two_pixels_per_containter(&pipe_ctx->stream->timing));
187 	struct mpc_dwb_flow_control flow_control;
188 	struct mpc *mpc = dc->res_pool->mpc;
189 	int i;
190 
191 	opp_cnt = get_odm_config(pipe_ctx, opp_inst);
192 
193 	if (opp_cnt > 1)
194 		pipe_ctx->stream_res.tg->funcs->set_odm_combine(
195 				pipe_ctx->stream_res.tg,
196 				opp_inst, opp_cnt,
197 				&pipe_ctx->stream->timing);
198 	else
199 		pipe_ctx->stream_res.tg->funcs->set_odm_bypass(
200 				pipe_ctx->stream_res.tg, &pipe_ctx->stream->timing);
201 
202 	rate_control_2x_pclk = rate_control_2x_pclk || opp_cnt > 1;
203 	flow_control.flow_ctrl_mode = 0;
204 	flow_control.flow_ctrl_cnt0 = 0x80;
205 	flow_control.flow_ctrl_cnt1 = calc_mpc_flow_ctrl_cnt(pipe_ctx->stream, opp_cnt);
206 	if (mpc->funcs->set_out_rate_control) {
207 		for (i = 0; i < opp_cnt; ++i) {
208 			mpc->funcs->set_out_rate_control(
209 					mpc, opp_inst[i],
210 					true,
211 					rate_control_2x_pclk,
212 					&flow_control);
213 		}
214 	}
215 
216 	for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) {
217 		odm_pipe->stream_res.opp->funcs->opp_pipe_clock_control(
218 				odm_pipe->stream_res.opp,
219 				true);
220 	}
221 
222 	if (pipe_ctx->stream_res.dsc) {
223 		struct pipe_ctx *current_pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[pipe_ctx->pipe_idx];
224 
225 		update_dsc_on_stream(pipe_ctx, pipe_ctx->stream->timing.flags.DSC);
226 
227 		/* Check if no longer using pipe for ODM, then need to disconnect DSC for that pipe */
228 		if (!pipe_ctx->next_odm_pipe && current_pipe_ctx->next_odm_pipe &&
229 				current_pipe_ctx->next_odm_pipe->stream_res.dsc) {
230 			struct display_stream_compressor *dsc = current_pipe_ctx->next_odm_pipe->stream_res.dsc;
231 			/* disconnect DSC block from stream */
232 			dsc->funcs->dsc_disconnect(dsc);
233 		}
234 	}
235 }
236 
237 void dcn314_dsc_pg_control(
238 		struct dce_hwseq *hws,
239 		unsigned int dsc_inst,
240 		bool power_on)
241 {
242 	uint32_t power_gate = power_on ? 0 : 1;
243 	uint32_t pwr_status = power_on ? 0 : 2;
244 	uint32_t org_ip_request_cntl = 0;
245 
246 	if (hws->ctx->dc->debug.disable_dsc_power_gate)
247 		return;
248 
249 	if (hws->ctx->dc->debug.root_clock_optimization.bits.dsc &&
250 		hws->ctx->dc->res_pool->dccg->funcs->enable_dsc &&
251 		power_on)
252 		hws->ctx->dc->res_pool->dccg->funcs->enable_dsc(
253 			hws->ctx->dc->res_pool->dccg, dsc_inst);
254 
255 	REG_GET(DC_IP_REQUEST_CNTL, IP_REQUEST_EN, &org_ip_request_cntl);
256 	if (org_ip_request_cntl == 0)
257 		REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 1);
258 
259 	switch (dsc_inst) {
260 	case 0: /* DSC0 */
261 		REG_UPDATE(DOMAIN16_PG_CONFIG,
262 				DOMAIN_POWER_GATE, power_gate);
263 
264 		REG_WAIT(DOMAIN16_PG_STATUS,
265 				DOMAIN_PGFSM_PWR_STATUS, pwr_status,
266 				1, 1000);
267 		break;
268 	case 1: /* DSC1 */
269 		REG_UPDATE(DOMAIN17_PG_CONFIG,
270 				DOMAIN_POWER_GATE, power_gate);
271 
272 		REG_WAIT(DOMAIN17_PG_STATUS,
273 				DOMAIN_PGFSM_PWR_STATUS, pwr_status,
274 				1, 1000);
275 		break;
276 	case 2: /* DSC2 */
277 		REG_UPDATE(DOMAIN18_PG_CONFIG,
278 				DOMAIN_POWER_GATE, power_gate);
279 
280 		REG_WAIT(DOMAIN18_PG_STATUS,
281 				DOMAIN_PGFSM_PWR_STATUS, pwr_status,
282 				1, 1000);
283 		break;
284 	case 3: /* DSC3 */
285 		REG_UPDATE(DOMAIN19_PG_CONFIG,
286 				DOMAIN_POWER_GATE, power_gate);
287 
288 		REG_WAIT(DOMAIN19_PG_STATUS,
289 				DOMAIN_PGFSM_PWR_STATUS, pwr_status,
290 				1, 1000);
291 		break;
292 	default:
293 		BREAK_TO_DEBUGGER();
294 		break;
295 	}
296 
297 	if (org_ip_request_cntl == 0)
298 		REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 0);
299 
300 	if (hws->ctx->dc->debug.root_clock_optimization.bits.dsc) {
301 		if (hws->ctx->dc->res_pool->dccg->funcs->disable_dsc && !power_on)
302 			hws->ctx->dc->res_pool->dccg->funcs->disable_dsc(
303 				hws->ctx->dc->res_pool->dccg, dsc_inst);
304 	}
305 
306 }
307 
308 void dcn314_enable_power_gating_plane(struct dce_hwseq *hws, bool enable)
309 {
310 	bool force_on = true; /* disable power gating */
311 	uint32_t org_ip_request_cntl = 0;
312 
313 	if (enable && !hws->ctx->dc->debug.disable_hubp_power_gate)
314 		force_on = false;
315 
316 	REG_GET(DC_IP_REQUEST_CNTL, IP_REQUEST_EN, &org_ip_request_cntl);
317 	if (org_ip_request_cntl == 0)
318 		REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 1);
319 	/* DCHUBP0/1/2/3/4/5 */
320 	REG_UPDATE(DOMAIN0_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on);
321 	REG_UPDATE(DOMAIN2_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on);
322 	/* DPP0/1/2/3/4/5 */
323 	REG_UPDATE(DOMAIN1_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on);
324 	REG_UPDATE(DOMAIN3_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on);
325 
326 	force_on = true; /* disable power gating */
327 	if (enable && !hws->ctx->dc->debug.disable_dsc_power_gate)
328 		force_on = false;
329 
330 	/* DCS0/1/2/3/4 */
331 	REG_UPDATE(DOMAIN16_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on);
332 	REG_UPDATE(DOMAIN17_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on);
333 	REG_UPDATE(DOMAIN18_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on);
334 	REG_UPDATE(DOMAIN19_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on);
335 
336 	if (org_ip_request_cntl == 0)
337 		REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 0);
338 }
339 
340 unsigned int dcn314_calculate_dccg_k1_k2_values(struct pipe_ctx *pipe_ctx, unsigned int *k1_div, unsigned int *k2_div)
341 {
342 	struct dc_stream_state *stream = pipe_ctx->stream;
343 	unsigned int odm_combine_factor = 0;
344 	bool two_pix_per_container = false;
345 
346 	two_pix_per_container = optc2_is_two_pixels_per_containter(&stream->timing);
347 	odm_combine_factor = get_odm_config(pipe_ctx, NULL);
348 
349 	if (stream->ctx->dc->link_srv->dp_is_128b_132b_signal(pipe_ctx)) {
350 		*k1_div = PIXEL_RATE_DIV_BY_1;
351 		*k2_div = PIXEL_RATE_DIV_BY_1;
352 	} else if (dc_is_hdmi_tmds_signal(pipe_ctx->stream->signal) || dc_is_dvi_signal(pipe_ctx->stream->signal)) {
353 		*k1_div = PIXEL_RATE_DIV_BY_1;
354 		if (stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR420)
355 			*k2_div = PIXEL_RATE_DIV_BY_2;
356 		else
357 			*k2_div = PIXEL_RATE_DIV_BY_4;
358 	} else if (dc_is_dp_signal(pipe_ctx->stream->signal) || dc_is_virtual_signal(pipe_ctx->stream->signal)) {
359 		if (two_pix_per_container) {
360 			*k1_div = PIXEL_RATE_DIV_BY_1;
361 			*k2_div = PIXEL_RATE_DIV_BY_2;
362 		} else {
363 			*k1_div = PIXEL_RATE_DIV_BY_1;
364 			*k2_div = PIXEL_RATE_DIV_BY_4;
365 			if (odm_combine_factor == 2)
366 				*k2_div = PIXEL_RATE_DIV_BY_2;
367 		}
368 	}
369 
370 	if ((*k1_div == PIXEL_RATE_DIV_NA) && (*k2_div == PIXEL_RATE_DIV_NA))
371 		ASSERT(false);
372 
373 	return odm_combine_factor;
374 }
375 
376 void dcn314_set_pixels_per_cycle(struct pipe_ctx *pipe_ctx)
377 {
378 	uint32_t pix_per_cycle = 1;
379 	uint32_t odm_combine_factor = 1;
380 
381 	if (!pipe_ctx || !pipe_ctx->stream || !pipe_ctx->stream_res.stream_enc)
382 		return;
383 
384 	odm_combine_factor = get_odm_config(pipe_ctx, NULL);
385 	if (optc2_is_two_pixels_per_containter(&pipe_ctx->stream->timing) || odm_combine_factor > 1)
386 		pix_per_cycle = 2;
387 
388 	if (pipe_ctx->stream_res.stream_enc->funcs->set_input_mode)
389 		pipe_ctx->stream_res.stream_enc->funcs->set_input_mode(pipe_ctx->stream_res.stream_enc,
390 				pix_per_cycle);
391 }
392 
393 void dcn314_resync_fifo_dccg_dio(struct dce_hwseq *hws, struct dc *dc, struct dc_state *context)
394 {
395 	unsigned int i;
396 	struct pipe_ctx *pipe = NULL;
397 	bool otg_disabled[MAX_PIPES] = {false};
398 
399 	for (i = 0; i < dc->res_pool->pipe_count; i++) {
400 		pipe = &dc->current_state->res_ctx.pipe_ctx[i];
401 
402 		if (pipe->top_pipe || pipe->prev_odm_pipe)
403 			continue;
404 
405 		if (pipe->stream && (pipe->stream->dpms_off || dc_is_virtual_signal(pipe->stream->signal))) {
406 			pipe->stream_res.tg->funcs->disable_crtc(pipe->stream_res.tg);
407 			reset_sync_context_for_pipe(dc, context, i);
408 			otg_disabled[i] = true;
409 		}
410 	}
411 
412 	hws->ctx->dc->res_pool->dccg->funcs->trigger_dio_fifo_resync(hws->ctx->dc->res_pool->dccg);
413 
414 	for (i = 0; i < dc->res_pool->pipe_count; i++) {
415 		pipe = &dc->current_state->res_ctx.pipe_ctx[i];
416 
417 		if (otg_disabled[i])
418 			pipe->stream_res.tg->funcs->enable_crtc(pipe->stream_res.tg);
419 	}
420 }
421 
422 void dcn314_dpp_root_clock_control(struct dce_hwseq *hws, unsigned int dpp_inst, bool clock_on)
423 {
424 	if (!hws->ctx->dc->debug.root_clock_optimization.bits.dpp)
425 		return;
426 
427 	if (hws->ctx->dc->res_pool->dccg->funcs->dpp_root_clock_control)
428 		hws->ctx->dc->res_pool->dccg->funcs->dpp_root_clock_control(
429 			hws->ctx->dc->res_pool->dccg, dpp_inst, clock_on);
430 }
431 
432 static void apply_symclk_on_tx_off_wa(struct dc_link *link)
433 {
434 	/* There are use cases where SYMCLK is referenced by OTG. For instance
435 	 * for TMDS signal, OTG relies SYMCLK even if TX video output is off.
436 	 * However current link interface will power off PHY when disabling link
437 	 * output. This will turn off SYMCLK generated by PHY. The workaround is
438 	 * to identify such case where SYMCLK is still in use by OTG when we
439 	 * power off PHY. When this is detected, we will temporarily power PHY
440 	 * back on and move PHY's SYMCLK state to SYMCLK_ON_TX_OFF by calling
441 	 * program_pix_clk interface. When OTG is disabled, we will then power
442 	 * off PHY by calling disable link output again.
443 	 *
444 	 * In future dcn generations, we plan to rework transmitter control
445 	 * interface so that we could have an option to set SYMCLK ON TX OFF
446 	 * state in one step without this workaround
447 	 */
448 
449 	struct dc *dc = link->ctx->dc;
450 	struct pipe_ctx *pipe_ctx = NULL;
451 	uint8_t i;
452 
453 	if (link->phy_state.symclk_ref_cnts.otg > 0) {
454 		for (i = 0; i < MAX_PIPES; i++) {
455 			pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[i];
456 			if (pipe_ctx->stream && pipe_ctx->stream->link == link && pipe_ctx->top_pipe == NULL) {
457 				pipe_ctx->clock_source->funcs->program_pix_clk(
458 						pipe_ctx->clock_source,
459 						&pipe_ctx->stream_res.pix_clk_params,
460 						dc->link_srv->dp_get_encoding_format(
461 								&pipe_ctx->link_config.dp_link_settings),
462 						&pipe_ctx->pll_settings);
463 				link->phy_state.symclk_state = SYMCLK_ON_TX_OFF;
464 				break;
465 			}
466 		}
467 	}
468 }
469 
470 void dcn314_disable_link_output(struct dc_link *link,
471 		const struct link_resource *link_res,
472 		enum signal_type signal)
473 {
474 	struct dc *dc = link->ctx->dc;
475 	const struct link_hwss *link_hwss = get_link_hwss(link, link_res);
476 	struct dmcu *dmcu = dc->res_pool->dmcu;
477 
478 	if (signal == SIGNAL_TYPE_EDP &&
479 			link->dc->hwss.edp_backlight_control)
480 		link->dc->hwss.edp_backlight_control(link, false);
481 	else if (dmcu != NULL && dmcu->funcs->lock_phy)
482 		dmcu->funcs->lock_phy(dmcu);
483 
484 	link_hwss->disable_link_output(link, link_res, signal);
485 	link->phy_state.symclk_state = SYMCLK_OFF_TX_OFF;
486 	/*
487 	 * Add the logic to extract BOTH power up and power down sequences
488 	 * from enable/disable link output and only call edp panel control
489 	 * in enable_link_dp and disable_link_dp once.
490 	 */
491 	if (dmcu != NULL && dmcu->funcs->lock_phy)
492 		dmcu->funcs->unlock_phy(dmcu);
493 	dc->link_srv->dp_trace_source_sequence(link, DPCD_SOURCE_SEQ_AFTER_DISABLE_LINK_PHY);
494 
495 	apply_symclk_on_tx_off_wa(link);
496 }
497