12083640fSNicholas Kazlauskas /* 22083640fSNicholas Kazlauskas * Copyright 2020 Advanced Micro Devices, Inc. 32083640fSNicholas Kazlauskas * 42083640fSNicholas Kazlauskas * Permission is hereby granted, free of charge, to any person obtaining a 52083640fSNicholas Kazlauskas * copy of this software and associated documentation files (the "Software"), 62083640fSNicholas Kazlauskas * to deal in the Software without restriction, including without limitation 72083640fSNicholas Kazlauskas * the rights to use, copy, modify, merge, publish, distribute, sublicense, 82083640fSNicholas Kazlauskas * and/or sell copies of the Software, and to permit persons to whom the 92083640fSNicholas Kazlauskas * Software is furnished to do so, subject to the following conditions: 102083640fSNicholas Kazlauskas * 112083640fSNicholas Kazlauskas * The above copyright notice and this permission notice shall be included in 122083640fSNicholas Kazlauskas * all copies or substantial portions of the Software. 132083640fSNicholas Kazlauskas * 142083640fSNicholas Kazlauskas * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 152083640fSNicholas Kazlauskas * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 162083640fSNicholas Kazlauskas * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 172083640fSNicholas Kazlauskas * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 182083640fSNicholas Kazlauskas * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 192083640fSNicholas Kazlauskas * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 202083640fSNicholas Kazlauskas * OTHER DEALINGS IN THE SOFTWARE. 212083640fSNicholas Kazlauskas * 222083640fSNicholas Kazlauskas * Authors: AMD 232083640fSNicholas Kazlauskas * 242083640fSNicholas Kazlauskas */ 252083640fSNicholas Kazlauskas 262083640fSNicholas Kazlauskas #ifndef _DCN31_RESOURCE_H_ 272083640fSNicholas Kazlauskas #define _DCN31_RESOURCE_H_ 282083640fSNicholas Kazlauskas 292083640fSNicholas Kazlauskas #include "core_types.h" 302083640fSNicholas Kazlauskas 312083640fSNicholas Kazlauskas #define TO_DCN31_RES_POOL(pool)\ 322083640fSNicholas Kazlauskas container_of(pool, struct dcn31_resource_pool, base) 332083640fSNicholas Kazlauskas 342083640fSNicholas Kazlauskas struct dcn31_resource_pool { 352083640fSNicholas Kazlauskas struct resource_pool base; 362083640fSNicholas Kazlauskas }; 372083640fSNicholas Kazlauskas 38876e835eSDmytro Laktyushkin bool dcn31_validate_bandwidth(struct dc *dc, 39876e835eSDmytro Laktyushkin struct dc_state *context, 40876e835eSDmytro Laktyushkin bool fast_validate); 41876e835eSDmytro Laktyushkin void dcn31_calculate_wm_and_dlg( 42876e835eSDmytro Laktyushkin struct dc *dc, struct dc_state *context, 43876e835eSDmytro Laktyushkin display_e2e_pipe_params_st *pipes, 44876e835eSDmytro Laktyushkin int pipe_cnt, 45876e835eSDmytro Laktyushkin int vlevel); 46876e835eSDmytro Laktyushkin void dcn31_update_soc_for_wm_a(struct dc *dc, struct dc_state *context); 47876e835eSDmytro Laktyushkin 482083640fSNicholas Kazlauskas struct resource_pool *dcn31_create_resource_pool( 492083640fSNicholas Kazlauskas const struct dc_init_data *init_data, 502083640fSNicholas Kazlauskas struct dc *dc); 512083640fSNicholas Kazlauskas 52*2eb82577SCharlene Liu /*temp: B0 specific before switch to dcn313 headers*/ 53*2eb82577SCharlene Liu #ifndef regPHYPLLF_PIXCLK_RESYNC_CNTL 54*2eb82577SCharlene Liu #define regPHYPLLF_PIXCLK_RESYNC_CNTL 0x007e 55*2eb82577SCharlene Liu #define regPHYPLLF_PIXCLK_RESYNC_CNTL_BASE_IDX 1 56*2eb82577SCharlene Liu #define regPHYPLLG_PIXCLK_RESYNC_CNTL 0x005f 57*2eb82577SCharlene Liu #define regPHYPLLG_PIXCLK_RESYNC_CNTL_BASE_IDX 1 58*2eb82577SCharlene Liu 59*2eb82577SCharlene Liu //PHYPLLF_PIXCLK_RESYNC_CNTL 60*2eb82577SCharlene Liu #define PHYPLLF_PIXCLK_RESYNC_CNTL__PHYPLLF_PIXCLK_RESYNC_ENABLE__SHIFT 0x0 61*2eb82577SCharlene Liu #define PHYPLLF_PIXCLK_RESYNC_CNTL__PHYPLLF_DEEP_COLOR_DTO_ENABLE_STATUS__SHIFT 0x1 62*2eb82577SCharlene Liu #define PHYPLLF_PIXCLK_RESYNC_CNTL__PHYPLLF_DCCG_DEEP_COLOR_CNTL__SHIFT 0x4 63*2eb82577SCharlene Liu #define PHYPLLF_PIXCLK_RESYNC_CNTL__PHYPLLF_PIXCLK_ENABLE__SHIFT 0x8 64*2eb82577SCharlene Liu #define PHYPLLF_PIXCLK_RESYNC_CNTL__PHYPLLF_PIXCLK_DOUBLE_RATE_ENABLE__SHIFT 0x9 65*2eb82577SCharlene Liu #define PHYPLLF_PIXCLK_RESYNC_CNTL__PHYPLLF_PIXCLK_RESYNC_ENABLE_MASK 0x00000001L 66*2eb82577SCharlene Liu #define PHYPLLF_PIXCLK_RESYNC_CNTL__PHYPLLF_DEEP_COLOR_DTO_ENABLE_STATUS_MASK 0x00000002L 67*2eb82577SCharlene Liu #define PHYPLLF_PIXCLK_RESYNC_CNTL__PHYPLLF_DCCG_DEEP_COLOR_CNTL_MASK 0x00000030L 68*2eb82577SCharlene Liu #define PHYPLLF_PIXCLK_RESYNC_CNTL__PHYPLLF_PIXCLK_ENABLE_MASK 0x00000100L 69*2eb82577SCharlene Liu #define PHYPLLF_PIXCLK_RESYNC_CNTL__PHYPLLF_PIXCLK_DOUBLE_RATE_ENABLE_MASK 0x00000200L 70*2eb82577SCharlene Liu 71*2eb82577SCharlene Liu //PHYPLLG_PIXCLK_RESYNC_CNTL 72*2eb82577SCharlene Liu #define PHYPLLG_PIXCLK_RESYNC_CNTL__PHYPLLG_PIXCLK_RESYNC_ENABLE__SHIFT 0x0 73*2eb82577SCharlene Liu #define PHYPLLG_PIXCLK_RESYNC_CNTL__PHYPLLG_DEEP_COLOR_DTO_ENABLE_STATUS__SHIFT 0x1 74*2eb82577SCharlene Liu #define PHYPLLG_PIXCLK_RESYNC_CNTL__PHYPLLG_DCCG_DEEP_COLOR_CNTL__SHIFT 0x4 75*2eb82577SCharlene Liu #define PHYPLLG_PIXCLK_RESYNC_CNTL__PHYPLLG_PIXCLK_ENABLE__SHIFT 0x8 76*2eb82577SCharlene Liu #define PHYPLLG_PIXCLK_RESYNC_CNTL__PHYPLLG_PIXCLK_DOUBLE_RATE_ENABLE__SHIFT 0x9 77*2eb82577SCharlene Liu #define PHYPLLG_PIXCLK_RESYNC_CNTL__PHYPLLG_PIXCLK_RESYNC_ENABLE_MASK 0x00000001L 78*2eb82577SCharlene Liu #define PHYPLLG_PIXCLK_RESYNC_CNTL__PHYPLLG_DEEP_COLOR_DTO_ENABLE_STATUS_MASK 0x00000002L 79*2eb82577SCharlene Liu #define PHYPLLG_PIXCLK_RESYNC_CNTL__PHYPLLG_DCCG_DEEP_COLOR_CNTL_MASK 0x00000030L 80*2eb82577SCharlene Liu #define PHYPLLG_PIXCLK_RESYNC_CNTL__PHYPLLG_PIXCLK_ENABLE_MASK 0x00000100L 81*2eb82577SCharlene Liu #define PHYPLLG_PIXCLK_RESYNC_CNTL__PHYPLLG_PIXCLK_DOUBLE_RATE_ENABLE_MASK 0x00000200L 82*2eb82577SCharlene Liu #endif 832083640fSNicholas Kazlauskas #endif /* _DCN31_RESOURCE_H_ */ 84