12083640fSNicholas Kazlauskas /* 22083640fSNicholas Kazlauskas * Copyright 2020 Advanced Micro Devices, Inc. 32083640fSNicholas Kazlauskas * 42083640fSNicholas Kazlauskas * Permission is hereby granted, free of charge, to any person obtaining a 52083640fSNicholas Kazlauskas * copy of this software and associated documentation files (the "Software"), 62083640fSNicholas Kazlauskas * to deal in the Software without restriction, including without limitation 72083640fSNicholas Kazlauskas * the rights to use, copy, modify, merge, publish, distribute, sublicense, 82083640fSNicholas Kazlauskas * and/or sell copies of the Software, and to permit persons to whom the 92083640fSNicholas Kazlauskas * Software is furnished to do so, subject to the following conditions: 102083640fSNicholas Kazlauskas * 112083640fSNicholas Kazlauskas * The above copyright notice and this permission notice shall be included in 122083640fSNicholas Kazlauskas * all copies or substantial portions of the Software. 132083640fSNicholas Kazlauskas * 142083640fSNicholas Kazlauskas * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 152083640fSNicholas Kazlauskas * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 162083640fSNicholas Kazlauskas * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 172083640fSNicholas Kazlauskas * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 182083640fSNicholas Kazlauskas * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 192083640fSNicholas Kazlauskas * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 202083640fSNicholas Kazlauskas * OTHER DEALINGS IN THE SOFTWARE. 212083640fSNicholas Kazlauskas * 222083640fSNicholas Kazlauskas * Authors: AMD 232083640fSNicholas Kazlauskas * 242083640fSNicholas Kazlauskas */ 252083640fSNicholas Kazlauskas 262083640fSNicholas Kazlauskas #ifndef _DCN31_RESOURCE_H_ 272083640fSNicholas Kazlauskas #define _DCN31_RESOURCE_H_ 282083640fSNicholas Kazlauskas 292083640fSNicholas Kazlauskas #include "core_types.h" 302083640fSNicholas Kazlauskas 312083640fSNicholas Kazlauskas #define TO_DCN31_RES_POOL(pool)\ 322083640fSNicholas Kazlauskas container_of(pool, struct dcn31_resource_pool, base) 332083640fSNicholas Kazlauskas 3426f4712aSMelissa Wen extern struct _vcs_dpi_ip_params_st dcn3_1_ip; 3526f4712aSMelissa Wen 362083640fSNicholas Kazlauskas struct dcn31_resource_pool { 372083640fSNicholas Kazlauskas struct resource_pool base; 382083640fSNicholas Kazlauskas }; 392083640fSNicholas Kazlauskas 40876e835eSDmytro Laktyushkin bool dcn31_validate_bandwidth(struct dc *dc, 41876e835eSDmytro Laktyushkin struct dc_state *context, 42876e835eSDmytro Laktyushkin bool fast_validate); 43876e835eSDmytro Laktyushkin void dcn31_calculate_wm_and_dlg( 44876e835eSDmytro Laktyushkin struct dc *dc, struct dc_state *context, 45876e835eSDmytro Laktyushkin display_e2e_pipe_params_st *pipes, 46876e835eSDmytro Laktyushkin int pipe_cnt, 47876e835eSDmytro Laktyushkin int vlevel); 486dc0fdedSNicholas Kazlauskas int dcn31_populate_dml_pipes_from_context( 496dc0fdedSNicholas Kazlauskas struct dc *dc, struct dc_state *context, 506dc0fdedSNicholas Kazlauskas display_e2e_pipe_params_st *pipes, 516dc0fdedSNicholas Kazlauskas bool fast_validate); 52*7324d02aSMelissa Wen void 53*7324d02aSMelissa Wen dcn31_populate_dml_writeback_from_context(struct dc *dc, 54*7324d02aSMelissa Wen struct resource_context *res_ctx, 55*7324d02aSMelissa Wen display_e2e_pipe_params_st *pipes); 56*7324d02aSMelissa Wen void 57*7324d02aSMelissa Wen dcn31_set_mcif_arb_params(struct dc *dc, 58*7324d02aSMelissa Wen struct dc_state *context, 59*7324d02aSMelissa Wen display_e2e_pipe_params_st *pipes, 60*7324d02aSMelissa Wen int pipe_cnt); 61876e835eSDmytro Laktyushkin 622083640fSNicholas Kazlauskas struct resource_pool *dcn31_create_resource_pool( 632083640fSNicholas Kazlauskas const struct dc_init_data *init_data, 642083640fSNicholas Kazlauskas struct dc *dc); 652083640fSNicholas Kazlauskas 662eb82577SCharlene Liu /*temp: B0 specific before switch to dcn313 headers*/ 672eb82577SCharlene Liu #ifndef regPHYPLLF_PIXCLK_RESYNC_CNTL 682eb82577SCharlene Liu #define regPHYPLLF_PIXCLK_RESYNC_CNTL 0x007e 692eb82577SCharlene Liu #define regPHYPLLF_PIXCLK_RESYNC_CNTL_BASE_IDX 1 702eb82577SCharlene Liu #define regPHYPLLG_PIXCLK_RESYNC_CNTL 0x005f 712eb82577SCharlene Liu #define regPHYPLLG_PIXCLK_RESYNC_CNTL_BASE_IDX 1 722eb82577SCharlene Liu 732eb82577SCharlene Liu //PHYPLLF_PIXCLK_RESYNC_CNTL 742eb82577SCharlene Liu #define PHYPLLF_PIXCLK_RESYNC_CNTL__PHYPLLF_PIXCLK_RESYNC_ENABLE__SHIFT 0x0 752eb82577SCharlene Liu #define PHYPLLF_PIXCLK_RESYNC_CNTL__PHYPLLF_DEEP_COLOR_DTO_ENABLE_STATUS__SHIFT 0x1 762eb82577SCharlene Liu #define PHYPLLF_PIXCLK_RESYNC_CNTL__PHYPLLF_DCCG_DEEP_COLOR_CNTL__SHIFT 0x4 772eb82577SCharlene Liu #define PHYPLLF_PIXCLK_RESYNC_CNTL__PHYPLLF_PIXCLK_ENABLE__SHIFT 0x8 782eb82577SCharlene Liu #define PHYPLLF_PIXCLK_RESYNC_CNTL__PHYPLLF_PIXCLK_DOUBLE_RATE_ENABLE__SHIFT 0x9 792eb82577SCharlene Liu #define PHYPLLF_PIXCLK_RESYNC_CNTL__PHYPLLF_PIXCLK_RESYNC_ENABLE_MASK 0x00000001L 802eb82577SCharlene Liu #define PHYPLLF_PIXCLK_RESYNC_CNTL__PHYPLLF_DEEP_COLOR_DTO_ENABLE_STATUS_MASK 0x00000002L 812eb82577SCharlene Liu #define PHYPLLF_PIXCLK_RESYNC_CNTL__PHYPLLF_DCCG_DEEP_COLOR_CNTL_MASK 0x00000030L 822eb82577SCharlene Liu #define PHYPLLF_PIXCLK_RESYNC_CNTL__PHYPLLF_PIXCLK_ENABLE_MASK 0x00000100L 832eb82577SCharlene Liu #define PHYPLLF_PIXCLK_RESYNC_CNTL__PHYPLLF_PIXCLK_DOUBLE_RATE_ENABLE_MASK 0x00000200L 842eb82577SCharlene Liu 852eb82577SCharlene Liu //PHYPLLG_PIXCLK_RESYNC_CNTL 862eb82577SCharlene Liu #define PHYPLLG_PIXCLK_RESYNC_CNTL__PHYPLLG_PIXCLK_RESYNC_ENABLE__SHIFT 0x0 872eb82577SCharlene Liu #define PHYPLLG_PIXCLK_RESYNC_CNTL__PHYPLLG_DEEP_COLOR_DTO_ENABLE_STATUS__SHIFT 0x1 882eb82577SCharlene Liu #define PHYPLLG_PIXCLK_RESYNC_CNTL__PHYPLLG_DCCG_DEEP_COLOR_CNTL__SHIFT 0x4 892eb82577SCharlene Liu #define PHYPLLG_PIXCLK_RESYNC_CNTL__PHYPLLG_PIXCLK_ENABLE__SHIFT 0x8 902eb82577SCharlene Liu #define PHYPLLG_PIXCLK_RESYNC_CNTL__PHYPLLG_PIXCLK_DOUBLE_RATE_ENABLE__SHIFT 0x9 912eb82577SCharlene Liu #define PHYPLLG_PIXCLK_RESYNC_CNTL__PHYPLLG_PIXCLK_RESYNC_ENABLE_MASK 0x00000001L 922eb82577SCharlene Liu #define PHYPLLG_PIXCLK_RESYNC_CNTL__PHYPLLG_DEEP_COLOR_DTO_ENABLE_STATUS_MASK 0x00000002L 932eb82577SCharlene Liu #define PHYPLLG_PIXCLK_RESYNC_CNTL__PHYPLLG_DCCG_DEEP_COLOR_CNTL_MASK 0x00000030L 942eb82577SCharlene Liu #define PHYPLLG_PIXCLK_RESYNC_CNTL__PHYPLLG_PIXCLK_ENABLE_MASK 0x00000100L 952eb82577SCharlene Liu #define PHYPLLG_PIXCLK_RESYNC_CNTL__PHYPLLG_PIXCLK_DOUBLE_RATE_ENABLE_MASK 0x00000200L 962eb82577SCharlene Liu #endif 972083640fSNicholas Kazlauskas #endif /* _DCN31_RESOURCE_H_ */ 98