1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 27 #include "dm_services.h" 28 #include "dc.h" 29 30 #include "dcn31/dcn31_init.h" 31 32 #include "resource.h" 33 #include "include/irq_service_interface.h" 34 #include "dcn31_resource.h" 35 36 #include "dcn20/dcn20_resource.h" 37 #include "dcn30/dcn30_resource.h" 38 39 #include "dcn10/dcn10_ipp.h" 40 #include "dcn30/dcn30_hubbub.h" 41 #include "dcn31/dcn31_hubbub.h" 42 #include "dcn30/dcn30_mpc.h" 43 #include "dcn31/dcn31_hubp.h" 44 #include "irq/dcn31/irq_service_dcn31.h" 45 #include "dcn30/dcn30_dpp.h" 46 #include "dcn31/dcn31_optc.h" 47 #include "dcn20/dcn20_hwseq.h" 48 #include "dcn30/dcn30_hwseq.h" 49 #include "dce110/dce110_hw_sequencer.h" 50 #include "dcn30/dcn30_opp.h" 51 #include "dcn20/dcn20_dsc.h" 52 #include "dcn30/dcn30_vpg.h" 53 #include "dcn30/dcn30_afmt.h" 54 #include "dcn30/dcn30_dio_stream_encoder.h" 55 #include "dcn31/dcn31_dio_link_encoder.h" 56 #include "dce/dce_clock_source.h" 57 #include "dce/dce_audio.h" 58 #include "dce/dce_hwseq.h" 59 #include "clk_mgr.h" 60 #include "virtual/virtual_stream_encoder.h" 61 #include "dce110/dce110_resource.h" 62 #include "dml/display_mode_vba.h" 63 #include "dcn31/dcn31_dccg.h" 64 #include "dcn10/dcn10_resource.h" 65 #include "dcn31_panel_cntl.h" 66 67 #include "dcn30/dcn30_dwb.h" 68 #include "dcn30/dcn30_mmhubbub.h" 69 70 // TODO: change include headers /amd/include/asic_reg after upstream 71 #include "yellow_carp_offset.h" 72 #include "dcn/dcn_3_1_2_offset.h" 73 #include "dcn/dcn_3_1_2_sh_mask.h" 74 #include "nbio/nbio_7_2_0_offset.h" 75 #include "dpcs/dpcs_4_2_0_offset.h" 76 #include "dpcs/dpcs_4_2_0_sh_mask.h" 77 #include "mmhub/mmhub_2_3_0_offset.h" 78 #include "mmhub/mmhub_2_3_0_sh_mask.h" 79 80 81 #define regDCHUBBUB_DEBUG_CTRL_0 0x04d6 82 #define regDCHUBBUB_DEBUG_CTRL_0_BASE_IDX 2 83 #define DCHUBBUB_DEBUG_CTRL_0__DET_DEPTH__SHIFT 0x10 84 #define DCHUBBUB_DEBUG_CTRL_0__DET_DEPTH_MASK 0x01FF0000L 85 86 #include "reg_helper.h" 87 #include "dce/dmub_abm.h" 88 #include "dce/dmub_psr.h" 89 #include "dce/dce_aux.h" 90 #include "dce/dce_i2c.h" 91 92 #include "dml/dcn30/display_mode_vba_30.h" 93 #include "vm_helper.h" 94 #include "dcn20/dcn20_vmid.h" 95 96 #include "link_enc_cfg.h" 97 98 #define DC_LOGGER_INIT(logger) 99 #define fixed16_to_double(x) (((double) x) / ((double) (1 << 16))) 100 #define fixed16_to_double_to_cpu(x) fixed16_to_double(le32_to_cpu(x)) 101 102 #define DCN3_1_DEFAULT_DET_SIZE 384 103 104 struct _vcs_dpi_ip_params_st dcn3_1_ip = { 105 .gpuvm_enable = 1, 106 .gpuvm_max_page_table_levels = 1, 107 .hostvm_enable = 1, 108 .hostvm_max_page_table_levels = 2, 109 .rob_buffer_size_kbytes = 64, 110 .det_buffer_size_kbytes = DCN3_1_DEFAULT_DET_SIZE, 111 .config_return_buffer_size_in_kbytes = 1792, 112 .compressed_buffer_segment_size_in_kbytes = 64, 113 .meta_fifo_size_in_kentries = 32, 114 .zero_size_buffer_entries = 512, 115 .compbuf_reserved_space_64b = 256, 116 .compbuf_reserved_space_zs = 64, 117 .dpp_output_buffer_pixels = 2560, 118 .opp_output_buffer_lines = 1, 119 .pixel_chunk_size_kbytes = 8, 120 .meta_chunk_size_kbytes = 2, 121 .min_meta_chunk_size_bytes = 256, 122 .writeback_chunk_size_kbytes = 8, 123 .ptoi_supported = false, 124 .num_dsc = 3, 125 .maximum_dsc_bits_per_component = 10, 126 .dsc422_native_support = false, 127 .is_line_buffer_bpp_fixed = true, 128 .line_buffer_fixed_bpp = 48, 129 .line_buffer_size_bits = 789504, 130 .max_line_buffer_lines = 12, 131 .writeback_interface_buffer_size_kbytes = 90, 132 .max_num_dpp = 4, 133 .max_num_otg = 4, 134 .max_num_hdmi_frl_outputs = 1, 135 .max_num_wb = 1, 136 .max_dchub_pscl_bw_pix_per_clk = 4, 137 .max_pscl_lb_bw_pix_per_clk = 2, 138 .max_lb_vscl_bw_pix_per_clk = 4, 139 .max_vscl_hscl_bw_pix_per_clk = 4, 140 .max_hscl_ratio = 6, 141 .max_vscl_ratio = 6, 142 .max_hscl_taps = 8, 143 .max_vscl_taps = 8, 144 .dpte_buffer_size_in_pte_reqs_luma = 64, 145 .dpte_buffer_size_in_pte_reqs_chroma = 34, 146 .dispclk_ramp_margin_percent = 1, 147 .max_inter_dcn_tile_repeaters = 8, 148 .cursor_buffer_size = 16, 149 .cursor_chunk_size = 2, 150 .writeback_line_buffer_buffer_size = 0, 151 .writeback_min_hscl_ratio = 1, 152 .writeback_min_vscl_ratio = 1, 153 .writeback_max_hscl_ratio = 1, 154 .writeback_max_vscl_ratio = 1, 155 .writeback_max_hscl_taps = 1, 156 .writeback_max_vscl_taps = 1, 157 .dppclk_delay_subtotal = 46, 158 .dppclk_delay_scl = 50, 159 .dppclk_delay_scl_lb_only = 16, 160 .dppclk_delay_cnvc_formatter = 27, 161 .dppclk_delay_cnvc_cursor = 6, 162 .dispclk_delay_subtotal = 119, 163 .dynamic_metadata_vm_enabled = false, 164 .odm_combine_4to1_supported = false, 165 .dcc_supported = true, 166 }; 167 168 struct _vcs_dpi_soc_bounding_box_st dcn3_1_soc = { 169 /*TODO: correct dispclk/dppclk voltage level determination*/ 170 .clock_limits = { 171 { 172 .state = 0, 173 .dispclk_mhz = 1200.0, 174 .dppclk_mhz = 1200.0, 175 .phyclk_mhz = 600.0, 176 .phyclk_d18_mhz = 667.0, 177 .dscclk_mhz = 186.0, 178 .dtbclk_mhz = 625.0, 179 }, 180 { 181 .state = 1, 182 .dispclk_mhz = 1200.0, 183 .dppclk_mhz = 1200.0, 184 .phyclk_mhz = 810.0, 185 .phyclk_d18_mhz = 667.0, 186 .dscclk_mhz = 209.0, 187 .dtbclk_mhz = 625.0, 188 }, 189 { 190 .state = 2, 191 .dispclk_mhz = 1200.0, 192 .dppclk_mhz = 1200.0, 193 .phyclk_mhz = 810.0, 194 .phyclk_d18_mhz = 667.0, 195 .dscclk_mhz = 209.0, 196 .dtbclk_mhz = 625.0, 197 }, 198 { 199 .state = 3, 200 .dispclk_mhz = 1200.0, 201 .dppclk_mhz = 1200.0, 202 .phyclk_mhz = 810.0, 203 .phyclk_d18_mhz = 667.0, 204 .dscclk_mhz = 371.0, 205 .dtbclk_mhz = 625.0, 206 }, 207 { 208 .state = 4, 209 .dispclk_mhz = 1200.0, 210 .dppclk_mhz = 1200.0, 211 .phyclk_mhz = 810.0, 212 .phyclk_d18_mhz = 667.0, 213 .dscclk_mhz = 417.0, 214 .dtbclk_mhz = 625.0, 215 }, 216 }, 217 .num_states = 5, 218 .sr_exit_time_us = 9.0, 219 .sr_enter_plus_exit_time_us = 11.0, 220 .sr_exit_z8_time_us = 402.0, 221 .sr_enter_plus_exit_z8_time_us = 520.0, 222 .writeback_latency_us = 12.0, 223 .dram_channel_width_bytes = 4, 224 .round_trip_ping_latency_dcfclk_cycles = 106, 225 .urgent_latency_pixel_data_only_us = 4.0, 226 .urgent_latency_pixel_mixed_with_vm_data_us = 4.0, 227 .urgent_latency_vm_data_only_us = 4.0, 228 .urgent_out_of_order_return_per_channel_pixel_only_bytes = 4096, 229 .urgent_out_of_order_return_per_channel_pixel_and_vm_bytes = 4096, 230 .urgent_out_of_order_return_per_channel_vm_only_bytes = 4096, 231 .pct_ideal_sdp_bw_after_urgent = 80.0, 232 .pct_ideal_dram_sdp_bw_after_urgent_pixel_only = 65.0, 233 .pct_ideal_dram_sdp_bw_after_urgent_pixel_and_vm = 60.0, 234 .pct_ideal_dram_sdp_bw_after_urgent_vm_only = 30.0, 235 .max_avg_sdp_bw_use_normal_percent = 60.0, 236 .max_avg_dram_bw_use_normal_percent = 60.0, 237 .fabric_datapath_to_dcn_data_return_bytes = 32, 238 .return_bus_width_bytes = 64, 239 .downspread_percent = 0.38, 240 .dcn_downspread_percent = 0.5, 241 .gpuvm_min_page_size_bytes = 4096, 242 .hostvm_min_page_size_bytes = 4096, 243 .do_urgent_latency_adjustment = false, 244 .urgent_latency_adjustment_fabric_clock_component_us = 0, 245 .urgent_latency_adjustment_fabric_clock_reference_mhz = 0, 246 }; 247 248 enum dcn31_clk_src_array_id { 249 DCN31_CLK_SRC_PLL0, 250 DCN31_CLK_SRC_PLL1, 251 DCN31_CLK_SRC_PLL2, 252 DCN31_CLK_SRC_PLL3, 253 DCN31_CLK_SRC_PLL4, 254 DCN30_CLK_SRC_TOTAL 255 }; 256 257 /* begin ********************* 258 * macros to expend register list macro defined in HW object header file 259 */ 260 261 /* DCN */ 262 /* TODO awful hack. fixup dcn20_dwb.h */ 263 #undef BASE_INNER 264 #define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg 265 266 #define BASE(seg) BASE_INNER(seg) 267 268 #define SR(reg_name)\ 269 .reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \ 270 reg ## reg_name 271 272 #define SRI(reg_name, block, id)\ 273 .reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 274 reg ## block ## id ## _ ## reg_name 275 276 #define SRI2(reg_name, block, id)\ 277 .reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \ 278 reg ## reg_name 279 280 #define SRIR(var_name, reg_name, block, id)\ 281 .var_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 282 reg ## block ## id ## _ ## reg_name 283 284 #define SRII(reg_name, block, id)\ 285 .reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 286 reg ## block ## id ## _ ## reg_name 287 288 #define SRII_MPC_RMU(reg_name, block, id)\ 289 .RMU##_##reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 290 reg ## block ## id ## _ ## reg_name 291 292 #define SRII_DWB(reg_name, temp_name, block, id)\ 293 .reg_name[id] = BASE(reg ## block ## id ## _ ## temp_name ## _BASE_IDX) + \ 294 reg ## block ## id ## _ ## temp_name 295 296 #define DCCG_SRII(reg_name, block, id)\ 297 .block ## _ ## reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 298 reg ## block ## id ## _ ## reg_name 299 300 #define VUPDATE_SRII(reg_name, block, id)\ 301 .reg_name[id] = BASE(reg ## reg_name ## _ ## block ## id ## _BASE_IDX) + \ 302 reg ## reg_name ## _ ## block ## id 303 304 /* NBIO */ 305 #define NBIO_BASE_INNER(seg) \ 306 NBIO_BASE__INST0_SEG ## seg 307 308 #define NBIO_BASE(seg) \ 309 NBIO_BASE_INNER(seg) 310 311 #define NBIO_SR(reg_name)\ 312 .reg_name = NBIO_BASE(regBIF_BX1_ ## reg_name ## _BASE_IDX) + \ 313 regBIF_BX1_ ## reg_name 314 315 /* MMHUB */ 316 #define MMHUB_BASE_INNER(seg) \ 317 MMHUB_BASE__INST0_SEG ## seg 318 319 #define MMHUB_BASE(seg) \ 320 MMHUB_BASE_INNER(seg) 321 322 #define MMHUB_SR(reg_name)\ 323 .reg_name = MMHUB_BASE(mm ## reg_name ## _BASE_IDX) + \ 324 mm ## reg_name 325 326 /* CLOCK */ 327 #define CLK_BASE_INNER(seg) \ 328 CLK_BASE__INST0_SEG ## seg 329 330 #define CLK_BASE(seg) \ 331 CLK_BASE_INNER(seg) 332 333 #define CLK_SRI(reg_name, block, inst)\ 334 .reg_name = CLK_BASE(reg ## block ## _ ## inst ## _ ## reg_name ## _BASE_IDX) + \ 335 reg ## block ## _ ## inst ## _ ## reg_name 336 337 338 static const struct bios_registers bios_regs = { 339 NBIO_SR(BIOS_SCRATCH_3), 340 NBIO_SR(BIOS_SCRATCH_6) 341 }; 342 343 #define clk_src_regs(index, pllid)\ 344 [index] = {\ 345 CS_COMMON_REG_LIST_DCN3_0(index, pllid),\ 346 } 347 348 static const struct dce110_clk_src_regs clk_src_regs[] = { 349 clk_src_regs(0, A), 350 clk_src_regs(1, B), 351 clk_src_regs(2, C), 352 clk_src_regs(3, D), 353 clk_src_regs(4, E) 354 }; 355 356 static const struct dce110_clk_src_shift cs_shift = { 357 CS_COMMON_MASK_SH_LIST_DCN2_0(__SHIFT) 358 }; 359 360 static const struct dce110_clk_src_mask cs_mask = { 361 CS_COMMON_MASK_SH_LIST_DCN2_0(_MASK) 362 }; 363 364 #define abm_regs(id)\ 365 [id] = {\ 366 ABM_DCN301_REG_LIST(id)\ 367 } 368 369 static const struct dce_abm_registers abm_regs[] = { 370 abm_regs(0), 371 abm_regs(1), 372 abm_regs(2), 373 abm_regs(3), 374 }; 375 376 static const struct dce_abm_shift abm_shift = { 377 ABM_MASK_SH_LIST_DCN30(__SHIFT) 378 }; 379 380 static const struct dce_abm_mask abm_mask = { 381 ABM_MASK_SH_LIST_DCN30(_MASK) 382 }; 383 384 #define audio_regs(id)\ 385 [id] = {\ 386 AUD_COMMON_REG_LIST(id)\ 387 } 388 389 static const struct dce_audio_registers audio_regs[] = { 390 audio_regs(0), 391 audio_regs(1), 392 audio_regs(2), 393 audio_regs(3), 394 audio_regs(4), 395 audio_regs(5), 396 audio_regs(6) 397 }; 398 399 #define DCE120_AUD_COMMON_MASK_SH_LIST(mask_sh)\ 400 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX, AZALIA_ENDPOINT_REG_INDEX, mask_sh),\ 401 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA, AZALIA_ENDPOINT_REG_DATA, mask_sh),\ 402 AUD_COMMON_MASK_SH_LIST_BASE(mask_sh) 403 404 static const struct dce_audio_shift audio_shift = { 405 DCE120_AUD_COMMON_MASK_SH_LIST(__SHIFT) 406 }; 407 408 static const struct dce_audio_mask audio_mask = { 409 DCE120_AUD_COMMON_MASK_SH_LIST(_MASK) 410 }; 411 412 #define vpg_regs(id)\ 413 [id] = {\ 414 VPG_DCN3_REG_LIST(id)\ 415 } 416 417 static const struct dcn30_vpg_registers vpg_regs[] = { 418 vpg_regs(0), 419 vpg_regs(1), 420 vpg_regs(2), 421 vpg_regs(3), 422 vpg_regs(4), 423 vpg_regs(5), 424 vpg_regs(6), 425 vpg_regs(7), 426 vpg_regs(8), 427 vpg_regs(9), 428 }; 429 430 static const struct dcn30_vpg_shift vpg_shift = { 431 DCN3_VPG_MASK_SH_LIST(__SHIFT) 432 }; 433 434 static const struct dcn30_vpg_mask vpg_mask = { 435 DCN3_VPG_MASK_SH_LIST(_MASK) 436 }; 437 438 #define afmt_regs(id)\ 439 [id] = {\ 440 AFMT_DCN3_REG_LIST(id)\ 441 } 442 443 static const struct dcn30_afmt_registers afmt_regs[] = { 444 afmt_regs(0), 445 afmt_regs(1), 446 afmt_regs(2), 447 afmt_regs(3), 448 afmt_regs(4), 449 afmt_regs(5) 450 }; 451 452 static const struct dcn30_afmt_shift afmt_shift = { 453 DCN3_AFMT_MASK_SH_LIST(__SHIFT) 454 }; 455 456 static const struct dcn30_afmt_mask afmt_mask = { 457 DCN3_AFMT_MASK_SH_LIST(_MASK) 458 }; 459 460 #define stream_enc_regs(id)\ 461 [id] = {\ 462 SE_DCN3_REG_LIST(id)\ 463 } 464 465 static const struct dcn10_stream_enc_registers stream_enc_regs[] = { 466 stream_enc_regs(0), 467 stream_enc_regs(1), 468 stream_enc_regs(2), 469 stream_enc_regs(3), 470 stream_enc_regs(4) 471 }; 472 473 static const struct dcn10_stream_encoder_shift se_shift = { 474 SE_COMMON_MASK_SH_LIST_DCN30(__SHIFT) 475 }; 476 477 static const struct dcn10_stream_encoder_mask se_mask = { 478 SE_COMMON_MASK_SH_LIST_DCN30(_MASK) 479 }; 480 481 482 #define aux_regs(id)\ 483 [id] = {\ 484 DCN2_AUX_REG_LIST(id)\ 485 } 486 487 static const struct dcn10_link_enc_aux_registers link_enc_aux_regs[] = { 488 aux_regs(0), 489 aux_regs(1), 490 aux_regs(2), 491 aux_regs(3), 492 aux_regs(4) 493 }; 494 495 #define hpd_regs(id)\ 496 [id] = {\ 497 HPD_REG_LIST(id)\ 498 } 499 500 static const struct dcn10_link_enc_hpd_registers link_enc_hpd_regs[] = { 501 hpd_regs(0), 502 hpd_regs(1), 503 hpd_regs(2), 504 hpd_regs(3), 505 hpd_regs(4) 506 }; 507 508 #define link_regs(id, phyid)\ 509 [id] = {\ 510 LE_DCN31_REG_LIST(id), \ 511 UNIPHY_DCN2_REG_LIST(phyid), \ 512 DPCS_DCN31_REG_LIST(id), \ 513 } 514 515 static const struct dce110_aux_registers_shift aux_shift = { 516 DCN_AUX_MASK_SH_LIST(__SHIFT) 517 }; 518 519 static const struct dce110_aux_registers_mask aux_mask = { 520 DCN_AUX_MASK_SH_LIST(_MASK) 521 }; 522 523 static const struct dcn10_link_enc_registers link_enc_regs[] = { 524 link_regs(0, A), 525 link_regs(1, B), 526 link_regs(2, C), 527 link_regs(3, D), 528 link_regs(4, E) 529 }; 530 531 static const struct dcn10_link_enc_shift le_shift = { 532 LINK_ENCODER_MASK_SH_LIST_DCN31(__SHIFT), \ 533 DPCS_DCN31_MASK_SH_LIST(__SHIFT) 534 }; 535 536 static const struct dcn10_link_enc_mask le_mask = { 537 LINK_ENCODER_MASK_SH_LIST_DCN31(_MASK), \ 538 DPCS_DCN31_MASK_SH_LIST(_MASK) 539 }; 540 541 #define dpp_regs(id)\ 542 [id] = {\ 543 DPP_REG_LIST_DCN30(id),\ 544 } 545 546 static const struct dcn3_dpp_registers dpp_regs[] = { 547 dpp_regs(0), 548 dpp_regs(1), 549 dpp_regs(2), 550 dpp_regs(3) 551 }; 552 553 static const struct dcn3_dpp_shift tf_shift = { 554 DPP_REG_LIST_SH_MASK_DCN30(__SHIFT) 555 }; 556 557 static const struct dcn3_dpp_mask tf_mask = { 558 DPP_REG_LIST_SH_MASK_DCN30(_MASK) 559 }; 560 561 #define opp_regs(id)\ 562 [id] = {\ 563 OPP_REG_LIST_DCN30(id),\ 564 } 565 566 static const struct dcn20_opp_registers opp_regs[] = { 567 opp_regs(0), 568 opp_regs(1), 569 opp_regs(2), 570 opp_regs(3) 571 }; 572 573 static const struct dcn20_opp_shift opp_shift = { 574 OPP_MASK_SH_LIST_DCN20(__SHIFT) 575 }; 576 577 static const struct dcn20_opp_mask opp_mask = { 578 OPP_MASK_SH_LIST_DCN20(_MASK) 579 }; 580 581 #define aux_engine_regs(id)\ 582 [id] = {\ 583 AUX_COMMON_REG_LIST0(id), \ 584 .AUXN_IMPCAL = 0, \ 585 .AUXP_IMPCAL = 0, \ 586 .AUX_RESET_MASK = DP_AUX0_AUX_CONTROL__AUX_RESET_MASK, \ 587 } 588 589 static const struct dce110_aux_registers aux_engine_regs[] = { 590 aux_engine_regs(0), 591 aux_engine_regs(1), 592 aux_engine_regs(2), 593 aux_engine_regs(3), 594 aux_engine_regs(4) 595 }; 596 597 #define dwbc_regs_dcn3(id)\ 598 [id] = {\ 599 DWBC_COMMON_REG_LIST_DCN30(id),\ 600 } 601 602 static const struct dcn30_dwbc_registers dwbc30_regs[] = { 603 dwbc_regs_dcn3(0), 604 }; 605 606 static const struct dcn30_dwbc_shift dwbc30_shift = { 607 DWBC_COMMON_MASK_SH_LIST_DCN30(__SHIFT) 608 }; 609 610 static const struct dcn30_dwbc_mask dwbc30_mask = { 611 DWBC_COMMON_MASK_SH_LIST_DCN30(_MASK) 612 }; 613 614 #define mcif_wb_regs_dcn3(id)\ 615 [id] = {\ 616 MCIF_WB_COMMON_REG_LIST_DCN30(id),\ 617 } 618 619 static const struct dcn30_mmhubbub_registers mcif_wb30_regs[] = { 620 mcif_wb_regs_dcn3(0) 621 }; 622 623 static const struct dcn30_mmhubbub_shift mcif_wb30_shift = { 624 MCIF_WB_COMMON_MASK_SH_LIST_DCN30(__SHIFT) 625 }; 626 627 static const struct dcn30_mmhubbub_mask mcif_wb30_mask = { 628 MCIF_WB_COMMON_MASK_SH_LIST_DCN30(_MASK) 629 }; 630 631 #define dsc_regsDCN20(id)\ 632 [id] = {\ 633 DSC_REG_LIST_DCN20(id)\ 634 } 635 636 static const struct dcn20_dsc_registers dsc_regs[] = { 637 dsc_regsDCN20(0), 638 dsc_regsDCN20(1), 639 dsc_regsDCN20(2) 640 }; 641 642 static const struct dcn20_dsc_shift dsc_shift = { 643 DSC_REG_LIST_SH_MASK_DCN20(__SHIFT) 644 }; 645 646 static const struct dcn20_dsc_mask dsc_mask = { 647 DSC_REG_LIST_SH_MASK_DCN20(_MASK) 648 }; 649 650 static const struct dcn30_mpc_registers mpc_regs = { 651 MPC_REG_LIST_DCN3_0(0), 652 MPC_REG_LIST_DCN3_0(1), 653 MPC_REG_LIST_DCN3_0(2), 654 MPC_REG_LIST_DCN3_0(3), 655 MPC_OUT_MUX_REG_LIST_DCN3_0(0), 656 MPC_OUT_MUX_REG_LIST_DCN3_0(1), 657 MPC_OUT_MUX_REG_LIST_DCN3_0(2), 658 MPC_OUT_MUX_REG_LIST_DCN3_0(3), 659 MPC_RMU_GLOBAL_REG_LIST_DCN3AG, 660 MPC_RMU_REG_LIST_DCN3AG(0), 661 MPC_RMU_REG_LIST_DCN3AG(1), 662 //MPC_RMU_REG_LIST_DCN3AG(2), 663 MPC_DWB_MUX_REG_LIST_DCN3_0(0), 664 }; 665 666 static const struct dcn30_mpc_shift mpc_shift = { 667 MPC_COMMON_MASK_SH_LIST_DCN30(__SHIFT) 668 }; 669 670 static const struct dcn30_mpc_mask mpc_mask = { 671 MPC_COMMON_MASK_SH_LIST_DCN30(_MASK) 672 }; 673 674 #define optc_regs(id)\ 675 [id] = {OPTC_COMMON_REG_LIST_DCN3_1(id)} 676 677 static const struct dcn_optc_registers optc_regs[] = { 678 optc_regs(0), 679 optc_regs(1), 680 optc_regs(2), 681 optc_regs(3) 682 }; 683 684 static const struct dcn_optc_shift optc_shift = { 685 OPTC_COMMON_MASK_SH_LIST_DCN3_1(__SHIFT) 686 }; 687 688 static const struct dcn_optc_mask optc_mask = { 689 OPTC_COMMON_MASK_SH_LIST_DCN3_1(_MASK) 690 }; 691 692 #define hubp_regs(id)\ 693 [id] = {\ 694 HUBP_REG_LIST_DCN30(id)\ 695 } 696 697 static const struct dcn_hubp2_registers hubp_regs[] = { 698 hubp_regs(0), 699 hubp_regs(1), 700 hubp_regs(2), 701 hubp_regs(3) 702 }; 703 704 705 static const struct dcn_hubp2_shift hubp_shift = { 706 HUBP_MASK_SH_LIST_DCN31(__SHIFT) 707 }; 708 709 static const struct dcn_hubp2_mask hubp_mask = { 710 HUBP_MASK_SH_LIST_DCN31(_MASK) 711 }; 712 static const struct dcn_hubbub_registers hubbub_reg = { 713 HUBBUB_REG_LIST_DCN31(0) 714 }; 715 716 static const struct dcn_hubbub_shift hubbub_shift = { 717 HUBBUB_MASK_SH_LIST_DCN31(__SHIFT) 718 }; 719 720 static const struct dcn_hubbub_mask hubbub_mask = { 721 HUBBUB_MASK_SH_LIST_DCN31(_MASK) 722 }; 723 724 static const struct dccg_registers dccg_regs = { 725 DCCG_REG_LIST_DCN31() 726 }; 727 728 static const struct dccg_shift dccg_shift = { 729 DCCG_MASK_SH_LIST_DCN31(__SHIFT) 730 }; 731 732 static const struct dccg_mask dccg_mask = { 733 DCCG_MASK_SH_LIST_DCN31(_MASK) 734 }; 735 736 737 #define SRII2(reg_name_pre, reg_name_post, id)\ 738 .reg_name_pre ## _ ## reg_name_post[id] = BASE(reg ## reg_name_pre \ 739 ## id ## _ ## reg_name_post ## _BASE_IDX) + \ 740 reg ## reg_name_pre ## id ## _ ## reg_name_post 741 742 743 #define HWSEQ_DCN31_REG_LIST()\ 744 SR(DCHUBBUB_GLOBAL_TIMER_CNTL), \ 745 SR(DCHUBBUB_ARB_HOSTVM_CNTL), \ 746 SR(DIO_MEM_PWR_CTRL), \ 747 SR(ODM_MEM_PWR_CTRL3), \ 748 SR(DMU_MEM_PWR_CNTL), \ 749 SR(MMHUBBUB_MEM_PWR_CNTL), \ 750 SR(DCCG_GATE_DISABLE_CNTL), \ 751 SR(DCCG_GATE_DISABLE_CNTL2), \ 752 SR(DCFCLK_CNTL),\ 753 SR(DC_MEM_GLOBAL_PWR_REQ_CNTL), \ 754 SRII(PIXEL_RATE_CNTL, OTG, 0), \ 755 SRII(PIXEL_RATE_CNTL, OTG, 1),\ 756 SRII(PIXEL_RATE_CNTL, OTG, 2),\ 757 SRII(PIXEL_RATE_CNTL, OTG, 3),\ 758 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 0),\ 759 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 1),\ 760 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 2),\ 761 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 3),\ 762 SR(MICROSECOND_TIME_BASE_DIV), \ 763 SR(MILLISECOND_TIME_BASE_DIV), \ 764 SR(DISPCLK_FREQ_CHANGE_CNTL), \ 765 SR(RBBMIF_TIMEOUT_DIS), \ 766 SR(RBBMIF_TIMEOUT_DIS_2), \ 767 SR(DCHUBBUB_CRC_CTRL), \ 768 SR(DPP_TOP0_DPP_CRC_CTRL), \ 769 SR(DPP_TOP0_DPP_CRC_VAL_B_A), \ 770 SR(DPP_TOP0_DPP_CRC_VAL_R_G), \ 771 SR(MPC_CRC_CTRL), \ 772 SR(MPC_CRC_RESULT_GB), \ 773 SR(MPC_CRC_RESULT_C), \ 774 SR(MPC_CRC_RESULT_AR), \ 775 SR(DOMAIN0_PG_CONFIG), \ 776 SR(DOMAIN1_PG_CONFIG), \ 777 SR(DOMAIN2_PG_CONFIG), \ 778 SR(DOMAIN3_PG_CONFIG), \ 779 SR(DOMAIN16_PG_CONFIG), \ 780 SR(DOMAIN17_PG_CONFIG), \ 781 SR(DOMAIN18_PG_CONFIG), \ 782 SR(DOMAIN0_PG_STATUS), \ 783 SR(DOMAIN1_PG_STATUS), \ 784 SR(DOMAIN2_PG_STATUS), \ 785 SR(DOMAIN3_PG_STATUS), \ 786 SR(DOMAIN16_PG_STATUS), \ 787 SR(DOMAIN17_PG_STATUS), \ 788 SR(DOMAIN18_PG_STATUS), \ 789 SR(D1VGA_CONTROL), \ 790 SR(D2VGA_CONTROL), \ 791 SR(D3VGA_CONTROL), \ 792 SR(D4VGA_CONTROL), \ 793 SR(D5VGA_CONTROL), \ 794 SR(D6VGA_CONTROL), \ 795 SR(DC_IP_REQUEST_CNTL), \ 796 SR(AZALIA_AUDIO_DTO), \ 797 SR(AZALIA_CONTROLLER_CLOCK_GATING) 798 799 static const struct dce_hwseq_registers hwseq_reg = { 800 HWSEQ_DCN31_REG_LIST() 801 }; 802 803 #define HWSEQ_DCN31_MASK_SH_LIST(mask_sh)\ 804 HWSEQ_DCN_MASK_SH_LIST(mask_sh), \ 805 HWS_SF(, DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_REFDIV, mask_sh), \ 806 HWS_SF(, DCHUBBUB_ARB_HOSTVM_CNTL, DISABLE_HOSTVM_FORCE_ALLOW_PSTATE, mask_sh), \ 807 HWS_SF(, DOMAIN0_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ 808 HWS_SF(, DOMAIN0_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ 809 HWS_SF(, DOMAIN1_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ 810 HWS_SF(, DOMAIN1_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ 811 HWS_SF(, DOMAIN2_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ 812 HWS_SF(, DOMAIN2_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ 813 HWS_SF(, DOMAIN3_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ 814 HWS_SF(, DOMAIN3_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ 815 HWS_SF(, DOMAIN16_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ 816 HWS_SF(, DOMAIN16_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ 817 HWS_SF(, DOMAIN17_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ 818 HWS_SF(, DOMAIN17_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ 819 HWS_SF(, DOMAIN18_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ 820 HWS_SF(, DOMAIN18_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ 821 HWS_SF(, DOMAIN0_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ 822 HWS_SF(, DOMAIN1_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ 823 HWS_SF(, DOMAIN2_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ 824 HWS_SF(, DOMAIN3_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ 825 HWS_SF(, DOMAIN16_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ 826 HWS_SF(, DOMAIN17_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ 827 HWS_SF(, DOMAIN18_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ 828 HWS_SF(, DC_IP_REQUEST_CNTL, IP_REQUEST_EN, mask_sh), \ 829 HWS_SF(, AZALIA_AUDIO_DTO, AZALIA_AUDIO_DTO_MODULE, mask_sh), \ 830 HWS_SF(, HPO_TOP_CLOCK_CONTROL, HPO_HDMISTREAMCLK_G_GATE_DIS, mask_sh), \ 831 HWS_SF(, DMU_MEM_PWR_CNTL, DMCU_ERAM_MEM_PWR_FORCE, mask_sh), \ 832 HWS_SF(, ODM_MEM_PWR_CTRL3, ODM_MEM_UNASSIGNED_PWR_MODE, mask_sh), \ 833 HWS_SF(, ODM_MEM_PWR_CTRL3, ODM_MEM_VBLANK_PWR_MODE, mask_sh), \ 834 HWS_SF(, MMHUBBUB_MEM_PWR_CNTL, VGA_MEM_PWR_FORCE, mask_sh) 835 836 static const struct dce_hwseq_shift hwseq_shift = { 837 HWSEQ_DCN31_MASK_SH_LIST(__SHIFT) 838 }; 839 840 static const struct dce_hwseq_mask hwseq_mask = { 841 HWSEQ_DCN31_MASK_SH_LIST(_MASK) 842 }; 843 #define vmid_regs(id)\ 844 [id] = {\ 845 DCN20_VMID_REG_LIST(id)\ 846 } 847 848 static const struct dcn_vmid_registers vmid_regs[] = { 849 vmid_regs(0), 850 vmid_regs(1), 851 vmid_regs(2), 852 vmid_regs(3), 853 vmid_regs(4), 854 vmid_regs(5), 855 vmid_regs(6), 856 vmid_regs(7), 857 vmid_regs(8), 858 vmid_regs(9), 859 vmid_regs(10), 860 vmid_regs(11), 861 vmid_regs(12), 862 vmid_regs(13), 863 vmid_regs(14), 864 vmid_regs(15) 865 }; 866 867 static const struct dcn20_vmid_shift vmid_shifts = { 868 DCN20_VMID_MASK_SH_LIST(__SHIFT) 869 }; 870 871 static const struct dcn20_vmid_mask vmid_masks = { 872 DCN20_VMID_MASK_SH_LIST(_MASK) 873 }; 874 875 static const struct resource_caps res_cap_dcn31 = { 876 .num_timing_generator = 4, 877 .num_opp = 4, 878 .num_video_plane = 4, 879 .num_audio = 5, 880 .num_stream_encoder = 5, 881 .num_dig_link_enc = 5, 882 .num_pll = 5, 883 .num_dwb = 1, 884 .num_ddc = 5, 885 .num_vmid = 16, 886 .num_mpc_3dlut = 2, 887 .num_dsc = 3, 888 }; 889 890 static const struct dc_plane_cap plane_cap = { 891 .type = DC_PLANE_TYPE_DCN_UNIVERSAL, 892 .blends_with_above = true, 893 .blends_with_below = true, 894 .per_pixel_alpha = true, 895 896 .pixel_format_support = { 897 .argb8888 = true, 898 .nv12 = true, 899 .fp16 = true, 900 .p010 = false, 901 .ayuv = false, 902 }, 903 904 .max_upscale_factor = { 905 .argb8888 = 16000, 906 .nv12 = 16000, 907 .fp16 = 16000 908 }, 909 910 // 6:1 downscaling ratio: 1000/6 = 166.666 911 .max_downscale_factor = { 912 .argb8888 = 167, 913 .nv12 = 167, 914 .fp16 = 167 915 }, 916 64, 917 64 918 }; 919 920 static const struct dc_debug_options debug_defaults_drv = { 921 .disable_dmcu = true, 922 .force_abm_enable = false, 923 .timing_trace = false, 924 .clock_trace = true, 925 .disable_pplib_clock_request = false, 926 .pipe_split_policy = MPC_SPLIT_AVOID, 927 .force_single_disp_pipe_split = false, 928 .disable_dcc = DCC_ENABLE, 929 .vsr_support = true, 930 .performance_trace = false, 931 .max_downscale_src_width = 3840,/*upto 4K*/ 932 .disable_pplib_wm_range = false, 933 .scl_reset_length10 = true, 934 .sanity_checks = false, 935 .underflow_assert_delay_us = 0xFFFFFFFF, 936 .dwb_fi_phase = -1, // -1 = disable, 937 .dmub_command_table = true, 938 .pstate_enabled = true, 939 .use_max_lb = true, 940 .enable_mem_low_power = { 941 .bits = { 942 .vga = false, 943 .i2c = false, 944 .dmcu = false, // This is previously known to cause hang on S3 cycles if enabled 945 .dscl = false, 946 .cm = false, 947 .mpc = false, 948 .optc = false, 949 } 950 }, 951 .optimize_edp_link_rate = true, 952 .enable_sw_cntl_psr = true, 953 }; 954 955 static const struct dc_debug_options debug_defaults_diags = { 956 .disable_dmcu = true, 957 .force_abm_enable = false, 958 .timing_trace = true, 959 .clock_trace = true, 960 .disable_dpp_power_gate = true, 961 .disable_hubp_power_gate = true, 962 .disable_clock_gate = true, 963 .disable_pplib_clock_request = true, 964 .disable_pplib_wm_range = true, 965 .disable_stutter = false, 966 .scl_reset_length10 = true, 967 .dwb_fi_phase = -1, // -1 = disable 968 .dmub_command_table = true, 969 .enable_tri_buf = true, 970 .use_max_lb = true 971 }; 972 973 static void dcn31_dpp_destroy(struct dpp **dpp) 974 { 975 kfree(TO_DCN20_DPP(*dpp)); 976 *dpp = NULL; 977 } 978 979 static struct dpp *dcn31_dpp_create( 980 struct dc_context *ctx, 981 uint32_t inst) 982 { 983 struct dcn3_dpp *dpp = 984 kzalloc(sizeof(struct dcn3_dpp), GFP_KERNEL); 985 986 if (!dpp) 987 return NULL; 988 989 if (dpp3_construct(dpp, ctx, inst, 990 &dpp_regs[inst], &tf_shift, &tf_mask)) 991 return &dpp->base; 992 993 BREAK_TO_DEBUGGER(); 994 kfree(dpp); 995 return NULL; 996 } 997 998 static struct output_pixel_processor *dcn31_opp_create( 999 struct dc_context *ctx, uint32_t inst) 1000 { 1001 struct dcn20_opp *opp = 1002 kzalloc(sizeof(struct dcn20_opp), GFP_KERNEL); 1003 1004 if (!opp) { 1005 BREAK_TO_DEBUGGER(); 1006 return NULL; 1007 } 1008 1009 dcn20_opp_construct(opp, ctx, inst, 1010 &opp_regs[inst], &opp_shift, &opp_mask); 1011 return &opp->base; 1012 } 1013 1014 static struct dce_aux *dcn31_aux_engine_create( 1015 struct dc_context *ctx, 1016 uint32_t inst) 1017 { 1018 struct aux_engine_dce110 *aux_engine = 1019 kzalloc(sizeof(struct aux_engine_dce110), GFP_KERNEL); 1020 1021 if (!aux_engine) 1022 return NULL; 1023 1024 dce110_aux_engine_construct(aux_engine, ctx, inst, 1025 SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD, 1026 &aux_engine_regs[inst], 1027 &aux_mask, 1028 &aux_shift, 1029 ctx->dc->caps.extended_aux_timeout_support); 1030 1031 return &aux_engine->base; 1032 } 1033 #define i2c_inst_regs(id) { I2C_HW_ENGINE_COMMON_REG_LIST_DCN30(id) } 1034 1035 static const struct dce_i2c_registers i2c_hw_regs[] = { 1036 i2c_inst_regs(1), 1037 i2c_inst_regs(2), 1038 i2c_inst_regs(3), 1039 i2c_inst_regs(4), 1040 i2c_inst_regs(5), 1041 }; 1042 1043 static const struct dce_i2c_shift i2c_shifts = { 1044 I2C_COMMON_MASK_SH_LIST_DCN30(__SHIFT) 1045 }; 1046 1047 static const struct dce_i2c_mask i2c_masks = { 1048 I2C_COMMON_MASK_SH_LIST_DCN30(_MASK) 1049 }; 1050 1051 static struct dce_i2c_hw *dcn31_i2c_hw_create( 1052 struct dc_context *ctx, 1053 uint32_t inst) 1054 { 1055 struct dce_i2c_hw *dce_i2c_hw = 1056 kzalloc(sizeof(struct dce_i2c_hw), GFP_KERNEL); 1057 1058 if (!dce_i2c_hw) 1059 return NULL; 1060 1061 dcn2_i2c_hw_construct(dce_i2c_hw, ctx, inst, 1062 &i2c_hw_regs[inst], &i2c_shifts, &i2c_masks); 1063 1064 return dce_i2c_hw; 1065 } 1066 static struct mpc *dcn31_mpc_create( 1067 struct dc_context *ctx, 1068 int num_mpcc, 1069 int num_rmu) 1070 { 1071 struct dcn30_mpc *mpc30 = kzalloc(sizeof(struct dcn30_mpc), 1072 GFP_KERNEL); 1073 1074 if (!mpc30) 1075 return NULL; 1076 1077 dcn30_mpc_construct(mpc30, ctx, 1078 &mpc_regs, 1079 &mpc_shift, 1080 &mpc_mask, 1081 num_mpcc, 1082 num_rmu); 1083 1084 return &mpc30->base; 1085 } 1086 1087 static struct hubbub *dcn31_hubbub_create(struct dc_context *ctx) 1088 { 1089 int i; 1090 1091 struct dcn20_hubbub *hubbub3 = kzalloc(sizeof(struct dcn20_hubbub), 1092 GFP_KERNEL); 1093 1094 if (!hubbub3) 1095 return NULL; 1096 1097 hubbub31_construct(hubbub3, ctx, 1098 &hubbub_reg, 1099 &hubbub_shift, 1100 &hubbub_mask, 1101 dcn3_1_ip.det_buffer_size_kbytes, 1102 dcn3_1_ip.pixel_chunk_size_kbytes, 1103 dcn3_1_ip.config_return_buffer_size_in_kbytes); 1104 1105 1106 for (i = 0; i < res_cap_dcn31.num_vmid; i++) { 1107 struct dcn20_vmid *vmid = &hubbub3->vmid[i]; 1108 1109 vmid->ctx = ctx; 1110 1111 vmid->regs = &vmid_regs[i]; 1112 vmid->shifts = &vmid_shifts; 1113 vmid->masks = &vmid_masks; 1114 } 1115 1116 return &hubbub3->base; 1117 } 1118 1119 static struct timing_generator *dcn31_timing_generator_create( 1120 struct dc_context *ctx, 1121 uint32_t instance) 1122 { 1123 struct optc *tgn10 = 1124 kzalloc(sizeof(struct optc), GFP_KERNEL); 1125 1126 if (!tgn10) 1127 return NULL; 1128 1129 tgn10->base.inst = instance; 1130 tgn10->base.ctx = ctx; 1131 1132 tgn10->tg_regs = &optc_regs[instance]; 1133 tgn10->tg_shift = &optc_shift; 1134 tgn10->tg_mask = &optc_mask; 1135 1136 dcn31_timing_generator_init(tgn10); 1137 1138 return &tgn10->base; 1139 } 1140 1141 static const struct encoder_feature_support link_enc_feature = { 1142 .max_hdmi_deep_color = COLOR_DEPTH_121212, 1143 .max_hdmi_pixel_clock = 600000, 1144 .hdmi_ycbcr420_supported = true, 1145 .dp_ycbcr420_supported = true, 1146 .fec_supported = true, 1147 .flags.bits.IS_HBR2_CAPABLE = true, 1148 .flags.bits.IS_HBR3_CAPABLE = true, 1149 .flags.bits.IS_TPS3_CAPABLE = true, 1150 .flags.bits.IS_TPS4_CAPABLE = true 1151 }; 1152 1153 static struct link_encoder *dcn31_link_encoder_create( 1154 const struct encoder_init_data *enc_init_data) 1155 { 1156 struct dcn20_link_encoder *enc20 = 1157 kzalloc(sizeof(struct dcn20_link_encoder), GFP_KERNEL); 1158 1159 if (!enc20) 1160 return NULL; 1161 1162 dcn31_link_encoder_construct(enc20, 1163 enc_init_data, 1164 &link_enc_feature, 1165 &link_enc_regs[enc_init_data->transmitter], 1166 &link_enc_aux_regs[enc_init_data->channel - 1], 1167 &link_enc_hpd_regs[enc_init_data->hpd_source], 1168 &le_shift, 1169 &le_mask); 1170 1171 return &enc20->enc10.base; 1172 } 1173 1174 /* Create a minimal link encoder object not associated with a particular 1175 * physical connector. 1176 * resource_funcs.link_enc_create_minimal 1177 */ 1178 static struct link_encoder *dcn31_link_enc_create_minimal( 1179 struct dc_context *ctx, enum engine_id eng_id) 1180 { 1181 struct dcn20_link_encoder *enc20; 1182 1183 if ((eng_id - ENGINE_ID_DIGA) > ctx->dc->res_pool->res_cap->num_dig_link_enc) 1184 return NULL; 1185 1186 enc20 = kzalloc(sizeof(struct dcn20_link_encoder), GFP_KERNEL); 1187 if (!enc20) 1188 return NULL; 1189 1190 dcn31_link_encoder_construct_minimal( 1191 enc20, 1192 ctx, 1193 &link_enc_feature, 1194 &link_enc_regs[eng_id - ENGINE_ID_DIGA], 1195 eng_id); 1196 1197 return &enc20->enc10.base; 1198 } 1199 1200 struct panel_cntl *dcn31_panel_cntl_create(const struct panel_cntl_init_data *init_data) 1201 { 1202 struct dcn31_panel_cntl *panel_cntl = 1203 kzalloc(sizeof(struct dcn31_panel_cntl), GFP_KERNEL); 1204 1205 if (!panel_cntl) 1206 return NULL; 1207 1208 dcn31_panel_cntl_construct(panel_cntl, init_data); 1209 1210 return &panel_cntl->base; 1211 } 1212 1213 static void read_dce_straps( 1214 struct dc_context *ctx, 1215 struct resource_straps *straps) 1216 { 1217 generic_reg_get(ctx, regDC_PINSTRAPS + BASE(regDC_PINSTRAPS_BASE_IDX), 1218 FN(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO), &straps->dc_pinstraps_audio); 1219 1220 } 1221 1222 static struct audio *dcn31_create_audio( 1223 struct dc_context *ctx, unsigned int inst) 1224 { 1225 return dce_audio_create(ctx, inst, 1226 &audio_regs[inst], &audio_shift, &audio_mask); 1227 } 1228 1229 static struct vpg *dcn31_vpg_create( 1230 struct dc_context *ctx, 1231 uint32_t inst) 1232 { 1233 struct dcn30_vpg *vpg3 = kzalloc(sizeof(struct dcn30_vpg), GFP_KERNEL); 1234 1235 if (!vpg3) 1236 return NULL; 1237 1238 vpg3_construct(vpg3, ctx, inst, 1239 &vpg_regs[inst], 1240 &vpg_shift, 1241 &vpg_mask); 1242 1243 return &vpg3->base; 1244 } 1245 1246 static struct afmt *dcn31_afmt_create( 1247 struct dc_context *ctx, 1248 uint32_t inst) 1249 { 1250 struct dcn30_afmt *afmt3 = kzalloc(sizeof(struct dcn30_afmt), GFP_KERNEL); 1251 1252 if (!afmt3) 1253 return NULL; 1254 1255 afmt3_construct(afmt3, ctx, inst, 1256 &afmt_regs[inst], 1257 &afmt_shift, 1258 &afmt_mask); 1259 1260 return &afmt3->base; 1261 } 1262 1263 static struct stream_encoder *dcn31_stream_encoder_create( 1264 enum engine_id eng_id, 1265 struct dc_context *ctx) 1266 { 1267 struct dcn10_stream_encoder *enc1; 1268 struct vpg *vpg; 1269 struct afmt *afmt; 1270 int vpg_inst; 1271 int afmt_inst; 1272 1273 /* Mapping of VPG, AFMT, DME register blocks to DIO block instance */ 1274 if (eng_id <= ENGINE_ID_DIGF) { 1275 vpg_inst = eng_id; 1276 afmt_inst = eng_id; 1277 } else 1278 return NULL; 1279 1280 enc1 = kzalloc(sizeof(struct dcn10_stream_encoder), GFP_KERNEL); 1281 vpg = dcn31_vpg_create(ctx, vpg_inst); 1282 afmt = dcn31_afmt_create(ctx, afmt_inst); 1283 1284 if (!enc1 || !vpg || !afmt) 1285 return NULL; 1286 1287 if (ctx->asic_id.chip_family == FAMILY_YELLOW_CARP && 1288 ctx->asic_id.hw_internal_rev == YELLOW_CARP_B0) { 1289 if ((eng_id == ENGINE_ID_DIGC) || (eng_id == ENGINE_ID_DIGD)) 1290 eng_id = eng_id + 3; // For B0 only. C->F, D->G. 1291 } 1292 1293 dcn30_dio_stream_encoder_construct(enc1, ctx, ctx->dc_bios, 1294 eng_id, vpg, afmt, 1295 &stream_enc_regs[eng_id], 1296 &se_shift, &se_mask); 1297 1298 return &enc1->base; 1299 } 1300 1301 static struct dce_hwseq *dcn31_hwseq_create( 1302 struct dc_context *ctx) 1303 { 1304 struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_KERNEL); 1305 1306 if (hws) { 1307 hws->ctx = ctx; 1308 hws->regs = &hwseq_reg; 1309 hws->shifts = &hwseq_shift; 1310 hws->masks = &hwseq_mask; 1311 } 1312 return hws; 1313 } 1314 static const struct resource_create_funcs res_create_funcs = { 1315 .read_dce_straps = read_dce_straps, 1316 .create_audio = dcn31_create_audio, 1317 .create_stream_encoder = dcn31_stream_encoder_create, 1318 .create_hwseq = dcn31_hwseq_create, 1319 }; 1320 1321 static const struct resource_create_funcs res_create_maximus_funcs = { 1322 .read_dce_straps = NULL, 1323 .create_audio = NULL, 1324 .create_stream_encoder = NULL, 1325 .create_hwseq = dcn31_hwseq_create, 1326 }; 1327 1328 static void dcn31_resource_destruct(struct dcn31_resource_pool *pool) 1329 { 1330 unsigned int i; 1331 1332 for (i = 0; i < pool->base.stream_enc_count; i++) { 1333 if (pool->base.stream_enc[i] != NULL) { 1334 if (pool->base.stream_enc[i]->vpg != NULL) { 1335 kfree(DCN30_VPG_FROM_VPG(pool->base.stream_enc[i]->vpg)); 1336 pool->base.stream_enc[i]->vpg = NULL; 1337 } 1338 if (pool->base.stream_enc[i]->afmt != NULL) { 1339 kfree(DCN30_AFMT_FROM_AFMT(pool->base.stream_enc[i]->afmt)); 1340 pool->base.stream_enc[i]->afmt = NULL; 1341 } 1342 kfree(DCN10STRENC_FROM_STRENC(pool->base.stream_enc[i])); 1343 pool->base.stream_enc[i] = NULL; 1344 } 1345 } 1346 1347 for (i = 0; i < pool->base.res_cap->num_dsc; i++) { 1348 if (pool->base.dscs[i] != NULL) 1349 dcn20_dsc_destroy(&pool->base.dscs[i]); 1350 } 1351 1352 if (pool->base.mpc != NULL) { 1353 kfree(TO_DCN20_MPC(pool->base.mpc)); 1354 pool->base.mpc = NULL; 1355 } 1356 if (pool->base.hubbub != NULL) { 1357 kfree(pool->base.hubbub); 1358 pool->base.hubbub = NULL; 1359 } 1360 for (i = 0; i < pool->base.pipe_count; i++) { 1361 if (pool->base.dpps[i] != NULL) 1362 dcn31_dpp_destroy(&pool->base.dpps[i]); 1363 1364 if (pool->base.ipps[i] != NULL) 1365 pool->base.ipps[i]->funcs->ipp_destroy(&pool->base.ipps[i]); 1366 1367 if (pool->base.hubps[i] != NULL) { 1368 kfree(TO_DCN20_HUBP(pool->base.hubps[i])); 1369 pool->base.hubps[i] = NULL; 1370 } 1371 1372 if (pool->base.irqs != NULL) { 1373 dal_irq_service_destroy(&pool->base.irqs); 1374 } 1375 } 1376 1377 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { 1378 if (pool->base.engines[i] != NULL) 1379 dce110_engine_destroy(&pool->base.engines[i]); 1380 if (pool->base.hw_i2cs[i] != NULL) { 1381 kfree(pool->base.hw_i2cs[i]); 1382 pool->base.hw_i2cs[i] = NULL; 1383 } 1384 if (pool->base.sw_i2cs[i] != NULL) { 1385 kfree(pool->base.sw_i2cs[i]); 1386 pool->base.sw_i2cs[i] = NULL; 1387 } 1388 } 1389 1390 for (i = 0; i < pool->base.res_cap->num_opp; i++) { 1391 if (pool->base.opps[i] != NULL) 1392 pool->base.opps[i]->funcs->opp_destroy(&pool->base.opps[i]); 1393 } 1394 1395 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { 1396 if (pool->base.timing_generators[i] != NULL) { 1397 kfree(DCN10TG_FROM_TG(pool->base.timing_generators[i])); 1398 pool->base.timing_generators[i] = NULL; 1399 } 1400 } 1401 1402 for (i = 0; i < pool->base.res_cap->num_dwb; i++) { 1403 if (pool->base.dwbc[i] != NULL) { 1404 kfree(TO_DCN30_DWBC(pool->base.dwbc[i])); 1405 pool->base.dwbc[i] = NULL; 1406 } 1407 if (pool->base.mcif_wb[i] != NULL) { 1408 kfree(TO_DCN30_MMHUBBUB(pool->base.mcif_wb[i])); 1409 pool->base.mcif_wb[i] = NULL; 1410 } 1411 } 1412 1413 for (i = 0; i < pool->base.audio_count; i++) { 1414 if (pool->base.audios[i]) 1415 dce_aud_destroy(&pool->base.audios[i]); 1416 } 1417 1418 for (i = 0; i < pool->base.clk_src_count; i++) { 1419 if (pool->base.clock_sources[i] != NULL) { 1420 dcn20_clock_source_destroy(&pool->base.clock_sources[i]); 1421 pool->base.clock_sources[i] = NULL; 1422 } 1423 } 1424 1425 for (i = 0; i < pool->base.res_cap->num_mpc_3dlut; i++) { 1426 if (pool->base.mpc_lut[i] != NULL) { 1427 dc_3dlut_func_release(pool->base.mpc_lut[i]); 1428 pool->base.mpc_lut[i] = NULL; 1429 } 1430 if (pool->base.mpc_shaper[i] != NULL) { 1431 dc_transfer_func_release(pool->base.mpc_shaper[i]); 1432 pool->base.mpc_shaper[i] = NULL; 1433 } 1434 } 1435 1436 if (pool->base.dp_clock_source != NULL) { 1437 dcn20_clock_source_destroy(&pool->base.dp_clock_source); 1438 pool->base.dp_clock_source = NULL; 1439 } 1440 1441 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { 1442 if (pool->base.multiple_abms[i] != NULL) 1443 dce_abm_destroy(&pool->base.multiple_abms[i]); 1444 } 1445 1446 if (pool->base.psr != NULL) 1447 dmub_psr_destroy(&pool->base.psr); 1448 1449 if (pool->base.dccg != NULL) 1450 dcn_dccg_destroy(&pool->base.dccg); 1451 } 1452 1453 static struct hubp *dcn31_hubp_create( 1454 struct dc_context *ctx, 1455 uint32_t inst) 1456 { 1457 struct dcn20_hubp *hubp2 = 1458 kzalloc(sizeof(struct dcn20_hubp), GFP_KERNEL); 1459 1460 if (!hubp2) 1461 return NULL; 1462 1463 if (hubp31_construct(hubp2, ctx, inst, 1464 &hubp_regs[inst], &hubp_shift, &hubp_mask)) 1465 return &hubp2->base; 1466 1467 BREAK_TO_DEBUGGER(); 1468 kfree(hubp2); 1469 return NULL; 1470 } 1471 1472 static bool dcn31_dwbc_create(struct dc_context *ctx, struct resource_pool *pool) 1473 { 1474 int i; 1475 uint32_t pipe_count = pool->res_cap->num_dwb; 1476 1477 for (i = 0; i < pipe_count; i++) { 1478 struct dcn30_dwbc *dwbc30 = kzalloc(sizeof(struct dcn30_dwbc), 1479 GFP_KERNEL); 1480 1481 if (!dwbc30) { 1482 dm_error("DC: failed to create dwbc30!\n"); 1483 return false; 1484 } 1485 1486 dcn30_dwbc_construct(dwbc30, ctx, 1487 &dwbc30_regs[i], 1488 &dwbc30_shift, 1489 &dwbc30_mask, 1490 i); 1491 1492 pool->dwbc[i] = &dwbc30->base; 1493 } 1494 return true; 1495 } 1496 1497 static bool dcn31_mmhubbub_create(struct dc_context *ctx, struct resource_pool *pool) 1498 { 1499 int i; 1500 uint32_t pipe_count = pool->res_cap->num_dwb; 1501 1502 for (i = 0; i < pipe_count; i++) { 1503 struct dcn30_mmhubbub *mcif_wb30 = kzalloc(sizeof(struct dcn30_mmhubbub), 1504 GFP_KERNEL); 1505 1506 if (!mcif_wb30) { 1507 dm_error("DC: failed to create mcif_wb30!\n"); 1508 return false; 1509 } 1510 1511 dcn30_mmhubbub_construct(mcif_wb30, ctx, 1512 &mcif_wb30_regs[i], 1513 &mcif_wb30_shift, 1514 &mcif_wb30_mask, 1515 i); 1516 1517 pool->mcif_wb[i] = &mcif_wb30->base; 1518 } 1519 return true; 1520 } 1521 1522 static struct display_stream_compressor *dcn31_dsc_create( 1523 struct dc_context *ctx, uint32_t inst) 1524 { 1525 struct dcn20_dsc *dsc = 1526 kzalloc(sizeof(struct dcn20_dsc), GFP_KERNEL); 1527 1528 if (!dsc) { 1529 BREAK_TO_DEBUGGER(); 1530 return NULL; 1531 } 1532 1533 dsc2_construct(dsc, ctx, inst, &dsc_regs[inst], &dsc_shift, &dsc_mask); 1534 return &dsc->base; 1535 } 1536 1537 static void dcn31_destroy_resource_pool(struct resource_pool **pool) 1538 { 1539 struct dcn31_resource_pool *dcn31_pool = TO_DCN31_RES_POOL(*pool); 1540 1541 dcn31_resource_destruct(dcn31_pool); 1542 kfree(dcn31_pool); 1543 *pool = NULL; 1544 } 1545 1546 static struct clock_source *dcn31_clock_source_create( 1547 struct dc_context *ctx, 1548 struct dc_bios *bios, 1549 enum clock_source_id id, 1550 const struct dce110_clk_src_regs *regs, 1551 bool dp_clk_src) 1552 { 1553 struct dce110_clk_src *clk_src = 1554 kzalloc(sizeof(struct dce110_clk_src), GFP_KERNEL); 1555 1556 if (!clk_src) 1557 return NULL; 1558 1559 if (dcn3_clk_src_construct(clk_src, ctx, bios, id, 1560 regs, &cs_shift, &cs_mask)) { 1561 clk_src->base.dp_clk_src = dp_clk_src; 1562 return &clk_src->base; 1563 } 1564 1565 BREAK_TO_DEBUGGER(); 1566 return NULL; 1567 } 1568 1569 static bool is_dual_plane(enum surface_pixel_format format) 1570 { 1571 return format >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN || format == SURFACE_PIXEL_FORMAT_GRPH_RGBE_ALPHA; 1572 } 1573 1574 static int dcn31_populate_dml_pipes_from_context( 1575 struct dc *dc, struct dc_state *context, 1576 display_e2e_pipe_params_st *pipes, 1577 bool fast_validate) 1578 { 1579 int i, pipe_cnt; 1580 struct resource_context *res_ctx = &context->res_ctx; 1581 struct pipe_ctx *pipe; 1582 1583 dcn20_populate_dml_pipes_from_context(dc, context, pipes, fast_validate); 1584 1585 for (i = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) { 1586 struct dc_crtc_timing *timing; 1587 1588 if (!res_ctx->pipe_ctx[i].stream) 1589 continue; 1590 pipe = &res_ctx->pipe_ctx[i]; 1591 timing = &pipe->stream->timing; 1592 1593 pipes[pipe_cnt].pipe.src.unbounded_req_mode = false; 1594 pipes[pipe_cnt].pipe.src.gpuvm = true; 1595 pipes[pipe_cnt].pipe.src.dcc_fraction_of_zs_req_luma = 0; 1596 pipes[pipe_cnt].pipe.src.dcc_fraction_of_zs_req_chroma = 0; 1597 pipes[pipe_cnt].pipe.dest.vfront_porch = timing->v_front_porch; 1598 pipes[pipe_cnt].pipe.src.dcc_rate = 3; 1599 pipes[pipe_cnt].dout.dsc_input_bpc = 0; 1600 1601 if (pipes[pipe_cnt].dout.dsc_enable) { 1602 switch (timing->display_color_depth) { 1603 case COLOR_DEPTH_888: 1604 pipes[pipe_cnt].dout.dsc_input_bpc = 8; 1605 break; 1606 case COLOR_DEPTH_101010: 1607 pipes[pipe_cnt].dout.dsc_input_bpc = 10; 1608 break; 1609 case COLOR_DEPTH_121212: 1610 pipes[pipe_cnt].dout.dsc_input_bpc = 12; 1611 break; 1612 default: 1613 ASSERT(0); 1614 break; 1615 } 1616 } 1617 1618 pipe_cnt++; 1619 } 1620 context->bw_ctx.dml.ip.det_buffer_size_kbytes = DCN3_1_DEFAULT_DET_SIZE; 1621 dc->config.enable_4to1MPC = false; 1622 if (pipe_cnt == 1 && pipe->plane_state && !dc->debug.disable_z9_mpc) { 1623 if (is_dual_plane(pipe->plane_state->format) 1624 && pipe->plane_state->src_rect.width <= 1920 && pipe->plane_state->src_rect.height <= 1080) { 1625 dc->config.enable_4to1MPC = true; 1626 } else if (!is_dual_plane(pipe->plane_state->format)) { 1627 context->bw_ctx.dml.ip.det_buffer_size_kbytes = 192; 1628 pipes[0].pipe.src.unbounded_req_mode = true; 1629 } 1630 } 1631 1632 return pipe_cnt; 1633 } 1634 1635 static void dcn31_update_soc_for_wm_a(struct dc *dc, struct dc_state *context) 1636 { 1637 if (dc->clk_mgr->bw_params->wm_table.entries[WM_A].valid) { 1638 context->bw_ctx.dml.soc.dram_clock_change_latency_us = dc->clk_mgr->bw_params->wm_table.entries[WM_A].pstate_latency_us; 1639 context->bw_ctx.dml.soc.sr_enter_plus_exit_time_us = dc->clk_mgr->bw_params->wm_table.entries[WM_A].sr_enter_plus_exit_time_us; 1640 context->bw_ctx.dml.soc.sr_exit_time_us = dc->clk_mgr->bw_params->wm_table.entries[WM_A].sr_exit_time_us; 1641 } 1642 } 1643 1644 static void dcn31_calculate_wm_and_dlg_fp( 1645 struct dc *dc, struct dc_state *context, 1646 display_e2e_pipe_params_st *pipes, 1647 int pipe_cnt, 1648 int vlevel) 1649 { 1650 int i, pipe_idx; 1651 double dcfclk = context->bw_ctx.dml.vba.DCFCLKState[vlevel][context->bw_ctx.dml.vba.maxMpcComb]; 1652 1653 if (context->bw_ctx.dml.soc.min_dcfclk > dcfclk) 1654 dcfclk = context->bw_ctx.dml.soc.min_dcfclk; 1655 1656 pipes[0].clks_cfg.voltage = vlevel; 1657 pipes[0].clks_cfg.dcfclk_mhz = dcfclk; 1658 pipes[0].clks_cfg.socclk_mhz = context->bw_ctx.dml.soc.clock_limits[vlevel].socclk_mhz; 1659 1660 #if 0 // TODO 1661 /* Set B: 1662 * TODO 1663 */ 1664 if (dc->clk_mgr->bw_params->wm_table.nv_entries[WM_B].valid) { 1665 if (vlevel == 0) { 1666 pipes[0].clks_cfg.voltage = 1; 1667 pipes[0].clks_cfg.dcfclk_mhz = context->bw_ctx.dml.soc.clock_limits[0].dcfclk_mhz; 1668 } 1669 context->bw_ctx.dml.soc.dram_clock_change_latency_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_B].dml_input.pstate_latency_us; 1670 context->bw_ctx.dml.soc.sr_enter_plus_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_B].dml_input.sr_enter_plus_exit_time_us; 1671 context->bw_ctx.dml.soc.sr_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_B].dml_input.sr_exit_time_us; 1672 } 1673 context->bw_ctx.bw.dcn.watermarks.b.urgent_ns = get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 1674 context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 1675 context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 1676 context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.cstate_enter_plus_exit_z8_ns = get_wm_z8_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 1677 context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.cstate_exit_z8_ns = get_wm_z8_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 1678 context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 1679 context->bw_ctx.bw.dcn.watermarks.b.pte_meta_urgent_ns = get_wm_memory_trip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 1680 context->bw_ctx.bw.dcn.watermarks.b.frac_urg_bw_nom = get_fraction_of_urgent_bandwidth(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 1681 context->bw_ctx.bw.dcn.watermarks.b.frac_urg_bw_flip = get_fraction_of_urgent_bandwidth_imm_flip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 1682 context->bw_ctx.bw.dcn.watermarks.b.urgent_latency_ns = get_urgent_latency(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 1683 1684 pipes[0].clks_cfg.voltage = vlevel; 1685 pipes[0].clks_cfg.dcfclk_mhz = dcfclk; 1686 1687 /* Set C: 1688 * TODO 1689 */ 1690 if (dc->clk_mgr->bw_params->wm_table.nv_entries[WM_C].valid) { 1691 context->bw_ctx.dml.soc.dram_clock_change_latency_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_C].dml_input.pstate_latency_us; 1692 context->bw_ctx.dml.soc.sr_enter_plus_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_C].dml_input.sr_enter_plus_exit_time_us; 1693 context->bw_ctx.dml.soc.sr_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_C].dml_input.sr_exit_time_us; 1694 } 1695 context->bw_ctx.bw.dcn.watermarks.c.urgent_ns = get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 1696 context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 1697 context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 1698 context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.cstate_enter_plus_exit_z8_ns = get_wm_z8_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 1699 context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.cstate_exit_z8_ns = get_wm_z8_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 1700 context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 1701 context->bw_ctx.bw.dcn.watermarks.c.pte_meta_urgent_ns = get_wm_memory_trip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 1702 context->bw_ctx.bw.dcn.watermarks.c.frac_urg_bw_nom = get_fraction_of_urgent_bandwidth(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 1703 context->bw_ctx.bw.dcn.watermarks.c.frac_urg_bw_flip = get_fraction_of_urgent_bandwidth_imm_flip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 1704 context->bw_ctx.bw.dcn.watermarks.c.urgent_latency_ns = get_urgent_latency(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 1705 1706 /* Set D: 1707 * TODO 1708 */ 1709 if (dc->clk_mgr->bw_params->wm_table.nv_entries[WM_D].valid) { 1710 context->bw_ctx.dml.soc.dram_clock_change_latency_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_D].dml_input.pstate_latency_us; 1711 context->bw_ctx.dml.soc.sr_enter_plus_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_D].dml_input.sr_enter_plus_exit_time_us; 1712 context->bw_ctx.dml.soc.sr_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_D].dml_input.sr_exit_time_us; 1713 } 1714 context->bw_ctx.bw.dcn.watermarks.d.urgent_ns = get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 1715 context->bw_ctx.bw.dcn.watermarks.d.cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 1716 context->bw_ctx.bw.dcn.watermarks.d.cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 1717 context->bw_ctx.bw.dcn.watermarks.d.cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 1718 context->bw_ctx.bw.dcn.watermarks.d.cstate_pstate.cstate_enter_plus_exit_z8_ns = get_wm_z8_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 1719 context->bw_ctx.bw.dcn.watermarks.d.cstate_pstate.cstate_exit_z8_ns = get_wm_z8_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 1720 context->bw_ctx.bw.dcn.watermarks.d.pte_meta_urgent_ns = get_wm_memory_trip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 1721 context->bw_ctx.bw.dcn.watermarks.d.frac_urg_bw_nom = get_fraction_of_urgent_bandwidth(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 1722 context->bw_ctx.bw.dcn.watermarks.d.frac_urg_bw_flip = get_fraction_of_urgent_bandwidth_imm_flip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 1723 context->bw_ctx.bw.dcn.watermarks.d.urgent_latency_ns = get_urgent_latency(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 1724 #endif 1725 1726 /* Set A: 1727 * All clocks min required 1728 * 1729 * Set A calculated last so that following calculations are based on Set A 1730 */ 1731 dc->res_pool->funcs->update_soc_for_wm_a(dc, context); 1732 context->bw_ctx.bw.dcn.watermarks.a.urgent_ns = get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 1733 context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 1734 context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 1735 context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 1736 context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.cstate_enter_plus_exit_z8_ns = get_wm_z8_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 1737 context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.cstate_exit_z8_ns = get_wm_z8_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 1738 context->bw_ctx.bw.dcn.watermarks.a.pte_meta_urgent_ns = get_wm_memory_trip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 1739 context->bw_ctx.bw.dcn.watermarks.a.frac_urg_bw_nom = get_fraction_of_urgent_bandwidth(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 1740 context->bw_ctx.bw.dcn.watermarks.a.frac_urg_bw_flip = get_fraction_of_urgent_bandwidth_imm_flip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 1741 context->bw_ctx.bw.dcn.watermarks.a.urgent_latency_ns = get_urgent_latency(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 1742 /* TODO: remove: */ 1743 context->bw_ctx.bw.dcn.watermarks.b = context->bw_ctx.bw.dcn.watermarks.a; 1744 context->bw_ctx.bw.dcn.watermarks.c = context->bw_ctx.bw.dcn.watermarks.a; 1745 context->bw_ctx.bw.dcn.watermarks.d = context->bw_ctx.bw.dcn.watermarks.a; 1746 /* end remove*/ 1747 1748 for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) { 1749 if (!context->res_ctx.pipe_ctx[i].stream) 1750 continue; 1751 1752 pipes[pipe_idx].clks_cfg.dispclk_mhz = get_dispclk_calculated(&context->bw_ctx.dml, pipes, pipe_cnt); 1753 pipes[pipe_idx].clks_cfg.dppclk_mhz = get_dppclk_calculated(&context->bw_ctx.dml, pipes, pipe_cnt, pipe_idx); 1754 1755 if (dc->config.forced_clocks) { 1756 pipes[pipe_idx].clks_cfg.dispclk_mhz = context->bw_ctx.dml.soc.clock_limits[0].dispclk_mhz; 1757 pipes[pipe_idx].clks_cfg.dppclk_mhz = context->bw_ctx.dml.soc.clock_limits[0].dppclk_mhz; 1758 } 1759 if (dc->debug.min_disp_clk_khz > pipes[pipe_idx].clks_cfg.dispclk_mhz * 1000) 1760 pipes[pipe_idx].clks_cfg.dispclk_mhz = dc->debug.min_disp_clk_khz / 1000.0; 1761 if (dc->debug.min_dpp_clk_khz > pipes[pipe_idx].clks_cfg.dppclk_mhz * 1000) 1762 pipes[pipe_idx].clks_cfg.dppclk_mhz = dc->debug.min_dpp_clk_khz / 1000.0; 1763 1764 pipe_idx++; 1765 } 1766 1767 dcn20_calculate_dlg_params(dc, context, pipes, pipe_cnt, vlevel); 1768 } 1769 1770 static void dcn31_calculate_wm_and_dlg( 1771 struct dc *dc, struct dc_state *context, 1772 display_e2e_pipe_params_st *pipes, 1773 int pipe_cnt, 1774 int vlevel) 1775 { 1776 DC_FP_START(); 1777 dcn31_calculate_wm_and_dlg_fp(dc, context, pipes, pipe_cnt, vlevel); 1778 DC_FP_END(); 1779 } 1780 1781 static struct dc_cap_funcs cap_funcs = { 1782 .get_dcc_compression_cap = dcn20_get_dcc_compression_cap 1783 }; 1784 1785 static void dcn31_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params) 1786 { 1787 struct clk_limit_table *clk_table = &bw_params->clk_table; 1788 struct _vcs_dpi_voltage_scaling_st clock_limits[DC__VOLTAGE_STATES]; 1789 unsigned int i, closest_clk_lvl; 1790 int j; 1791 1792 // Default clock levels are used for diags, which may lead to overclocking. 1793 if (!IS_DIAG_DC(dc->ctx->dce_environment)) { 1794 int max_dispclk_mhz = 0, max_dppclk_mhz = 0; 1795 1796 dcn3_1_ip.max_num_otg = dc->res_pool->res_cap->num_timing_generator; 1797 dcn3_1_ip.max_num_dpp = dc->res_pool->pipe_count; 1798 dcn3_1_soc.num_chans = bw_params->num_channels; 1799 1800 ASSERT(clk_table->num_entries); 1801 1802 /* Prepass to find max clocks independent of voltage level. */ 1803 for (i = 0; i < clk_table->num_entries; ++i) { 1804 if (clk_table->entries[i].dispclk_mhz > max_dispclk_mhz) 1805 max_dispclk_mhz = clk_table->entries[i].dispclk_mhz; 1806 if (clk_table->entries[i].dppclk_mhz > max_dppclk_mhz) 1807 max_dppclk_mhz = clk_table->entries[i].dppclk_mhz; 1808 } 1809 1810 for (i = 0; i < clk_table->num_entries; i++) { 1811 /* loop backwards*/ 1812 for (closest_clk_lvl = 0, j = dcn3_1_soc.num_states - 1; j >= 0; j--) { 1813 if ((unsigned int) dcn3_1_soc.clock_limits[j].dcfclk_mhz <= clk_table->entries[i].dcfclk_mhz) { 1814 closest_clk_lvl = j; 1815 break; 1816 } 1817 } 1818 1819 clock_limits[i].state = i; 1820 1821 /* Clocks dependent on voltage level. */ 1822 clock_limits[i].dcfclk_mhz = clk_table->entries[i].dcfclk_mhz; 1823 clock_limits[i].fabricclk_mhz = clk_table->entries[i].fclk_mhz; 1824 clock_limits[i].socclk_mhz = clk_table->entries[i].socclk_mhz; 1825 clock_limits[i].dram_speed_mts = clk_table->entries[i].memclk_mhz * 2 * clk_table->entries[i].wck_ratio; 1826 1827 /* Clocks independent of voltage level. */ 1828 clock_limits[i].dispclk_mhz = max_dispclk_mhz ? max_dispclk_mhz : 1829 dcn3_1_soc.clock_limits[closest_clk_lvl].dispclk_mhz; 1830 1831 clock_limits[i].dppclk_mhz = max_dppclk_mhz ? max_dppclk_mhz : 1832 dcn3_1_soc.clock_limits[closest_clk_lvl].dppclk_mhz; 1833 1834 clock_limits[i].dram_bw_per_chan_gbps = dcn3_1_soc.clock_limits[closest_clk_lvl].dram_bw_per_chan_gbps; 1835 clock_limits[i].dscclk_mhz = dcn3_1_soc.clock_limits[closest_clk_lvl].dscclk_mhz; 1836 clock_limits[i].dtbclk_mhz = dcn3_1_soc.clock_limits[closest_clk_lvl].dtbclk_mhz; 1837 clock_limits[i].phyclk_d18_mhz = dcn3_1_soc.clock_limits[closest_clk_lvl].phyclk_d18_mhz; 1838 clock_limits[i].phyclk_mhz = dcn3_1_soc.clock_limits[closest_clk_lvl].phyclk_mhz; 1839 } 1840 for (i = 0; i < clk_table->num_entries; i++) 1841 dcn3_1_soc.clock_limits[i] = clock_limits[i]; 1842 if (clk_table->num_entries) { 1843 dcn3_1_soc.num_states = clk_table->num_entries; 1844 } 1845 } 1846 1847 dcn3_1_soc.dispclk_dppclk_vco_speed_mhz = dc->clk_mgr->dentist_vco_freq_khz / 1000.0; 1848 dc->dml.soc.dispclk_dppclk_vco_speed_mhz = dc->clk_mgr->dentist_vco_freq_khz / 1000.0; 1849 1850 if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) 1851 dml_init_instance(&dc->dml, &dcn3_1_soc, &dcn3_1_ip, DML_PROJECT_DCN31); 1852 else 1853 dml_init_instance(&dc->dml, &dcn3_1_soc, &dcn3_1_ip, DML_PROJECT_DCN31_FPGA); 1854 } 1855 1856 static struct resource_funcs dcn31_res_pool_funcs = { 1857 .destroy = dcn31_destroy_resource_pool, 1858 .link_enc_create = dcn31_link_encoder_create, 1859 .link_enc_create_minimal = dcn31_link_enc_create_minimal, 1860 .link_encs_assign = link_enc_cfg_link_encs_assign, 1861 .link_enc_unassign = link_enc_cfg_link_enc_unassign, 1862 .panel_cntl_create = dcn31_panel_cntl_create, 1863 .validate_bandwidth = dcn30_validate_bandwidth, 1864 .calculate_wm_and_dlg = dcn31_calculate_wm_and_dlg, 1865 .update_soc_for_wm_a = dcn31_update_soc_for_wm_a, 1866 .populate_dml_pipes = dcn31_populate_dml_pipes_from_context, 1867 .acquire_idle_pipe_for_layer = dcn20_acquire_idle_pipe_for_layer, 1868 .add_stream_to_ctx = dcn30_add_stream_to_ctx, 1869 .add_dsc_to_stream_resource = dcn20_add_dsc_to_stream_resource, 1870 .remove_stream_from_ctx = dcn20_remove_stream_from_ctx, 1871 .populate_dml_writeback_from_context = dcn30_populate_dml_writeback_from_context, 1872 .set_mcif_arb_params = dcn30_set_mcif_arb_params, 1873 .find_first_free_match_stream_enc_for_link = dcn10_find_first_free_match_stream_enc_for_link, 1874 .acquire_post_bldn_3dlut = dcn30_acquire_post_bldn_3dlut, 1875 .release_post_bldn_3dlut = dcn30_release_post_bldn_3dlut, 1876 .update_bw_bounding_box = dcn31_update_bw_bounding_box, 1877 .patch_unknown_plane_state = dcn20_patch_unknown_plane_state, 1878 }; 1879 1880 static struct clock_source *dcn30_clock_source_create( 1881 struct dc_context *ctx, 1882 struct dc_bios *bios, 1883 enum clock_source_id id, 1884 const struct dce110_clk_src_regs *regs, 1885 bool dp_clk_src) 1886 { 1887 struct dce110_clk_src *clk_src = 1888 kzalloc(sizeof(struct dce110_clk_src), GFP_KERNEL); 1889 1890 if (!clk_src) 1891 return NULL; 1892 1893 if (dcn3_clk_src_construct(clk_src, ctx, bios, id, 1894 regs, &cs_shift, &cs_mask)) { 1895 clk_src->base.dp_clk_src = dp_clk_src; 1896 return &clk_src->base; 1897 } 1898 1899 BREAK_TO_DEBUGGER(); 1900 return NULL; 1901 } 1902 1903 static bool dcn31_resource_construct( 1904 uint8_t num_virtual_links, 1905 struct dc *dc, 1906 struct dcn31_resource_pool *pool) 1907 { 1908 int i; 1909 struct dc_context *ctx = dc->ctx; 1910 struct irq_service_init_data init_data; 1911 1912 DC_FP_START(); 1913 1914 ctx->dc_bios->regs = &bios_regs; 1915 1916 pool->base.res_cap = &res_cap_dcn31; 1917 1918 pool->base.funcs = &dcn31_res_pool_funcs; 1919 1920 /************************************************* 1921 * Resource + asic cap harcoding * 1922 *************************************************/ 1923 pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE; 1924 pool->base.pipe_count = pool->base.res_cap->num_timing_generator; 1925 pool->base.mpcc_count = pool->base.res_cap->num_timing_generator; 1926 dc->caps.max_downscale_ratio = 600; 1927 dc->caps.i2c_speed_in_khz = 100; 1928 dc->caps.i2c_speed_in_khz_hdcp = 5; /*1.4 w/a applied by default*/ 1929 dc->caps.max_cursor_size = 256; 1930 dc->caps.min_horizontal_blanking_period = 80; 1931 dc->caps.dmdata_alloc_size = 2048; 1932 1933 dc->caps.max_slave_planes = 1; 1934 dc->caps.max_slave_yuv_planes = 1; 1935 dc->caps.max_slave_rgb_planes = 1; 1936 dc->caps.post_blend_color_processing = true; 1937 dc->caps.force_dp_tps4_for_cp2520 = true; 1938 dc->caps.extended_aux_timeout_support = true; 1939 dc->caps.dmcub_support = true; 1940 dc->caps.is_apu = true; 1941 1942 /* Color pipeline capabilities */ 1943 dc->caps.color.dpp.dcn_arch = 1; 1944 dc->caps.color.dpp.input_lut_shared = 0; 1945 dc->caps.color.dpp.icsc = 1; 1946 dc->caps.color.dpp.dgam_ram = 0; // must use gamma_corr 1947 dc->caps.color.dpp.dgam_rom_caps.srgb = 1; 1948 dc->caps.color.dpp.dgam_rom_caps.bt2020 = 1; 1949 dc->caps.color.dpp.dgam_rom_caps.gamma2_2 = 1; 1950 dc->caps.color.dpp.dgam_rom_caps.pq = 1; 1951 dc->caps.color.dpp.dgam_rom_caps.hlg = 1; 1952 dc->caps.color.dpp.post_csc = 1; 1953 dc->caps.color.dpp.gamma_corr = 1; 1954 dc->caps.color.dpp.dgam_rom_for_yuv = 0; 1955 1956 dc->caps.color.dpp.hw_3d_lut = 1; 1957 dc->caps.color.dpp.ogam_ram = 1; 1958 // no OGAM ROM on DCN301 1959 dc->caps.color.dpp.ogam_rom_caps.srgb = 0; 1960 dc->caps.color.dpp.ogam_rom_caps.bt2020 = 0; 1961 dc->caps.color.dpp.ogam_rom_caps.gamma2_2 = 0; 1962 dc->caps.color.dpp.ogam_rom_caps.pq = 0; 1963 dc->caps.color.dpp.ogam_rom_caps.hlg = 0; 1964 dc->caps.color.dpp.ocsc = 0; 1965 1966 dc->caps.color.mpc.gamut_remap = 1; 1967 dc->caps.color.mpc.num_3dluts = pool->base.res_cap->num_mpc_3dlut; //2 1968 dc->caps.color.mpc.ogam_ram = 1; 1969 dc->caps.color.mpc.ogam_rom_caps.srgb = 0; 1970 dc->caps.color.mpc.ogam_rom_caps.bt2020 = 0; 1971 dc->caps.color.mpc.ogam_rom_caps.gamma2_2 = 0; 1972 dc->caps.color.mpc.ogam_rom_caps.pq = 0; 1973 dc->caps.color.mpc.ogam_rom_caps.hlg = 0; 1974 dc->caps.color.mpc.ocsc = 1; 1975 1976 /* read VBIOS LTTPR caps */ 1977 { 1978 if (ctx->dc_bios->funcs->get_lttpr_caps) { 1979 enum bp_result bp_query_result; 1980 uint8_t is_vbios_lttpr_enable = 0; 1981 1982 bp_query_result = ctx->dc_bios->funcs->get_lttpr_caps(ctx->dc_bios, &is_vbios_lttpr_enable); 1983 dc->caps.vbios_lttpr_enable = (bp_query_result == BP_RESULT_OK) && !!is_vbios_lttpr_enable; 1984 } 1985 1986 /* interop bit is implicit */ 1987 { 1988 dc->caps.vbios_lttpr_aware = true; 1989 } 1990 } 1991 1992 if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV) 1993 dc->debug = debug_defaults_drv; 1994 else if (dc->ctx->dce_environment == DCE_ENV_FPGA_MAXIMUS) { 1995 dc->debug = debug_defaults_diags; 1996 } else 1997 dc->debug = debug_defaults_diags; 1998 // Init the vm_helper 1999 if (dc->vm_helper) 2000 vm_helper_init(dc->vm_helper, 16); 2001 2002 /************************************************* 2003 * Create resources * 2004 *************************************************/ 2005 2006 /* Clock Sources for Pixel Clock*/ 2007 pool->base.clock_sources[DCN31_CLK_SRC_PLL0] = 2008 dcn30_clock_source_create(ctx, ctx->dc_bios, 2009 CLOCK_SOURCE_COMBO_PHY_PLL0, 2010 &clk_src_regs[0], false); 2011 pool->base.clock_sources[DCN31_CLK_SRC_PLL1] = 2012 dcn30_clock_source_create(ctx, ctx->dc_bios, 2013 CLOCK_SOURCE_COMBO_PHY_PLL1, 2014 &clk_src_regs[1], false); 2015 pool->base.clock_sources[DCN31_CLK_SRC_PLL2] = 2016 dcn30_clock_source_create(ctx, ctx->dc_bios, 2017 CLOCK_SOURCE_COMBO_PHY_PLL2, 2018 &clk_src_regs[2], false); 2019 pool->base.clock_sources[DCN31_CLK_SRC_PLL3] = 2020 dcn30_clock_source_create(ctx, ctx->dc_bios, 2021 CLOCK_SOURCE_COMBO_PHY_PLL3, 2022 &clk_src_regs[3], false); 2023 pool->base.clock_sources[DCN31_CLK_SRC_PLL4] = 2024 dcn30_clock_source_create(ctx, ctx->dc_bios, 2025 CLOCK_SOURCE_COMBO_PHY_PLL4, 2026 &clk_src_regs[4], false); 2027 2028 pool->base.clk_src_count = DCN30_CLK_SRC_TOTAL; 2029 2030 /* todo: not reuse phy_pll registers */ 2031 pool->base.dp_clock_source = 2032 dcn31_clock_source_create(ctx, ctx->dc_bios, 2033 CLOCK_SOURCE_ID_DP_DTO, 2034 &clk_src_regs[0], true); 2035 2036 for (i = 0; i < pool->base.clk_src_count; i++) { 2037 if (pool->base.clock_sources[i] == NULL) { 2038 dm_error("DC: failed to create clock sources!\n"); 2039 BREAK_TO_DEBUGGER(); 2040 goto create_fail; 2041 } 2042 } 2043 2044 /* TODO: DCCG */ 2045 pool->base.dccg = dccg31_create(ctx, &dccg_regs, &dccg_shift, &dccg_mask); 2046 if (pool->base.dccg == NULL) { 2047 dm_error("DC: failed to create dccg!\n"); 2048 BREAK_TO_DEBUGGER(); 2049 goto create_fail; 2050 } 2051 2052 /* TODO: IRQ */ 2053 init_data.ctx = dc->ctx; 2054 pool->base.irqs = dal_irq_service_dcn31_create(&init_data); 2055 if (!pool->base.irqs) 2056 goto create_fail; 2057 2058 /* HUBBUB */ 2059 pool->base.hubbub = dcn31_hubbub_create(ctx); 2060 if (pool->base.hubbub == NULL) { 2061 BREAK_TO_DEBUGGER(); 2062 dm_error("DC: failed to create hubbub!\n"); 2063 goto create_fail; 2064 } 2065 2066 /* HUBPs, DPPs, OPPs and TGs */ 2067 for (i = 0; i < pool->base.pipe_count; i++) { 2068 pool->base.hubps[i] = dcn31_hubp_create(ctx, i); 2069 if (pool->base.hubps[i] == NULL) { 2070 BREAK_TO_DEBUGGER(); 2071 dm_error( 2072 "DC: failed to create hubps!\n"); 2073 goto create_fail; 2074 } 2075 2076 pool->base.dpps[i] = dcn31_dpp_create(ctx, i); 2077 if (pool->base.dpps[i] == NULL) { 2078 BREAK_TO_DEBUGGER(); 2079 dm_error( 2080 "DC: failed to create dpps!\n"); 2081 goto create_fail; 2082 } 2083 } 2084 2085 for (i = 0; i < pool->base.res_cap->num_opp; i++) { 2086 pool->base.opps[i] = dcn31_opp_create(ctx, i); 2087 if (pool->base.opps[i] == NULL) { 2088 BREAK_TO_DEBUGGER(); 2089 dm_error( 2090 "DC: failed to create output pixel processor!\n"); 2091 goto create_fail; 2092 } 2093 } 2094 2095 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { 2096 pool->base.timing_generators[i] = dcn31_timing_generator_create( 2097 ctx, i); 2098 if (pool->base.timing_generators[i] == NULL) { 2099 BREAK_TO_DEBUGGER(); 2100 dm_error("DC: failed to create tg!\n"); 2101 goto create_fail; 2102 } 2103 } 2104 pool->base.timing_generator_count = i; 2105 2106 /* PSR */ 2107 pool->base.psr = dmub_psr_create(ctx); 2108 if (pool->base.psr == NULL) { 2109 dm_error("DC: failed to create psr obj!\n"); 2110 BREAK_TO_DEBUGGER(); 2111 goto create_fail; 2112 } 2113 2114 /* ABM */ 2115 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { 2116 pool->base.multiple_abms[i] = dmub_abm_create(ctx, 2117 &abm_regs[i], 2118 &abm_shift, 2119 &abm_mask); 2120 if (pool->base.multiple_abms[i] == NULL) { 2121 dm_error("DC: failed to create abm for pipe %d!\n", i); 2122 BREAK_TO_DEBUGGER(); 2123 goto create_fail; 2124 } 2125 } 2126 2127 /* MPC and DSC */ 2128 pool->base.mpc = dcn31_mpc_create(ctx, pool->base.mpcc_count, pool->base.res_cap->num_mpc_3dlut); 2129 if (pool->base.mpc == NULL) { 2130 BREAK_TO_DEBUGGER(); 2131 dm_error("DC: failed to create mpc!\n"); 2132 goto create_fail; 2133 } 2134 2135 for (i = 0; i < pool->base.res_cap->num_dsc; i++) { 2136 pool->base.dscs[i] = dcn31_dsc_create(ctx, i); 2137 if (pool->base.dscs[i] == NULL) { 2138 BREAK_TO_DEBUGGER(); 2139 dm_error("DC: failed to create display stream compressor %d!\n", i); 2140 goto create_fail; 2141 } 2142 } 2143 2144 /* DWB and MMHUBBUB */ 2145 if (!dcn31_dwbc_create(ctx, &pool->base)) { 2146 BREAK_TO_DEBUGGER(); 2147 dm_error("DC: failed to create dwbc!\n"); 2148 goto create_fail; 2149 } 2150 2151 if (!dcn31_mmhubbub_create(ctx, &pool->base)) { 2152 BREAK_TO_DEBUGGER(); 2153 dm_error("DC: failed to create mcif_wb!\n"); 2154 goto create_fail; 2155 } 2156 2157 /* AUX and I2C */ 2158 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { 2159 pool->base.engines[i] = dcn31_aux_engine_create(ctx, i); 2160 if (pool->base.engines[i] == NULL) { 2161 BREAK_TO_DEBUGGER(); 2162 dm_error( 2163 "DC:failed to create aux engine!!\n"); 2164 goto create_fail; 2165 } 2166 pool->base.hw_i2cs[i] = dcn31_i2c_hw_create(ctx, i); 2167 if (pool->base.hw_i2cs[i] == NULL) { 2168 BREAK_TO_DEBUGGER(); 2169 dm_error( 2170 "DC:failed to create hw i2c!!\n"); 2171 goto create_fail; 2172 } 2173 pool->base.sw_i2cs[i] = NULL; 2174 } 2175 2176 /* Audio, Stream Encoders including HPO and virtual, MPC 3D LUTs */ 2177 if (!resource_construct(num_virtual_links, dc, &pool->base, 2178 (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment) ? 2179 &res_create_funcs : &res_create_maximus_funcs))) 2180 goto create_fail; 2181 2182 /* HW Sequencer and Plane caps */ 2183 dcn31_hw_sequencer_construct(dc); 2184 2185 dc->caps.max_planes = pool->base.pipe_count; 2186 2187 for (i = 0; i < dc->caps.max_planes; ++i) 2188 dc->caps.planes[i] = plane_cap; 2189 2190 dc->cap_funcs = cap_funcs; 2191 2192 DC_FP_END(); 2193 2194 return true; 2195 2196 create_fail: 2197 2198 DC_FP_END(); 2199 dcn31_resource_destruct(pool); 2200 2201 return false; 2202 } 2203 2204 struct resource_pool *dcn31_create_resource_pool( 2205 const struct dc_init_data *init_data, 2206 struct dc *dc) 2207 { 2208 struct dcn31_resource_pool *pool = 2209 kzalloc(sizeof(struct dcn31_resource_pool), GFP_KERNEL); 2210 2211 if (!pool) 2212 return NULL; 2213 2214 if (dcn31_resource_construct(init_data->num_virtual_links, dc, pool)) 2215 return &pool->base; 2216 2217 BREAK_TO_DEBUGGER(); 2218 kfree(pool); 2219 return NULL; 2220 } 2221