1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 27 #include "dm_services.h" 28 #include "dc.h" 29 30 #include "dcn31/dcn31_init.h" 31 32 #include "resource.h" 33 #include "include/irq_service_interface.h" 34 #include "dcn31_resource.h" 35 36 #include "dcn20/dcn20_resource.h" 37 #include "dcn30/dcn30_resource.h" 38 39 #include "dcn10/dcn10_ipp.h" 40 #include "dcn30/dcn30_hubbub.h" 41 #include "dcn31/dcn31_hubbub.h" 42 #include "dcn30/dcn30_mpc.h" 43 #include "dcn31/dcn31_hubp.h" 44 #include "irq/dcn31/irq_service_dcn31.h" 45 #include "dcn30/dcn30_dpp.h" 46 #include "dcn31/dcn31_optc.h" 47 #include "dcn20/dcn20_hwseq.h" 48 #include "dcn30/dcn30_hwseq.h" 49 #include "dce110/dce110_hw_sequencer.h" 50 #include "dcn30/dcn30_opp.h" 51 #include "dcn20/dcn20_dsc.h" 52 #include "dcn30/dcn30_vpg.h" 53 #include "dcn30/dcn30_afmt.h" 54 #include "dcn30/dcn30_dio_stream_encoder.h" 55 #include "dcn31/dcn31_dio_link_encoder.h" 56 #include "dce/dce_clock_source.h" 57 #include "dce/dce_audio.h" 58 #include "dce/dce_hwseq.h" 59 #include "clk_mgr.h" 60 #include "virtual/virtual_stream_encoder.h" 61 #include "dce110/dce110_resource.h" 62 #include "dml/display_mode_vba.h" 63 #include "dcn31/dcn31_dccg.h" 64 #include "dcn10/dcn10_resource.h" 65 #include "dcn31_panel_cntl.h" 66 67 #include "dcn30/dcn30_dwb.h" 68 #include "dcn30/dcn30_mmhubbub.h" 69 70 // TODO: change include headers /amd/include/asic_reg after upstream 71 #include "yellow_carp_offset.h" 72 #include "dcn/dcn_3_1_2_offset.h" 73 #include "dcn/dcn_3_1_2_sh_mask.h" 74 #include "nbio/nbio_7_2_0_offset.h" 75 #include "dpcs/dpcs_4_2_0_offset.h" 76 #include "dpcs/dpcs_4_2_0_sh_mask.h" 77 #include "mmhub/mmhub_2_3_0_offset.h" 78 #include "mmhub/mmhub_2_3_0_sh_mask.h" 79 80 81 #define regDCHUBBUB_DEBUG_CTRL_0 0x04d6 82 #define regDCHUBBUB_DEBUG_CTRL_0_BASE_IDX 2 83 #define DCHUBBUB_DEBUG_CTRL_0__DET_DEPTH__SHIFT 0x10 84 #define DCHUBBUB_DEBUG_CTRL_0__DET_DEPTH_MASK 0x01FF0000L 85 86 #include "reg_helper.h" 87 #include "dce/dmub_abm.h" 88 #include "dce/dmub_psr.h" 89 #include "dce/dce_aux.h" 90 #include "dce/dce_i2c.h" 91 92 #include "dml/dcn30/display_mode_vba_30.h" 93 #include "vm_helper.h" 94 #include "dcn20/dcn20_vmid.h" 95 96 #include "link_enc_cfg.h" 97 98 #define DC_LOGGER_INIT(logger) 99 #define fixed16_to_double(x) (((double) x) / ((double) (1 << 16))) 100 #define fixed16_to_double_to_cpu(x) fixed16_to_double(le32_to_cpu(x)) 101 102 #define DCN3_1_DEFAULT_DET_SIZE 384 103 104 struct _vcs_dpi_ip_params_st dcn3_1_ip = { 105 .gpuvm_enable = 1, 106 .gpuvm_max_page_table_levels = 1, 107 .hostvm_enable = 1, 108 .hostvm_max_page_table_levels = 2, 109 .rob_buffer_size_kbytes = 64, 110 .det_buffer_size_kbytes = DCN3_1_DEFAULT_DET_SIZE, 111 .config_return_buffer_size_in_kbytes = 1792, 112 .compressed_buffer_segment_size_in_kbytes = 64, 113 .meta_fifo_size_in_kentries = 32, 114 .zero_size_buffer_entries = 512, 115 .compbuf_reserved_space_64b = 256, 116 .compbuf_reserved_space_zs = 64, 117 .dpp_output_buffer_pixels = 2560, 118 .opp_output_buffer_lines = 1, 119 .pixel_chunk_size_kbytes = 8, 120 .meta_chunk_size_kbytes = 2, 121 .min_meta_chunk_size_bytes = 256, 122 .writeback_chunk_size_kbytes = 8, 123 .ptoi_supported = false, 124 .num_dsc = 3, 125 .maximum_dsc_bits_per_component = 10, 126 .dsc422_native_support = false, 127 .is_line_buffer_bpp_fixed = true, 128 .line_buffer_fixed_bpp = 48, 129 .line_buffer_size_bits = 789504, 130 .max_line_buffer_lines = 12, 131 .writeback_interface_buffer_size_kbytes = 90, 132 .max_num_dpp = 4, 133 .max_num_otg = 4, 134 .max_num_hdmi_frl_outputs = 1, 135 .max_num_wb = 1, 136 .max_dchub_pscl_bw_pix_per_clk = 4, 137 .max_pscl_lb_bw_pix_per_clk = 2, 138 .max_lb_vscl_bw_pix_per_clk = 4, 139 .max_vscl_hscl_bw_pix_per_clk = 4, 140 .max_hscl_ratio = 6, 141 .max_vscl_ratio = 6, 142 .max_hscl_taps = 8, 143 .max_vscl_taps = 8, 144 .dpte_buffer_size_in_pte_reqs_luma = 64, 145 .dpte_buffer_size_in_pte_reqs_chroma = 34, 146 .dispclk_ramp_margin_percent = 1, 147 .max_inter_dcn_tile_repeaters = 8, 148 .cursor_buffer_size = 16, 149 .cursor_chunk_size = 2, 150 .writeback_line_buffer_buffer_size = 0, 151 .writeback_min_hscl_ratio = 1, 152 .writeback_min_vscl_ratio = 1, 153 .writeback_max_hscl_ratio = 1, 154 .writeback_max_vscl_ratio = 1, 155 .writeback_max_hscl_taps = 1, 156 .writeback_max_vscl_taps = 1, 157 .dppclk_delay_subtotal = 46, 158 .dppclk_delay_scl = 50, 159 .dppclk_delay_scl_lb_only = 16, 160 .dppclk_delay_cnvc_formatter = 27, 161 .dppclk_delay_cnvc_cursor = 6, 162 .dispclk_delay_subtotal = 119, 163 .dynamic_metadata_vm_enabled = false, 164 .odm_combine_4to1_supported = false, 165 .dcc_supported = true, 166 }; 167 168 struct _vcs_dpi_soc_bounding_box_st dcn3_1_soc = { 169 /*TODO: correct dispclk/dppclk voltage level determination*/ 170 .clock_limits = { 171 { 172 .state = 0, 173 .dispclk_mhz = 1200.0, 174 .dppclk_mhz = 1200.0, 175 .phyclk_mhz = 600.0, 176 .phyclk_d18_mhz = 667.0, 177 .dscclk_mhz = 186.0, 178 .dtbclk_mhz = 625.0, 179 }, 180 { 181 .state = 1, 182 .dispclk_mhz = 1200.0, 183 .dppclk_mhz = 1200.0, 184 .phyclk_mhz = 810.0, 185 .phyclk_d18_mhz = 667.0, 186 .dscclk_mhz = 209.0, 187 .dtbclk_mhz = 625.0, 188 }, 189 { 190 .state = 2, 191 .dispclk_mhz = 1200.0, 192 .dppclk_mhz = 1200.0, 193 .phyclk_mhz = 810.0, 194 .phyclk_d18_mhz = 667.0, 195 .dscclk_mhz = 209.0, 196 .dtbclk_mhz = 625.0, 197 }, 198 { 199 .state = 3, 200 .dispclk_mhz = 1200.0, 201 .dppclk_mhz = 1200.0, 202 .phyclk_mhz = 810.0, 203 .phyclk_d18_mhz = 667.0, 204 .dscclk_mhz = 371.0, 205 .dtbclk_mhz = 625.0, 206 }, 207 { 208 .state = 4, 209 .dispclk_mhz = 1200.0, 210 .dppclk_mhz = 1200.0, 211 .phyclk_mhz = 810.0, 212 .phyclk_d18_mhz = 667.0, 213 .dscclk_mhz = 417.0, 214 .dtbclk_mhz = 625.0, 215 }, 216 }, 217 .num_states = 5, 218 .sr_exit_time_us = 9.0, 219 .sr_enter_plus_exit_time_us = 11.0, 220 .sr_exit_z8_time_us = 402.0, 221 .sr_enter_plus_exit_z8_time_us = 520.0, 222 .writeback_latency_us = 12.0, 223 .round_trip_ping_latency_dcfclk_cycles = 106, 224 .urgent_latency_pixel_data_only_us = 4.0, 225 .urgent_latency_pixel_mixed_with_vm_data_us = 4.0, 226 .urgent_latency_vm_data_only_us = 4.0, 227 .urgent_out_of_order_return_per_channel_pixel_only_bytes = 4096, 228 .urgent_out_of_order_return_per_channel_pixel_and_vm_bytes = 4096, 229 .urgent_out_of_order_return_per_channel_vm_only_bytes = 4096, 230 .pct_ideal_sdp_bw_after_urgent = 80.0, 231 .pct_ideal_dram_sdp_bw_after_urgent_pixel_only = 65.0, 232 .pct_ideal_dram_sdp_bw_after_urgent_pixel_and_vm = 60.0, 233 .pct_ideal_dram_sdp_bw_after_urgent_vm_only = 30.0, 234 .max_avg_sdp_bw_use_normal_percent = 60.0, 235 .max_avg_dram_bw_use_normal_percent = 60.0, 236 .fabric_datapath_to_dcn_data_return_bytes = 32, 237 .return_bus_width_bytes = 64, 238 .downspread_percent = 0.38, 239 .dcn_downspread_percent = 0.5, 240 .gpuvm_min_page_size_bytes = 4096, 241 .hostvm_min_page_size_bytes = 4096, 242 .do_urgent_latency_adjustment = false, 243 .urgent_latency_adjustment_fabric_clock_component_us = 0, 244 .urgent_latency_adjustment_fabric_clock_reference_mhz = 0, 245 }; 246 247 enum dcn31_clk_src_array_id { 248 DCN31_CLK_SRC_PLL0, 249 DCN31_CLK_SRC_PLL1, 250 DCN31_CLK_SRC_PLL2, 251 DCN31_CLK_SRC_PLL3, 252 DCN31_CLK_SRC_PLL4, 253 DCN30_CLK_SRC_TOTAL 254 }; 255 256 /* begin ********************* 257 * macros to expend register list macro defined in HW object header file 258 */ 259 260 /* DCN */ 261 /* TODO awful hack. fixup dcn20_dwb.h */ 262 #undef BASE_INNER 263 #define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg 264 265 #define BASE(seg) BASE_INNER(seg) 266 267 #define SR(reg_name)\ 268 .reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \ 269 reg ## reg_name 270 271 #define SRI(reg_name, block, id)\ 272 .reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 273 reg ## block ## id ## _ ## reg_name 274 275 #define SRI2(reg_name, block, id)\ 276 .reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \ 277 reg ## reg_name 278 279 #define SRIR(var_name, reg_name, block, id)\ 280 .var_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 281 reg ## block ## id ## _ ## reg_name 282 283 #define SRII(reg_name, block, id)\ 284 .reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 285 reg ## block ## id ## _ ## reg_name 286 287 #define SRII_MPC_RMU(reg_name, block, id)\ 288 .RMU##_##reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 289 reg ## block ## id ## _ ## reg_name 290 291 #define SRII_DWB(reg_name, temp_name, block, id)\ 292 .reg_name[id] = BASE(reg ## block ## id ## _ ## temp_name ## _BASE_IDX) + \ 293 reg ## block ## id ## _ ## temp_name 294 295 #define DCCG_SRII(reg_name, block, id)\ 296 .block ## _ ## reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 297 reg ## block ## id ## _ ## reg_name 298 299 #define VUPDATE_SRII(reg_name, block, id)\ 300 .reg_name[id] = BASE(reg ## reg_name ## _ ## block ## id ## _BASE_IDX) + \ 301 reg ## reg_name ## _ ## block ## id 302 303 /* NBIO */ 304 #define NBIO_BASE_INNER(seg) \ 305 NBIO_BASE__INST0_SEG ## seg 306 307 #define NBIO_BASE(seg) \ 308 NBIO_BASE_INNER(seg) 309 310 #define NBIO_SR(reg_name)\ 311 .reg_name = NBIO_BASE(regBIF_BX1_ ## reg_name ## _BASE_IDX) + \ 312 regBIF_BX1_ ## reg_name 313 314 /* MMHUB */ 315 #define MMHUB_BASE_INNER(seg) \ 316 MMHUB_BASE__INST0_SEG ## seg 317 318 #define MMHUB_BASE(seg) \ 319 MMHUB_BASE_INNER(seg) 320 321 #define MMHUB_SR(reg_name)\ 322 .reg_name = MMHUB_BASE(mm ## reg_name ## _BASE_IDX) + \ 323 mm ## reg_name 324 325 /* CLOCK */ 326 #define CLK_BASE_INNER(seg) \ 327 CLK_BASE__INST0_SEG ## seg 328 329 #define CLK_BASE(seg) \ 330 CLK_BASE_INNER(seg) 331 332 #define CLK_SRI(reg_name, block, inst)\ 333 .reg_name = CLK_BASE(reg ## block ## _ ## inst ## _ ## reg_name ## _BASE_IDX) + \ 334 reg ## block ## _ ## inst ## _ ## reg_name 335 336 337 static const struct bios_registers bios_regs = { 338 NBIO_SR(BIOS_SCRATCH_3), 339 NBIO_SR(BIOS_SCRATCH_6) 340 }; 341 342 #define clk_src_regs(index, pllid)\ 343 [index] = {\ 344 CS_COMMON_REG_LIST_DCN3_0(index, pllid),\ 345 } 346 347 static const struct dce110_clk_src_regs clk_src_regs[] = { 348 clk_src_regs(0, A), 349 clk_src_regs(1, B), 350 clk_src_regs(2, C), 351 clk_src_regs(3, D), 352 clk_src_regs(4, E) 353 }; 354 355 static const struct dce110_clk_src_shift cs_shift = { 356 CS_COMMON_MASK_SH_LIST_DCN2_0(__SHIFT) 357 }; 358 359 static const struct dce110_clk_src_mask cs_mask = { 360 CS_COMMON_MASK_SH_LIST_DCN2_0(_MASK) 361 }; 362 363 #define abm_regs(id)\ 364 [id] = {\ 365 ABM_DCN301_REG_LIST(id)\ 366 } 367 368 static const struct dce_abm_registers abm_regs[] = { 369 abm_regs(0), 370 abm_regs(1), 371 abm_regs(2), 372 abm_regs(3), 373 }; 374 375 static const struct dce_abm_shift abm_shift = { 376 ABM_MASK_SH_LIST_DCN30(__SHIFT) 377 }; 378 379 static const struct dce_abm_mask abm_mask = { 380 ABM_MASK_SH_LIST_DCN30(_MASK) 381 }; 382 383 #define audio_regs(id)\ 384 [id] = {\ 385 AUD_COMMON_REG_LIST(id)\ 386 } 387 388 static const struct dce_audio_registers audio_regs[] = { 389 audio_regs(0), 390 audio_regs(1), 391 audio_regs(2), 392 audio_regs(3), 393 audio_regs(4), 394 audio_regs(5), 395 audio_regs(6) 396 }; 397 398 #define DCE120_AUD_COMMON_MASK_SH_LIST(mask_sh)\ 399 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX, AZALIA_ENDPOINT_REG_INDEX, mask_sh),\ 400 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA, AZALIA_ENDPOINT_REG_DATA, mask_sh),\ 401 AUD_COMMON_MASK_SH_LIST_BASE(mask_sh) 402 403 static const struct dce_audio_shift audio_shift = { 404 DCE120_AUD_COMMON_MASK_SH_LIST(__SHIFT) 405 }; 406 407 static const struct dce_audio_mask audio_mask = { 408 DCE120_AUD_COMMON_MASK_SH_LIST(_MASK) 409 }; 410 411 #define vpg_regs(id)\ 412 [id] = {\ 413 VPG_DCN3_REG_LIST(id)\ 414 } 415 416 static const struct dcn30_vpg_registers vpg_regs[] = { 417 vpg_regs(0), 418 vpg_regs(1), 419 vpg_regs(2), 420 vpg_regs(3), 421 vpg_regs(4), 422 vpg_regs(5), 423 vpg_regs(6), 424 vpg_regs(7), 425 vpg_regs(8), 426 vpg_regs(9), 427 }; 428 429 static const struct dcn30_vpg_shift vpg_shift = { 430 DCN3_VPG_MASK_SH_LIST(__SHIFT) 431 }; 432 433 static const struct dcn30_vpg_mask vpg_mask = { 434 DCN3_VPG_MASK_SH_LIST(_MASK) 435 }; 436 437 #define afmt_regs(id)\ 438 [id] = {\ 439 AFMT_DCN3_REG_LIST(id)\ 440 } 441 442 static const struct dcn30_afmt_registers afmt_regs[] = { 443 afmt_regs(0), 444 afmt_regs(1), 445 afmt_regs(2), 446 afmt_regs(3), 447 afmt_regs(4), 448 afmt_regs(5) 449 }; 450 451 static const struct dcn30_afmt_shift afmt_shift = { 452 DCN3_AFMT_MASK_SH_LIST(__SHIFT) 453 }; 454 455 static const struct dcn30_afmt_mask afmt_mask = { 456 DCN3_AFMT_MASK_SH_LIST(_MASK) 457 }; 458 459 #define stream_enc_regs(id)\ 460 [id] = {\ 461 SE_DCN3_REG_LIST(id)\ 462 } 463 464 static const struct dcn10_stream_enc_registers stream_enc_regs[] = { 465 stream_enc_regs(0), 466 stream_enc_regs(1), 467 stream_enc_regs(2), 468 stream_enc_regs(3), 469 stream_enc_regs(4) 470 }; 471 472 static const struct dcn10_stream_encoder_shift se_shift = { 473 SE_COMMON_MASK_SH_LIST_DCN30(__SHIFT) 474 }; 475 476 static const struct dcn10_stream_encoder_mask se_mask = { 477 SE_COMMON_MASK_SH_LIST_DCN30(_MASK) 478 }; 479 480 481 #define aux_regs(id)\ 482 [id] = {\ 483 DCN2_AUX_REG_LIST(id)\ 484 } 485 486 static const struct dcn10_link_enc_aux_registers link_enc_aux_regs[] = { 487 aux_regs(0), 488 aux_regs(1), 489 aux_regs(2), 490 aux_regs(3), 491 aux_regs(4) 492 }; 493 494 #define hpd_regs(id)\ 495 [id] = {\ 496 HPD_REG_LIST(id)\ 497 } 498 499 static const struct dcn10_link_enc_hpd_registers link_enc_hpd_regs[] = { 500 hpd_regs(0), 501 hpd_regs(1), 502 hpd_regs(2), 503 hpd_regs(3), 504 hpd_regs(4) 505 }; 506 507 #define link_regs(id, phyid)\ 508 [id] = {\ 509 LE_DCN31_REG_LIST(id), \ 510 UNIPHY_DCN2_REG_LIST(phyid), \ 511 DPCS_DCN31_REG_LIST(id), \ 512 } 513 514 static const struct dce110_aux_registers_shift aux_shift = { 515 DCN_AUX_MASK_SH_LIST(__SHIFT) 516 }; 517 518 static const struct dce110_aux_registers_mask aux_mask = { 519 DCN_AUX_MASK_SH_LIST(_MASK) 520 }; 521 522 static const struct dcn10_link_enc_registers link_enc_regs[] = { 523 link_regs(0, A), 524 link_regs(1, B), 525 link_regs(2, C), 526 link_regs(3, D), 527 link_regs(4, E) 528 }; 529 530 static const struct dcn10_link_enc_shift le_shift = { 531 LINK_ENCODER_MASK_SH_LIST_DCN31(__SHIFT), \ 532 DPCS_DCN31_MASK_SH_LIST(__SHIFT) 533 }; 534 535 static const struct dcn10_link_enc_mask le_mask = { 536 LINK_ENCODER_MASK_SH_LIST_DCN31(_MASK), \ 537 DPCS_DCN31_MASK_SH_LIST(_MASK) 538 }; 539 540 #define dpp_regs(id)\ 541 [id] = {\ 542 DPP_REG_LIST_DCN30(id),\ 543 } 544 545 static const struct dcn3_dpp_registers dpp_regs[] = { 546 dpp_regs(0), 547 dpp_regs(1), 548 dpp_regs(2), 549 dpp_regs(3) 550 }; 551 552 static const struct dcn3_dpp_shift tf_shift = { 553 DPP_REG_LIST_SH_MASK_DCN30(__SHIFT) 554 }; 555 556 static const struct dcn3_dpp_mask tf_mask = { 557 DPP_REG_LIST_SH_MASK_DCN30(_MASK) 558 }; 559 560 #define opp_regs(id)\ 561 [id] = {\ 562 OPP_REG_LIST_DCN30(id),\ 563 } 564 565 static const struct dcn20_opp_registers opp_regs[] = { 566 opp_regs(0), 567 opp_regs(1), 568 opp_regs(2), 569 opp_regs(3) 570 }; 571 572 static const struct dcn20_opp_shift opp_shift = { 573 OPP_MASK_SH_LIST_DCN20(__SHIFT) 574 }; 575 576 static const struct dcn20_opp_mask opp_mask = { 577 OPP_MASK_SH_LIST_DCN20(_MASK) 578 }; 579 580 #define aux_engine_regs(id)\ 581 [id] = {\ 582 AUX_COMMON_REG_LIST0(id), \ 583 .AUXN_IMPCAL = 0, \ 584 .AUXP_IMPCAL = 0, \ 585 .AUX_RESET_MASK = DP_AUX0_AUX_CONTROL__AUX_RESET_MASK, \ 586 } 587 588 static const struct dce110_aux_registers aux_engine_regs[] = { 589 aux_engine_regs(0), 590 aux_engine_regs(1), 591 aux_engine_regs(2), 592 aux_engine_regs(3), 593 aux_engine_regs(4) 594 }; 595 596 #define dwbc_regs_dcn3(id)\ 597 [id] = {\ 598 DWBC_COMMON_REG_LIST_DCN30(id),\ 599 } 600 601 static const struct dcn30_dwbc_registers dwbc30_regs[] = { 602 dwbc_regs_dcn3(0), 603 }; 604 605 static const struct dcn30_dwbc_shift dwbc30_shift = { 606 DWBC_COMMON_MASK_SH_LIST_DCN30(__SHIFT) 607 }; 608 609 static const struct dcn30_dwbc_mask dwbc30_mask = { 610 DWBC_COMMON_MASK_SH_LIST_DCN30(_MASK) 611 }; 612 613 #define mcif_wb_regs_dcn3(id)\ 614 [id] = {\ 615 MCIF_WB_COMMON_REG_LIST_DCN30(id),\ 616 } 617 618 static const struct dcn30_mmhubbub_registers mcif_wb30_regs[] = { 619 mcif_wb_regs_dcn3(0) 620 }; 621 622 static const struct dcn30_mmhubbub_shift mcif_wb30_shift = { 623 MCIF_WB_COMMON_MASK_SH_LIST_DCN30(__SHIFT) 624 }; 625 626 static const struct dcn30_mmhubbub_mask mcif_wb30_mask = { 627 MCIF_WB_COMMON_MASK_SH_LIST_DCN30(_MASK) 628 }; 629 630 #define dsc_regsDCN20(id)\ 631 [id] = {\ 632 DSC_REG_LIST_DCN20(id)\ 633 } 634 635 static const struct dcn20_dsc_registers dsc_regs[] = { 636 dsc_regsDCN20(0), 637 dsc_regsDCN20(1), 638 dsc_regsDCN20(2) 639 }; 640 641 static const struct dcn20_dsc_shift dsc_shift = { 642 DSC_REG_LIST_SH_MASK_DCN20(__SHIFT) 643 }; 644 645 static const struct dcn20_dsc_mask dsc_mask = { 646 DSC_REG_LIST_SH_MASK_DCN20(_MASK) 647 }; 648 649 static const struct dcn30_mpc_registers mpc_regs = { 650 MPC_REG_LIST_DCN3_0(0), 651 MPC_REG_LIST_DCN3_0(1), 652 MPC_REG_LIST_DCN3_0(2), 653 MPC_REG_LIST_DCN3_0(3), 654 MPC_OUT_MUX_REG_LIST_DCN3_0(0), 655 MPC_OUT_MUX_REG_LIST_DCN3_0(1), 656 MPC_OUT_MUX_REG_LIST_DCN3_0(2), 657 MPC_OUT_MUX_REG_LIST_DCN3_0(3), 658 MPC_RMU_GLOBAL_REG_LIST_DCN3AG, 659 MPC_RMU_REG_LIST_DCN3AG(0), 660 MPC_RMU_REG_LIST_DCN3AG(1), 661 //MPC_RMU_REG_LIST_DCN3AG(2), 662 MPC_DWB_MUX_REG_LIST_DCN3_0(0), 663 }; 664 665 static const struct dcn30_mpc_shift mpc_shift = { 666 MPC_COMMON_MASK_SH_LIST_DCN30(__SHIFT) 667 }; 668 669 static const struct dcn30_mpc_mask mpc_mask = { 670 MPC_COMMON_MASK_SH_LIST_DCN30(_MASK) 671 }; 672 673 #define optc_regs(id)\ 674 [id] = {OPTC_COMMON_REG_LIST_DCN3_1(id)} 675 676 static const struct dcn_optc_registers optc_regs[] = { 677 optc_regs(0), 678 optc_regs(1), 679 optc_regs(2), 680 optc_regs(3) 681 }; 682 683 static const struct dcn_optc_shift optc_shift = { 684 OPTC_COMMON_MASK_SH_LIST_DCN3_1(__SHIFT) 685 }; 686 687 static const struct dcn_optc_mask optc_mask = { 688 OPTC_COMMON_MASK_SH_LIST_DCN3_1(_MASK) 689 }; 690 691 #define hubp_regs(id)\ 692 [id] = {\ 693 HUBP_REG_LIST_DCN30(id)\ 694 } 695 696 static const struct dcn_hubp2_registers hubp_regs[] = { 697 hubp_regs(0), 698 hubp_regs(1), 699 hubp_regs(2), 700 hubp_regs(3) 701 }; 702 703 704 static const struct dcn_hubp2_shift hubp_shift = { 705 HUBP_MASK_SH_LIST_DCN31(__SHIFT) 706 }; 707 708 static const struct dcn_hubp2_mask hubp_mask = { 709 HUBP_MASK_SH_LIST_DCN31(_MASK) 710 }; 711 static const struct dcn_hubbub_registers hubbub_reg = { 712 HUBBUB_REG_LIST_DCN31(0) 713 }; 714 715 static const struct dcn_hubbub_shift hubbub_shift = { 716 HUBBUB_MASK_SH_LIST_DCN31(__SHIFT) 717 }; 718 719 static const struct dcn_hubbub_mask hubbub_mask = { 720 HUBBUB_MASK_SH_LIST_DCN31(_MASK) 721 }; 722 723 static const struct dccg_registers dccg_regs = { 724 DCCG_REG_LIST_DCN31() 725 }; 726 727 static const struct dccg_shift dccg_shift = { 728 DCCG_MASK_SH_LIST_DCN31(__SHIFT) 729 }; 730 731 static const struct dccg_mask dccg_mask = { 732 DCCG_MASK_SH_LIST_DCN31(_MASK) 733 }; 734 735 736 #define SRII2(reg_name_pre, reg_name_post, id)\ 737 .reg_name_pre ## _ ## reg_name_post[id] = BASE(reg ## reg_name_pre \ 738 ## id ## _ ## reg_name_post ## _BASE_IDX) + \ 739 reg ## reg_name_pre ## id ## _ ## reg_name_post 740 741 742 #define HWSEQ_DCN31_REG_LIST()\ 743 SR(DCHUBBUB_GLOBAL_TIMER_CNTL), \ 744 SR(DIO_MEM_PWR_CTRL), \ 745 SR(ODM_MEM_PWR_CTRL3), \ 746 SR(DMU_MEM_PWR_CNTL), \ 747 SR(MMHUBBUB_MEM_PWR_CNTL), \ 748 SR(DCCG_GATE_DISABLE_CNTL), \ 749 SR(DCCG_GATE_DISABLE_CNTL2), \ 750 SR(DCFCLK_CNTL),\ 751 SR(DC_MEM_GLOBAL_PWR_REQ_CNTL), \ 752 SRII(PIXEL_RATE_CNTL, OTG, 0), \ 753 SRII(PIXEL_RATE_CNTL, OTG, 1),\ 754 SRII(PIXEL_RATE_CNTL, OTG, 2),\ 755 SRII(PIXEL_RATE_CNTL, OTG, 3),\ 756 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 0),\ 757 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 1),\ 758 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 2),\ 759 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 3),\ 760 SR(MICROSECOND_TIME_BASE_DIV), \ 761 SR(MILLISECOND_TIME_BASE_DIV), \ 762 SR(DISPCLK_FREQ_CHANGE_CNTL), \ 763 SR(RBBMIF_TIMEOUT_DIS), \ 764 SR(RBBMIF_TIMEOUT_DIS_2), \ 765 SR(DCHUBBUB_CRC_CTRL), \ 766 SR(DPP_TOP0_DPP_CRC_CTRL), \ 767 SR(DPP_TOP0_DPP_CRC_VAL_B_A), \ 768 SR(DPP_TOP0_DPP_CRC_VAL_R_G), \ 769 SR(MPC_CRC_CTRL), \ 770 SR(MPC_CRC_RESULT_GB), \ 771 SR(MPC_CRC_RESULT_C), \ 772 SR(MPC_CRC_RESULT_AR), \ 773 SR(DOMAIN0_PG_CONFIG), \ 774 SR(DOMAIN1_PG_CONFIG), \ 775 SR(DOMAIN2_PG_CONFIG), \ 776 SR(DOMAIN3_PG_CONFIG), \ 777 SR(DOMAIN16_PG_CONFIG), \ 778 SR(DOMAIN17_PG_CONFIG), \ 779 SR(DOMAIN18_PG_CONFIG), \ 780 SR(DOMAIN0_PG_STATUS), \ 781 SR(DOMAIN1_PG_STATUS), \ 782 SR(DOMAIN2_PG_STATUS), \ 783 SR(DOMAIN3_PG_STATUS), \ 784 SR(DOMAIN16_PG_STATUS), \ 785 SR(DOMAIN17_PG_STATUS), \ 786 SR(DOMAIN18_PG_STATUS), \ 787 SR(D1VGA_CONTROL), \ 788 SR(D2VGA_CONTROL), \ 789 SR(D3VGA_CONTROL), \ 790 SR(D4VGA_CONTROL), \ 791 SR(D5VGA_CONTROL), \ 792 SR(D6VGA_CONTROL), \ 793 SR(DC_IP_REQUEST_CNTL), \ 794 SR(AZALIA_AUDIO_DTO), \ 795 SR(AZALIA_CONTROLLER_CLOCK_GATING) 796 797 static const struct dce_hwseq_registers hwseq_reg = { 798 HWSEQ_DCN31_REG_LIST() 799 }; 800 801 #define HWSEQ_DCN31_MASK_SH_LIST(mask_sh)\ 802 HWSEQ_DCN_MASK_SH_LIST(mask_sh), \ 803 HWS_SF(, DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_REFDIV, mask_sh), \ 804 HWS_SF(, DOMAIN0_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ 805 HWS_SF(, DOMAIN0_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ 806 HWS_SF(, DOMAIN1_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ 807 HWS_SF(, DOMAIN1_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ 808 HWS_SF(, DOMAIN2_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ 809 HWS_SF(, DOMAIN2_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ 810 HWS_SF(, DOMAIN3_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ 811 HWS_SF(, DOMAIN3_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ 812 HWS_SF(, DOMAIN16_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ 813 HWS_SF(, DOMAIN16_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ 814 HWS_SF(, DOMAIN17_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ 815 HWS_SF(, DOMAIN17_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ 816 HWS_SF(, DOMAIN18_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ 817 HWS_SF(, DOMAIN18_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ 818 HWS_SF(, DOMAIN0_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ 819 HWS_SF(, DOMAIN1_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ 820 HWS_SF(, DOMAIN2_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ 821 HWS_SF(, DOMAIN3_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ 822 HWS_SF(, DOMAIN16_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ 823 HWS_SF(, DOMAIN17_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ 824 HWS_SF(, DOMAIN18_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ 825 HWS_SF(, DC_IP_REQUEST_CNTL, IP_REQUEST_EN, mask_sh), \ 826 HWS_SF(, AZALIA_AUDIO_DTO, AZALIA_AUDIO_DTO_MODULE, mask_sh), \ 827 HWS_SF(, HPO_TOP_CLOCK_CONTROL, HPO_HDMISTREAMCLK_G_GATE_DIS, mask_sh), \ 828 HWS_SF(, DMU_MEM_PWR_CNTL, DMCU_ERAM_MEM_PWR_FORCE, mask_sh), \ 829 HWS_SF(, ODM_MEM_PWR_CTRL3, ODM_MEM_UNASSIGNED_PWR_MODE, mask_sh), \ 830 HWS_SF(, ODM_MEM_PWR_CTRL3, ODM_MEM_VBLANK_PWR_MODE, mask_sh), \ 831 HWS_SF(, MMHUBBUB_MEM_PWR_CNTL, VGA_MEM_PWR_FORCE, mask_sh) 832 833 static const struct dce_hwseq_shift hwseq_shift = { 834 HWSEQ_DCN31_MASK_SH_LIST(__SHIFT) 835 }; 836 837 static const struct dce_hwseq_mask hwseq_mask = { 838 HWSEQ_DCN31_MASK_SH_LIST(_MASK) 839 }; 840 #define vmid_regs(id)\ 841 [id] = {\ 842 DCN20_VMID_REG_LIST(id)\ 843 } 844 845 static const struct dcn_vmid_registers vmid_regs[] = { 846 vmid_regs(0), 847 vmid_regs(1), 848 vmid_regs(2), 849 vmid_regs(3), 850 vmid_regs(4), 851 vmid_regs(5), 852 vmid_regs(6), 853 vmid_regs(7), 854 vmid_regs(8), 855 vmid_regs(9), 856 vmid_regs(10), 857 vmid_regs(11), 858 vmid_regs(12), 859 vmid_regs(13), 860 vmid_regs(14), 861 vmid_regs(15) 862 }; 863 864 static const struct dcn20_vmid_shift vmid_shifts = { 865 DCN20_VMID_MASK_SH_LIST(__SHIFT) 866 }; 867 868 static const struct dcn20_vmid_mask vmid_masks = { 869 DCN20_VMID_MASK_SH_LIST(_MASK) 870 }; 871 872 static const struct resource_caps res_cap_dcn31 = { 873 .num_timing_generator = 4, 874 .num_opp = 4, 875 .num_video_plane = 4, 876 .num_audio = 5, 877 .num_stream_encoder = 5, 878 .num_dig_link_enc = 5, 879 .num_pll = 5, 880 .num_dwb = 1, 881 .num_ddc = 5, 882 .num_vmid = 16, 883 .num_mpc_3dlut = 2, 884 .num_dsc = 3, 885 }; 886 887 static const struct dc_plane_cap plane_cap = { 888 .type = DC_PLANE_TYPE_DCN_UNIVERSAL, 889 .blends_with_above = true, 890 .blends_with_below = true, 891 .per_pixel_alpha = true, 892 893 .pixel_format_support = { 894 .argb8888 = true, 895 .nv12 = true, 896 .fp16 = true, 897 .p010 = false, 898 .ayuv = false, 899 }, 900 901 .max_upscale_factor = { 902 .argb8888 = 16000, 903 .nv12 = 16000, 904 .fp16 = 16000 905 }, 906 907 // 6:1 downscaling ratio: 1000/6 = 166.666 908 .max_downscale_factor = { 909 .argb8888 = 167, 910 .nv12 = 167, 911 .fp16 = 167 912 }, 913 64, 914 64 915 }; 916 917 static const struct dc_debug_options debug_defaults_drv = { 918 .disable_dmcu = true, 919 .force_abm_enable = false, 920 .timing_trace = false, 921 .clock_trace = true, 922 .disable_pplib_clock_request = false, 923 .pipe_split_policy = MPC_SPLIT_AVOID, 924 .force_single_disp_pipe_split = false, 925 .disable_dcc = DCC_ENABLE, 926 .vsr_support = true, 927 .performance_trace = false, 928 .max_downscale_src_width = 7680,/*upto 8K*/ 929 .disable_pplib_wm_range = false, 930 .scl_reset_length10 = true, 931 .sanity_checks = false, 932 .underflow_assert_delay_us = 0xFFFFFFFF, 933 .dwb_fi_phase = -1, // -1 = disable, 934 .dmub_command_table = true, 935 .pstate_enabled = true, 936 .use_max_lb = true, 937 .pstate_enabled = true, 938 .enable_mem_low_power = { 939 .bits = { 940 .vga = false, 941 .i2c = false, 942 .dmcu = false, // This is previously known to cause hang on S3 cycles if enabled 943 .dscl = false, 944 .cm = false, 945 .mpc = false, 946 .optc = false, 947 } 948 }, 949 .optimize_edp_link_rate = true, 950 .enable_sw_cntl_psr = true, 951 }; 952 953 static const struct dc_debug_options debug_defaults_diags = { 954 .disable_dmcu = true, 955 .force_abm_enable = false, 956 .timing_trace = true, 957 .clock_trace = true, 958 .disable_dpp_power_gate = true, 959 .disable_hubp_power_gate = true, 960 .disable_clock_gate = true, 961 .disable_pplib_clock_request = true, 962 .disable_pplib_wm_range = true, 963 .disable_stutter = false, 964 .scl_reset_length10 = true, 965 .dwb_fi_phase = -1, // -1 = disable 966 .dmub_command_table = true, 967 .enable_tri_buf = true, 968 .use_max_lb = true 969 }; 970 971 static void dcn31_dpp_destroy(struct dpp **dpp) 972 { 973 kfree(TO_DCN20_DPP(*dpp)); 974 *dpp = NULL; 975 } 976 977 static struct dpp *dcn31_dpp_create( 978 struct dc_context *ctx, 979 uint32_t inst) 980 { 981 struct dcn3_dpp *dpp = 982 kzalloc(sizeof(struct dcn3_dpp), GFP_KERNEL); 983 984 if (!dpp) 985 return NULL; 986 987 if (dpp3_construct(dpp, ctx, inst, 988 &dpp_regs[inst], &tf_shift, &tf_mask)) 989 return &dpp->base; 990 991 BREAK_TO_DEBUGGER(); 992 kfree(dpp); 993 return NULL; 994 } 995 996 static struct output_pixel_processor *dcn31_opp_create( 997 struct dc_context *ctx, uint32_t inst) 998 { 999 struct dcn20_opp *opp = 1000 kzalloc(sizeof(struct dcn20_opp), GFP_KERNEL); 1001 1002 if (!opp) { 1003 BREAK_TO_DEBUGGER(); 1004 return NULL; 1005 } 1006 1007 dcn20_opp_construct(opp, ctx, inst, 1008 &opp_regs[inst], &opp_shift, &opp_mask); 1009 return &opp->base; 1010 } 1011 1012 static struct dce_aux *dcn31_aux_engine_create( 1013 struct dc_context *ctx, 1014 uint32_t inst) 1015 { 1016 struct aux_engine_dce110 *aux_engine = 1017 kzalloc(sizeof(struct aux_engine_dce110), GFP_KERNEL); 1018 1019 if (!aux_engine) 1020 return NULL; 1021 1022 dce110_aux_engine_construct(aux_engine, ctx, inst, 1023 SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD, 1024 &aux_engine_regs[inst], 1025 &aux_mask, 1026 &aux_shift, 1027 ctx->dc->caps.extended_aux_timeout_support); 1028 1029 return &aux_engine->base; 1030 } 1031 #define i2c_inst_regs(id) { I2C_HW_ENGINE_COMMON_REG_LIST_DCN30(id) } 1032 1033 static const struct dce_i2c_registers i2c_hw_regs[] = { 1034 i2c_inst_regs(1), 1035 i2c_inst_regs(2), 1036 i2c_inst_regs(3), 1037 i2c_inst_regs(4), 1038 i2c_inst_regs(5), 1039 }; 1040 1041 static const struct dce_i2c_shift i2c_shifts = { 1042 I2C_COMMON_MASK_SH_LIST_DCN30(__SHIFT) 1043 }; 1044 1045 static const struct dce_i2c_mask i2c_masks = { 1046 I2C_COMMON_MASK_SH_LIST_DCN30(_MASK) 1047 }; 1048 1049 static struct dce_i2c_hw *dcn31_i2c_hw_create( 1050 struct dc_context *ctx, 1051 uint32_t inst) 1052 { 1053 struct dce_i2c_hw *dce_i2c_hw = 1054 kzalloc(sizeof(struct dce_i2c_hw), GFP_KERNEL); 1055 1056 if (!dce_i2c_hw) 1057 return NULL; 1058 1059 dcn2_i2c_hw_construct(dce_i2c_hw, ctx, inst, 1060 &i2c_hw_regs[inst], &i2c_shifts, &i2c_masks); 1061 1062 return dce_i2c_hw; 1063 } 1064 static struct mpc *dcn31_mpc_create( 1065 struct dc_context *ctx, 1066 int num_mpcc, 1067 int num_rmu) 1068 { 1069 struct dcn30_mpc *mpc30 = kzalloc(sizeof(struct dcn30_mpc), 1070 GFP_KERNEL); 1071 1072 if (!mpc30) 1073 return NULL; 1074 1075 dcn30_mpc_construct(mpc30, ctx, 1076 &mpc_regs, 1077 &mpc_shift, 1078 &mpc_mask, 1079 num_mpcc, 1080 num_rmu); 1081 1082 return &mpc30->base; 1083 } 1084 1085 static struct hubbub *dcn31_hubbub_create(struct dc_context *ctx) 1086 { 1087 int i; 1088 1089 struct dcn20_hubbub *hubbub3 = kzalloc(sizeof(struct dcn20_hubbub), 1090 GFP_KERNEL); 1091 1092 if (!hubbub3) 1093 return NULL; 1094 1095 hubbub31_construct(hubbub3, ctx, 1096 &hubbub_reg, 1097 &hubbub_shift, 1098 &hubbub_mask, 1099 dcn3_1_ip.det_buffer_size_kbytes, 1100 dcn3_1_ip.pixel_chunk_size_kbytes, 1101 dcn3_1_ip.config_return_buffer_size_in_kbytes); 1102 1103 1104 for (i = 0; i < res_cap_dcn31.num_vmid; i++) { 1105 struct dcn20_vmid *vmid = &hubbub3->vmid[i]; 1106 1107 vmid->ctx = ctx; 1108 1109 vmid->regs = &vmid_regs[i]; 1110 vmid->shifts = &vmid_shifts; 1111 vmid->masks = &vmid_masks; 1112 } 1113 1114 return &hubbub3->base; 1115 } 1116 1117 static struct timing_generator *dcn31_timing_generator_create( 1118 struct dc_context *ctx, 1119 uint32_t instance) 1120 { 1121 struct optc *tgn10 = 1122 kzalloc(sizeof(struct optc), GFP_KERNEL); 1123 1124 if (!tgn10) 1125 return NULL; 1126 1127 tgn10->base.inst = instance; 1128 tgn10->base.ctx = ctx; 1129 1130 tgn10->tg_regs = &optc_regs[instance]; 1131 tgn10->tg_shift = &optc_shift; 1132 tgn10->tg_mask = &optc_mask; 1133 1134 dcn31_timing_generator_init(tgn10); 1135 1136 return &tgn10->base; 1137 } 1138 1139 static const struct encoder_feature_support link_enc_feature = { 1140 .max_hdmi_deep_color = COLOR_DEPTH_121212, 1141 .max_hdmi_pixel_clock = 600000, 1142 .hdmi_ycbcr420_supported = true, 1143 .dp_ycbcr420_supported = true, 1144 .fec_supported = true, 1145 .flags.bits.IS_HBR2_CAPABLE = true, 1146 .flags.bits.IS_HBR3_CAPABLE = true, 1147 .flags.bits.IS_TPS3_CAPABLE = true, 1148 .flags.bits.IS_TPS4_CAPABLE = true 1149 }; 1150 1151 static struct link_encoder *dcn31_link_encoder_create( 1152 const struct encoder_init_data *enc_init_data) 1153 { 1154 struct dcn20_link_encoder *enc20 = 1155 kzalloc(sizeof(struct dcn20_link_encoder), GFP_KERNEL); 1156 1157 if (!enc20) 1158 return NULL; 1159 1160 dcn31_link_encoder_construct(enc20, 1161 enc_init_data, 1162 &link_enc_feature, 1163 &link_enc_regs[enc_init_data->transmitter], 1164 &link_enc_aux_regs[enc_init_data->channel - 1], 1165 &link_enc_hpd_regs[enc_init_data->hpd_source], 1166 &le_shift, 1167 &le_mask); 1168 1169 return &enc20->enc10.base; 1170 } 1171 1172 /* Create a minimal link encoder object not associated with a particular 1173 * physical connector. 1174 * resource_funcs.link_enc_create_minimal 1175 */ 1176 static struct link_encoder *dcn31_link_enc_create_minimal( 1177 struct dc_context *ctx, enum engine_id eng_id) 1178 { 1179 struct dcn20_link_encoder *enc20; 1180 1181 if ((eng_id - ENGINE_ID_DIGA) > ctx->dc->res_pool->res_cap->num_dig_link_enc) 1182 return NULL; 1183 1184 enc20 = kzalloc(sizeof(struct dcn20_link_encoder), GFP_KERNEL); 1185 if (!enc20) 1186 return NULL; 1187 1188 dcn31_link_encoder_construct_minimal( 1189 enc20, 1190 ctx, 1191 &link_enc_feature, 1192 &link_enc_regs[eng_id - ENGINE_ID_DIGA], 1193 eng_id); 1194 1195 return &enc20->enc10.base; 1196 } 1197 1198 struct panel_cntl *dcn31_panel_cntl_create(const struct panel_cntl_init_data *init_data) 1199 { 1200 struct dcn31_panel_cntl *panel_cntl = 1201 kzalloc(sizeof(struct dcn31_panel_cntl), GFP_KERNEL); 1202 1203 if (!panel_cntl) 1204 return NULL; 1205 1206 dcn31_panel_cntl_construct(panel_cntl, init_data); 1207 1208 return &panel_cntl->base; 1209 } 1210 1211 static void read_dce_straps( 1212 struct dc_context *ctx, 1213 struct resource_straps *straps) 1214 { 1215 generic_reg_get(ctx, regDC_PINSTRAPS + BASE(regDC_PINSTRAPS_BASE_IDX), 1216 FN(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO), &straps->dc_pinstraps_audio); 1217 1218 } 1219 1220 static struct audio *dcn31_create_audio( 1221 struct dc_context *ctx, unsigned int inst) 1222 { 1223 return dce_audio_create(ctx, inst, 1224 &audio_regs[inst], &audio_shift, &audio_mask); 1225 } 1226 1227 static struct vpg *dcn31_vpg_create( 1228 struct dc_context *ctx, 1229 uint32_t inst) 1230 { 1231 struct dcn30_vpg *vpg3 = kzalloc(sizeof(struct dcn30_vpg), GFP_KERNEL); 1232 1233 if (!vpg3) 1234 return NULL; 1235 1236 vpg3_construct(vpg3, ctx, inst, 1237 &vpg_regs[inst], 1238 &vpg_shift, 1239 &vpg_mask); 1240 1241 return &vpg3->base; 1242 } 1243 1244 static struct afmt *dcn31_afmt_create( 1245 struct dc_context *ctx, 1246 uint32_t inst) 1247 { 1248 struct dcn30_afmt *afmt3 = kzalloc(sizeof(struct dcn30_afmt), GFP_KERNEL); 1249 1250 if (!afmt3) 1251 return NULL; 1252 1253 afmt3_construct(afmt3, ctx, inst, 1254 &afmt_regs[inst], 1255 &afmt_shift, 1256 &afmt_mask); 1257 1258 return &afmt3->base; 1259 } 1260 1261 static struct stream_encoder *dcn31_stream_encoder_create( 1262 enum engine_id eng_id, 1263 struct dc_context *ctx) 1264 { 1265 struct dcn10_stream_encoder *enc1; 1266 struct vpg *vpg; 1267 struct afmt *afmt; 1268 int vpg_inst; 1269 int afmt_inst; 1270 1271 /* Mapping of VPG, AFMT, DME register blocks to DIO block instance */ 1272 if (eng_id <= ENGINE_ID_DIGF) { 1273 vpg_inst = eng_id; 1274 afmt_inst = eng_id; 1275 } else 1276 return NULL; 1277 1278 enc1 = kzalloc(sizeof(struct dcn10_stream_encoder), GFP_KERNEL); 1279 vpg = dcn31_vpg_create(ctx, vpg_inst); 1280 afmt = dcn31_afmt_create(ctx, afmt_inst); 1281 1282 if (!enc1 || !vpg || !afmt) 1283 return NULL; 1284 1285 dcn30_dio_stream_encoder_construct(enc1, ctx, ctx->dc_bios, 1286 eng_id, vpg, afmt, 1287 &stream_enc_regs[eng_id], 1288 &se_shift, &se_mask); 1289 1290 return &enc1->base; 1291 } 1292 1293 static struct dce_hwseq *dcn31_hwseq_create( 1294 struct dc_context *ctx) 1295 { 1296 struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_KERNEL); 1297 1298 if (hws) { 1299 hws->ctx = ctx; 1300 hws->regs = &hwseq_reg; 1301 hws->shifts = &hwseq_shift; 1302 hws->masks = &hwseq_mask; 1303 } 1304 return hws; 1305 } 1306 static const struct resource_create_funcs res_create_funcs = { 1307 .read_dce_straps = read_dce_straps, 1308 .create_audio = dcn31_create_audio, 1309 .create_stream_encoder = dcn31_stream_encoder_create, 1310 .create_hwseq = dcn31_hwseq_create, 1311 }; 1312 1313 static const struct resource_create_funcs res_create_maximus_funcs = { 1314 .read_dce_straps = NULL, 1315 .create_audio = NULL, 1316 .create_stream_encoder = NULL, 1317 .create_hwseq = dcn31_hwseq_create, 1318 }; 1319 1320 static void dcn31_resource_destruct(struct dcn31_resource_pool *pool) 1321 { 1322 unsigned int i; 1323 1324 for (i = 0; i < pool->base.stream_enc_count; i++) { 1325 if (pool->base.stream_enc[i] != NULL) { 1326 if (pool->base.stream_enc[i]->vpg != NULL) { 1327 kfree(DCN30_VPG_FROM_VPG(pool->base.stream_enc[i]->vpg)); 1328 pool->base.stream_enc[i]->vpg = NULL; 1329 } 1330 if (pool->base.stream_enc[i]->afmt != NULL) { 1331 kfree(DCN30_AFMT_FROM_AFMT(pool->base.stream_enc[i]->afmt)); 1332 pool->base.stream_enc[i]->afmt = NULL; 1333 } 1334 kfree(DCN10STRENC_FROM_STRENC(pool->base.stream_enc[i])); 1335 pool->base.stream_enc[i] = NULL; 1336 } 1337 } 1338 1339 for (i = 0; i < pool->base.res_cap->num_dsc; i++) { 1340 if (pool->base.dscs[i] != NULL) 1341 dcn20_dsc_destroy(&pool->base.dscs[i]); 1342 } 1343 1344 if (pool->base.mpc != NULL) { 1345 kfree(TO_DCN20_MPC(pool->base.mpc)); 1346 pool->base.mpc = NULL; 1347 } 1348 if (pool->base.hubbub != NULL) { 1349 kfree(pool->base.hubbub); 1350 pool->base.hubbub = NULL; 1351 } 1352 for (i = 0; i < pool->base.pipe_count; i++) { 1353 if (pool->base.dpps[i] != NULL) 1354 dcn31_dpp_destroy(&pool->base.dpps[i]); 1355 1356 if (pool->base.ipps[i] != NULL) 1357 pool->base.ipps[i]->funcs->ipp_destroy(&pool->base.ipps[i]); 1358 1359 if (pool->base.hubps[i] != NULL) { 1360 kfree(TO_DCN20_HUBP(pool->base.hubps[i])); 1361 pool->base.hubps[i] = NULL; 1362 } 1363 1364 if (pool->base.irqs != NULL) { 1365 dal_irq_service_destroy(&pool->base.irqs); 1366 } 1367 } 1368 1369 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { 1370 if (pool->base.engines[i] != NULL) 1371 dce110_engine_destroy(&pool->base.engines[i]); 1372 if (pool->base.hw_i2cs[i] != NULL) { 1373 kfree(pool->base.hw_i2cs[i]); 1374 pool->base.hw_i2cs[i] = NULL; 1375 } 1376 if (pool->base.sw_i2cs[i] != NULL) { 1377 kfree(pool->base.sw_i2cs[i]); 1378 pool->base.sw_i2cs[i] = NULL; 1379 } 1380 } 1381 1382 for (i = 0; i < pool->base.res_cap->num_opp; i++) { 1383 if (pool->base.opps[i] != NULL) 1384 pool->base.opps[i]->funcs->opp_destroy(&pool->base.opps[i]); 1385 } 1386 1387 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { 1388 if (pool->base.timing_generators[i] != NULL) { 1389 kfree(DCN10TG_FROM_TG(pool->base.timing_generators[i])); 1390 pool->base.timing_generators[i] = NULL; 1391 } 1392 } 1393 1394 for (i = 0; i < pool->base.res_cap->num_dwb; i++) { 1395 if (pool->base.dwbc[i] != NULL) { 1396 kfree(TO_DCN30_DWBC(pool->base.dwbc[i])); 1397 pool->base.dwbc[i] = NULL; 1398 } 1399 if (pool->base.mcif_wb[i] != NULL) { 1400 kfree(TO_DCN30_MMHUBBUB(pool->base.mcif_wb[i])); 1401 pool->base.mcif_wb[i] = NULL; 1402 } 1403 } 1404 1405 for (i = 0; i < pool->base.audio_count; i++) { 1406 if (pool->base.audios[i]) 1407 dce_aud_destroy(&pool->base.audios[i]); 1408 } 1409 1410 for (i = 0; i < pool->base.clk_src_count; i++) { 1411 if (pool->base.clock_sources[i] != NULL) { 1412 dcn20_clock_source_destroy(&pool->base.clock_sources[i]); 1413 pool->base.clock_sources[i] = NULL; 1414 } 1415 } 1416 1417 for (i = 0; i < pool->base.res_cap->num_mpc_3dlut; i++) { 1418 if (pool->base.mpc_lut[i] != NULL) { 1419 dc_3dlut_func_release(pool->base.mpc_lut[i]); 1420 pool->base.mpc_lut[i] = NULL; 1421 } 1422 if (pool->base.mpc_shaper[i] != NULL) { 1423 dc_transfer_func_release(pool->base.mpc_shaper[i]); 1424 pool->base.mpc_shaper[i] = NULL; 1425 } 1426 } 1427 1428 if (pool->base.dp_clock_source != NULL) { 1429 dcn20_clock_source_destroy(&pool->base.dp_clock_source); 1430 pool->base.dp_clock_source = NULL; 1431 } 1432 1433 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { 1434 if (pool->base.multiple_abms[i] != NULL) 1435 dce_abm_destroy(&pool->base.multiple_abms[i]); 1436 } 1437 1438 if (pool->base.psr != NULL) 1439 dmub_psr_destroy(&pool->base.psr); 1440 1441 if (pool->base.dccg != NULL) 1442 dcn_dccg_destroy(&pool->base.dccg); 1443 } 1444 1445 static struct hubp *dcn31_hubp_create( 1446 struct dc_context *ctx, 1447 uint32_t inst) 1448 { 1449 struct dcn20_hubp *hubp2 = 1450 kzalloc(sizeof(struct dcn20_hubp), GFP_KERNEL); 1451 1452 if (!hubp2) 1453 return NULL; 1454 1455 if (hubp31_construct(hubp2, ctx, inst, 1456 &hubp_regs[inst], &hubp_shift, &hubp_mask)) 1457 return &hubp2->base; 1458 1459 BREAK_TO_DEBUGGER(); 1460 kfree(hubp2); 1461 return NULL; 1462 } 1463 1464 static bool dcn31_dwbc_create(struct dc_context *ctx, struct resource_pool *pool) 1465 { 1466 int i; 1467 uint32_t pipe_count = pool->res_cap->num_dwb; 1468 1469 for (i = 0; i < pipe_count; i++) { 1470 struct dcn30_dwbc *dwbc30 = kzalloc(sizeof(struct dcn30_dwbc), 1471 GFP_KERNEL); 1472 1473 if (!dwbc30) { 1474 dm_error("DC: failed to create dwbc30!\n"); 1475 return false; 1476 } 1477 1478 dcn30_dwbc_construct(dwbc30, ctx, 1479 &dwbc30_regs[i], 1480 &dwbc30_shift, 1481 &dwbc30_mask, 1482 i); 1483 1484 pool->dwbc[i] = &dwbc30->base; 1485 } 1486 return true; 1487 } 1488 1489 static bool dcn31_mmhubbub_create(struct dc_context *ctx, struct resource_pool *pool) 1490 { 1491 int i; 1492 uint32_t pipe_count = pool->res_cap->num_dwb; 1493 1494 for (i = 0; i < pipe_count; i++) { 1495 struct dcn30_mmhubbub *mcif_wb30 = kzalloc(sizeof(struct dcn30_mmhubbub), 1496 GFP_KERNEL); 1497 1498 if (!mcif_wb30) { 1499 dm_error("DC: failed to create mcif_wb30!\n"); 1500 return false; 1501 } 1502 1503 dcn30_mmhubbub_construct(mcif_wb30, ctx, 1504 &mcif_wb30_regs[i], 1505 &mcif_wb30_shift, 1506 &mcif_wb30_mask, 1507 i); 1508 1509 pool->mcif_wb[i] = &mcif_wb30->base; 1510 } 1511 return true; 1512 } 1513 1514 static struct display_stream_compressor *dcn31_dsc_create( 1515 struct dc_context *ctx, uint32_t inst) 1516 { 1517 struct dcn20_dsc *dsc = 1518 kzalloc(sizeof(struct dcn20_dsc), GFP_KERNEL); 1519 1520 if (!dsc) { 1521 BREAK_TO_DEBUGGER(); 1522 return NULL; 1523 } 1524 1525 dsc2_construct(dsc, ctx, inst, &dsc_regs[inst], &dsc_shift, &dsc_mask); 1526 return &dsc->base; 1527 } 1528 1529 static void dcn31_destroy_resource_pool(struct resource_pool **pool) 1530 { 1531 struct dcn31_resource_pool *dcn31_pool = TO_DCN31_RES_POOL(*pool); 1532 1533 dcn31_resource_destruct(dcn31_pool); 1534 kfree(dcn31_pool); 1535 *pool = NULL; 1536 } 1537 1538 static struct clock_source *dcn31_clock_source_create( 1539 struct dc_context *ctx, 1540 struct dc_bios *bios, 1541 enum clock_source_id id, 1542 const struct dce110_clk_src_regs *regs, 1543 bool dp_clk_src) 1544 { 1545 struct dce110_clk_src *clk_src = 1546 kzalloc(sizeof(struct dce110_clk_src), GFP_KERNEL); 1547 1548 if (!clk_src) 1549 return NULL; 1550 1551 if (dcn3_clk_src_construct(clk_src, ctx, bios, id, 1552 regs, &cs_shift, &cs_mask)) { 1553 clk_src->base.dp_clk_src = dp_clk_src; 1554 return &clk_src->base; 1555 } 1556 1557 BREAK_TO_DEBUGGER(); 1558 return NULL; 1559 } 1560 1561 static bool is_dual_plane(enum surface_pixel_format format) 1562 { 1563 return format >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN || format == SURFACE_PIXEL_FORMAT_GRPH_RGBE_ALPHA; 1564 } 1565 1566 static int dcn31_populate_dml_pipes_from_context( 1567 struct dc *dc, struct dc_state *context, 1568 display_e2e_pipe_params_st *pipes, 1569 bool fast_validate) 1570 { 1571 int i, pipe_cnt; 1572 struct resource_context *res_ctx = &context->res_ctx; 1573 struct pipe_ctx *pipe; 1574 1575 dcn20_populate_dml_pipes_from_context(dc, context, pipes, fast_validate); 1576 1577 for (i = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) { 1578 struct dc_crtc_timing *timing; 1579 1580 if (!res_ctx->pipe_ctx[i].stream) 1581 continue; 1582 pipe = &res_ctx->pipe_ctx[i]; 1583 timing = &pipe->stream->timing; 1584 1585 pipes[pipe_cnt].pipe.src.unbounded_req_mode = false; 1586 pipes[pipe_cnt].pipe.src.gpuvm = true; 1587 pipes[pipe_cnt].pipe.src.dcc_fraction_of_zs_req_luma = 0; 1588 pipes[pipe_cnt].pipe.src.dcc_fraction_of_zs_req_chroma = 0; 1589 pipes[pipe_cnt].pipe.dest.vfront_porch = timing->v_front_porch; 1590 pipes[pipe_cnt].pipe.src.dcc_rate = 3; 1591 pipes[pipe_cnt].dout.dsc_input_bpc = 0; 1592 1593 if (pipes[pipe_cnt].dout.dsc_enable) { 1594 switch (timing->display_color_depth) { 1595 case COLOR_DEPTH_888: 1596 pipes[pipe_cnt].dout.dsc_input_bpc = 8; 1597 break; 1598 case COLOR_DEPTH_101010: 1599 pipes[pipe_cnt].dout.dsc_input_bpc = 10; 1600 break; 1601 case COLOR_DEPTH_121212: 1602 pipes[pipe_cnt].dout.dsc_input_bpc = 12; 1603 break; 1604 default: 1605 ASSERT(0); 1606 break; 1607 } 1608 } 1609 1610 pipe_cnt++; 1611 } 1612 context->bw_ctx.dml.ip.det_buffer_size_kbytes = DCN3_1_DEFAULT_DET_SIZE; 1613 dc->config.enable_4to1MPC = false; 1614 if (pipe_cnt == 1 && pipe->plane_state && !dc->debug.disable_z9_mpc) { 1615 if (is_dual_plane(pipe->plane_state->format) 1616 && pipe->plane_state->src_rect.width <= 1920 && pipe->plane_state->src_rect.height <= 1080) { 1617 dc->config.enable_4to1MPC = true; 1618 } else if (!is_dual_plane(pipe->plane_state->format)) { 1619 context->bw_ctx.dml.ip.det_buffer_size_kbytes = 192; 1620 pipes[0].pipe.src.unbounded_req_mode = true; 1621 } 1622 } 1623 1624 return pipe_cnt; 1625 } 1626 1627 static void dcn31_update_soc_for_wm_a(struct dc *dc, struct dc_state *context) 1628 { 1629 if (dc->clk_mgr->bw_params->wm_table.entries[WM_A].valid) { 1630 context->bw_ctx.dml.soc.dram_clock_change_latency_us = dc->clk_mgr->bw_params->wm_table.entries[WM_A].pstate_latency_us; 1631 context->bw_ctx.dml.soc.sr_enter_plus_exit_time_us = dc->clk_mgr->bw_params->wm_table.entries[WM_A].sr_enter_plus_exit_time_us; 1632 context->bw_ctx.dml.soc.sr_exit_time_us = dc->clk_mgr->bw_params->wm_table.entries[WM_A].sr_exit_time_us; 1633 } 1634 } 1635 1636 static void dcn31_calculate_wm_and_dlg_fp( 1637 struct dc *dc, struct dc_state *context, 1638 display_e2e_pipe_params_st *pipes, 1639 int pipe_cnt, 1640 int vlevel) 1641 { 1642 int i, pipe_idx; 1643 double dcfclk = context->bw_ctx.dml.vba.DCFCLKState[vlevel][context->bw_ctx.dml.vba.maxMpcComb]; 1644 1645 if (context->bw_ctx.dml.soc.min_dcfclk > dcfclk) 1646 dcfclk = context->bw_ctx.dml.soc.min_dcfclk; 1647 1648 pipes[0].clks_cfg.voltage = vlevel; 1649 pipes[0].clks_cfg.dcfclk_mhz = dcfclk; 1650 pipes[0].clks_cfg.socclk_mhz = context->bw_ctx.dml.soc.clock_limits[vlevel].socclk_mhz; 1651 1652 #if 0 // TODO 1653 /* Set B: 1654 * TODO 1655 */ 1656 if (dc->clk_mgr->bw_params->wm_table.nv_entries[WM_B].valid) { 1657 if (vlevel == 0) { 1658 pipes[0].clks_cfg.voltage = 1; 1659 pipes[0].clks_cfg.dcfclk_mhz = context->bw_ctx.dml.soc.clock_limits[0].dcfclk_mhz; 1660 } 1661 context->bw_ctx.dml.soc.dram_clock_change_latency_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_B].dml_input.pstate_latency_us; 1662 context->bw_ctx.dml.soc.sr_enter_plus_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_B].dml_input.sr_enter_plus_exit_time_us; 1663 context->bw_ctx.dml.soc.sr_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_B].dml_input.sr_exit_time_us; 1664 } 1665 context->bw_ctx.bw.dcn.watermarks.b.urgent_ns = get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 1666 context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 1667 context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 1668 context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.cstate_enter_plus_exit_z8_ns = get_wm_z8_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 1669 context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.cstate_exit_z8_ns = get_wm_z8_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 1670 context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 1671 context->bw_ctx.bw.dcn.watermarks.b.pte_meta_urgent_ns = get_wm_memory_trip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 1672 context->bw_ctx.bw.dcn.watermarks.b.frac_urg_bw_nom = get_fraction_of_urgent_bandwidth(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 1673 context->bw_ctx.bw.dcn.watermarks.b.frac_urg_bw_flip = get_fraction_of_urgent_bandwidth_imm_flip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 1674 context->bw_ctx.bw.dcn.watermarks.b.urgent_latency_ns = get_urgent_latency(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 1675 1676 pipes[0].clks_cfg.voltage = vlevel; 1677 pipes[0].clks_cfg.dcfclk_mhz = dcfclk; 1678 1679 /* Set C: 1680 * TODO 1681 */ 1682 if (dc->clk_mgr->bw_params->wm_table.nv_entries[WM_C].valid) { 1683 context->bw_ctx.dml.soc.dram_clock_change_latency_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_C].dml_input.pstate_latency_us; 1684 context->bw_ctx.dml.soc.sr_enter_plus_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_C].dml_input.sr_enter_plus_exit_time_us; 1685 context->bw_ctx.dml.soc.sr_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_C].dml_input.sr_exit_time_us; 1686 } 1687 context->bw_ctx.bw.dcn.watermarks.c.urgent_ns = get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 1688 context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 1689 context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 1690 context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.cstate_enter_plus_exit_z8_ns = get_wm_z8_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 1691 context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.cstate_exit_z8_ns = get_wm_z8_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 1692 context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 1693 context->bw_ctx.bw.dcn.watermarks.c.pte_meta_urgent_ns = get_wm_memory_trip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 1694 context->bw_ctx.bw.dcn.watermarks.c.frac_urg_bw_nom = get_fraction_of_urgent_bandwidth(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 1695 context->bw_ctx.bw.dcn.watermarks.c.frac_urg_bw_flip = get_fraction_of_urgent_bandwidth_imm_flip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 1696 context->bw_ctx.bw.dcn.watermarks.c.urgent_latency_ns = get_urgent_latency(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 1697 1698 /* Set D: 1699 * TODO 1700 */ 1701 if (dc->clk_mgr->bw_params->wm_table.nv_entries[WM_D].valid) { 1702 context->bw_ctx.dml.soc.dram_clock_change_latency_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_D].dml_input.pstate_latency_us; 1703 context->bw_ctx.dml.soc.sr_enter_plus_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_D].dml_input.sr_enter_plus_exit_time_us; 1704 context->bw_ctx.dml.soc.sr_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_D].dml_input.sr_exit_time_us; 1705 } 1706 context->bw_ctx.bw.dcn.watermarks.d.urgent_ns = get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 1707 context->bw_ctx.bw.dcn.watermarks.d.cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 1708 context->bw_ctx.bw.dcn.watermarks.d.cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 1709 context->bw_ctx.bw.dcn.watermarks.d.cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 1710 context->bw_ctx.bw.dcn.watermarks.d.cstate_pstate.cstate_enter_plus_exit_z8_ns = get_wm_z8_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 1711 context->bw_ctx.bw.dcn.watermarks.d.cstate_pstate.cstate_exit_z8_ns = get_wm_z8_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 1712 context->bw_ctx.bw.dcn.watermarks.d.pte_meta_urgent_ns = get_wm_memory_trip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 1713 context->bw_ctx.bw.dcn.watermarks.d.frac_urg_bw_nom = get_fraction_of_urgent_bandwidth(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 1714 context->bw_ctx.bw.dcn.watermarks.d.frac_urg_bw_flip = get_fraction_of_urgent_bandwidth_imm_flip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 1715 context->bw_ctx.bw.dcn.watermarks.d.urgent_latency_ns = get_urgent_latency(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 1716 #endif 1717 1718 /* Set A: 1719 * All clocks min required 1720 * 1721 * Set A calculated last so that following calculations are based on Set A 1722 */ 1723 dc->res_pool->funcs->update_soc_for_wm_a(dc, context); 1724 context->bw_ctx.bw.dcn.watermarks.a.urgent_ns = get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 1725 context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 1726 context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 1727 context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 1728 context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.cstate_enter_plus_exit_z8_ns = get_wm_z8_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 1729 context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.cstate_exit_z8_ns = get_wm_z8_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 1730 context->bw_ctx.bw.dcn.watermarks.a.pte_meta_urgent_ns = get_wm_memory_trip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 1731 context->bw_ctx.bw.dcn.watermarks.a.frac_urg_bw_nom = get_fraction_of_urgent_bandwidth(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 1732 context->bw_ctx.bw.dcn.watermarks.a.frac_urg_bw_flip = get_fraction_of_urgent_bandwidth_imm_flip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 1733 context->bw_ctx.bw.dcn.watermarks.a.urgent_latency_ns = get_urgent_latency(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 1734 /* TODO: remove: */ 1735 context->bw_ctx.bw.dcn.watermarks.b = context->bw_ctx.bw.dcn.watermarks.a; 1736 context->bw_ctx.bw.dcn.watermarks.c = context->bw_ctx.bw.dcn.watermarks.a; 1737 context->bw_ctx.bw.dcn.watermarks.d = context->bw_ctx.bw.dcn.watermarks.a; 1738 /* end remove*/ 1739 1740 for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) { 1741 if (!context->res_ctx.pipe_ctx[i].stream) 1742 continue; 1743 1744 pipes[pipe_idx].clks_cfg.dispclk_mhz = get_dispclk_calculated(&context->bw_ctx.dml, pipes, pipe_cnt); 1745 pipes[pipe_idx].clks_cfg.dppclk_mhz = get_dppclk_calculated(&context->bw_ctx.dml, pipes, pipe_cnt, pipe_idx); 1746 1747 if (dc->config.forced_clocks) { 1748 pipes[pipe_idx].clks_cfg.dispclk_mhz = context->bw_ctx.dml.soc.clock_limits[0].dispclk_mhz; 1749 pipes[pipe_idx].clks_cfg.dppclk_mhz = context->bw_ctx.dml.soc.clock_limits[0].dppclk_mhz; 1750 } 1751 if (dc->debug.min_disp_clk_khz > pipes[pipe_idx].clks_cfg.dispclk_mhz * 1000) 1752 pipes[pipe_idx].clks_cfg.dispclk_mhz = dc->debug.min_disp_clk_khz / 1000.0; 1753 if (dc->debug.min_dpp_clk_khz > pipes[pipe_idx].clks_cfg.dppclk_mhz * 1000) 1754 pipes[pipe_idx].clks_cfg.dppclk_mhz = dc->debug.min_dpp_clk_khz / 1000.0; 1755 1756 pipe_idx++; 1757 } 1758 1759 dcn20_calculate_dlg_params(dc, context, pipes, pipe_cnt, vlevel); 1760 } 1761 1762 static void dcn31_calculate_wm_and_dlg( 1763 struct dc *dc, struct dc_state *context, 1764 display_e2e_pipe_params_st *pipes, 1765 int pipe_cnt, 1766 int vlevel) 1767 { 1768 DC_FP_START(); 1769 dcn31_calculate_wm_and_dlg_fp(dc, context, pipes, pipe_cnt, vlevel); 1770 DC_FP_END(); 1771 } 1772 1773 static struct dc_cap_funcs cap_funcs = { 1774 .get_dcc_compression_cap = dcn20_get_dcc_compression_cap 1775 }; 1776 1777 static void dcn31_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params) 1778 { 1779 struct clk_limit_table *clk_table = &bw_params->clk_table; 1780 struct _vcs_dpi_voltage_scaling_st clock_limits[DC__VOLTAGE_STATES]; 1781 unsigned int i, closest_clk_lvl; 1782 int j; 1783 1784 // Default clock levels are used for diags, which may lead to overclocking. 1785 if (!IS_DIAG_DC(dc->ctx->dce_environment)) { 1786 int max_dispclk_mhz = 0, max_dppclk_mhz = 0; 1787 1788 dcn3_1_ip.max_num_otg = dc->res_pool->res_cap->num_timing_generator; 1789 dcn3_1_ip.max_num_dpp = dc->res_pool->pipe_count; 1790 dcn3_1_soc.num_chans = bw_params->num_channels; 1791 1792 ASSERT(clk_table->num_entries); 1793 1794 /* Prepass to find max clocks independent of voltage level. */ 1795 for (i = 0; i < clk_table->num_entries; ++i) { 1796 if (clk_table->entries[i].dispclk_mhz > max_dispclk_mhz) 1797 max_dispclk_mhz = clk_table->entries[i].dispclk_mhz; 1798 if (clk_table->entries[i].dppclk_mhz > max_dppclk_mhz) 1799 max_dppclk_mhz = clk_table->entries[i].dppclk_mhz; 1800 } 1801 1802 for (i = 0; i < clk_table->num_entries; i++) { 1803 /* loop backwards*/ 1804 for (closest_clk_lvl = 0, j = dcn3_1_soc.num_states - 1; j >= 0; j--) { 1805 if ((unsigned int) dcn3_1_soc.clock_limits[j].dcfclk_mhz <= clk_table->entries[i].dcfclk_mhz) { 1806 closest_clk_lvl = j; 1807 break; 1808 } 1809 } 1810 1811 clock_limits[i].state = i; 1812 1813 /* Clocks dependent on voltage level. */ 1814 clock_limits[i].dcfclk_mhz = clk_table->entries[i].dcfclk_mhz; 1815 clock_limits[i].fabricclk_mhz = clk_table->entries[i].fclk_mhz; 1816 clock_limits[i].socclk_mhz = clk_table->entries[i].socclk_mhz; 1817 clock_limits[i].dram_speed_mts = clk_table->entries[i].memclk_mhz * 2 * clk_table->entries[i].wck_ratio; 1818 1819 /* Clocks independent of voltage level. */ 1820 clock_limits[i].dispclk_mhz = max_dispclk_mhz ? max_dispclk_mhz : 1821 dcn3_1_soc.clock_limits[closest_clk_lvl].dispclk_mhz; 1822 1823 clock_limits[i].dppclk_mhz = max_dppclk_mhz ? max_dppclk_mhz : 1824 dcn3_1_soc.clock_limits[closest_clk_lvl].dppclk_mhz; 1825 1826 clock_limits[i].dram_bw_per_chan_gbps = dcn3_1_soc.clock_limits[closest_clk_lvl].dram_bw_per_chan_gbps; 1827 clock_limits[i].dscclk_mhz = dcn3_1_soc.clock_limits[closest_clk_lvl].dscclk_mhz; 1828 clock_limits[i].dtbclk_mhz = dcn3_1_soc.clock_limits[closest_clk_lvl].dtbclk_mhz; 1829 clock_limits[i].phyclk_d18_mhz = dcn3_1_soc.clock_limits[closest_clk_lvl].phyclk_d18_mhz; 1830 clock_limits[i].phyclk_mhz = dcn3_1_soc.clock_limits[closest_clk_lvl].phyclk_mhz; 1831 } 1832 for (i = 0; i < clk_table->num_entries; i++) 1833 dcn3_1_soc.clock_limits[i] = clock_limits[i]; 1834 if (clk_table->num_entries) { 1835 dcn3_1_soc.num_states = clk_table->num_entries; 1836 } 1837 } 1838 1839 dcn3_1_soc.dispclk_dppclk_vco_speed_mhz = dc->clk_mgr->dentist_vco_freq_khz / 1000.0; 1840 dc->dml.soc.dispclk_dppclk_vco_speed_mhz = dc->clk_mgr->dentist_vco_freq_khz / 1000.0; 1841 1842 if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) 1843 dml_init_instance(&dc->dml, &dcn3_1_soc, &dcn3_1_ip, DML_PROJECT_DCN31); 1844 else 1845 dml_init_instance(&dc->dml, &dcn3_1_soc, &dcn3_1_ip, DML_PROJECT_DCN31_FPGA); 1846 } 1847 1848 static struct resource_funcs dcn31_res_pool_funcs = { 1849 .destroy = dcn31_destroy_resource_pool, 1850 .link_enc_create = dcn31_link_encoder_create, 1851 .link_enc_create_minimal = dcn31_link_enc_create_minimal, 1852 .link_encs_assign = link_enc_cfg_link_encs_assign, 1853 .link_enc_unassign = link_enc_cfg_link_enc_unassign, 1854 .panel_cntl_create = dcn31_panel_cntl_create, 1855 .validate_bandwidth = dcn30_validate_bandwidth, 1856 .calculate_wm_and_dlg = dcn31_calculate_wm_and_dlg, 1857 .update_soc_for_wm_a = dcn31_update_soc_for_wm_a, 1858 .populate_dml_pipes = dcn31_populate_dml_pipes_from_context, 1859 .acquire_idle_pipe_for_layer = dcn20_acquire_idle_pipe_for_layer, 1860 .add_stream_to_ctx = dcn30_add_stream_to_ctx, 1861 .add_dsc_to_stream_resource = dcn20_add_dsc_to_stream_resource, 1862 .remove_stream_from_ctx = dcn20_remove_stream_from_ctx, 1863 .populate_dml_writeback_from_context = dcn30_populate_dml_writeback_from_context, 1864 .set_mcif_arb_params = dcn30_set_mcif_arb_params, 1865 .find_first_free_match_stream_enc_for_link = dcn10_find_first_free_match_stream_enc_for_link, 1866 .acquire_post_bldn_3dlut = dcn30_acquire_post_bldn_3dlut, 1867 .release_post_bldn_3dlut = dcn30_release_post_bldn_3dlut, 1868 .update_bw_bounding_box = dcn31_update_bw_bounding_box, 1869 .patch_unknown_plane_state = dcn20_patch_unknown_plane_state, 1870 }; 1871 1872 static struct clock_source *dcn30_clock_source_create( 1873 struct dc_context *ctx, 1874 struct dc_bios *bios, 1875 enum clock_source_id id, 1876 const struct dce110_clk_src_regs *regs, 1877 bool dp_clk_src) 1878 { 1879 struct dce110_clk_src *clk_src = 1880 kzalloc(sizeof(struct dce110_clk_src), GFP_KERNEL); 1881 1882 if (!clk_src) 1883 return NULL; 1884 1885 if (dcn3_clk_src_construct(clk_src, ctx, bios, id, 1886 regs, &cs_shift, &cs_mask)) { 1887 clk_src->base.dp_clk_src = dp_clk_src; 1888 return &clk_src->base; 1889 } 1890 1891 BREAK_TO_DEBUGGER(); 1892 return NULL; 1893 } 1894 1895 static bool dcn31_resource_construct( 1896 uint8_t num_virtual_links, 1897 struct dc *dc, 1898 struct dcn31_resource_pool *pool) 1899 { 1900 int i; 1901 struct dc_context *ctx = dc->ctx; 1902 struct irq_service_init_data init_data; 1903 1904 DC_FP_START(); 1905 1906 ctx->dc_bios->regs = &bios_regs; 1907 1908 pool->base.res_cap = &res_cap_dcn31; 1909 1910 pool->base.funcs = &dcn31_res_pool_funcs; 1911 1912 /************************************************* 1913 * Resource + asic cap harcoding * 1914 *************************************************/ 1915 pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE; 1916 pool->base.pipe_count = pool->base.res_cap->num_timing_generator; 1917 pool->base.mpcc_count = pool->base.res_cap->num_timing_generator; 1918 dc->caps.max_downscale_ratio = 600; 1919 dc->caps.i2c_speed_in_khz = 100; 1920 dc->caps.i2c_speed_in_khz_hdcp = 5; /*1.4 w/a applied by default*/ 1921 dc->caps.max_cursor_size = 256; 1922 dc->caps.min_horizontal_blanking_period = 80; 1923 dc->caps.dmdata_alloc_size = 2048; 1924 1925 dc->caps.max_slave_planes = 1; 1926 dc->caps.max_slave_yuv_planes = 1; 1927 dc->caps.max_slave_rgb_planes = 1; 1928 dc->caps.post_blend_color_processing = true; 1929 dc->caps.force_dp_tps4_for_cp2520 = true; 1930 dc->caps.extended_aux_timeout_support = true; 1931 dc->caps.dmcub_support = true; 1932 dc->caps.is_apu = true; 1933 1934 /* Color pipeline capabilities */ 1935 dc->caps.color.dpp.dcn_arch = 1; 1936 dc->caps.color.dpp.input_lut_shared = 0; 1937 dc->caps.color.dpp.icsc = 1; 1938 dc->caps.color.dpp.dgam_ram = 0; // must use gamma_corr 1939 dc->caps.color.dpp.dgam_rom_caps.srgb = 1; 1940 dc->caps.color.dpp.dgam_rom_caps.bt2020 = 1; 1941 dc->caps.color.dpp.dgam_rom_caps.gamma2_2 = 1; 1942 dc->caps.color.dpp.dgam_rom_caps.pq = 1; 1943 dc->caps.color.dpp.dgam_rom_caps.hlg = 1; 1944 dc->caps.color.dpp.post_csc = 1; 1945 dc->caps.color.dpp.gamma_corr = 1; 1946 dc->caps.color.dpp.dgam_rom_for_yuv = 0; 1947 1948 dc->caps.color.dpp.hw_3d_lut = 1; 1949 dc->caps.color.dpp.ogam_ram = 1; 1950 // no OGAM ROM on DCN301 1951 dc->caps.color.dpp.ogam_rom_caps.srgb = 0; 1952 dc->caps.color.dpp.ogam_rom_caps.bt2020 = 0; 1953 dc->caps.color.dpp.ogam_rom_caps.gamma2_2 = 0; 1954 dc->caps.color.dpp.ogam_rom_caps.pq = 0; 1955 dc->caps.color.dpp.ogam_rom_caps.hlg = 0; 1956 dc->caps.color.dpp.ocsc = 0; 1957 1958 dc->caps.color.mpc.gamut_remap = 1; 1959 dc->caps.color.mpc.num_3dluts = pool->base.res_cap->num_mpc_3dlut; //2 1960 dc->caps.color.mpc.ogam_ram = 1; 1961 dc->caps.color.mpc.ogam_rom_caps.srgb = 0; 1962 dc->caps.color.mpc.ogam_rom_caps.bt2020 = 0; 1963 dc->caps.color.mpc.ogam_rom_caps.gamma2_2 = 0; 1964 dc->caps.color.mpc.ogam_rom_caps.pq = 0; 1965 dc->caps.color.mpc.ogam_rom_caps.hlg = 0; 1966 dc->caps.color.mpc.ocsc = 1; 1967 1968 if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV) 1969 dc->debug = debug_defaults_drv; 1970 else if (dc->ctx->dce_environment == DCE_ENV_FPGA_MAXIMUS) { 1971 dc->debug = debug_defaults_diags; 1972 } else 1973 dc->debug = debug_defaults_diags; 1974 // Init the vm_helper 1975 if (dc->vm_helper) 1976 vm_helper_init(dc->vm_helper, 16); 1977 1978 /************************************************* 1979 * Create resources * 1980 *************************************************/ 1981 1982 /* Clock Sources for Pixel Clock*/ 1983 pool->base.clock_sources[DCN31_CLK_SRC_PLL0] = 1984 dcn30_clock_source_create(ctx, ctx->dc_bios, 1985 CLOCK_SOURCE_COMBO_PHY_PLL0, 1986 &clk_src_regs[0], false); 1987 pool->base.clock_sources[DCN31_CLK_SRC_PLL1] = 1988 dcn30_clock_source_create(ctx, ctx->dc_bios, 1989 CLOCK_SOURCE_COMBO_PHY_PLL1, 1990 &clk_src_regs[1], false); 1991 pool->base.clock_sources[DCN31_CLK_SRC_PLL2] = 1992 dcn30_clock_source_create(ctx, ctx->dc_bios, 1993 CLOCK_SOURCE_COMBO_PHY_PLL2, 1994 &clk_src_regs[2], false); 1995 pool->base.clock_sources[DCN31_CLK_SRC_PLL3] = 1996 dcn30_clock_source_create(ctx, ctx->dc_bios, 1997 CLOCK_SOURCE_COMBO_PHY_PLL3, 1998 &clk_src_regs[3], false); 1999 pool->base.clock_sources[DCN31_CLK_SRC_PLL4] = 2000 dcn30_clock_source_create(ctx, ctx->dc_bios, 2001 CLOCK_SOURCE_COMBO_PHY_PLL4, 2002 &clk_src_regs[4], false); 2003 2004 pool->base.clk_src_count = DCN30_CLK_SRC_TOTAL; 2005 2006 /* todo: not reuse phy_pll registers */ 2007 pool->base.dp_clock_source = 2008 dcn31_clock_source_create(ctx, ctx->dc_bios, 2009 CLOCK_SOURCE_ID_DP_DTO, 2010 &clk_src_regs[0], true); 2011 2012 for (i = 0; i < pool->base.clk_src_count; i++) { 2013 if (pool->base.clock_sources[i] == NULL) { 2014 dm_error("DC: failed to create clock sources!\n"); 2015 BREAK_TO_DEBUGGER(); 2016 goto create_fail; 2017 } 2018 } 2019 2020 /* TODO: DCCG */ 2021 pool->base.dccg = dccg31_create(ctx, &dccg_regs, &dccg_shift, &dccg_mask); 2022 if (pool->base.dccg == NULL) { 2023 dm_error("DC: failed to create dccg!\n"); 2024 BREAK_TO_DEBUGGER(); 2025 goto create_fail; 2026 } 2027 2028 /* TODO: IRQ */ 2029 init_data.ctx = dc->ctx; 2030 pool->base.irqs = dal_irq_service_dcn31_create(&init_data); 2031 if (!pool->base.irqs) 2032 goto create_fail; 2033 2034 /* HUBBUB */ 2035 pool->base.hubbub = dcn31_hubbub_create(ctx); 2036 if (pool->base.hubbub == NULL) { 2037 BREAK_TO_DEBUGGER(); 2038 dm_error("DC: failed to create hubbub!\n"); 2039 goto create_fail; 2040 } 2041 2042 /* HUBPs, DPPs, OPPs and TGs */ 2043 for (i = 0; i < pool->base.pipe_count; i++) { 2044 pool->base.hubps[i] = dcn31_hubp_create(ctx, i); 2045 if (pool->base.hubps[i] == NULL) { 2046 BREAK_TO_DEBUGGER(); 2047 dm_error( 2048 "DC: failed to create hubps!\n"); 2049 goto create_fail; 2050 } 2051 2052 pool->base.dpps[i] = dcn31_dpp_create(ctx, i); 2053 if (pool->base.dpps[i] == NULL) { 2054 BREAK_TO_DEBUGGER(); 2055 dm_error( 2056 "DC: failed to create dpps!\n"); 2057 goto create_fail; 2058 } 2059 } 2060 2061 for (i = 0; i < pool->base.res_cap->num_opp; i++) { 2062 pool->base.opps[i] = dcn31_opp_create(ctx, i); 2063 if (pool->base.opps[i] == NULL) { 2064 BREAK_TO_DEBUGGER(); 2065 dm_error( 2066 "DC: failed to create output pixel processor!\n"); 2067 goto create_fail; 2068 } 2069 } 2070 2071 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { 2072 pool->base.timing_generators[i] = dcn31_timing_generator_create( 2073 ctx, i); 2074 if (pool->base.timing_generators[i] == NULL) { 2075 BREAK_TO_DEBUGGER(); 2076 dm_error("DC: failed to create tg!\n"); 2077 goto create_fail; 2078 } 2079 } 2080 pool->base.timing_generator_count = i; 2081 2082 /* PSR */ 2083 pool->base.psr = dmub_psr_create(ctx); 2084 if (pool->base.psr == NULL) { 2085 dm_error("DC: failed to create psr obj!\n"); 2086 BREAK_TO_DEBUGGER(); 2087 goto create_fail; 2088 } 2089 2090 /* ABM */ 2091 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { 2092 pool->base.multiple_abms[i] = dmub_abm_create(ctx, 2093 &abm_regs[i], 2094 &abm_shift, 2095 &abm_mask); 2096 if (pool->base.multiple_abms[i] == NULL) { 2097 dm_error("DC: failed to create abm for pipe %d!\n", i); 2098 BREAK_TO_DEBUGGER(); 2099 goto create_fail; 2100 } 2101 } 2102 2103 /* MPC and DSC */ 2104 pool->base.mpc = dcn31_mpc_create(ctx, pool->base.mpcc_count, pool->base.res_cap->num_mpc_3dlut); 2105 if (pool->base.mpc == NULL) { 2106 BREAK_TO_DEBUGGER(); 2107 dm_error("DC: failed to create mpc!\n"); 2108 goto create_fail; 2109 } 2110 2111 for (i = 0; i < pool->base.res_cap->num_dsc; i++) { 2112 pool->base.dscs[i] = dcn31_dsc_create(ctx, i); 2113 if (pool->base.dscs[i] == NULL) { 2114 BREAK_TO_DEBUGGER(); 2115 dm_error("DC: failed to create display stream compressor %d!\n", i); 2116 goto create_fail; 2117 } 2118 } 2119 2120 /* DWB and MMHUBBUB */ 2121 if (!dcn31_dwbc_create(ctx, &pool->base)) { 2122 BREAK_TO_DEBUGGER(); 2123 dm_error("DC: failed to create dwbc!\n"); 2124 goto create_fail; 2125 } 2126 2127 if (!dcn31_mmhubbub_create(ctx, &pool->base)) { 2128 BREAK_TO_DEBUGGER(); 2129 dm_error("DC: failed to create mcif_wb!\n"); 2130 goto create_fail; 2131 } 2132 2133 /* AUX and I2C */ 2134 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { 2135 pool->base.engines[i] = dcn31_aux_engine_create(ctx, i); 2136 if (pool->base.engines[i] == NULL) { 2137 BREAK_TO_DEBUGGER(); 2138 dm_error( 2139 "DC:failed to create aux engine!!\n"); 2140 goto create_fail; 2141 } 2142 pool->base.hw_i2cs[i] = dcn31_i2c_hw_create(ctx, i); 2143 if (pool->base.hw_i2cs[i] == NULL) { 2144 BREAK_TO_DEBUGGER(); 2145 dm_error( 2146 "DC:failed to create hw i2c!!\n"); 2147 goto create_fail; 2148 } 2149 pool->base.sw_i2cs[i] = NULL; 2150 } 2151 2152 /* Audio, Stream Encoders including HPO and virtual, MPC 3D LUTs */ 2153 if (!resource_construct(num_virtual_links, dc, &pool->base, 2154 (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment) ? 2155 &res_create_funcs : &res_create_maximus_funcs))) 2156 goto create_fail; 2157 2158 /* HW Sequencer and Plane caps */ 2159 dcn31_hw_sequencer_construct(dc); 2160 2161 dc->caps.max_planes = pool->base.pipe_count; 2162 2163 for (i = 0; i < dc->caps.max_planes; ++i) 2164 dc->caps.planes[i] = plane_cap; 2165 2166 dc->cap_funcs = cap_funcs; 2167 2168 DC_FP_END(); 2169 2170 return true; 2171 2172 create_fail: 2173 2174 DC_FP_END(); 2175 dcn31_resource_destruct(pool); 2176 2177 return false; 2178 } 2179 2180 struct resource_pool *dcn31_create_resource_pool( 2181 const struct dc_init_data *init_data, 2182 struct dc *dc) 2183 { 2184 struct dcn31_resource_pool *pool = 2185 kzalloc(sizeof(struct dcn31_resource_pool), GFP_KERNEL); 2186 2187 if (!pool) 2188 return NULL; 2189 2190 if (dcn31_resource_construct(init_data->num_virtual_links, dc, pool)) 2191 return &pool->base; 2192 2193 BREAK_TO_DEBUGGER(); 2194 kfree(pool); 2195 return NULL; 2196 } 2197