1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 27 #include "dm_services.h" 28 #include "dc.h" 29 30 #include "dcn31/dcn31_init.h" 31 32 #include "resource.h" 33 #include "include/irq_service_interface.h" 34 #include "dcn31_resource.h" 35 36 #include "dcn20/dcn20_resource.h" 37 #include "dcn30/dcn30_resource.h" 38 39 #include "dcn10/dcn10_ipp.h" 40 #include "dcn30/dcn30_hubbub.h" 41 #include "dcn31/dcn31_hubbub.h" 42 #include "dcn30/dcn30_mpc.h" 43 #include "dcn31/dcn31_hubp.h" 44 #include "irq/dcn31/irq_service_dcn31.h" 45 #include "dcn30/dcn30_dpp.h" 46 #include "dcn31/dcn31_optc.h" 47 #include "dcn20/dcn20_hwseq.h" 48 #include "dcn30/dcn30_hwseq.h" 49 #include "dce110/dce110_hw_sequencer.h" 50 #include "dcn30/dcn30_opp.h" 51 #include "dcn20/dcn20_dsc.h" 52 #include "dcn30/dcn30_vpg.h" 53 #include "dcn30/dcn30_afmt.h" 54 #include "dcn30/dcn30_dio_stream_encoder.h" 55 #include "dcn31/dcn31_hpo_dp_stream_encoder.h" 56 #include "dcn31/dcn31_hpo_dp_link_encoder.h" 57 #include "dcn31/dcn31_apg.h" 58 #include "dcn31/dcn31_dio_link_encoder.h" 59 #include "dcn31/dcn31_vpg.h" 60 #include "dcn31/dcn31_afmt.h" 61 #include "dce/dce_clock_source.h" 62 #include "dce/dce_audio.h" 63 #include "dce/dce_hwseq.h" 64 #include "clk_mgr.h" 65 #include "virtual/virtual_stream_encoder.h" 66 #include "dce110/dce110_resource.h" 67 #include "dml/display_mode_vba.h" 68 #include "dcn31/dcn31_dccg.h" 69 #include "dcn10/dcn10_resource.h" 70 #include "dcn31_panel_cntl.h" 71 72 #include "dcn30/dcn30_dwb.h" 73 #include "dcn30/dcn30_mmhubbub.h" 74 75 // TODO: change include headers /amd/include/asic_reg after upstream 76 #include "yellow_carp_offset.h" 77 #include "dcn/dcn_3_1_2_offset.h" 78 #include "dcn/dcn_3_1_2_sh_mask.h" 79 #include "nbio/nbio_7_2_0_offset.h" 80 #include "dpcs/dpcs_4_2_0_offset.h" 81 #include "dpcs/dpcs_4_2_0_sh_mask.h" 82 #include "mmhub/mmhub_2_3_0_offset.h" 83 #include "mmhub/mmhub_2_3_0_sh_mask.h" 84 85 86 #define regDCHUBBUB_DEBUG_CTRL_0 0x04d6 87 #define regDCHUBBUB_DEBUG_CTRL_0_BASE_IDX 2 88 #define DCHUBBUB_DEBUG_CTRL_0__DET_DEPTH__SHIFT 0x10 89 #define DCHUBBUB_DEBUG_CTRL_0__DET_DEPTH_MASK 0x01FF0000L 90 91 #include "reg_helper.h" 92 #include "dce/dmub_abm.h" 93 #include "dce/dmub_psr.h" 94 #include "dce/dce_aux.h" 95 #include "dce/dce_i2c.h" 96 97 #include "dml/dcn30/display_mode_vba_30.h" 98 #include "vm_helper.h" 99 #include "dcn20/dcn20_vmid.h" 100 101 #include "link_enc_cfg.h" 102 103 #define DC_LOGGER_INIT(logger) 104 105 #define DCN3_1_DEFAULT_DET_SIZE 384 106 107 struct _vcs_dpi_ip_params_st dcn3_1_ip = { 108 .gpuvm_enable = 1, 109 .gpuvm_max_page_table_levels = 1, 110 .hostvm_enable = 1, 111 .hostvm_max_page_table_levels = 2, 112 .rob_buffer_size_kbytes = 64, 113 .det_buffer_size_kbytes = DCN3_1_DEFAULT_DET_SIZE, 114 .config_return_buffer_size_in_kbytes = 1792, 115 .compressed_buffer_segment_size_in_kbytes = 64, 116 .meta_fifo_size_in_kentries = 32, 117 .zero_size_buffer_entries = 512, 118 .compbuf_reserved_space_64b = 256, 119 .compbuf_reserved_space_zs = 64, 120 .dpp_output_buffer_pixels = 2560, 121 .opp_output_buffer_lines = 1, 122 .pixel_chunk_size_kbytes = 8, 123 .meta_chunk_size_kbytes = 2, 124 .min_meta_chunk_size_bytes = 256, 125 .writeback_chunk_size_kbytes = 8, 126 .ptoi_supported = false, 127 .num_dsc = 3, 128 .maximum_dsc_bits_per_component = 10, 129 .dsc422_native_support = false, 130 .is_line_buffer_bpp_fixed = true, 131 .line_buffer_fixed_bpp = 48, 132 .line_buffer_size_bits = 789504, 133 .max_line_buffer_lines = 12, 134 .writeback_interface_buffer_size_kbytes = 90, 135 .max_num_dpp = 4, 136 .max_num_otg = 4, 137 .max_num_hdmi_frl_outputs = 1, 138 .max_num_wb = 1, 139 .max_dchub_pscl_bw_pix_per_clk = 4, 140 .max_pscl_lb_bw_pix_per_clk = 2, 141 .max_lb_vscl_bw_pix_per_clk = 4, 142 .max_vscl_hscl_bw_pix_per_clk = 4, 143 .max_hscl_ratio = 6, 144 .max_vscl_ratio = 6, 145 .max_hscl_taps = 8, 146 .max_vscl_taps = 8, 147 .dpte_buffer_size_in_pte_reqs_luma = 64, 148 .dpte_buffer_size_in_pte_reqs_chroma = 34, 149 .dispclk_ramp_margin_percent = 1, 150 .max_inter_dcn_tile_repeaters = 8, 151 .cursor_buffer_size = 16, 152 .cursor_chunk_size = 2, 153 .writeback_line_buffer_buffer_size = 0, 154 .writeback_min_hscl_ratio = 1, 155 .writeback_min_vscl_ratio = 1, 156 .writeback_max_hscl_ratio = 1, 157 .writeback_max_vscl_ratio = 1, 158 .writeback_max_hscl_taps = 1, 159 .writeback_max_vscl_taps = 1, 160 .dppclk_delay_subtotal = 46, 161 .dppclk_delay_scl = 50, 162 .dppclk_delay_scl_lb_only = 16, 163 .dppclk_delay_cnvc_formatter = 27, 164 .dppclk_delay_cnvc_cursor = 6, 165 .dispclk_delay_subtotal = 119, 166 .dynamic_metadata_vm_enabled = false, 167 .odm_combine_4to1_supported = false, 168 .dcc_supported = true, 169 }; 170 171 struct _vcs_dpi_soc_bounding_box_st dcn3_1_soc = { 172 /*TODO: correct dispclk/dppclk voltage level determination*/ 173 .clock_limits = { 174 { 175 .state = 0, 176 .dispclk_mhz = 1200.0, 177 .dppclk_mhz = 1200.0, 178 .phyclk_mhz = 600.0, 179 .phyclk_d18_mhz = 667.0, 180 .dscclk_mhz = 186.0, 181 .dtbclk_mhz = 625.0, 182 }, 183 { 184 .state = 1, 185 .dispclk_mhz = 1200.0, 186 .dppclk_mhz = 1200.0, 187 .phyclk_mhz = 810.0, 188 .phyclk_d18_mhz = 667.0, 189 .dscclk_mhz = 209.0, 190 .dtbclk_mhz = 625.0, 191 }, 192 { 193 .state = 2, 194 .dispclk_mhz = 1200.0, 195 .dppclk_mhz = 1200.0, 196 .phyclk_mhz = 810.0, 197 .phyclk_d18_mhz = 667.0, 198 .dscclk_mhz = 209.0, 199 .dtbclk_mhz = 625.0, 200 }, 201 { 202 .state = 3, 203 .dispclk_mhz = 1200.0, 204 .dppclk_mhz = 1200.0, 205 .phyclk_mhz = 810.0, 206 .phyclk_d18_mhz = 667.0, 207 .dscclk_mhz = 371.0, 208 .dtbclk_mhz = 625.0, 209 }, 210 { 211 .state = 4, 212 .dispclk_mhz = 1200.0, 213 .dppclk_mhz = 1200.0, 214 .phyclk_mhz = 810.0, 215 .phyclk_d18_mhz = 667.0, 216 .dscclk_mhz = 417.0, 217 .dtbclk_mhz = 625.0, 218 }, 219 }, 220 .num_states = 5, 221 .sr_exit_time_us = 9.0, 222 .sr_enter_plus_exit_time_us = 11.0, 223 .sr_exit_z8_time_us = 442.0, 224 .sr_enter_plus_exit_z8_time_us = 560.0, 225 .writeback_latency_us = 12.0, 226 .dram_channel_width_bytes = 4, 227 .round_trip_ping_latency_dcfclk_cycles = 106, 228 .urgent_latency_pixel_data_only_us = 4.0, 229 .urgent_latency_pixel_mixed_with_vm_data_us = 4.0, 230 .urgent_latency_vm_data_only_us = 4.0, 231 .urgent_out_of_order_return_per_channel_pixel_only_bytes = 4096, 232 .urgent_out_of_order_return_per_channel_pixel_and_vm_bytes = 4096, 233 .urgent_out_of_order_return_per_channel_vm_only_bytes = 4096, 234 .pct_ideal_sdp_bw_after_urgent = 80.0, 235 .pct_ideal_dram_sdp_bw_after_urgent_pixel_only = 65.0, 236 .pct_ideal_dram_sdp_bw_after_urgent_pixel_and_vm = 60.0, 237 .pct_ideal_dram_sdp_bw_after_urgent_vm_only = 30.0, 238 .max_avg_sdp_bw_use_normal_percent = 60.0, 239 .max_avg_dram_bw_use_normal_percent = 60.0, 240 .fabric_datapath_to_dcn_data_return_bytes = 32, 241 .return_bus_width_bytes = 64, 242 .downspread_percent = 0.38, 243 .dcn_downspread_percent = 0.5, 244 .gpuvm_min_page_size_bytes = 4096, 245 .hostvm_min_page_size_bytes = 4096, 246 .do_urgent_latency_adjustment = false, 247 .urgent_latency_adjustment_fabric_clock_component_us = 0, 248 .urgent_latency_adjustment_fabric_clock_reference_mhz = 0, 249 }; 250 251 enum dcn31_clk_src_array_id { 252 DCN31_CLK_SRC_PLL0, 253 DCN31_CLK_SRC_PLL1, 254 DCN31_CLK_SRC_PLL2, 255 DCN31_CLK_SRC_PLL3, 256 DCN31_CLK_SRC_PLL4, 257 DCN30_CLK_SRC_TOTAL 258 }; 259 260 /* begin ********************* 261 * macros to expend register list macro defined in HW object header file 262 */ 263 264 /* DCN */ 265 /* TODO awful hack. fixup dcn20_dwb.h */ 266 #undef BASE_INNER 267 #define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg 268 269 #define BASE(seg) BASE_INNER(seg) 270 271 #define SR(reg_name)\ 272 .reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \ 273 reg ## reg_name 274 275 #define SRI(reg_name, block, id)\ 276 .reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 277 reg ## block ## id ## _ ## reg_name 278 279 #define SRI2(reg_name, block, id)\ 280 .reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \ 281 reg ## reg_name 282 283 #define SRIR(var_name, reg_name, block, id)\ 284 .var_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 285 reg ## block ## id ## _ ## reg_name 286 287 #define SRII(reg_name, block, id)\ 288 .reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 289 reg ## block ## id ## _ ## reg_name 290 291 #define SRII_MPC_RMU(reg_name, block, id)\ 292 .RMU##_##reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 293 reg ## block ## id ## _ ## reg_name 294 295 #define SRII_DWB(reg_name, temp_name, block, id)\ 296 .reg_name[id] = BASE(reg ## block ## id ## _ ## temp_name ## _BASE_IDX) + \ 297 reg ## block ## id ## _ ## temp_name 298 299 #define DCCG_SRII(reg_name, block, id)\ 300 .block ## _ ## reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 301 reg ## block ## id ## _ ## reg_name 302 303 #define VUPDATE_SRII(reg_name, block, id)\ 304 .reg_name[id] = BASE(reg ## reg_name ## _ ## block ## id ## _BASE_IDX) + \ 305 reg ## reg_name ## _ ## block ## id 306 307 /* NBIO */ 308 #define NBIO_BASE_INNER(seg) \ 309 NBIO_BASE__INST0_SEG ## seg 310 311 #define NBIO_BASE(seg) \ 312 NBIO_BASE_INNER(seg) 313 314 #define NBIO_SR(reg_name)\ 315 .reg_name = NBIO_BASE(regBIF_BX1_ ## reg_name ## _BASE_IDX) + \ 316 regBIF_BX1_ ## reg_name 317 318 /* MMHUB */ 319 #define MMHUB_BASE_INNER(seg) \ 320 MMHUB_BASE__INST0_SEG ## seg 321 322 #define MMHUB_BASE(seg) \ 323 MMHUB_BASE_INNER(seg) 324 325 #define MMHUB_SR(reg_name)\ 326 .reg_name = MMHUB_BASE(mm ## reg_name ## _BASE_IDX) + \ 327 mm ## reg_name 328 329 /* CLOCK */ 330 #define CLK_BASE_INNER(seg) \ 331 CLK_BASE__INST0_SEG ## seg 332 333 #define CLK_BASE(seg) \ 334 CLK_BASE_INNER(seg) 335 336 #define CLK_SRI(reg_name, block, inst)\ 337 .reg_name = CLK_BASE(reg ## block ## _ ## inst ## _ ## reg_name ## _BASE_IDX) + \ 338 reg ## block ## _ ## inst ## _ ## reg_name 339 340 341 static const struct bios_registers bios_regs = { 342 NBIO_SR(BIOS_SCRATCH_3), 343 NBIO_SR(BIOS_SCRATCH_6) 344 }; 345 346 #define clk_src_regs(index, pllid)\ 347 [index] = {\ 348 CS_COMMON_REG_LIST_DCN3_0(index, pllid),\ 349 } 350 351 static const struct dce110_clk_src_regs clk_src_regs[] = { 352 clk_src_regs(0, A), 353 clk_src_regs(1, B), 354 clk_src_regs(2, C), 355 clk_src_regs(3, D), 356 clk_src_regs(4, E) 357 }; 358 /*pll_id being rempped in dmub, in driver it is logical instance*/ 359 static const struct dce110_clk_src_regs clk_src_regs_b0[] = { 360 clk_src_regs(0, A), 361 clk_src_regs(1, B), 362 clk_src_regs(2, F), 363 clk_src_regs(3, G), 364 clk_src_regs(4, E) 365 }; 366 367 static const struct dce110_clk_src_shift cs_shift = { 368 CS_COMMON_MASK_SH_LIST_DCN2_0(__SHIFT) 369 }; 370 371 static const struct dce110_clk_src_mask cs_mask = { 372 CS_COMMON_MASK_SH_LIST_DCN2_0(_MASK) 373 }; 374 375 #define abm_regs(id)\ 376 [id] = {\ 377 ABM_DCN302_REG_LIST(id)\ 378 } 379 380 static const struct dce_abm_registers abm_regs[] = { 381 abm_regs(0), 382 abm_regs(1), 383 abm_regs(2), 384 abm_regs(3), 385 }; 386 387 static const struct dce_abm_shift abm_shift = { 388 ABM_MASK_SH_LIST_DCN30(__SHIFT) 389 }; 390 391 static const struct dce_abm_mask abm_mask = { 392 ABM_MASK_SH_LIST_DCN30(_MASK) 393 }; 394 395 #define audio_regs(id)\ 396 [id] = {\ 397 AUD_COMMON_REG_LIST(id)\ 398 } 399 400 static const struct dce_audio_registers audio_regs[] = { 401 audio_regs(0), 402 audio_regs(1), 403 audio_regs(2), 404 audio_regs(3), 405 audio_regs(4), 406 audio_regs(5), 407 audio_regs(6) 408 }; 409 410 #define DCE120_AUD_COMMON_MASK_SH_LIST(mask_sh)\ 411 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX, AZALIA_ENDPOINT_REG_INDEX, mask_sh),\ 412 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA, AZALIA_ENDPOINT_REG_DATA, mask_sh),\ 413 AUD_COMMON_MASK_SH_LIST_BASE(mask_sh) 414 415 static const struct dce_audio_shift audio_shift = { 416 DCE120_AUD_COMMON_MASK_SH_LIST(__SHIFT) 417 }; 418 419 static const struct dce_audio_mask audio_mask = { 420 DCE120_AUD_COMMON_MASK_SH_LIST(_MASK) 421 }; 422 423 #define vpg_regs(id)\ 424 [id] = {\ 425 VPG_DCN31_REG_LIST(id)\ 426 } 427 428 static const struct dcn31_vpg_registers vpg_regs[] = { 429 vpg_regs(0), 430 vpg_regs(1), 431 vpg_regs(2), 432 vpg_regs(3), 433 vpg_regs(4), 434 vpg_regs(5), 435 vpg_regs(6), 436 vpg_regs(7), 437 vpg_regs(8), 438 vpg_regs(9), 439 }; 440 441 static const struct dcn31_vpg_shift vpg_shift = { 442 DCN31_VPG_MASK_SH_LIST(__SHIFT) 443 }; 444 445 static const struct dcn31_vpg_mask vpg_mask = { 446 DCN31_VPG_MASK_SH_LIST(_MASK) 447 }; 448 449 #define afmt_regs(id)\ 450 [id] = {\ 451 AFMT_DCN31_REG_LIST(id)\ 452 } 453 454 static const struct dcn31_afmt_registers afmt_regs[] = { 455 afmt_regs(0), 456 afmt_regs(1), 457 afmt_regs(2), 458 afmt_regs(3), 459 afmt_regs(4), 460 afmt_regs(5) 461 }; 462 463 static const struct dcn31_afmt_shift afmt_shift = { 464 DCN31_AFMT_MASK_SH_LIST(__SHIFT) 465 }; 466 467 static const struct dcn31_afmt_mask afmt_mask = { 468 DCN31_AFMT_MASK_SH_LIST(_MASK) 469 }; 470 471 #define apg_regs(id)\ 472 [id] = {\ 473 APG_DCN31_REG_LIST(id)\ 474 } 475 476 static const struct dcn31_apg_registers apg_regs[] = { 477 apg_regs(0), 478 apg_regs(1), 479 apg_regs(2), 480 apg_regs(3) 481 }; 482 483 static const struct dcn31_apg_shift apg_shift = { 484 DCN31_APG_MASK_SH_LIST(__SHIFT) 485 }; 486 487 static const struct dcn31_apg_mask apg_mask = { 488 DCN31_APG_MASK_SH_LIST(_MASK) 489 }; 490 491 #define stream_enc_regs(id)\ 492 [id] = {\ 493 SE_DCN3_REG_LIST(id)\ 494 } 495 496 static const struct dcn10_stream_enc_registers stream_enc_regs[] = { 497 stream_enc_regs(0), 498 stream_enc_regs(1), 499 stream_enc_regs(2), 500 stream_enc_regs(3), 501 stream_enc_regs(4) 502 }; 503 504 static const struct dcn10_stream_encoder_shift se_shift = { 505 SE_COMMON_MASK_SH_LIST_DCN30(__SHIFT) 506 }; 507 508 static const struct dcn10_stream_encoder_mask se_mask = { 509 SE_COMMON_MASK_SH_LIST_DCN30(_MASK) 510 }; 511 512 513 #define aux_regs(id)\ 514 [id] = {\ 515 DCN2_AUX_REG_LIST(id)\ 516 } 517 518 static const struct dcn10_link_enc_aux_registers link_enc_aux_regs[] = { 519 aux_regs(0), 520 aux_regs(1), 521 aux_regs(2), 522 aux_regs(3), 523 aux_regs(4) 524 }; 525 526 #define hpd_regs(id)\ 527 [id] = {\ 528 HPD_REG_LIST(id)\ 529 } 530 531 static const struct dcn10_link_enc_hpd_registers link_enc_hpd_regs[] = { 532 hpd_regs(0), 533 hpd_regs(1), 534 hpd_regs(2), 535 hpd_regs(3), 536 hpd_regs(4) 537 }; 538 539 #define link_regs(id, phyid)\ 540 [id] = {\ 541 LE_DCN31_REG_LIST(id), \ 542 UNIPHY_DCN2_REG_LIST(phyid), \ 543 DPCS_DCN31_REG_LIST(id), \ 544 } 545 546 static const struct dce110_aux_registers_shift aux_shift = { 547 DCN_AUX_MASK_SH_LIST(__SHIFT) 548 }; 549 550 static const struct dce110_aux_registers_mask aux_mask = { 551 DCN_AUX_MASK_SH_LIST(_MASK) 552 }; 553 554 static const struct dcn10_link_enc_registers link_enc_regs[] = { 555 link_regs(0, A), 556 link_regs(1, B), 557 link_regs(2, C), 558 link_regs(3, D), 559 link_regs(4, E) 560 }; 561 562 static const struct dcn10_link_enc_shift le_shift = { 563 LINK_ENCODER_MASK_SH_LIST_DCN31(__SHIFT), \ 564 DPCS_DCN31_MASK_SH_LIST(__SHIFT) 565 }; 566 567 static const struct dcn10_link_enc_mask le_mask = { 568 LINK_ENCODER_MASK_SH_LIST_DCN31(_MASK), \ 569 DPCS_DCN31_MASK_SH_LIST(_MASK) 570 }; 571 572 #define hpo_dp_stream_encoder_reg_list(id)\ 573 [id] = {\ 574 DCN3_1_HPO_DP_STREAM_ENC_REG_LIST(id)\ 575 } 576 577 static const struct dcn31_hpo_dp_stream_encoder_registers hpo_dp_stream_enc_regs[] = { 578 hpo_dp_stream_encoder_reg_list(0), 579 hpo_dp_stream_encoder_reg_list(1), 580 hpo_dp_stream_encoder_reg_list(2), 581 hpo_dp_stream_encoder_reg_list(3), 582 }; 583 584 static const struct dcn31_hpo_dp_stream_encoder_shift hpo_dp_se_shift = { 585 DCN3_1_HPO_DP_STREAM_ENC_MASK_SH_LIST(__SHIFT) 586 }; 587 588 static const struct dcn31_hpo_dp_stream_encoder_mask hpo_dp_se_mask = { 589 DCN3_1_HPO_DP_STREAM_ENC_MASK_SH_LIST(_MASK) 590 }; 591 592 #define hpo_dp_link_encoder_reg_list(id)\ 593 [id] = {\ 594 DCN3_1_HPO_DP_LINK_ENC_REG_LIST(id),\ 595 DCN3_1_RDPCSTX_REG_LIST(0),\ 596 DCN3_1_RDPCSTX_REG_LIST(1),\ 597 DCN3_1_RDPCSTX_REG_LIST(2),\ 598 DCN3_1_RDPCSTX_REG_LIST(3),\ 599 DCN3_1_RDPCSTX_REG_LIST(4)\ 600 } 601 602 static const struct dcn31_hpo_dp_link_encoder_registers hpo_dp_link_enc_regs[] = { 603 hpo_dp_link_encoder_reg_list(0), 604 hpo_dp_link_encoder_reg_list(1), 605 }; 606 607 static const struct dcn31_hpo_dp_link_encoder_shift hpo_dp_le_shift = { 608 DCN3_1_HPO_DP_LINK_ENC_MASK_SH_LIST(__SHIFT) 609 }; 610 611 static const struct dcn31_hpo_dp_link_encoder_mask hpo_dp_le_mask = { 612 DCN3_1_HPO_DP_LINK_ENC_MASK_SH_LIST(_MASK) 613 }; 614 615 #define dpp_regs(id)\ 616 [id] = {\ 617 DPP_REG_LIST_DCN30(id),\ 618 } 619 620 static const struct dcn3_dpp_registers dpp_regs[] = { 621 dpp_regs(0), 622 dpp_regs(1), 623 dpp_regs(2), 624 dpp_regs(3) 625 }; 626 627 static const struct dcn3_dpp_shift tf_shift = { 628 DPP_REG_LIST_SH_MASK_DCN30(__SHIFT) 629 }; 630 631 static const struct dcn3_dpp_mask tf_mask = { 632 DPP_REG_LIST_SH_MASK_DCN30(_MASK) 633 }; 634 635 #define opp_regs(id)\ 636 [id] = {\ 637 OPP_REG_LIST_DCN30(id),\ 638 } 639 640 static const struct dcn20_opp_registers opp_regs[] = { 641 opp_regs(0), 642 opp_regs(1), 643 opp_regs(2), 644 opp_regs(3) 645 }; 646 647 static const struct dcn20_opp_shift opp_shift = { 648 OPP_MASK_SH_LIST_DCN20(__SHIFT) 649 }; 650 651 static const struct dcn20_opp_mask opp_mask = { 652 OPP_MASK_SH_LIST_DCN20(_MASK) 653 }; 654 655 #define aux_engine_regs(id)\ 656 [id] = {\ 657 AUX_COMMON_REG_LIST0(id), \ 658 .AUXN_IMPCAL = 0, \ 659 .AUXP_IMPCAL = 0, \ 660 .AUX_RESET_MASK = DP_AUX0_AUX_CONTROL__AUX_RESET_MASK, \ 661 } 662 663 static const struct dce110_aux_registers aux_engine_regs[] = { 664 aux_engine_regs(0), 665 aux_engine_regs(1), 666 aux_engine_regs(2), 667 aux_engine_regs(3), 668 aux_engine_regs(4) 669 }; 670 671 #define dwbc_regs_dcn3(id)\ 672 [id] = {\ 673 DWBC_COMMON_REG_LIST_DCN30(id),\ 674 } 675 676 static const struct dcn30_dwbc_registers dwbc30_regs[] = { 677 dwbc_regs_dcn3(0), 678 }; 679 680 static const struct dcn30_dwbc_shift dwbc30_shift = { 681 DWBC_COMMON_MASK_SH_LIST_DCN30(__SHIFT) 682 }; 683 684 static const struct dcn30_dwbc_mask dwbc30_mask = { 685 DWBC_COMMON_MASK_SH_LIST_DCN30(_MASK) 686 }; 687 688 #define mcif_wb_regs_dcn3(id)\ 689 [id] = {\ 690 MCIF_WB_COMMON_REG_LIST_DCN30(id),\ 691 } 692 693 static const struct dcn30_mmhubbub_registers mcif_wb30_regs[] = { 694 mcif_wb_regs_dcn3(0) 695 }; 696 697 static const struct dcn30_mmhubbub_shift mcif_wb30_shift = { 698 MCIF_WB_COMMON_MASK_SH_LIST_DCN30(__SHIFT) 699 }; 700 701 static const struct dcn30_mmhubbub_mask mcif_wb30_mask = { 702 MCIF_WB_COMMON_MASK_SH_LIST_DCN30(_MASK) 703 }; 704 705 #define dsc_regsDCN20(id)\ 706 [id] = {\ 707 DSC_REG_LIST_DCN20(id)\ 708 } 709 710 static const struct dcn20_dsc_registers dsc_regs[] = { 711 dsc_regsDCN20(0), 712 dsc_regsDCN20(1), 713 dsc_regsDCN20(2) 714 }; 715 716 static const struct dcn20_dsc_shift dsc_shift = { 717 DSC_REG_LIST_SH_MASK_DCN20(__SHIFT) 718 }; 719 720 static const struct dcn20_dsc_mask dsc_mask = { 721 DSC_REG_LIST_SH_MASK_DCN20(_MASK) 722 }; 723 724 static const struct dcn30_mpc_registers mpc_regs = { 725 MPC_REG_LIST_DCN3_0(0), 726 MPC_REG_LIST_DCN3_0(1), 727 MPC_REG_LIST_DCN3_0(2), 728 MPC_REG_LIST_DCN3_0(3), 729 MPC_OUT_MUX_REG_LIST_DCN3_0(0), 730 MPC_OUT_MUX_REG_LIST_DCN3_0(1), 731 MPC_OUT_MUX_REG_LIST_DCN3_0(2), 732 MPC_OUT_MUX_REG_LIST_DCN3_0(3), 733 MPC_RMU_GLOBAL_REG_LIST_DCN3AG, 734 MPC_RMU_REG_LIST_DCN3AG(0), 735 MPC_RMU_REG_LIST_DCN3AG(1), 736 //MPC_RMU_REG_LIST_DCN3AG(2), 737 MPC_DWB_MUX_REG_LIST_DCN3_0(0), 738 }; 739 740 static const struct dcn30_mpc_shift mpc_shift = { 741 MPC_COMMON_MASK_SH_LIST_DCN30(__SHIFT) 742 }; 743 744 static const struct dcn30_mpc_mask mpc_mask = { 745 MPC_COMMON_MASK_SH_LIST_DCN30(_MASK) 746 }; 747 748 #define optc_regs(id)\ 749 [id] = {OPTC_COMMON_REG_LIST_DCN3_1(id)} 750 751 static const struct dcn_optc_registers optc_regs[] = { 752 optc_regs(0), 753 optc_regs(1), 754 optc_regs(2), 755 optc_regs(3) 756 }; 757 758 static const struct dcn_optc_shift optc_shift = { 759 OPTC_COMMON_MASK_SH_LIST_DCN3_1(__SHIFT) 760 }; 761 762 static const struct dcn_optc_mask optc_mask = { 763 OPTC_COMMON_MASK_SH_LIST_DCN3_1(_MASK) 764 }; 765 766 #define hubp_regs(id)\ 767 [id] = {\ 768 HUBP_REG_LIST_DCN30(id)\ 769 } 770 771 static const struct dcn_hubp2_registers hubp_regs[] = { 772 hubp_regs(0), 773 hubp_regs(1), 774 hubp_regs(2), 775 hubp_regs(3) 776 }; 777 778 779 static const struct dcn_hubp2_shift hubp_shift = { 780 HUBP_MASK_SH_LIST_DCN31(__SHIFT) 781 }; 782 783 static const struct dcn_hubp2_mask hubp_mask = { 784 HUBP_MASK_SH_LIST_DCN31(_MASK) 785 }; 786 static const struct dcn_hubbub_registers hubbub_reg = { 787 HUBBUB_REG_LIST_DCN31(0) 788 }; 789 790 static const struct dcn_hubbub_shift hubbub_shift = { 791 HUBBUB_MASK_SH_LIST_DCN31(__SHIFT) 792 }; 793 794 static const struct dcn_hubbub_mask hubbub_mask = { 795 HUBBUB_MASK_SH_LIST_DCN31(_MASK) 796 }; 797 798 static const struct dccg_registers dccg_regs = { 799 DCCG_REG_LIST_DCN31() 800 }; 801 802 static const struct dccg_shift dccg_shift = { 803 DCCG_MASK_SH_LIST_DCN31(__SHIFT) 804 }; 805 806 static const struct dccg_mask dccg_mask = { 807 DCCG_MASK_SH_LIST_DCN31(_MASK) 808 }; 809 810 811 #define SRII2(reg_name_pre, reg_name_post, id)\ 812 .reg_name_pre ## _ ## reg_name_post[id] = BASE(reg ## reg_name_pre \ 813 ## id ## _ ## reg_name_post ## _BASE_IDX) + \ 814 reg ## reg_name_pre ## id ## _ ## reg_name_post 815 816 817 #define HWSEQ_DCN31_REG_LIST()\ 818 SR(DCHUBBUB_GLOBAL_TIMER_CNTL), \ 819 SR(DCHUBBUB_ARB_HOSTVM_CNTL), \ 820 SR(DIO_MEM_PWR_CTRL), \ 821 SR(ODM_MEM_PWR_CTRL3), \ 822 SR(DMU_MEM_PWR_CNTL), \ 823 SR(MMHUBBUB_MEM_PWR_CNTL), \ 824 SR(DCCG_GATE_DISABLE_CNTL), \ 825 SR(DCCG_GATE_DISABLE_CNTL2), \ 826 SR(DCFCLK_CNTL),\ 827 SR(DC_MEM_GLOBAL_PWR_REQ_CNTL), \ 828 SRII(PIXEL_RATE_CNTL, OTG, 0), \ 829 SRII(PIXEL_RATE_CNTL, OTG, 1),\ 830 SRII(PIXEL_RATE_CNTL, OTG, 2),\ 831 SRII(PIXEL_RATE_CNTL, OTG, 3),\ 832 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 0),\ 833 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 1),\ 834 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 2),\ 835 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 3),\ 836 SR(MICROSECOND_TIME_BASE_DIV), \ 837 SR(MILLISECOND_TIME_BASE_DIV), \ 838 SR(DISPCLK_FREQ_CHANGE_CNTL), \ 839 SR(RBBMIF_TIMEOUT_DIS), \ 840 SR(RBBMIF_TIMEOUT_DIS_2), \ 841 SR(DCHUBBUB_CRC_CTRL), \ 842 SR(DPP_TOP0_DPP_CRC_CTRL), \ 843 SR(DPP_TOP0_DPP_CRC_VAL_B_A), \ 844 SR(DPP_TOP0_DPP_CRC_VAL_R_G), \ 845 SR(MPC_CRC_CTRL), \ 846 SR(MPC_CRC_RESULT_GB), \ 847 SR(MPC_CRC_RESULT_C), \ 848 SR(MPC_CRC_RESULT_AR), \ 849 SR(DOMAIN0_PG_CONFIG), \ 850 SR(DOMAIN1_PG_CONFIG), \ 851 SR(DOMAIN2_PG_CONFIG), \ 852 SR(DOMAIN3_PG_CONFIG), \ 853 SR(DOMAIN16_PG_CONFIG), \ 854 SR(DOMAIN17_PG_CONFIG), \ 855 SR(DOMAIN18_PG_CONFIG), \ 856 SR(DOMAIN0_PG_STATUS), \ 857 SR(DOMAIN1_PG_STATUS), \ 858 SR(DOMAIN2_PG_STATUS), \ 859 SR(DOMAIN3_PG_STATUS), \ 860 SR(DOMAIN16_PG_STATUS), \ 861 SR(DOMAIN17_PG_STATUS), \ 862 SR(DOMAIN18_PG_STATUS), \ 863 SR(D1VGA_CONTROL), \ 864 SR(D2VGA_CONTROL), \ 865 SR(D3VGA_CONTROL), \ 866 SR(D4VGA_CONTROL), \ 867 SR(D5VGA_CONTROL), \ 868 SR(D6VGA_CONTROL), \ 869 SR(DC_IP_REQUEST_CNTL), \ 870 SR(AZALIA_AUDIO_DTO), \ 871 SR(AZALIA_CONTROLLER_CLOCK_GATING), \ 872 SR(HPO_TOP_HW_CONTROL) 873 874 static const struct dce_hwseq_registers hwseq_reg = { 875 HWSEQ_DCN31_REG_LIST() 876 }; 877 878 #define HWSEQ_DCN31_MASK_SH_LIST(mask_sh)\ 879 HWSEQ_DCN_MASK_SH_LIST(mask_sh), \ 880 HWS_SF(, DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_REFDIV, mask_sh), \ 881 HWS_SF(, DCHUBBUB_ARB_HOSTVM_CNTL, DISABLE_HOSTVM_FORCE_ALLOW_PSTATE, mask_sh), \ 882 HWS_SF(, DOMAIN0_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ 883 HWS_SF(, DOMAIN0_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ 884 HWS_SF(, DOMAIN1_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ 885 HWS_SF(, DOMAIN1_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ 886 HWS_SF(, DOMAIN2_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ 887 HWS_SF(, DOMAIN2_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ 888 HWS_SF(, DOMAIN3_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ 889 HWS_SF(, DOMAIN3_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ 890 HWS_SF(, DOMAIN16_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ 891 HWS_SF(, DOMAIN16_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ 892 HWS_SF(, DOMAIN17_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ 893 HWS_SF(, DOMAIN17_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ 894 HWS_SF(, DOMAIN18_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ 895 HWS_SF(, DOMAIN18_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ 896 HWS_SF(, DOMAIN0_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ 897 HWS_SF(, DOMAIN1_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ 898 HWS_SF(, DOMAIN2_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ 899 HWS_SF(, DOMAIN3_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ 900 HWS_SF(, DOMAIN16_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ 901 HWS_SF(, DOMAIN17_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ 902 HWS_SF(, DOMAIN18_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ 903 HWS_SF(, DC_IP_REQUEST_CNTL, IP_REQUEST_EN, mask_sh), \ 904 HWS_SF(, AZALIA_AUDIO_DTO, AZALIA_AUDIO_DTO_MODULE, mask_sh), \ 905 HWS_SF(, HPO_TOP_CLOCK_CONTROL, HPO_HDMISTREAMCLK_G_GATE_DIS, mask_sh), \ 906 HWS_SF(, DMU_MEM_PWR_CNTL, DMCU_ERAM_MEM_PWR_FORCE, mask_sh), \ 907 HWS_SF(, ODM_MEM_PWR_CTRL3, ODM_MEM_UNASSIGNED_PWR_MODE, mask_sh), \ 908 HWS_SF(, ODM_MEM_PWR_CTRL3, ODM_MEM_VBLANK_PWR_MODE, mask_sh), \ 909 HWS_SF(, MMHUBBUB_MEM_PWR_CNTL, VGA_MEM_PWR_FORCE, mask_sh), \ 910 HWS_SF(, DIO_MEM_PWR_CTRL, I2C_LIGHT_SLEEP_FORCE, mask_sh), \ 911 HWS_SF(, HPO_TOP_HW_CONTROL, HPO_IO_EN, mask_sh) 912 913 static const struct dce_hwseq_shift hwseq_shift = { 914 HWSEQ_DCN31_MASK_SH_LIST(__SHIFT) 915 }; 916 917 static const struct dce_hwseq_mask hwseq_mask = { 918 HWSEQ_DCN31_MASK_SH_LIST(_MASK) 919 }; 920 #define vmid_regs(id)\ 921 [id] = {\ 922 DCN20_VMID_REG_LIST(id)\ 923 } 924 925 static const struct dcn_vmid_registers vmid_regs[] = { 926 vmid_regs(0), 927 vmid_regs(1), 928 vmid_regs(2), 929 vmid_regs(3), 930 vmid_regs(4), 931 vmid_regs(5), 932 vmid_regs(6), 933 vmid_regs(7), 934 vmid_regs(8), 935 vmid_regs(9), 936 vmid_regs(10), 937 vmid_regs(11), 938 vmid_regs(12), 939 vmid_regs(13), 940 vmid_regs(14), 941 vmid_regs(15) 942 }; 943 944 static const struct dcn20_vmid_shift vmid_shifts = { 945 DCN20_VMID_MASK_SH_LIST(__SHIFT) 946 }; 947 948 static const struct dcn20_vmid_mask vmid_masks = { 949 DCN20_VMID_MASK_SH_LIST(_MASK) 950 }; 951 952 static const struct resource_caps res_cap_dcn31 = { 953 .num_timing_generator = 4, 954 .num_opp = 4, 955 .num_video_plane = 4, 956 .num_audio = 5, 957 .num_stream_encoder = 5, 958 .num_dig_link_enc = 5, 959 .num_hpo_dp_stream_encoder = 4, 960 .num_hpo_dp_link_encoder = 2, 961 .num_pll = 5, 962 .num_dwb = 1, 963 .num_ddc = 5, 964 .num_vmid = 16, 965 .num_mpc_3dlut = 2, 966 .num_dsc = 3, 967 }; 968 969 static const struct dc_plane_cap plane_cap = { 970 .type = DC_PLANE_TYPE_DCN_UNIVERSAL, 971 .blends_with_above = true, 972 .blends_with_below = true, 973 .per_pixel_alpha = true, 974 975 .pixel_format_support = { 976 .argb8888 = true, 977 .nv12 = true, 978 .fp16 = true, 979 .p010 = false, 980 .ayuv = false, 981 }, 982 983 .max_upscale_factor = { 984 .argb8888 = 16000, 985 .nv12 = 16000, 986 .fp16 = 16000 987 }, 988 989 // 6:1 downscaling ratio: 1000/6 = 166.666 990 .max_downscale_factor = { 991 .argb8888 = 167, 992 .nv12 = 167, 993 .fp16 = 167 994 }, 995 64, 996 64 997 }; 998 999 static const struct dc_debug_options debug_defaults_drv = { 1000 .disable_dmcu = true, 1001 .force_abm_enable = false, 1002 .timing_trace = false, 1003 .clock_trace = true, 1004 .disable_pplib_clock_request = false, 1005 .pipe_split_policy = MPC_SPLIT_DYNAMIC, 1006 .force_single_disp_pipe_split = false, 1007 .disable_dcc = DCC_ENABLE, 1008 .vsr_support = true, 1009 .performance_trace = false, 1010 .max_downscale_src_width = 4096,/*upto true 4K*/ 1011 .disable_pplib_wm_range = false, 1012 .scl_reset_length10 = true, 1013 .sanity_checks = false, 1014 .underflow_assert_delay_us = 0xFFFFFFFF, 1015 .dwb_fi_phase = -1, // -1 = disable, 1016 .dmub_command_table = true, 1017 .pstate_enabled = true, 1018 .use_max_lb = true, 1019 .enable_mem_low_power = { 1020 .bits = { 1021 .vga = true, 1022 .i2c = true, 1023 .dmcu = false, // This is previously known to cause hang on S3 cycles if enabled 1024 .dscl = true, 1025 .cm = true, 1026 .mpc = true, 1027 .optc = true, 1028 .vpg = true, 1029 .afmt = true, 1030 } 1031 }, 1032 .optimize_edp_link_rate = true, 1033 .enable_sw_cntl_psr = true, 1034 }; 1035 1036 static const struct dc_debug_options debug_defaults_diags = { 1037 .disable_dmcu = true, 1038 .force_abm_enable = false, 1039 .timing_trace = true, 1040 .clock_trace = true, 1041 .disable_dpp_power_gate = true, 1042 .disable_hubp_power_gate = true, 1043 .disable_clock_gate = true, 1044 .disable_pplib_clock_request = true, 1045 .disable_pplib_wm_range = true, 1046 .disable_stutter = false, 1047 .scl_reset_length10 = true, 1048 .dwb_fi_phase = -1, // -1 = disable 1049 .dmub_command_table = true, 1050 .enable_tri_buf = true, 1051 .use_max_lb = true 1052 }; 1053 1054 static void dcn31_dpp_destroy(struct dpp **dpp) 1055 { 1056 kfree(TO_DCN20_DPP(*dpp)); 1057 *dpp = NULL; 1058 } 1059 1060 static struct dpp *dcn31_dpp_create( 1061 struct dc_context *ctx, 1062 uint32_t inst) 1063 { 1064 struct dcn3_dpp *dpp = 1065 kzalloc(sizeof(struct dcn3_dpp), GFP_KERNEL); 1066 1067 if (!dpp) 1068 return NULL; 1069 1070 if (dpp3_construct(dpp, ctx, inst, 1071 &dpp_regs[inst], &tf_shift, &tf_mask)) 1072 return &dpp->base; 1073 1074 BREAK_TO_DEBUGGER(); 1075 kfree(dpp); 1076 return NULL; 1077 } 1078 1079 static struct output_pixel_processor *dcn31_opp_create( 1080 struct dc_context *ctx, uint32_t inst) 1081 { 1082 struct dcn20_opp *opp = 1083 kzalloc(sizeof(struct dcn20_opp), GFP_KERNEL); 1084 1085 if (!opp) { 1086 BREAK_TO_DEBUGGER(); 1087 return NULL; 1088 } 1089 1090 dcn20_opp_construct(opp, ctx, inst, 1091 &opp_regs[inst], &opp_shift, &opp_mask); 1092 return &opp->base; 1093 } 1094 1095 static struct dce_aux *dcn31_aux_engine_create( 1096 struct dc_context *ctx, 1097 uint32_t inst) 1098 { 1099 struct aux_engine_dce110 *aux_engine = 1100 kzalloc(sizeof(struct aux_engine_dce110), GFP_KERNEL); 1101 1102 if (!aux_engine) 1103 return NULL; 1104 1105 dce110_aux_engine_construct(aux_engine, ctx, inst, 1106 SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD, 1107 &aux_engine_regs[inst], 1108 &aux_mask, 1109 &aux_shift, 1110 ctx->dc->caps.extended_aux_timeout_support); 1111 1112 return &aux_engine->base; 1113 } 1114 #define i2c_inst_regs(id) { I2C_HW_ENGINE_COMMON_REG_LIST_DCN30(id) } 1115 1116 static const struct dce_i2c_registers i2c_hw_regs[] = { 1117 i2c_inst_regs(1), 1118 i2c_inst_regs(2), 1119 i2c_inst_regs(3), 1120 i2c_inst_regs(4), 1121 i2c_inst_regs(5), 1122 }; 1123 1124 static const struct dce_i2c_shift i2c_shifts = { 1125 I2C_COMMON_MASK_SH_LIST_DCN30(__SHIFT) 1126 }; 1127 1128 static const struct dce_i2c_mask i2c_masks = { 1129 I2C_COMMON_MASK_SH_LIST_DCN30(_MASK) 1130 }; 1131 1132 static struct dce_i2c_hw *dcn31_i2c_hw_create( 1133 struct dc_context *ctx, 1134 uint32_t inst) 1135 { 1136 struct dce_i2c_hw *dce_i2c_hw = 1137 kzalloc(sizeof(struct dce_i2c_hw), GFP_KERNEL); 1138 1139 if (!dce_i2c_hw) 1140 return NULL; 1141 1142 dcn2_i2c_hw_construct(dce_i2c_hw, ctx, inst, 1143 &i2c_hw_regs[inst], &i2c_shifts, &i2c_masks); 1144 1145 return dce_i2c_hw; 1146 } 1147 static struct mpc *dcn31_mpc_create( 1148 struct dc_context *ctx, 1149 int num_mpcc, 1150 int num_rmu) 1151 { 1152 struct dcn30_mpc *mpc30 = kzalloc(sizeof(struct dcn30_mpc), 1153 GFP_KERNEL); 1154 1155 if (!mpc30) 1156 return NULL; 1157 1158 dcn30_mpc_construct(mpc30, ctx, 1159 &mpc_regs, 1160 &mpc_shift, 1161 &mpc_mask, 1162 num_mpcc, 1163 num_rmu); 1164 1165 return &mpc30->base; 1166 } 1167 1168 static struct hubbub *dcn31_hubbub_create(struct dc_context *ctx) 1169 { 1170 int i; 1171 1172 struct dcn20_hubbub *hubbub3 = kzalloc(sizeof(struct dcn20_hubbub), 1173 GFP_KERNEL); 1174 1175 if (!hubbub3) 1176 return NULL; 1177 1178 hubbub31_construct(hubbub3, ctx, 1179 &hubbub_reg, 1180 &hubbub_shift, 1181 &hubbub_mask, 1182 dcn3_1_ip.det_buffer_size_kbytes, 1183 dcn3_1_ip.pixel_chunk_size_kbytes, 1184 dcn3_1_ip.config_return_buffer_size_in_kbytes); 1185 1186 1187 for (i = 0; i < res_cap_dcn31.num_vmid; i++) { 1188 struct dcn20_vmid *vmid = &hubbub3->vmid[i]; 1189 1190 vmid->ctx = ctx; 1191 1192 vmid->regs = &vmid_regs[i]; 1193 vmid->shifts = &vmid_shifts; 1194 vmid->masks = &vmid_masks; 1195 } 1196 1197 return &hubbub3->base; 1198 } 1199 1200 static struct timing_generator *dcn31_timing_generator_create( 1201 struct dc_context *ctx, 1202 uint32_t instance) 1203 { 1204 struct optc *tgn10 = 1205 kzalloc(sizeof(struct optc), GFP_KERNEL); 1206 1207 if (!tgn10) 1208 return NULL; 1209 1210 tgn10->base.inst = instance; 1211 tgn10->base.ctx = ctx; 1212 1213 tgn10->tg_regs = &optc_regs[instance]; 1214 tgn10->tg_shift = &optc_shift; 1215 tgn10->tg_mask = &optc_mask; 1216 1217 dcn31_timing_generator_init(tgn10); 1218 1219 return &tgn10->base; 1220 } 1221 1222 static const struct encoder_feature_support link_enc_feature = { 1223 .max_hdmi_deep_color = COLOR_DEPTH_121212, 1224 .max_hdmi_pixel_clock = 600000, 1225 .hdmi_ycbcr420_supported = true, 1226 .dp_ycbcr420_supported = true, 1227 .fec_supported = true, 1228 .flags.bits.IS_HBR2_CAPABLE = true, 1229 .flags.bits.IS_HBR3_CAPABLE = true, 1230 .flags.bits.IS_TPS3_CAPABLE = true, 1231 .flags.bits.IS_TPS4_CAPABLE = true 1232 }; 1233 1234 static struct link_encoder *dcn31_link_encoder_create( 1235 const struct encoder_init_data *enc_init_data) 1236 { 1237 struct dcn20_link_encoder *enc20 = 1238 kzalloc(sizeof(struct dcn20_link_encoder), GFP_KERNEL); 1239 1240 if (!enc20) 1241 return NULL; 1242 1243 dcn31_link_encoder_construct(enc20, 1244 enc_init_data, 1245 &link_enc_feature, 1246 &link_enc_regs[enc_init_data->transmitter], 1247 &link_enc_aux_regs[enc_init_data->channel - 1], 1248 &link_enc_hpd_regs[enc_init_data->hpd_source], 1249 &le_shift, 1250 &le_mask); 1251 1252 return &enc20->enc10.base; 1253 } 1254 1255 /* Create a minimal link encoder object not associated with a particular 1256 * physical connector. 1257 * resource_funcs.link_enc_create_minimal 1258 */ 1259 static struct link_encoder *dcn31_link_enc_create_minimal( 1260 struct dc_context *ctx, enum engine_id eng_id) 1261 { 1262 struct dcn20_link_encoder *enc20; 1263 1264 if ((eng_id - ENGINE_ID_DIGA) > ctx->dc->res_pool->res_cap->num_dig_link_enc) 1265 return NULL; 1266 1267 enc20 = kzalloc(sizeof(struct dcn20_link_encoder), GFP_KERNEL); 1268 if (!enc20) 1269 return NULL; 1270 1271 dcn31_link_encoder_construct_minimal( 1272 enc20, 1273 ctx, 1274 &link_enc_feature, 1275 &link_enc_regs[eng_id - ENGINE_ID_DIGA], 1276 eng_id); 1277 1278 return &enc20->enc10.base; 1279 } 1280 1281 struct panel_cntl *dcn31_panel_cntl_create(const struct panel_cntl_init_data *init_data) 1282 { 1283 struct dcn31_panel_cntl *panel_cntl = 1284 kzalloc(sizeof(struct dcn31_panel_cntl), GFP_KERNEL); 1285 1286 if (!panel_cntl) 1287 return NULL; 1288 1289 dcn31_panel_cntl_construct(panel_cntl, init_data); 1290 1291 return &panel_cntl->base; 1292 } 1293 1294 static void read_dce_straps( 1295 struct dc_context *ctx, 1296 struct resource_straps *straps) 1297 { 1298 generic_reg_get(ctx, regDC_PINSTRAPS + BASE(regDC_PINSTRAPS_BASE_IDX), 1299 FN(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO), &straps->dc_pinstraps_audio); 1300 1301 } 1302 1303 static struct audio *dcn31_create_audio( 1304 struct dc_context *ctx, unsigned int inst) 1305 { 1306 return dce_audio_create(ctx, inst, 1307 &audio_regs[inst], &audio_shift, &audio_mask); 1308 } 1309 1310 static struct vpg *dcn31_vpg_create( 1311 struct dc_context *ctx, 1312 uint32_t inst) 1313 { 1314 struct dcn31_vpg *vpg31 = kzalloc(sizeof(struct dcn31_vpg), GFP_KERNEL); 1315 1316 if (!vpg31) 1317 return NULL; 1318 1319 vpg31_construct(vpg31, ctx, inst, 1320 &vpg_regs[inst], 1321 &vpg_shift, 1322 &vpg_mask); 1323 1324 return &vpg31->base; 1325 } 1326 1327 static struct afmt *dcn31_afmt_create( 1328 struct dc_context *ctx, 1329 uint32_t inst) 1330 { 1331 struct dcn31_afmt *afmt31 = kzalloc(sizeof(struct dcn31_afmt), GFP_KERNEL); 1332 1333 if (!afmt31) 1334 return NULL; 1335 1336 afmt31_construct(afmt31, ctx, inst, 1337 &afmt_regs[inst], 1338 &afmt_shift, 1339 &afmt_mask); 1340 1341 // Light sleep by default, no need to power down here 1342 1343 return &afmt31->base; 1344 } 1345 1346 static struct apg *dcn31_apg_create( 1347 struct dc_context *ctx, 1348 uint32_t inst) 1349 { 1350 struct dcn31_apg *apg31 = kzalloc(sizeof(struct dcn31_apg), GFP_KERNEL); 1351 1352 if (!apg31) 1353 return NULL; 1354 1355 apg31_construct(apg31, ctx, inst, 1356 &apg_regs[inst], 1357 &apg_shift, 1358 &apg_mask); 1359 1360 return &apg31->base; 1361 } 1362 1363 static struct stream_encoder *dcn31_stream_encoder_create( 1364 enum engine_id eng_id, 1365 struct dc_context *ctx) 1366 { 1367 struct dcn10_stream_encoder *enc1; 1368 struct vpg *vpg; 1369 struct afmt *afmt; 1370 int vpg_inst; 1371 int afmt_inst; 1372 1373 /* Mapping of VPG, AFMT, DME register blocks to DIO block instance */ 1374 if (eng_id <= ENGINE_ID_DIGF) { 1375 vpg_inst = eng_id; 1376 afmt_inst = eng_id; 1377 } else 1378 return NULL; 1379 1380 enc1 = kzalloc(sizeof(struct dcn10_stream_encoder), GFP_KERNEL); 1381 vpg = dcn31_vpg_create(ctx, vpg_inst); 1382 afmt = dcn31_afmt_create(ctx, afmt_inst); 1383 1384 if (!enc1 || !vpg || !afmt) { 1385 kfree(enc1); 1386 kfree(vpg); 1387 kfree(afmt); 1388 return NULL; 1389 } 1390 1391 if (ctx->asic_id.chip_family == FAMILY_YELLOW_CARP && 1392 ctx->asic_id.hw_internal_rev == YELLOW_CARP_B0) { 1393 if ((eng_id == ENGINE_ID_DIGC) || (eng_id == ENGINE_ID_DIGD)) 1394 eng_id = eng_id + 3; // For B0 only. C->F, D->G. 1395 } 1396 1397 dcn30_dio_stream_encoder_construct(enc1, ctx, ctx->dc_bios, 1398 eng_id, vpg, afmt, 1399 &stream_enc_regs[eng_id], 1400 &se_shift, &se_mask); 1401 1402 return &enc1->base; 1403 } 1404 1405 static struct hpo_dp_stream_encoder *dcn31_hpo_dp_stream_encoder_create( 1406 enum engine_id eng_id, 1407 struct dc_context *ctx) 1408 { 1409 struct dcn31_hpo_dp_stream_encoder *hpo_dp_enc31; 1410 struct vpg *vpg; 1411 struct apg *apg; 1412 uint32_t hpo_dp_inst; 1413 uint32_t vpg_inst; 1414 uint32_t apg_inst; 1415 1416 ASSERT((eng_id >= ENGINE_ID_HPO_DP_0) && (eng_id <= ENGINE_ID_HPO_DP_3)); 1417 hpo_dp_inst = eng_id - ENGINE_ID_HPO_DP_0; 1418 1419 /* Mapping of VPG register blocks to HPO DP block instance: 1420 * VPG[6] -> HPO_DP[0] 1421 * VPG[7] -> HPO_DP[1] 1422 * VPG[8] -> HPO_DP[2] 1423 * VPG[9] -> HPO_DP[3] 1424 */ 1425 vpg_inst = hpo_dp_inst + 6; 1426 1427 /* Mapping of APG register blocks to HPO DP block instance: 1428 * APG[0] -> HPO_DP[0] 1429 * APG[1] -> HPO_DP[1] 1430 * APG[2] -> HPO_DP[2] 1431 * APG[3] -> HPO_DP[3] 1432 */ 1433 apg_inst = hpo_dp_inst; 1434 1435 /* allocate HPO stream encoder and create VPG sub-block */ 1436 hpo_dp_enc31 = kzalloc(sizeof(struct dcn31_hpo_dp_stream_encoder), GFP_KERNEL); 1437 vpg = dcn31_vpg_create(ctx, vpg_inst); 1438 apg = dcn31_apg_create(ctx, apg_inst); 1439 1440 if (!hpo_dp_enc31 || !vpg || !apg) { 1441 kfree(hpo_dp_enc31); 1442 kfree(vpg); 1443 kfree(apg); 1444 return NULL; 1445 } 1446 1447 dcn31_hpo_dp_stream_encoder_construct(hpo_dp_enc31, ctx, ctx->dc_bios, 1448 hpo_dp_inst, eng_id, vpg, apg, 1449 &hpo_dp_stream_enc_regs[hpo_dp_inst], 1450 &hpo_dp_se_shift, &hpo_dp_se_mask); 1451 1452 return &hpo_dp_enc31->base; 1453 } 1454 1455 static struct hpo_dp_link_encoder *dcn31_hpo_dp_link_encoder_create( 1456 uint8_t inst, 1457 struct dc_context *ctx) 1458 { 1459 struct dcn31_hpo_dp_link_encoder *hpo_dp_enc31; 1460 1461 /* allocate HPO link encoder */ 1462 hpo_dp_enc31 = kzalloc(sizeof(struct dcn31_hpo_dp_link_encoder), GFP_KERNEL); 1463 1464 hpo_dp_link_encoder31_construct(hpo_dp_enc31, ctx, inst, 1465 &hpo_dp_link_enc_regs[inst], 1466 &hpo_dp_le_shift, &hpo_dp_le_mask); 1467 1468 return &hpo_dp_enc31->base; 1469 } 1470 1471 static struct dce_hwseq *dcn31_hwseq_create( 1472 struct dc_context *ctx) 1473 { 1474 struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_KERNEL); 1475 1476 if (hws) { 1477 hws->ctx = ctx; 1478 hws->regs = &hwseq_reg; 1479 hws->shifts = &hwseq_shift; 1480 hws->masks = &hwseq_mask; 1481 /* DCN3.1 FPGA Workaround 1482 * Need to enable HPO DP Stream Encoder before setting OTG master enable. 1483 * To do so, move calling function enable_stream_timing to only be done AFTER calling 1484 * function core_link_enable_stream 1485 */ 1486 if (IS_FPGA_MAXIMUS_DC(ctx->dce_environment)) 1487 hws->wa.dp_hpo_and_otg_sequence = true; 1488 } 1489 return hws; 1490 } 1491 static const struct resource_create_funcs res_create_funcs = { 1492 .read_dce_straps = read_dce_straps, 1493 .create_audio = dcn31_create_audio, 1494 .create_stream_encoder = dcn31_stream_encoder_create, 1495 .create_hpo_dp_stream_encoder = dcn31_hpo_dp_stream_encoder_create, 1496 .create_hpo_dp_link_encoder = dcn31_hpo_dp_link_encoder_create, 1497 .create_hwseq = dcn31_hwseq_create, 1498 }; 1499 1500 static const struct resource_create_funcs res_create_maximus_funcs = { 1501 .read_dce_straps = NULL, 1502 .create_audio = NULL, 1503 .create_stream_encoder = NULL, 1504 .create_hpo_dp_stream_encoder = dcn31_hpo_dp_stream_encoder_create, 1505 .create_hpo_dp_link_encoder = dcn31_hpo_dp_link_encoder_create, 1506 .create_hwseq = dcn31_hwseq_create, 1507 }; 1508 1509 static void dcn31_resource_destruct(struct dcn31_resource_pool *pool) 1510 { 1511 unsigned int i; 1512 1513 for (i = 0; i < pool->base.stream_enc_count; i++) { 1514 if (pool->base.stream_enc[i] != NULL) { 1515 if (pool->base.stream_enc[i]->vpg != NULL) { 1516 kfree(DCN30_VPG_FROM_VPG(pool->base.stream_enc[i]->vpg)); 1517 pool->base.stream_enc[i]->vpg = NULL; 1518 } 1519 if (pool->base.stream_enc[i]->afmt != NULL) { 1520 kfree(DCN30_AFMT_FROM_AFMT(pool->base.stream_enc[i]->afmt)); 1521 pool->base.stream_enc[i]->afmt = NULL; 1522 } 1523 kfree(DCN10STRENC_FROM_STRENC(pool->base.stream_enc[i])); 1524 pool->base.stream_enc[i] = NULL; 1525 } 1526 } 1527 1528 for (i = 0; i < pool->base.hpo_dp_stream_enc_count; i++) { 1529 if (pool->base.hpo_dp_stream_enc[i] != NULL) { 1530 if (pool->base.hpo_dp_stream_enc[i]->vpg != NULL) { 1531 kfree(DCN30_VPG_FROM_VPG(pool->base.hpo_dp_stream_enc[i]->vpg)); 1532 pool->base.hpo_dp_stream_enc[i]->vpg = NULL; 1533 } 1534 if (pool->base.hpo_dp_stream_enc[i]->apg != NULL) { 1535 kfree(DCN31_APG_FROM_APG(pool->base.hpo_dp_stream_enc[i]->apg)); 1536 pool->base.hpo_dp_stream_enc[i]->apg = NULL; 1537 } 1538 kfree(DCN3_1_HPO_DP_STREAM_ENC_FROM_HPO_STREAM_ENC(pool->base.hpo_dp_stream_enc[i])); 1539 pool->base.hpo_dp_stream_enc[i] = NULL; 1540 } 1541 } 1542 1543 for (i = 0; i < pool->base.hpo_dp_link_enc_count; i++) { 1544 if (pool->base.hpo_dp_link_enc[i] != NULL) { 1545 kfree(DCN3_1_HPO_DP_LINK_ENC_FROM_HPO_LINK_ENC(pool->base.hpo_dp_link_enc[i])); 1546 pool->base.hpo_dp_link_enc[i] = NULL; 1547 } 1548 } 1549 1550 for (i = 0; i < pool->base.res_cap->num_dsc; i++) { 1551 if (pool->base.dscs[i] != NULL) 1552 dcn20_dsc_destroy(&pool->base.dscs[i]); 1553 } 1554 1555 if (pool->base.mpc != NULL) { 1556 kfree(TO_DCN20_MPC(pool->base.mpc)); 1557 pool->base.mpc = NULL; 1558 } 1559 if (pool->base.hubbub != NULL) { 1560 kfree(pool->base.hubbub); 1561 pool->base.hubbub = NULL; 1562 } 1563 for (i = 0; i < pool->base.pipe_count; i++) { 1564 if (pool->base.dpps[i] != NULL) 1565 dcn31_dpp_destroy(&pool->base.dpps[i]); 1566 1567 if (pool->base.ipps[i] != NULL) 1568 pool->base.ipps[i]->funcs->ipp_destroy(&pool->base.ipps[i]); 1569 1570 if (pool->base.hubps[i] != NULL) { 1571 kfree(TO_DCN20_HUBP(pool->base.hubps[i])); 1572 pool->base.hubps[i] = NULL; 1573 } 1574 1575 if (pool->base.irqs != NULL) { 1576 dal_irq_service_destroy(&pool->base.irqs); 1577 } 1578 } 1579 1580 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { 1581 if (pool->base.engines[i] != NULL) 1582 dce110_engine_destroy(&pool->base.engines[i]); 1583 if (pool->base.hw_i2cs[i] != NULL) { 1584 kfree(pool->base.hw_i2cs[i]); 1585 pool->base.hw_i2cs[i] = NULL; 1586 } 1587 if (pool->base.sw_i2cs[i] != NULL) { 1588 kfree(pool->base.sw_i2cs[i]); 1589 pool->base.sw_i2cs[i] = NULL; 1590 } 1591 } 1592 1593 for (i = 0; i < pool->base.res_cap->num_opp; i++) { 1594 if (pool->base.opps[i] != NULL) 1595 pool->base.opps[i]->funcs->opp_destroy(&pool->base.opps[i]); 1596 } 1597 1598 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { 1599 if (pool->base.timing_generators[i] != NULL) { 1600 kfree(DCN10TG_FROM_TG(pool->base.timing_generators[i])); 1601 pool->base.timing_generators[i] = NULL; 1602 } 1603 } 1604 1605 for (i = 0; i < pool->base.res_cap->num_dwb; i++) { 1606 if (pool->base.dwbc[i] != NULL) { 1607 kfree(TO_DCN30_DWBC(pool->base.dwbc[i])); 1608 pool->base.dwbc[i] = NULL; 1609 } 1610 if (pool->base.mcif_wb[i] != NULL) { 1611 kfree(TO_DCN30_MMHUBBUB(pool->base.mcif_wb[i])); 1612 pool->base.mcif_wb[i] = NULL; 1613 } 1614 } 1615 1616 for (i = 0; i < pool->base.audio_count; i++) { 1617 if (pool->base.audios[i]) 1618 dce_aud_destroy(&pool->base.audios[i]); 1619 } 1620 1621 for (i = 0; i < pool->base.clk_src_count; i++) { 1622 if (pool->base.clock_sources[i] != NULL) { 1623 dcn20_clock_source_destroy(&pool->base.clock_sources[i]); 1624 pool->base.clock_sources[i] = NULL; 1625 } 1626 } 1627 1628 for (i = 0; i < pool->base.res_cap->num_mpc_3dlut; i++) { 1629 if (pool->base.mpc_lut[i] != NULL) { 1630 dc_3dlut_func_release(pool->base.mpc_lut[i]); 1631 pool->base.mpc_lut[i] = NULL; 1632 } 1633 if (pool->base.mpc_shaper[i] != NULL) { 1634 dc_transfer_func_release(pool->base.mpc_shaper[i]); 1635 pool->base.mpc_shaper[i] = NULL; 1636 } 1637 } 1638 1639 if (pool->base.dp_clock_source != NULL) { 1640 dcn20_clock_source_destroy(&pool->base.dp_clock_source); 1641 pool->base.dp_clock_source = NULL; 1642 } 1643 1644 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { 1645 if (pool->base.multiple_abms[i] != NULL) 1646 dce_abm_destroy(&pool->base.multiple_abms[i]); 1647 } 1648 1649 if (pool->base.psr != NULL) 1650 dmub_psr_destroy(&pool->base.psr); 1651 1652 if (pool->base.dccg != NULL) 1653 dcn_dccg_destroy(&pool->base.dccg); 1654 } 1655 1656 static struct hubp *dcn31_hubp_create( 1657 struct dc_context *ctx, 1658 uint32_t inst) 1659 { 1660 struct dcn20_hubp *hubp2 = 1661 kzalloc(sizeof(struct dcn20_hubp), GFP_KERNEL); 1662 1663 if (!hubp2) 1664 return NULL; 1665 1666 if (hubp31_construct(hubp2, ctx, inst, 1667 &hubp_regs[inst], &hubp_shift, &hubp_mask)) 1668 return &hubp2->base; 1669 1670 BREAK_TO_DEBUGGER(); 1671 kfree(hubp2); 1672 return NULL; 1673 } 1674 1675 static bool dcn31_dwbc_create(struct dc_context *ctx, struct resource_pool *pool) 1676 { 1677 int i; 1678 uint32_t pipe_count = pool->res_cap->num_dwb; 1679 1680 for (i = 0; i < pipe_count; i++) { 1681 struct dcn30_dwbc *dwbc30 = kzalloc(sizeof(struct dcn30_dwbc), 1682 GFP_KERNEL); 1683 1684 if (!dwbc30) { 1685 dm_error("DC: failed to create dwbc30!\n"); 1686 return false; 1687 } 1688 1689 dcn30_dwbc_construct(dwbc30, ctx, 1690 &dwbc30_regs[i], 1691 &dwbc30_shift, 1692 &dwbc30_mask, 1693 i); 1694 1695 pool->dwbc[i] = &dwbc30->base; 1696 } 1697 return true; 1698 } 1699 1700 static bool dcn31_mmhubbub_create(struct dc_context *ctx, struct resource_pool *pool) 1701 { 1702 int i; 1703 uint32_t pipe_count = pool->res_cap->num_dwb; 1704 1705 for (i = 0; i < pipe_count; i++) { 1706 struct dcn30_mmhubbub *mcif_wb30 = kzalloc(sizeof(struct dcn30_mmhubbub), 1707 GFP_KERNEL); 1708 1709 if (!mcif_wb30) { 1710 dm_error("DC: failed to create mcif_wb30!\n"); 1711 return false; 1712 } 1713 1714 dcn30_mmhubbub_construct(mcif_wb30, ctx, 1715 &mcif_wb30_regs[i], 1716 &mcif_wb30_shift, 1717 &mcif_wb30_mask, 1718 i); 1719 1720 pool->mcif_wb[i] = &mcif_wb30->base; 1721 } 1722 return true; 1723 } 1724 1725 static struct display_stream_compressor *dcn31_dsc_create( 1726 struct dc_context *ctx, uint32_t inst) 1727 { 1728 struct dcn20_dsc *dsc = 1729 kzalloc(sizeof(struct dcn20_dsc), GFP_KERNEL); 1730 1731 if (!dsc) { 1732 BREAK_TO_DEBUGGER(); 1733 return NULL; 1734 } 1735 1736 dsc2_construct(dsc, ctx, inst, &dsc_regs[inst], &dsc_shift, &dsc_mask); 1737 return &dsc->base; 1738 } 1739 1740 static void dcn31_destroy_resource_pool(struct resource_pool **pool) 1741 { 1742 struct dcn31_resource_pool *dcn31_pool = TO_DCN31_RES_POOL(*pool); 1743 1744 dcn31_resource_destruct(dcn31_pool); 1745 kfree(dcn31_pool); 1746 *pool = NULL; 1747 } 1748 1749 static struct clock_source *dcn31_clock_source_create( 1750 struct dc_context *ctx, 1751 struct dc_bios *bios, 1752 enum clock_source_id id, 1753 const struct dce110_clk_src_regs *regs, 1754 bool dp_clk_src) 1755 { 1756 struct dce110_clk_src *clk_src = 1757 kzalloc(sizeof(struct dce110_clk_src), GFP_KERNEL); 1758 1759 if (!clk_src) 1760 return NULL; 1761 1762 if (dcn3_clk_src_construct(clk_src, ctx, bios, id, 1763 regs, &cs_shift, &cs_mask)) { 1764 clk_src->base.dp_clk_src = dp_clk_src; 1765 return &clk_src->base; 1766 } 1767 1768 BREAK_TO_DEBUGGER(); 1769 return NULL; 1770 } 1771 1772 static bool is_dual_plane(enum surface_pixel_format format) 1773 { 1774 return format >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN || format == SURFACE_PIXEL_FORMAT_GRPH_RGBE_ALPHA; 1775 } 1776 1777 static int dcn31_populate_dml_pipes_from_context( 1778 struct dc *dc, struct dc_state *context, 1779 display_e2e_pipe_params_st *pipes, 1780 bool fast_validate) 1781 { 1782 int i, pipe_cnt; 1783 struct resource_context *res_ctx = &context->res_ctx; 1784 struct pipe_ctx *pipe; 1785 1786 dcn20_populate_dml_pipes_from_context(dc, context, pipes, fast_validate); 1787 1788 for (i = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) { 1789 struct dc_crtc_timing *timing; 1790 1791 if (!res_ctx->pipe_ctx[i].stream) 1792 continue; 1793 pipe = &res_ctx->pipe_ctx[i]; 1794 timing = &pipe->stream->timing; 1795 1796 /* 1797 * Immediate flip can be set dynamically after enabling the plane. 1798 * We need to require support for immediate flip or underflow can be 1799 * intermittently experienced depending on peak b/w requirements. 1800 */ 1801 pipes[pipe_cnt].pipe.src.immediate_flip = true; 1802 1803 pipes[pipe_cnt].pipe.src.unbounded_req_mode = false; 1804 pipes[pipe_cnt].pipe.src.gpuvm = true; 1805 pipes[pipe_cnt].pipe.src.dcc_fraction_of_zs_req_luma = 0; 1806 pipes[pipe_cnt].pipe.src.dcc_fraction_of_zs_req_chroma = 0; 1807 pipes[pipe_cnt].pipe.dest.vfront_porch = timing->v_front_porch; 1808 pipes[pipe_cnt].pipe.src.dcc_rate = 3; 1809 pipes[pipe_cnt].dout.dsc_input_bpc = 0; 1810 1811 if (pipes[pipe_cnt].dout.dsc_enable) { 1812 switch (timing->display_color_depth) { 1813 case COLOR_DEPTH_888: 1814 pipes[pipe_cnt].dout.dsc_input_bpc = 8; 1815 break; 1816 case COLOR_DEPTH_101010: 1817 pipes[pipe_cnt].dout.dsc_input_bpc = 10; 1818 break; 1819 case COLOR_DEPTH_121212: 1820 pipes[pipe_cnt].dout.dsc_input_bpc = 12; 1821 break; 1822 default: 1823 ASSERT(0); 1824 break; 1825 } 1826 } 1827 1828 pipe_cnt++; 1829 } 1830 context->bw_ctx.dml.ip.det_buffer_size_kbytes = DCN3_1_DEFAULT_DET_SIZE; 1831 dc->config.enable_4to1MPC = false; 1832 if (pipe_cnt == 1 && pipe->plane_state && !dc->debug.disable_z9_mpc) { 1833 if (is_dual_plane(pipe->plane_state->format) 1834 && pipe->plane_state->src_rect.width <= 1920 && pipe->plane_state->src_rect.height <= 1080) { 1835 dc->config.enable_4to1MPC = true; 1836 } else if (!is_dual_plane(pipe->plane_state->format)) { 1837 context->bw_ctx.dml.ip.det_buffer_size_kbytes = 192; 1838 pipes[0].pipe.src.unbounded_req_mode = true; 1839 } 1840 } 1841 1842 return pipe_cnt; 1843 } 1844 1845 void dcn31_update_soc_for_wm_a(struct dc *dc, struct dc_state *context) 1846 { 1847 if (dc->clk_mgr->bw_params->wm_table.entries[WM_A].valid) { 1848 context->bw_ctx.dml.soc.dram_clock_change_latency_us = dc->clk_mgr->bw_params->wm_table.entries[WM_A].pstate_latency_us; 1849 context->bw_ctx.dml.soc.sr_enter_plus_exit_time_us = dc->clk_mgr->bw_params->wm_table.entries[WM_A].sr_enter_plus_exit_time_us; 1850 context->bw_ctx.dml.soc.sr_exit_time_us = dc->clk_mgr->bw_params->wm_table.entries[WM_A].sr_exit_time_us; 1851 } 1852 } 1853 1854 static void dcn31_calculate_wm_and_dlg_fp( 1855 struct dc *dc, struct dc_state *context, 1856 display_e2e_pipe_params_st *pipes, 1857 int pipe_cnt, 1858 int vlevel) 1859 { 1860 int i, pipe_idx; 1861 double dcfclk = context->bw_ctx.dml.vba.DCFCLKState[vlevel][context->bw_ctx.dml.vba.maxMpcComb]; 1862 1863 if (context->bw_ctx.dml.soc.min_dcfclk > dcfclk) 1864 dcfclk = context->bw_ctx.dml.soc.min_dcfclk; 1865 1866 /* We don't recalculate clocks for 0 pipe configs, which can block 1867 * S0i3 as high clocks will block low power states 1868 * Override any clocks that can block S0i3 to min here 1869 */ 1870 if (pipe_cnt == 0) { 1871 context->bw_ctx.bw.dcn.clk.dcfclk_khz = dcfclk; // always should be vlevel 0 1872 return; 1873 } 1874 1875 pipes[0].clks_cfg.voltage = vlevel; 1876 pipes[0].clks_cfg.dcfclk_mhz = dcfclk; 1877 pipes[0].clks_cfg.socclk_mhz = context->bw_ctx.dml.soc.clock_limits[vlevel].socclk_mhz; 1878 1879 #if 0 // TODO 1880 /* Set B: 1881 * TODO 1882 */ 1883 if (dc->clk_mgr->bw_params->wm_table.nv_entries[WM_B].valid) { 1884 if (vlevel == 0) { 1885 pipes[0].clks_cfg.voltage = 1; 1886 pipes[0].clks_cfg.dcfclk_mhz = context->bw_ctx.dml.soc.clock_limits[0].dcfclk_mhz; 1887 } 1888 context->bw_ctx.dml.soc.dram_clock_change_latency_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_B].dml_input.pstate_latency_us; 1889 context->bw_ctx.dml.soc.sr_enter_plus_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_B].dml_input.sr_enter_plus_exit_time_us; 1890 context->bw_ctx.dml.soc.sr_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_B].dml_input.sr_exit_time_us; 1891 } 1892 context->bw_ctx.bw.dcn.watermarks.b.urgent_ns = get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 1893 context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 1894 context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 1895 context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.cstate_enter_plus_exit_z8_ns = get_wm_z8_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 1896 context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.cstate_exit_z8_ns = get_wm_z8_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 1897 context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 1898 context->bw_ctx.bw.dcn.watermarks.b.pte_meta_urgent_ns = get_wm_memory_trip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 1899 context->bw_ctx.bw.dcn.watermarks.b.frac_urg_bw_nom = get_fraction_of_urgent_bandwidth(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 1900 context->bw_ctx.bw.dcn.watermarks.b.frac_urg_bw_flip = get_fraction_of_urgent_bandwidth_imm_flip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 1901 context->bw_ctx.bw.dcn.watermarks.b.urgent_latency_ns = get_urgent_latency(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 1902 1903 pipes[0].clks_cfg.voltage = vlevel; 1904 pipes[0].clks_cfg.dcfclk_mhz = dcfclk; 1905 1906 /* Set C: 1907 * TODO 1908 */ 1909 if (dc->clk_mgr->bw_params->wm_table.nv_entries[WM_C].valid) { 1910 context->bw_ctx.dml.soc.dram_clock_change_latency_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_C].dml_input.pstate_latency_us; 1911 context->bw_ctx.dml.soc.sr_enter_plus_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_C].dml_input.sr_enter_plus_exit_time_us; 1912 context->bw_ctx.dml.soc.sr_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_C].dml_input.sr_exit_time_us; 1913 } 1914 context->bw_ctx.bw.dcn.watermarks.c.urgent_ns = get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 1915 context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 1916 context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 1917 context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.cstate_enter_plus_exit_z8_ns = get_wm_z8_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 1918 context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.cstate_exit_z8_ns = get_wm_z8_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 1919 context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 1920 context->bw_ctx.bw.dcn.watermarks.c.pte_meta_urgent_ns = get_wm_memory_trip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 1921 context->bw_ctx.bw.dcn.watermarks.c.frac_urg_bw_nom = get_fraction_of_urgent_bandwidth(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 1922 context->bw_ctx.bw.dcn.watermarks.c.frac_urg_bw_flip = get_fraction_of_urgent_bandwidth_imm_flip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 1923 context->bw_ctx.bw.dcn.watermarks.c.urgent_latency_ns = get_urgent_latency(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 1924 1925 /* Set D: 1926 * TODO 1927 */ 1928 if (dc->clk_mgr->bw_params->wm_table.nv_entries[WM_D].valid) { 1929 context->bw_ctx.dml.soc.dram_clock_change_latency_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_D].dml_input.pstate_latency_us; 1930 context->bw_ctx.dml.soc.sr_enter_plus_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_D].dml_input.sr_enter_plus_exit_time_us; 1931 context->bw_ctx.dml.soc.sr_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_D].dml_input.sr_exit_time_us; 1932 } 1933 context->bw_ctx.bw.dcn.watermarks.d.urgent_ns = get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 1934 context->bw_ctx.bw.dcn.watermarks.d.cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 1935 context->bw_ctx.bw.dcn.watermarks.d.cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 1936 context->bw_ctx.bw.dcn.watermarks.d.cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 1937 context->bw_ctx.bw.dcn.watermarks.d.cstate_pstate.cstate_enter_plus_exit_z8_ns = get_wm_z8_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 1938 context->bw_ctx.bw.dcn.watermarks.d.cstate_pstate.cstate_exit_z8_ns = get_wm_z8_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 1939 context->bw_ctx.bw.dcn.watermarks.d.pte_meta_urgent_ns = get_wm_memory_trip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 1940 context->bw_ctx.bw.dcn.watermarks.d.frac_urg_bw_nom = get_fraction_of_urgent_bandwidth(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 1941 context->bw_ctx.bw.dcn.watermarks.d.frac_urg_bw_flip = get_fraction_of_urgent_bandwidth_imm_flip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 1942 context->bw_ctx.bw.dcn.watermarks.d.urgent_latency_ns = get_urgent_latency(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 1943 #endif 1944 1945 /* Set A: 1946 * All clocks min required 1947 * 1948 * Set A calculated last so that following calculations are based on Set A 1949 */ 1950 dc->res_pool->funcs->update_soc_for_wm_a(dc, context); 1951 context->bw_ctx.bw.dcn.watermarks.a.urgent_ns = get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 1952 context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 1953 context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 1954 context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 1955 context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.cstate_enter_plus_exit_z8_ns = get_wm_z8_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 1956 context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.cstate_exit_z8_ns = get_wm_z8_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 1957 context->bw_ctx.bw.dcn.watermarks.a.pte_meta_urgent_ns = get_wm_memory_trip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 1958 context->bw_ctx.bw.dcn.watermarks.a.frac_urg_bw_nom = get_fraction_of_urgent_bandwidth(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 1959 context->bw_ctx.bw.dcn.watermarks.a.frac_urg_bw_flip = get_fraction_of_urgent_bandwidth_imm_flip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 1960 context->bw_ctx.bw.dcn.watermarks.a.urgent_latency_ns = get_urgent_latency(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 1961 /* TODO: remove: */ 1962 context->bw_ctx.bw.dcn.watermarks.b = context->bw_ctx.bw.dcn.watermarks.a; 1963 context->bw_ctx.bw.dcn.watermarks.c = context->bw_ctx.bw.dcn.watermarks.a; 1964 context->bw_ctx.bw.dcn.watermarks.d = context->bw_ctx.bw.dcn.watermarks.a; 1965 /* end remove*/ 1966 1967 for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) { 1968 if (!context->res_ctx.pipe_ctx[i].stream) 1969 continue; 1970 1971 pipes[pipe_idx].clks_cfg.dispclk_mhz = get_dispclk_calculated(&context->bw_ctx.dml, pipes, pipe_cnt); 1972 pipes[pipe_idx].clks_cfg.dppclk_mhz = get_dppclk_calculated(&context->bw_ctx.dml, pipes, pipe_cnt, pipe_idx); 1973 1974 if (dc->config.forced_clocks) { 1975 pipes[pipe_idx].clks_cfg.dispclk_mhz = context->bw_ctx.dml.soc.clock_limits[0].dispclk_mhz; 1976 pipes[pipe_idx].clks_cfg.dppclk_mhz = context->bw_ctx.dml.soc.clock_limits[0].dppclk_mhz; 1977 } 1978 if (dc->debug.min_disp_clk_khz > pipes[pipe_idx].clks_cfg.dispclk_mhz * 1000) 1979 pipes[pipe_idx].clks_cfg.dispclk_mhz = dc->debug.min_disp_clk_khz / 1000.0; 1980 if (dc->debug.min_dpp_clk_khz > pipes[pipe_idx].clks_cfg.dppclk_mhz * 1000) 1981 pipes[pipe_idx].clks_cfg.dppclk_mhz = dc->debug.min_dpp_clk_khz / 1000.0; 1982 1983 pipe_idx++; 1984 } 1985 1986 dcn20_calculate_dlg_params(dc, context, pipes, pipe_cnt, vlevel); 1987 } 1988 1989 void dcn31_calculate_wm_and_dlg( 1990 struct dc *dc, struct dc_state *context, 1991 display_e2e_pipe_params_st *pipes, 1992 int pipe_cnt, 1993 int vlevel) 1994 { 1995 DC_FP_START(); 1996 dcn31_calculate_wm_and_dlg_fp(dc, context, pipes, pipe_cnt, vlevel); 1997 DC_FP_END(); 1998 } 1999 2000 bool dcn31_validate_bandwidth(struct dc *dc, 2001 struct dc_state *context, 2002 bool fast_validate) 2003 { 2004 bool out = false; 2005 2006 BW_VAL_TRACE_SETUP(); 2007 2008 int vlevel = 0; 2009 int pipe_cnt = 0; 2010 display_e2e_pipe_params_st *pipes = kzalloc(dc->res_pool->pipe_count * sizeof(display_e2e_pipe_params_st), GFP_KERNEL); 2011 DC_LOGGER_INIT(dc->ctx->logger); 2012 2013 BW_VAL_TRACE_COUNT(); 2014 2015 out = dcn30_internal_validate_bw(dc, context, pipes, &pipe_cnt, &vlevel, fast_validate); 2016 2017 // Disable fast_validate to set min dcfclk in alculate_wm_and_dlg 2018 if (pipe_cnt == 0) 2019 fast_validate = false; 2020 2021 if (!out) 2022 goto validate_fail; 2023 2024 BW_VAL_TRACE_END_VOLTAGE_LEVEL(); 2025 2026 if (fast_validate) { 2027 BW_VAL_TRACE_SKIP(fast); 2028 goto validate_out; 2029 } 2030 2031 dc->res_pool->funcs->calculate_wm_and_dlg(dc, context, pipes, pipe_cnt, vlevel); 2032 2033 BW_VAL_TRACE_END_WATERMARKS(); 2034 2035 goto validate_out; 2036 2037 validate_fail: 2038 DC_LOG_WARNING("Mode Validation Warning: %s failed validation.\n", 2039 dml_get_status_message(context->bw_ctx.dml.vba.ValidationStatus[context->bw_ctx.dml.vba.soc.num_states])); 2040 2041 BW_VAL_TRACE_SKIP(fail); 2042 out = false; 2043 2044 validate_out: 2045 kfree(pipes); 2046 2047 BW_VAL_TRACE_FINISH(); 2048 2049 return out; 2050 } 2051 2052 static struct dc_cap_funcs cap_funcs = { 2053 .get_dcc_compression_cap = dcn20_get_dcc_compression_cap 2054 }; 2055 2056 static void dcn31_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params) 2057 { 2058 struct clk_limit_table *clk_table = &bw_params->clk_table; 2059 struct _vcs_dpi_voltage_scaling_st clock_limits[DC__VOLTAGE_STATES]; 2060 unsigned int i, closest_clk_lvl; 2061 int j; 2062 2063 // Default clock levels are used for diags, which may lead to overclocking. 2064 if (!IS_DIAG_DC(dc->ctx->dce_environment)) { 2065 int max_dispclk_mhz = 0, max_dppclk_mhz = 0; 2066 2067 dcn3_1_ip.max_num_otg = dc->res_pool->res_cap->num_timing_generator; 2068 dcn3_1_ip.max_num_dpp = dc->res_pool->pipe_count; 2069 dcn3_1_soc.num_chans = bw_params->num_channels; 2070 2071 ASSERT(clk_table->num_entries); 2072 2073 /* Prepass to find max clocks independent of voltage level. */ 2074 for (i = 0; i < clk_table->num_entries; ++i) { 2075 if (clk_table->entries[i].dispclk_mhz > max_dispclk_mhz) 2076 max_dispclk_mhz = clk_table->entries[i].dispclk_mhz; 2077 if (clk_table->entries[i].dppclk_mhz > max_dppclk_mhz) 2078 max_dppclk_mhz = clk_table->entries[i].dppclk_mhz; 2079 } 2080 2081 for (i = 0; i < clk_table->num_entries; i++) { 2082 /* loop backwards*/ 2083 for (closest_clk_lvl = 0, j = dcn3_1_soc.num_states - 1; j >= 0; j--) { 2084 if ((unsigned int) dcn3_1_soc.clock_limits[j].dcfclk_mhz <= clk_table->entries[i].dcfclk_mhz) { 2085 closest_clk_lvl = j; 2086 break; 2087 } 2088 } 2089 2090 clock_limits[i].state = i; 2091 2092 /* Clocks dependent on voltage level. */ 2093 clock_limits[i].dcfclk_mhz = clk_table->entries[i].dcfclk_mhz; 2094 clock_limits[i].fabricclk_mhz = clk_table->entries[i].fclk_mhz; 2095 clock_limits[i].socclk_mhz = clk_table->entries[i].socclk_mhz; 2096 clock_limits[i].dram_speed_mts = clk_table->entries[i].memclk_mhz * 2 * clk_table->entries[i].wck_ratio; 2097 2098 /* Clocks independent of voltage level. */ 2099 clock_limits[i].dispclk_mhz = max_dispclk_mhz ? max_dispclk_mhz : 2100 dcn3_1_soc.clock_limits[closest_clk_lvl].dispclk_mhz; 2101 2102 clock_limits[i].dppclk_mhz = max_dppclk_mhz ? max_dppclk_mhz : 2103 dcn3_1_soc.clock_limits[closest_clk_lvl].dppclk_mhz; 2104 2105 clock_limits[i].dram_bw_per_chan_gbps = dcn3_1_soc.clock_limits[closest_clk_lvl].dram_bw_per_chan_gbps; 2106 clock_limits[i].dscclk_mhz = dcn3_1_soc.clock_limits[closest_clk_lvl].dscclk_mhz; 2107 clock_limits[i].dtbclk_mhz = dcn3_1_soc.clock_limits[closest_clk_lvl].dtbclk_mhz; 2108 clock_limits[i].phyclk_d18_mhz = dcn3_1_soc.clock_limits[closest_clk_lvl].phyclk_d18_mhz; 2109 clock_limits[i].phyclk_mhz = dcn3_1_soc.clock_limits[closest_clk_lvl].phyclk_mhz; 2110 } 2111 for (i = 0; i < clk_table->num_entries; i++) 2112 dcn3_1_soc.clock_limits[i] = clock_limits[i]; 2113 if (clk_table->num_entries) { 2114 dcn3_1_soc.num_states = clk_table->num_entries; 2115 } 2116 } 2117 2118 dcn3_1_soc.dispclk_dppclk_vco_speed_mhz = dc->clk_mgr->dentist_vco_freq_khz / 1000.0; 2119 dc->dml.soc.dispclk_dppclk_vco_speed_mhz = dc->clk_mgr->dentist_vco_freq_khz / 1000.0; 2120 2121 if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) 2122 dml_init_instance(&dc->dml, &dcn3_1_soc, &dcn3_1_ip, DML_PROJECT_DCN31); 2123 else 2124 dml_init_instance(&dc->dml, &dcn3_1_soc, &dcn3_1_ip, DML_PROJECT_DCN31_FPGA); 2125 } 2126 2127 static struct resource_funcs dcn31_res_pool_funcs = { 2128 .destroy = dcn31_destroy_resource_pool, 2129 .link_enc_create = dcn31_link_encoder_create, 2130 .link_enc_create_minimal = dcn31_link_enc_create_minimal, 2131 .link_encs_assign = link_enc_cfg_link_encs_assign, 2132 .link_enc_unassign = link_enc_cfg_link_enc_unassign, 2133 .panel_cntl_create = dcn31_panel_cntl_create, 2134 .validate_bandwidth = dcn31_validate_bandwidth, 2135 .calculate_wm_and_dlg = dcn31_calculate_wm_and_dlg, 2136 .update_soc_for_wm_a = dcn31_update_soc_for_wm_a, 2137 .populate_dml_pipes = dcn31_populate_dml_pipes_from_context, 2138 .acquire_idle_pipe_for_layer = dcn20_acquire_idle_pipe_for_layer, 2139 .add_stream_to_ctx = dcn30_add_stream_to_ctx, 2140 .add_dsc_to_stream_resource = dcn20_add_dsc_to_stream_resource, 2141 .remove_stream_from_ctx = dcn20_remove_stream_from_ctx, 2142 .populate_dml_writeback_from_context = dcn30_populate_dml_writeback_from_context, 2143 .set_mcif_arb_params = dcn30_set_mcif_arb_params, 2144 .find_first_free_match_stream_enc_for_link = dcn10_find_first_free_match_stream_enc_for_link, 2145 .acquire_post_bldn_3dlut = dcn30_acquire_post_bldn_3dlut, 2146 .release_post_bldn_3dlut = dcn30_release_post_bldn_3dlut, 2147 .update_bw_bounding_box = dcn31_update_bw_bounding_box, 2148 .patch_unknown_plane_state = dcn20_patch_unknown_plane_state, 2149 }; 2150 2151 static struct clock_source *dcn30_clock_source_create( 2152 struct dc_context *ctx, 2153 struct dc_bios *bios, 2154 enum clock_source_id id, 2155 const struct dce110_clk_src_regs *regs, 2156 bool dp_clk_src) 2157 { 2158 struct dce110_clk_src *clk_src = 2159 kzalloc(sizeof(struct dce110_clk_src), GFP_KERNEL); 2160 2161 if (!clk_src) 2162 return NULL; 2163 2164 if (dcn3_clk_src_construct(clk_src, ctx, bios, id, 2165 regs, &cs_shift, &cs_mask)) { 2166 clk_src->base.dp_clk_src = dp_clk_src; 2167 return &clk_src->base; 2168 } 2169 2170 BREAK_TO_DEBUGGER(); 2171 return NULL; 2172 } 2173 2174 static bool dcn31_resource_construct( 2175 uint8_t num_virtual_links, 2176 struct dc *dc, 2177 struct dcn31_resource_pool *pool) 2178 { 2179 int i; 2180 struct dc_context *ctx = dc->ctx; 2181 struct irq_service_init_data init_data; 2182 2183 DC_FP_START(); 2184 2185 ctx->dc_bios->regs = &bios_regs; 2186 2187 pool->base.res_cap = &res_cap_dcn31; 2188 2189 pool->base.funcs = &dcn31_res_pool_funcs; 2190 2191 /************************************************* 2192 * Resource + asic cap harcoding * 2193 *************************************************/ 2194 pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE; 2195 pool->base.pipe_count = pool->base.res_cap->num_timing_generator; 2196 pool->base.mpcc_count = pool->base.res_cap->num_timing_generator; 2197 dc->caps.max_downscale_ratio = 600; 2198 dc->caps.i2c_speed_in_khz = 100; 2199 dc->caps.i2c_speed_in_khz_hdcp = 5; /*1.4 w/a applied by default*/ 2200 dc->caps.max_cursor_size = 256; 2201 dc->caps.min_horizontal_blanking_period = 80; 2202 dc->caps.dmdata_alloc_size = 2048; 2203 2204 dc->caps.max_slave_planes = 1; 2205 dc->caps.max_slave_yuv_planes = 1; 2206 dc->caps.max_slave_rgb_planes = 1; 2207 dc->caps.post_blend_color_processing = true; 2208 dc->caps.force_dp_tps4_for_cp2520 = true; 2209 dc->caps.dp_hpo = true; 2210 dc->caps.extended_aux_timeout_support = true; 2211 dc->caps.dmcub_support = true; 2212 dc->caps.is_apu = true; 2213 2214 /* Color pipeline capabilities */ 2215 dc->caps.color.dpp.dcn_arch = 1; 2216 dc->caps.color.dpp.input_lut_shared = 0; 2217 dc->caps.color.dpp.icsc = 1; 2218 dc->caps.color.dpp.dgam_ram = 0; // must use gamma_corr 2219 dc->caps.color.dpp.dgam_rom_caps.srgb = 1; 2220 dc->caps.color.dpp.dgam_rom_caps.bt2020 = 1; 2221 dc->caps.color.dpp.dgam_rom_caps.gamma2_2 = 1; 2222 dc->caps.color.dpp.dgam_rom_caps.pq = 1; 2223 dc->caps.color.dpp.dgam_rom_caps.hlg = 1; 2224 dc->caps.color.dpp.post_csc = 1; 2225 dc->caps.color.dpp.gamma_corr = 1; 2226 dc->caps.color.dpp.dgam_rom_for_yuv = 0; 2227 2228 dc->caps.color.dpp.hw_3d_lut = 1; 2229 dc->caps.color.dpp.ogam_ram = 1; 2230 // no OGAM ROM on DCN301 2231 dc->caps.color.dpp.ogam_rom_caps.srgb = 0; 2232 dc->caps.color.dpp.ogam_rom_caps.bt2020 = 0; 2233 dc->caps.color.dpp.ogam_rom_caps.gamma2_2 = 0; 2234 dc->caps.color.dpp.ogam_rom_caps.pq = 0; 2235 dc->caps.color.dpp.ogam_rom_caps.hlg = 0; 2236 dc->caps.color.dpp.ocsc = 0; 2237 2238 dc->caps.color.mpc.gamut_remap = 1; 2239 dc->caps.color.mpc.num_3dluts = pool->base.res_cap->num_mpc_3dlut; //2 2240 dc->caps.color.mpc.ogam_ram = 1; 2241 dc->caps.color.mpc.ogam_rom_caps.srgb = 0; 2242 dc->caps.color.mpc.ogam_rom_caps.bt2020 = 0; 2243 dc->caps.color.mpc.ogam_rom_caps.gamma2_2 = 0; 2244 dc->caps.color.mpc.ogam_rom_caps.pq = 0; 2245 dc->caps.color.mpc.ogam_rom_caps.hlg = 0; 2246 dc->caps.color.mpc.ocsc = 1; 2247 2248 /* read VBIOS LTTPR caps */ 2249 { 2250 if (ctx->dc_bios->funcs->get_lttpr_caps) { 2251 enum bp_result bp_query_result; 2252 uint8_t is_vbios_lttpr_enable = 0; 2253 2254 bp_query_result = ctx->dc_bios->funcs->get_lttpr_caps(ctx->dc_bios, &is_vbios_lttpr_enable); 2255 dc->caps.vbios_lttpr_enable = (bp_query_result == BP_RESULT_OK) && !!is_vbios_lttpr_enable; 2256 } 2257 2258 /* interop bit is implicit */ 2259 { 2260 dc->caps.vbios_lttpr_aware = true; 2261 } 2262 } 2263 2264 if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV) 2265 dc->debug = debug_defaults_drv; 2266 else if (dc->ctx->dce_environment == DCE_ENV_FPGA_MAXIMUS) { 2267 dc->debug = debug_defaults_diags; 2268 } else 2269 dc->debug = debug_defaults_diags; 2270 // Init the vm_helper 2271 if (dc->vm_helper) 2272 vm_helper_init(dc->vm_helper, 16); 2273 2274 /************************************************* 2275 * Create resources * 2276 *************************************************/ 2277 2278 /* Clock Sources for Pixel Clock*/ 2279 pool->base.clock_sources[DCN31_CLK_SRC_PLL0] = 2280 dcn30_clock_source_create(ctx, ctx->dc_bios, 2281 CLOCK_SOURCE_COMBO_PHY_PLL0, 2282 &clk_src_regs[0], false); 2283 pool->base.clock_sources[DCN31_CLK_SRC_PLL1] = 2284 dcn30_clock_source_create(ctx, ctx->dc_bios, 2285 CLOCK_SOURCE_COMBO_PHY_PLL1, 2286 &clk_src_regs[1], false); 2287 /*move phypllx_pixclk_resync to dmub next*/ 2288 if (dc->ctx->asic_id.hw_internal_rev == YELLOW_CARP_B0) { 2289 pool->base.clock_sources[DCN31_CLK_SRC_PLL2] = 2290 dcn30_clock_source_create(ctx, ctx->dc_bios, 2291 CLOCK_SOURCE_COMBO_PHY_PLL2, 2292 &clk_src_regs_b0[2], false); 2293 pool->base.clock_sources[DCN31_CLK_SRC_PLL3] = 2294 dcn30_clock_source_create(ctx, ctx->dc_bios, 2295 CLOCK_SOURCE_COMBO_PHY_PLL3, 2296 &clk_src_regs_b0[3], false); 2297 } else { 2298 pool->base.clock_sources[DCN31_CLK_SRC_PLL2] = 2299 dcn30_clock_source_create(ctx, ctx->dc_bios, 2300 CLOCK_SOURCE_COMBO_PHY_PLL2, 2301 &clk_src_regs[2], false); 2302 pool->base.clock_sources[DCN31_CLK_SRC_PLL3] = 2303 dcn30_clock_source_create(ctx, ctx->dc_bios, 2304 CLOCK_SOURCE_COMBO_PHY_PLL3, 2305 &clk_src_regs[3], false); 2306 } 2307 2308 pool->base.clock_sources[DCN31_CLK_SRC_PLL4] = 2309 dcn30_clock_source_create(ctx, ctx->dc_bios, 2310 CLOCK_SOURCE_COMBO_PHY_PLL4, 2311 &clk_src_regs[4], false); 2312 2313 pool->base.clk_src_count = DCN30_CLK_SRC_TOTAL; 2314 2315 /* todo: not reuse phy_pll registers */ 2316 pool->base.dp_clock_source = 2317 dcn31_clock_source_create(ctx, ctx->dc_bios, 2318 CLOCK_SOURCE_ID_DP_DTO, 2319 &clk_src_regs[0], true); 2320 2321 for (i = 0; i < pool->base.clk_src_count; i++) { 2322 if (pool->base.clock_sources[i] == NULL) { 2323 dm_error("DC: failed to create clock sources!\n"); 2324 BREAK_TO_DEBUGGER(); 2325 goto create_fail; 2326 } 2327 } 2328 2329 /* TODO: DCCG */ 2330 pool->base.dccg = dccg31_create(ctx, &dccg_regs, &dccg_shift, &dccg_mask); 2331 if (pool->base.dccg == NULL) { 2332 dm_error("DC: failed to create dccg!\n"); 2333 BREAK_TO_DEBUGGER(); 2334 goto create_fail; 2335 } 2336 2337 /* TODO: IRQ */ 2338 init_data.ctx = dc->ctx; 2339 pool->base.irqs = dal_irq_service_dcn31_create(&init_data); 2340 if (!pool->base.irqs) 2341 goto create_fail; 2342 2343 /* HUBBUB */ 2344 pool->base.hubbub = dcn31_hubbub_create(ctx); 2345 if (pool->base.hubbub == NULL) { 2346 BREAK_TO_DEBUGGER(); 2347 dm_error("DC: failed to create hubbub!\n"); 2348 goto create_fail; 2349 } 2350 2351 /* HUBPs, DPPs, OPPs and TGs */ 2352 for (i = 0; i < pool->base.pipe_count; i++) { 2353 pool->base.hubps[i] = dcn31_hubp_create(ctx, i); 2354 if (pool->base.hubps[i] == NULL) { 2355 BREAK_TO_DEBUGGER(); 2356 dm_error( 2357 "DC: failed to create hubps!\n"); 2358 goto create_fail; 2359 } 2360 2361 pool->base.dpps[i] = dcn31_dpp_create(ctx, i); 2362 if (pool->base.dpps[i] == NULL) { 2363 BREAK_TO_DEBUGGER(); 2364 dm_error( 2365 "DC: failed to create dpps!\n"); 2366 goto create_fail; 2367 } 2368 } 2369 2370 for (i = 0; i < pool->base.res_cap->num_opp; i++) { 2371 pool->base.opps[i] = dcn31_opp_create(ctx, i); 2372 if (pool->base.opps[i] == NULL) { 2373 BREAK_TO_DEBUGGER(); 2374 dm_error( 2375 "DC: failed to create output pixel processor!\n"); 2376 goto create_fail; 2377 } 2378 } 2379 2380 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { 2381 pool->base.timing_generators[i] = dcn31_timing_generator_create( 2382 ctx, i); 2383 if (pool->base.timing_generators[i] == NULL) { 2384 BREAK_TO_DEBUGGER(); 2385 dm_error("DC: failed to create tg!\n"); 2386 goto create_fail; 2387 } 2388 } 2389 pool->base.timing_generator_count = i; 2390 2391 /* PSR */ 2392 pool->base.psr = dmub_psr_create(ctx); 2393 if (pool->base.psr == NULL) { 2394 dm_error("DC: failed to create psr obj!\n"); 2395 BREAK_TO_DEBUGGER(); 2396 goto create_fail; 2397 } 2398 2399 /* ABM */ 2400 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { 2401 pool->base.multiple_abms[i] = dmub_abm_create(ctx, 2402 &abm_regs[i], 2403 &abm_shift, 2404 &abm_mask); 2405 if (pool->base.multiple_abms[i] == NULL) { 2406 dm_error("DC: failed to create abm for pipe %d!\n", i); 2407 BREAK_TO_DEBUGGER(); 2408 goto create_fail; 2409 } 2410 } 2411 2412 /* MPC and DSC */ 2413 pool->base.mpc = dcn31_mpc_create(ctx, pool->base.mpcc_count, pool->base.res_cap->num_mpc_3dlut); 2414 if (pool->base.mpc == NULL) { 2415 BREAK_TO_DEBUGGER(); 2416 dm_error("DC: failed to create mpc!\n"); 2417 goto create_fail; 2418 } 2419 2420 for (i = 0; i < pool->base.res_cap->num_dsc; i++) { 2421 pool->base.dscs[i] = dcn31_dsc_create(ctx, i); 2422 if (pool->base.dscs[i] == NULL) { 2423 BREAK_TO_DEBUGGER(); 2424 dm_error("DC: failed to create display stream compressor %d!\n", i); 2425 goto create_fail; 2426 } 2427 } 2428 2429 /* DWB and MMHUBBUB */ 2430 if (!dcn31_dwbc_create(ctx, &pool->base)) { 2431 BREAK_TO_DEBUGGER(); 2432 dm_error("DC: failed to create dwbc!\n"); 2433 goto create_fail; 2434 } 2435 2436 if (!dcn31_mmhubbub_create(ctx, &pool->base)) { 2437 BREAK_TO_DEBUGGER(); 2438 dm_error("DC: failed to create mcif_wb!\n"); 2439 goto create_fail; 2440 } 2441 2442 /* AUX and I2C */ 2443 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { 2444 pool->base.engines[i] = dcn31_aux_engine_create(ctx, i); 2445 if (pool->base.engines[i] == NULL) { 2446 BREAK_TO_DEBUGGER(); 2447 dm_error( 2448 "DC:failed to create aux engine!!\n"); 2449 goto create_fail; 2450 } 2451 pool->base.hw_i2cs[i] = dcn31_i2c_hw_create(ctx, i); 2452 if (pool->base.hw_i2cs[i] == NULL) { 2453 BREAK_TO_DEBUGGER(); 2454 dm_error( 2455 "DC:failed to create hw i2c!!\n"); 2456 goto create_fail; 2457 } 2458 pool->base.sw_i2cs[i] = NULL; 2459 } 2460 2461 if (dc->ctx->asic_id.chip_family == FAMILY_YELLOW_CARP && 2462 dc->ctx->asic_id.hw_internal_rev == YELLOW_CARP_B0 && 2463 !dc->debug.dpia_debug.bits.disable_dpia) { 2464 /* YELLOW CARP B0 has 4 DPIA's */ 2465 pool->base.usb4_dpia_count = 4; 2466 } 2467 2468 /* Audio, Stream Encoders including HPO and virtual, MPC 3D LUTs */ 2469 if (!resource_construct(num_virtual_links, dc, &pool->base, 2470 (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment) ? 2471 &res_create_funcs : &res_create_maximus_funcs))) 2472 goto create_fail; 2473 2474 /* HW Sequencer and Plane caps */ 2475 dcn31_hw_sequencer_construct(dc); 2476 2477 dc->caps.max_planes = pool->base.pipe_count; 2478 2479 for (i = 0; i < dc->caps.max_planes; ++i) 2480 dc->caps.planes[i] = plane_cap; 2481 2482 dc->cap_funcs = cap_funcs; 2483 2484 dc->dcn_ip->max_num_dpp = dcn3_1_ip.max_num_dpp; 2485 2486 DC_FP_END(); 2487 2488 return true; 2489 2490 create_fail: 2491 2492 DC_FP_END(); 2493 dcn31_resource_destruct(pool); 2494 2495 return false; 2496 } 2497 2498 struct resource_pool *dcn31_create_resource_pool( 2499 const struct dc_init_data *init_data, 2500 struct dc *dc) 2501 { 2502 struct dcn31_resource_pool *pool = 2503 kzalloc(sizeof(struct dcn31_resource_pool), GFP_KERNEL); 2504 2505 if (!pool) 2506 return NULL; 2507 2508 if (dcn31_resource_construct(init_data->num_virtual_links, dc, pool)) 2509 return &pool->base; 2510 2511 BREAK_TO_DEBUGGER(); 2512 kfree(pool); 2513 return NULL; 2514 } 2515