1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 27 #include "dm_services.h" 28 #include "dc.h" 29 30 #include "dcn31/dcn31_init.h" 31 32 #include "resource.h" 33 #include "include/irq_service_interface.h" 34 #include "dcn31_resource.h" 35 36 #include "dcn20/dcn20_resource.h" 37 #include "dcn30/dcn30_resource.h" 38 39 #include "dcn10/dcn10_ipp.h" 40 #include "dcn30/dcn30_hubbub.h" 41 #include "dcn31/dcn31_hubbub.h" 42 #include "dcn30/dcn30_mpc.h" 43 #include "dcn31/dcn31_hubp.h" 44 #include "irq/dcn31/irq_service_dcn31.h" 45 #include "dcn30/dcn30_dpp.h" 46 #include "dcn31/dcn31_optc.h" 47 #include "dcn20/dcn20_hwseq.h" 48 #include "dcn30/dcn30_hwseq.h" 49 #include "dce110/dce110_hw_sequencer.h" 50 #include "dcn30/dcn30_opp.h" 51 #include "dcn20/dcn20_dsc.h" 52 #include "dcn30/dcn30_vpg.h" 53 #include "dcn30/dcn30_afmt.h" 54 #include "dcn30/dcn30_dio_stream_encoder.h" 55 #include "dcn31/dcn31_hpo_dp_stream_encoder.h" 56 #include "dcn31/dcn31_hpo_dp_link_encoder.h" 57 #include "dcn31/dcn31_apg.h" 58 #include "dcn31/dcn31_dio_link_encoder.h" 59 #include "dcn31/dcn31_vpg.h" 60 #include "dcn31/dcn31_afmt.h" 61 #include "dce/dce_clock_source.h" 62 #include "dce/dce_audio.h" 63 #include "dce/dce_hwseq.h" 64 #include "clk_mgr.h" 65 #include "virtual/virtual_stream_encoder.h" 66 #include "dce110/dce110_resource.h" 67 #include "dml/display_mode_vba.h" 68 #include "dcn31/dcn31_dccg.h" 69 #include "dcn10/dcn10_resource.h" 70 #include "dcn31_panel_cntl.h" 71 72 #include "dcn30/dcn30_dwb.h" 73 #include "dcn30/dcn30_mmhubbub.h" 74 75 // TODO: change include headers /amd/include/asic_reg after upstream 76 #include "yellow_carp_offset.h" 77 #include "dcn/dcn_3_1_2_offset.h" 78 #include "dcn/dcn_3_1_2_sh_mask.h" 79 #include "nbio/nbio_7_2_0_offset.h" 80 #include "dpcs/dpcs_4_2_0_offset.h" 81 #include "dpcs/dpcs_4_2_0_sh_mask.h" 82 #include "mmhub/mmhub_2_3_0_offset.h" 83 #include "mmhub/mmhub_2_3_0_sh_mask.h" 84 85 86 #define regDCHUBBUB_DEBUG_CTRL_0 0x04d6 87 #define regDCHUBBUB_DEBUG_CTRL_0_BASE_IDX 2 88 #define DCHUBBUB_DEBUG_CTRL_0__DET_DEPTH__SHIFT 0x10 89 #define DCHUBBUB_DEBUG_CTRL_0__DET_DEPTH_MASK 0x01FF0000L 90 91 #include "reg_helper.h" 92 #include "dce/dmub_abm.h" 93 #include "dce/dmub_psr.h" 94 #include "dce/dce_aux.h" 95 #include "dce/dce_i2c.h" 96 97 #include "dml/dcn30/display_mode_vba_30.h" 98 #include "vm_helper.h" 99 #include "dcn20/dcn20_vmid.h" 100 101 #include "link_enc_cfg.h" 102 103 #define DC_LOGGER_INIT(logger) 104 105 #define DCN3_1_DEFAULT_DET_SIZE 384 106 107 struct _vcs_dpi_ip_params_st dcn3_1_ip = { 108 .gpuvm_enable = 1, 109 .gpuvm_max_page_table_levels = 1, 110 .hostvm_enable = 1, 111 .hostvm_max_page_table_levels = 2, 112 .rob_buffer_size_kbytes = 64, 113 .det_buffer_size_kbytes = DCN3_1_DEFAULT_DET_SIZE, 114 .config_return_buffer_size_in_kbytes = 1792, 115 .compressed_buffer_segment_size_in_kbytes = 64, 116 .meta_fifo_size_in_kentries = 32, 117 .zero_size_buffer_entries = 512, 118 .compbuf_reserved_space_64b = 256, 119 .compbuf_reserved_space_zs = 64, 120 .dpp_output_buffer_pixels = 2560, 121 .opp_output_buffer_lines = 1, 122 .pixel_chunk_size_kbytes = 8, 123 .meta_chunk_size_kbytes = 2, 124 .min_meta_chunk_size_bytes = 256, 125 .writeback_chunk_size_kbytes = 8, 126 .ptoi_supported = false, 127 .num_dsc = 3, 128 .maximum_dsc_bits_per_component = 10, 129 .dsc422_native_support = false, 130 .is_line_buffer_bpp_fixed = true, 131 .line_buffer_fixed_bpp = 48, 132 .line_buffer_size_bits = 789504, 133 .max_line_buffer_lines = 12, 134 .writeback_interface_buffer_size_kbytes = 90, 135 .max_num_dpp = 4, 136 .max_num_otg = 4, 137 .max_num_hdmi_frl_outputs = 1, 138 .max_num_wb = 1, 139 .max_dchub_pscl_bw_pix_per_clk = 4, 140 .max_pscl_lb_bw_pix_per_clk = 2, 141 .max_lb_vscl_bw_pix_per_clk = 4, 142 .max_vscl_hscl_bw_pix_per_clk = 4, 143 .max_hscl_ratio = 6, 144 .max_vscl_ratio = 6, 145 .max_hscl_taps = 8, 146 .max_vscl_taps = 8, 147 .dpte_buffer_size_in_pte_reqs_luma = 64, 148 .dpte_buffer_size_in_pte_reqs_chroma = 34, 149 .dispclk_ramp_margin_percent = 1, 150 .max_inter_dcn_tile_repeaters = 8, 151 .cursor_buffer_size = 16, 152 .cursor_chunk_size = 2, 153 .writeback_line_buffer_buffer_size = 0, 154 .writeback_min_hscl_ratio = 1, 155 .writeback_min_vscl_ratio = 1, 156 .writeback_max_hscl_ratio = 1, 157 .writeback_max_vscl_ratio = 1, 158 .writeback_max_hscl_taps = 1, 159 .writeback_max_vscl_taps = 1, 160 .dppclk_delay_subtotal = 46, 161 .dppclk_delay_scl = 50, 162 .dppclk_delay_scl_lb_only = 16, 163 .dppclk_delay_cnvc_formatter = 27, 164 .dppclk_delay_cnvc_cursor = 6, 165 .dispclk_delay_subtotal = 119, 166 .dynamic_metadata_vm_enabled = false, 167 .odm_combine_4to1_supported = false, 168 .dcc_supported = true, 169 }; 170 171 struct _vcs_dpi_soc_bounding_box_st dcn3_1_soc = { 172 /*TODO: correct dispclk/dppclk voltage level determination*/ 173 .clock_limits = { 174 { 175 .state = 0, 176 .dispclk_mhz = 1200.0, 177 .dppclk_mhz = 1200.0, 178 .phyclk_mhz = 600.0, 179 .phyclk_d18_mhz = 667.0, 180 .dscclk_mhz = 186.0, 181 .dtbclk_mhz = 625.0, 182 }, 183 { 184 .state = 1, 185 .dispclk_mhz = 1200.0, 186 .dppclk_mhz = 1200.0, 187 .phyclk_mhz = 810.0, 188 .phyclk_d18_mhz = 667.0, 189 .dscclk_mhz = 209.0, 190 .dtbclk_mhz = 625.0, 191 }, 192 { 193 .state = 2, 194 .dispclk_mhz = 1200.0, 195 .dppclk_mhz = 1200.0, 196 .phyclk_mhz = 810.0, 197 .phyclk_d18_mhz = 667.0, 198 .dscclk_mhz = 209.0, 199 .dtbclk_mhz = 625.0, 200 }, 201 { 202 .state = 3, 203 .dispclk_mhz = 1200.0, 204 .dppclk_mhz = 1200.0, 205 .phyclk_mhz = 810.0, 206 .phyclk_d18_mhz = 667.0, 207 .dscclk_mhz = 371.0, 208 .dtbclk_mhz = 625.0, 209 }, 210 { 211 .state = 4, 212 .dispclk_mhz = 1200.0, 213 .dppclk_mhz = 1200.0, 214 .phyclk_mhz = 810.0, 215 .phyclk_d18_mhz = 667.0, 216 .dscclk_mhz = 417.0, 217 .dtbclk_mhz = 625.0, 218 }, 219 }, 220 .num_states = 5, 221 .sr_exit_time_us = 9.0, 222 .sr_enter_plus_exit_time_us = 11.0, 223 .sr_exit_z8_time_us = 442.0, 224 .sr_enter_plus_exit_z8_time_us = 560.0, 225 .writeback_latency_us = 12.0, 226 .dram_channel_width_bytes = 4, 227 .round_trip_ping_latency_dcfclk_cycles = 106, 228 .urgent_latency_pixel_data_only_us = 4.0, 229 .urgent_latency_pixel_mixed_with_vm_data_us = 4.0, 230 .urgent_latency_vm_data_only_us = 4.0, 231 .urgent_out_of_order_return_per_channel_pixel_only_bytes = 4096, 232 .urgent_out_of_order_return_per_channel_pixel_and_vm_bytes = 4096, 233 .urgent_out_of_order_return_per_channel_vm_only_bytes = 4096, 234 .pct_ideal_sdp_bw_after_urgent = 80.0, 235 .pct_ideal_dram_sdp_bw_after_urgent_pixel_only = 65.0, 236 .pct_ideal_dram_sdp_bw_after_urgent_pixel_and_vm = 60.0, 237 .pct_ideal_dram_sdp_bw_after_urgent_vm_only = 30.0, 238 .max_avg_sdp_bw_use_normal_percent = 60.0, 239 .max_avg_dram_bw_use_normal_percent = 60.0, 240 .fabric_datapath_to_dcn_data_return_bytes = 32, 241 .return_bus_width_bytes = 64, 242 .downspread_percent = 0.38, 243 .dcn_downspread_percent = 0.5, 244 .gpuvm_min_page_size_bytes = 4096, 245 .hostvm_min_page_size_bytes = 4096, 246 .do_urgent_latency_adjustment = false, 247 .urgent_latency_adjustment_fabric_clock_component_us = 0, 248 .urgent_latency_adjustment_fabric_clock_reference_mhz = 0, 249 }; 250 251 enum dcn31_clk_src_array_id { 252 DCN31_CLK_SRC_PLL0, 253 DCN31_CLK_SRC_PLL1, 254 DCN31_CLK_SRC_PLL2, 255 DCN31_CLK_SRC_PLL3, 256 DCN31_CLK_SRC_PLL4, 257 DCN30_CLK_SRC_TOTAL 258 }; 259 260 /* begin ********************* 261 * macros to expend register list macro defined in HW object header file 262 */ 263 264 /* DCN */ 265 /* TODO awful hack. fixup dcn20_dwb.h */ 266 #undef BASE_INNER 267 #define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg 268 269 #define BASE(seg) BASE_INNER(seg) 270 271 #define SR(reg_name)\ 272 .reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \ 273 reg ## reg_name 274 275 #define SRI(reg_name, block, id)\ 276 .reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 277 reg ## block ## id ## _ ## reg_name 278 279 #define SRI2(reg_name, block, id)\ 280 .reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \ 281 reg ## reg_name 282 283 #define SRIR(var_name, reg_name, block, id)\ 284 .var_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 285 reg ## block ## id ## _ ## reg_name 286 287 #define SRII(reg_name, block, id)\ 288 .reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 289 reg ## block ## id ## _ ## reg_name 290 291 #define SRII_MPC_RMU(reg_name, block, id)\ 292 .RMU##_##reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 293 reg ## block ## id ## _ ## reg_name 294 295 #define SRII_DWB(reg_name, temp_name, block, id)\ 296 .reg_name[id] = BASE(reg ## block ## id ## _ ## temp_name ## _BASE_IDX) + \ 297 reg ## block ## id ## _ ## temp_name 298 299 #define DCCG_SRII(reg_name, block, id)\ 300 .block ## _ ## reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 301 reg ## block ## id ## _ ## reg_name 302 303 #define VUPDATE_SRII(reg_name, block, id)\ 304 .reg_name[id] = BASE(reg ## reg_name ## _ ## block ## id ## _BASE_IDX) + \ 305 reg ## reg_name ## _ ## block ## id 306 307 /* NBIO */ 308 #define NBIO_BASE_INNER(seg) \ 309 NBIO_BASE__INST0_SEG ## seg 310 311 #define NBIO_BASE(seg) \ 312 NBIO_BASE_INNER(seg) 313 314 #define NBIO_SR(reg_name)\ 315 .reg_name = NBIO_BASE(regBIF_BX1_ ## reg_name ## _BASE_IDX) + \ 316 regBIF_BX1_ ## reg_name 317 318 /* MMHUB */ 319 #define MMHUB_BASE_INNER(seg) \ 320 MMHUB_BASE__INST0_SEG ## seg 321 322 #define MMHUB_BASE(seg) \ 323 MMHUB_BASE_INNER(seg) 324 325 #define MMHUB_SR(reg_name)\ 326 .reg_name = MMHUB_BASE(mm ## reg_name ## _BASE_IDX) + \ 327 mm ## reg_name 328 329 /* CLOCK */ 330 #define CLK_BASE_INNER(seg) \ 331 CLK_BASE__INST0_SEG ## seg 332 333 #define CLK_BASE(seg) \ 334 CLK_BASE_INNER(seg) 335 336 #define CLK_SRI(reg_name, block, inst)\ 337 .reg_name = CLK_BASE(reg ## block ## _ ## inst ## _ ## reg_name ## _BASE_IDX) + \ 338 reg ## block ## _ ## inst ## _ ## reg_name 339 340 341 static const struct bios_registers bios_regs = { 342 NBIO_SR(BIOS_SCRATCH_3), 343 NBIO_SR(BIOS_SCRATCH_6) 344 }; 345 346 #define clk_src_regs(index, pllid)\ 347 [index] = {\ 348 CS_COMMON_REG_LIST_DCN3_0(index, pllid),\ 349 } 350 351 static const struct dce110_clk_src_regs clk_src_regs[] = { 352 clk_src_regs(0, A), 353 clk_src_regs(1, B), 354 clk_src_regs(2, C), 355 clk_src_regs(3, D), 356 clk_src_regs(4, E) 357 }; 358 /*pll_id being rempped in dmub, in driver it is logical instance*/ 359 static const struct dce110_clk_src_regs clk_src_regs_b0[] = { 360 clk_src_regs(0, A), 361 clk_src_regs(1, B), 362 clk_src_regs(2, F), 363 clk_src_regs(3, G), 364 clk_src_regs(4, E) 365 }; 366 367 static const struct dce110_clk_src_shift cs_shift = { 368 CS_COMMON_MASK_SH_LIST_DCN2_0(__SHIFT) 369 }; 370 371 static const struct dce110_clk_src_mask cs_mask = { 372 CS_COMMON_MASK_SH_LIST_DCN2_0(_MASK) 373 }; 374 375 #define abm_regs(id)\ 376 [id] = {\ 377 ABM_DCN302_REG_LIST(id)\ 378 } 379 380 static const struct dce_abm_registers abm_regs[] = { 381 abm_regs(0), 382 abm_regs(1), 383 abm_regs(2), 384 abm_regs(3), 385 }; 386 387 static const struct dce_abm_shift abm_shift = { 388 ABM_MASK_SH_LIST_DCN30(__SHIFT) 389 }; 390 391 static const struct dce_abm_mask abm_mask = { 392 ABM_MASK_SH_LIST_DCN30(_MASK) 393 }; 394 395 #define audio_regs(id)\ 396 [id] = {\ 397 AUD_COMMON_REG_LIST(id)\ 398 } 399 400 static const struct dce_audio_registers audio_regs[] = { 401 audio_regs(0), 402 audio_regs(1), 403 audio_regs(2), 404 audio_regs(3), 405 audio_regs(4), 406 audio_regs(5), 407 audio_regs(6) 408 }; 409 410 #define DCE120_AUD_COMMON_MASK_SH_LIST(mask_sh)\ 411 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX, AZALIA_ENDPOINT_REG_INDEX, mask_sh),\ 412 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA, AZALIA_ENDPOINT_REG_DATA, mask_sh),\ 413 AUD_COMMON_MASK_SH_LIST_BASE(mask_sh) 414 415 static const struct dce_audio_shift audio_shift = { 416 DCE120_AUD_COMMON_MASK_SH_LIST(__SHIFT) 417 }; 418 419 static const struct dce_audio_mask audio_mask = { 420 DCE120_AUD_COMMON_MASK_SH_LIST(_MASK) 421 }; 422 423 #define vpg_regs(id)\ 424 [id] = {\ 425 VPG_DCN31_REG_LIST(id)\ 426 } 427 428 static const struct dcn31_vpg_registers vpg_regs[] = { 429 vpg_regs(0), 430 vpg_regs(1), 431 vpg_regs(2), 432 vpg_regs(3), 433 vpg_regs(4), 434 vpg_regs(5), 435 vpg_regs(6), 436 vpg_regs(7), 437 vpg_regs(8), 438 vpg_regs(9), 439 }; 440 441 static const struct dcn31_vpg_shift vpg_shift = { 442 DCN31_VPG_MASK_SH_LIST(__SHIFT) 443 }; 444 445 static const struct dcn31_vpg_mask vpg_mask = { 446 DCN31_VPG_MASK_SH_LIST(_MASK) 447 }; 448 449 #define afmt_regs(id)\ 450 [id] = {\ 451 AFMT_DCN31_REG_LIST(id)\ 452 } 453 454 static const struct dcn31_afmt_registers afmt_regs[] = { 455 afmt_regs(0), 456 afmt_regs(1), 457 afmt_regs(2), 458 afmt_regs(3), 459 afmt_regs(4), 460 afmt_regs(5) 461 }; 462 463 static const struct dcn31_afmt_shift afmt_shift = { 464 DCN31_AFMT_MASK_SH_LIST(__SHIFT) 465 }; 466 467 static const struct dcn31_afmt_mask afmt_mask = { 468 DCN31_AFMT_MASK_SH_LIST(_MASK) 469 }; 470 471 #define apg_regs(id)\ 472 [id] = {\ 473 APG_DCN31_REG_LIST(id)\ 474 } 475 476 static const struct dcn31_apg_registers apg_regs[] = { 477 apg_regs(0), 478 apg_regs(1), 479 apg_regs(2), 480 apg_regs(3) 481 }; 482 483 static const struct dcn31_apg_shift apg_shift = { 484 DCN31_APG_MASK_SH_LIST(__SHIFT) 485 }; 486 487 static const struct dcn31_apg_mask apg_mask = { 488 DCN31_APG_MASK_SH_LIST(_MASK) 489 }; 490 491 #define stream_enc_regs(id)\ 492 [id] = {\ 493 SE_DCN3_REG_LIST(id)\ 494 } 495 496 /* Some encoders won't be initialized here - but they're logical, not physical. */ 497 static const struct dcn10_stream_enc_registers stream_enc_regs[ENGINE_ID_COUNT] = { 498 stream_enc_regs(0), 499 stream_enc_regs(1), 500 stream_enc_regs(2), 501 stream_enc_regs(3), 502 stream_enc_regs(4) 503 }; 504 505 static const struct dcn10_stream_encoder_shift se_shift = { 506 SE_COMMON_MASK_SH_LIST_DCN30(__SHIFT) 507 }; 508 509 static const struct dcn10_stream_encoder_mask se_mask = { 510 SE_COMMON_MASK_SH_LIST_DCN30(_MASK) 511 }; 512 513 514 #define aux_regs(id)\ 515 [id] = {\ 516 DCN2_AUX_REG_LIST(id)\ 517 } 518 519 static const struct dcn10_link_enc_aux_registers link_enc_aux_regs[] = { 520 aux_regs(0), 521 aux_regs(1), 522 aux_regs(2), 523 aux_regs(3), 524 aux_regs(4) 525 }; 526 527 #define hpd_regs(id)\ 528 [id] = {\ 529 HPD_REG_LIST(id)\ 530 } 531 532 static const struct dcn10_link_enc_hpd_registers link_enc_hpd_regs[] = { 533 hpd_regs(0), 534 hpd_regs(1), 535 hpd_regs(2), 536 hpd_regs(3), 537 hpd_regs(4) 538 }; 539 540 #define link_regs(id, phyid)\ 541 [id] = {\ 542 LE_DCN31_REG_LIST(id), \ 543 UNIPHY_DCN2_REG_LIST(phyid), \ 544 DPCS_DCN31_REG_LIST(id), \ 545 } 546 547 static const struct dce110_aux_registers_shift aux_shift = { 548 DCN_AUX_MASK_SH_LIST(__SHIFT) 549 }; 550 551 static const struct dce110_aux_registers_mask aux_mask = { 552 DCN_AUX_MASK_SH_LIST(_MASK) 553 }; 554 555 static const struct dcn10_link_enc_registers link_enc_regs[] = { 556 link_regs(0, A), 557 link_regs(1, B), 558 link_regs(2, C), 559 link_regs(3, D), 560 link_regs(4, E) 561 }; 562 563 static const struct dcn10_link_enc_shift le_shift = { 564 LINK_ENCODER_MASK_SH_LIST_DCN31(__SHIFT), \ 565 DPCS_DCN31_MASK_SH_LIST(__SHIFT) 566 }; 567 568 static const struct dcn10_link_enc_mask le_mask = { 569 LINK_ENCODER_MASK_SH_LIST_DCN31(_MASK), \ 570 DPCS_DCN31_MASK_SH_LIST(_MASK) 571 }; 572 573 #define hpo_dp_stream_encoder_reg_list(id)\ 574 [id] = {\ 575 DCN3_1_HPO_DP_STREAM_ENC_REG_LIST(id)\ 576 } 577 578 static const struct dcn31_hpo_dp_stream_encoder_registers hpo_dp_stream_enc_regs[] = { 579 hpo_dp_stream_encoder_reg_list(0), 580 hpo_dp_stream_encoder_reg_list(1), 581 hpo_dp_stream_encoder_reg_list(2), 582 hpo_dp_stream_encoder_reg_list(3), 583 }; 584 585 static const struct dcn31_hpo_dp_stream_encoder_shift hpo_dp_se_shift = { 586 DCN3_1_HPO_DP_STREAM_ENC_MASK_SH_LIST(__SHIFT) 587 }; 588 589 static const struct dcn31_hpo_dp_stream_encoder_mask hpo_dp_se_mask = { 590 DCN3_1_HPO_DP_STREAM_ENC_MASK_SH_LIST(_MASK) 591 }; 592 593 #define hpo_dp_link_encoder_reg_list(id)\ 594 [id] = {\ 595 DCN3_1_HPO_DP_LINK_ENC_REG_LIST(id),\ 596 DCN3_1_RDPCSTX_REG_LIST(0),\ 597 DCN3_1_RDPCSTX_REG_LIST(1),\ 598 DCN3_1_RDPCSTX_REG_LIST(2),\ 599 DCN3_1_RDPCSTX_REG_LIST(3),\ 600 DCN3_1_RDPCSTX_REG_LIST(4)\ 601 } 602 603 static const struct dcn31_hpo_dp_link_encoder_registers hpo_dp_link_enc_regs[] = { 604 hpo_dp_link_encoder_reg_list(0), 605 hpo_dp_link_encoder_reg_list(1), 606 }; 607 608 static const struct dcn31_hpo_dp_link_encoder_shift hpo_dp_le_shift = { 609 DCN3_1_HPO_DP_LINK_ENC_MASK_SH_LIST(__SHIFT) 610 }; 611 612 static const struct dcn31_hpo_dp_link_encoder_mask hpo_dp_le_mask = { 613 DCN3_1_HPO_DP_LINK_ENC_MASK_SH_LIST(_MASK) 614 }; 615 616 #define dpp_regs(id)\ 617 [id] = {\ 618 DPP_REG_LIST_DCN30(id),\ 619 } 620 621 static const struct dcn3_dpp_registers dpp_regs[] = { 622 dpp_regs(0), 623 dpp_regs(1), 624 dpp_regs(2), 625 dpp_regs(3) 626 }; 627 628 static const struct dcn3_dpp_shift tf_shift = { 629 DPP_REG_LIST_SH_MASK_DCN30(__SHIFT) 630 }; 631 632 static const struct dcn3_dpp_mask tf_mask = { 633 DPP_REG_LIST_SH_MASK_DCN30(_MASK) 634 }; 635 636 #define opp_regs(id)\ 637 [id] = {\ 638 OPP_REG_LIST_DCN30(id),\ 639 } 640 641 static const struct dcn20_opp_registers opp_regs[] = { 642 opp_regs(0), 643 opp_regs(1), 644 opp_regs(2), 645 opp_regs(3) 646 }; 647 648 static const struct dcn20_opp_shift opp_shift = { 649 OPP_MASK_SH_LIST_DCN20(__SHIFT) 650 }; 651 652 static const struct dcn20_opp_mask opp_mask = { 653 OPP_MASK_SH_LIST_DCN20(_MASK) 654 }; 655 656 #define aux_engine_regs(id)\ 657 [id] = {\ 658 AUX_COMMON_REG_LIST0(id), \ 659 .AUXN_IMPCAL = 0, \ 660 .AUXP_IMPCAL = 0, \ 661 .AUX_RESET_MASK = DP_AUX0_AUX_CONTROL__AUX_RESET_MASK, \ 662 } 663 664 static const struct dce110_aux_registers aux_engine_regs[] = { 665 aux_engine_regs(0), 666 aux_engine_regs(1), 667 aux_engine_regs(2), 668 aux_engine_regs(3), 669 aux_engine_regs(4) 670 }; 671 672 #define dwbc_regs_dcn3(id)\ 673 [id] = {\ 674 DWBC_COMMON_REG_LIST_DCN30(id),\ 675 } 676 677 static const struct dcn30_dwbc_registers dwbc30_regs[] = { 678 dwbc_regs_dcn3(0), 679 }; 680 681 static const struct dcn30_dwbc_shift dwbc30_shift = { 682 DWBC_COMMON_MASK_SH_LIST_DCN30(__SHIFT) 683 }; 684 685 static const struct dcn30_dwbc_mask dwbc30_mask = { 686 DWBC_COMMON_MASK_SH_LIST_DCN30(_MASK) 687 }; 688 689 #define mcif_wb_regs_dcn3(id)\ 690 [id] = {\ 691 MCIF_WB_COMMON_REG_LIST_DCN30(id),\ 692 } 693 694 static const struct dcn30_mmhubbub_registers mcif_wb30_regs[] = { 695 mcif_wb_regs_dcn3(0) 696 }; 697 698 static const struct dcn30_mmhubbub_shift mcif_wb30_shift = { 699 MCIF_WB_COMMON_MASK_SH_LIST_DCN30(__SHIFT) 700 }; 701 702 static const struct dcn30_mmhubbub_mask mcif_wb30_mask = { 703 MCIF_WB_COMMON_MASK_SH_LIST_DCN30(_MASK) 704 }; 705 706 #define dsc_regsDCN20(id)\ 707 [id] = {\ 708 DSC_REG_LIST_DCN20(id)\ 709 } 710 711 static const struct dcn20_dsc_registers dsc_regs[] = { 712 dsc_regsDCN20(0), 713 dsc_regsDCN20(1), 714 dsc_regsDCN20(2) 715 }; 716 717 static const struct dcn20_dsc_shift dsc_shift = { 718 DSC_REG_LIST_SH_MASK_DCN20(__SHIFT) 719 }; 720 721 static const struct dcn20_dsc_mask dsc_mask = { 722 DSC_REG_LIST_SH_MASK_DCN20(_MASK) 723 }; 724 725 static const struct dcn30_mpc_registers mpc_regs = { 726 MPC_REG_LIST_DCN3_0(0), 727 MPC_REG_LIST_DCN3_0(1), 728 MPC_REG_LIST_DCN3_0(2), 729 MPC_REG_LIST_DCN3_0(3), 730 MPC_OUT_MUX_REG_LIST_DCN3_0(0), 731 MPC_OUT_MUX_REG_LIST_DCN3_0(1), 732 MPC_OUT_MUX_REG_LIST_DCN3_0(2), 733 MPC_OUT_MUX_REG_LIST_DCN3_0(3), 734 MPC_RMU_GLOBAL_REG_LIST_DCN3AG, 735 MPC_RMU_REG_LIST_DCN3AG(0), 736 MPC_RMU_REG_LIST_DCN3AG(1), 737 //MPC_RMU_REG_LIST_DCN3AG(2), 738 MPC_DWB_MUX_REG_LIST_DCN3_0(0), 739 }; 740 741 static const struct dcn30_mpc_shift mpc_shift = { 742 MPC_COMMON_MASK_SH_LIST_DCN30(__SHIFT) 743 }; 744 745 static const struct dcn30_mpc_mask mpc_mask = { 746 MPC_COMMON_MASK_SH_LIST_DCN30(_MASK) 747 }; 748 749 #define optc_regs(id)\ 750 [id] = {OPTC_COMMON_REG_LIST_DCN3_1(id)} 751 752 static const struct dcn_optc_registers optc_regs[] = { 753 optc_regs(0), 754 optc_regs(1), 755 optc_regs(2), 756 optc_regs(3) 757 }; 758 759 static const struct dcn_optc_shift optc_shift = { 760 OPTC_COMMON_MASK_SH_LIST_DCN3_1(__SHIFT) 761 }; 762 763 static const struct dcn_optc_mask optc_mask = { 764 OPTC_COMMON_MASK_SH_LIST_DCN3_1(_MASK) 765 }; 766 767 #define hubp_regs(id)\ 768 [id] = {\ 769 HUBP_REG_LIST_DCN30(id)\ 770 } 771 772 static const struct dcn_hubp2_registers hubp_regs[] = { 773 hubp_regs(0), 774 hubp_regs(1), 775 hubp_regs(2), 776 hubp_regs(3) 777 }; 778 779 780 static const struct dcn_hubp2_shift hubp_shift = { 781 HUBP_MASK_SH_LIST_DCN31(__SHIFT) 782 }; 783 784 static const struct dcn_hubp2_mask hubp_mask = { 785 HUBP_MASK_SH_LIST_DCN31(_MASK) 786 }; 787 static const struct dcn_hubbub_registers hubbub_reg = { 788 HUBBUB_REG_LIST_DCN31(0) 789 }; 790 791 static const struct dcn_hubbub_shift hubbub_shift = { 792 HUBBUB_MASK_SH_LIST_DCN31(__SHIFT) 793 }; 794 795 static const struct dcn_hubbub_mask hubbub_mask = { 796 HUBBUB_MASK_SH_LIST_DCN31(_MASK) 797 }; 798 799 static const struct dccg_registers dccg_regs = { 800 DCCG_REG_LIST_DCN31() 801 }; 802 803 static const struct dccg_shift dccg_shift = { 804 DCCG_MASK_SH_LIST_DCN31(__SHIFT) 805 }; 806 807 static const struct dccg_mask dccg_mask = { 808 DCCG_MASK_SH_LIST_DCN31(_MASK) 809 }; 810 811 812 #define SRII2(reg_name_pre, reg_name_post, id)\ 813 .reg_name_pre ## _ ## reg_name_post[id] = BASE(reg ## reg_name_pre \ 814 ## id ## _ ## reg_name_post ## _BASE_IDX) + \ 815 reg ## reg_name_pre ## id ## _ ## reg_name_post 816 817 818 #define HWSEQ_DCN31_REG_LIST()\ 819 SR(DCHUBBUB_GLOBAL_TIMER_CNTL), \ 820 SR(DCHUBBUB_ARB_HOSTVM_CNTL), \ 821 SR(DIO_MEM_PWR_CTRL), \ 822 SR(ODM_MEM_PWR_CTRL3), \ 823 SR(DMU_MEM_PWR_CNTL), \ 824 SR(MMHUBBUB_MEM_PWR_CNTL), \ 825 SR(DCCG_GATE_DISABLE_CNTL), \ 826 SR(DCCG_GATE_DISABLE_CNTL2), \ 827 SR(DCFCLK_CNTL),\ 828 SR(DC_MEM_GLOBAL_PWR_REQ_CNTL), \ 829 SRII(PIXEL_RATE_CNTL, OTG, 0), \ 830 SRII(PIXEL_RATE_CNTL, OTG, 1),\ 831 SRII(PIXEL_RATE_CNTL, OTG, 2),\ 832 SRII(PIXEL_RATE_CNTL, OTG, 3),\ 833 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 0),\ 834 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 1),\ 835 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 2),\ 836 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 3),\ 837 SR(MICROSECOND_TIME_BASE_DIV), \ 838 SR(MILLISECOND_TIME_BASE_DIV), \ 839 SR(DISPCLK_FREQ_CHANGE_CNTL), \ 840 SR(RBBMIF_TIMEOUT_DIS), \ 841 SR(RBBMIF_TIMEOUT_DIS_2), \ 842 SR(DCHUBBUB_CRC_CTRL), \ 843 SR(DPP_TOP0_DPP_CRC_CTRL), \ 844 SR(DPP_TOP0_DPP_CRC_VAL_B_A), \ 845 SR(DPP_TOP0_DPP_CRC_VAL_R_G), \ 846 SR(MPC_CRC_CTRL), \ 847 SR(MPC_CRC_RESULT_GB), \ 848 SR(MPC_CRC_RESULT_C), \ 849 SR(MPC_CRC_RESULT_AR), \ 850 SR(DOMAIN0_PG_CONFIG), \ 851 SR(DOMAIN1_PG_CONFIG), \ 852 SR(DOMAIN2_PG_CONFIG), \ 853 SR(DOMAIN3_PG_CONFIG), \ 854 SR(DOMAIN16_PG_CONFIG), \ 855 SR(DOMAIN17_PG_CONFIG), \ 856 SR(DOMAIN18_PG_CONFIG), \ 857 SR(DOMAIN0_PG_STATUS), \ 858 SR(DOMAIN1_PG_STATUS), \ 859 SR(DOMAIN2_PG_STATUS), \ 860 SR(DOMAIN3_PG_STATUS), \ 861 SR(DOMAIN16_PG_STATUS), \ 862 SR(DOMAIN17_PG_STATUS), \ 863 SR(DOMAIN18_PG_STATUS), \ 864 SR(D1VGA_CONTROL), \ 865 SR(D2VGA_CONTROL), \ 866 SR(D3VGA_CONTROL), \ 867 SR(D4VGA_CONTROL), \ 868 SR(D5VGA_CONTROL), \ 869 SR(D6VGA_CONTROL), \ 870 SR(DC_IP_REQUEST_CNTL), \ 871 SR(AZALIA_AUDIO_DTO), \ 872 SR(AZALIA_CONTROLLER_CLOCK_GATING), \ 873 SR(HPO_TOP_HW_CONTROL) 874 875 static const struct dce_hwseq_registers hwseq_reg = { 876 HWSEQ_DCN31_REG_LIST() 877 }; 878 879 #define HWSEQ_DCN31_MASK_SH_LIST(mask_sh)\ 880 HWSEQ_DCN_MASK_SH_LIST(mask_sh), \ 881 HWS_SF(, DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_REFDIV, mask_sh), \ 882 HWS_SF(, DCHUBBUB_ARB_HOSTVM_CNTL, DISABLE_HOSTVM_FORCE_ALLOW_PSTATE, mask_sh), \ 883 HWS_SF(, DOMAIN0_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ 884 HWS_SF(, DOMAIN0_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ 885 HWS_SF(, DOMAIN1_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ 886 HWS_SF(, DOMAIN1_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ 887 HWS_SF(, DOMAIN2_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ 888 HWS_SF(, DOMAIN2_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ 889 HWS_SF(, DOMAIN3_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ 890 HWS_SF(, DOMAIN3_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ 891 HWS_SF(, DOMAIN16_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ 892 HWS_SF(, DOMAIN16_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ 893 HWS_SF(, DOMAIN17_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ 894 HWS_SF(, DOMAIN17_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ 895 HWS_SF(, DOMAIN18_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ 896 HWS_SF(, DOMAIN18_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ 897 HWS_SF(, DOMAIN0_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ 898 HWS_SF(, DOMAIN1_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ 899 HWS_SF(, DOMAIN2_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ 900 HWS_SF(, DOMAIN3_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ 901 HWS_SF(, DOMAIN16_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ 902 HWS_SF(, DOMAIN17_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ 903 HWS_SF(, DOMAIN18_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ 904 HWS_SF(, DC_IP_REQUEST_CNTL, IP_REQUEST_EN, mask_sh), \ 905 HWS_SF(, AZALIA_AUDIO_DTO, AZALIA_AUDIO_DTO_MODULE, mask_sh), \ 906 HWS_SF(, HPO_TOP_CLOCK_CONTROL, HPO_HDMISTREAMCLK_G_GATE_DIS, mask_sh), \ 907 HWS_SF(, DMU_MEM_PWR_CNTL, DMCU_ERAM_MEM_PWR_FORCE, mask_sh), \ 908 HWS_SF(, ODM_MEM_PWR_CTRL3, ODM_MEM_UNASSIGNED_PWR_MODE, mask_sh), \ 909 HWS_SF(, ODM_MEM_PWR_CTRL3, ODM_MEM_VBLANK_PWR_MODE, mask_sh), \ 910 HWS_SF(, MMHUBBUB_MEM_PWR_CNTL, VGA_MEM_PWR_FORCE, mask_sh), \ 911 HWS_SF(, DIO_MEM_PWR_CTRL, I2C_LIGHT_SLEEP_FORCE, mask_sh), \ 912 HWS_SF(, HPO_TOP_HW_CONTROL, HPO_IO_EN, mask_sh) 913 914 static const struct dce_hwseq_shift hwseq_shift = { 915 HWSEQ_DCN31_MASK_SH_LIST(__SHIFT) 916 }; 917 918 static const struct dce_hwseq_mask hwseq_mask = { 919 HWSEQ_DCN31_MASK_SH_LIST(_MASK) 920 }; 921 #define vmid_regs(id)\ 922 [id] = {\ 923 DCN20_VMID_REG_LIST(id)\ 924 } 925 926 static const struct dcn_vmid_registers vmid_regs[] = { 927 vmid_regs(0), 928 vmid_regs(1), 929 vmid_regs(2), 930 vmid_regs(3), 931 vmid_regs(4), 932 vmid_regs(5), 933 vmid_regs(6), 934 vmid_regs(7), 935 vmid_regs(8), 936 vmid_regs(9), 937 vmid_regs(10), 938 vmid_regs(11), 939 vmid_regs(12), 940 vmid_regs(13), 941 vmid_regs(14), 942 vmid_regs(15) 943 }; 944 945 static const struct dcn20_vmid_shift vmid_shifts = { 946 DCN20_VMID_MASK_SH_LIST(__SHIFT) 947 }; 948 949 static const struct dcn20_vmid_mask vmid_masks = { 950 DCN20_VMID_MASK_SH_LIST(_MASK) 951 }; 952 953 static const struct resource_caps res_cap_dcn31 = { 954 .num_timing_generator = 4, 955 .num_opp = 4, 956 .num_video_plane = 4, 957 .num_audio = 5, 958 .num_stream_encoder = 5, 959 .num_dig_link_enc = 5, 960 .num_hpo_dp_stream_encoder = 4, 961 .num_hpo_dp_link_encoder = 2, 962 .num_pll = 5, 963 .num_dwb = 1, 964 .num_ddc = 5, 965 .num_vmid = 16, 966 .num_mpc_3dlut = 2, 967 .num_dsc = 3, 968 }; 969 970 static const struct dc_plane_cap plane_cap = { 971 .type = DC_PLANE_TYPE_DCN_UNIVERSAL, 972 .blends_with_above = true, 973 .blends_with_below = true, 974 .per_pixel_alpha = true, 975 976 .pixel_format_support = { 977 .argb8888 = true, 978 .nv12 = true, 979 .fp16 = true, 980 .p010 = true, 981 .ayuv = false, 982 }, 983 984 .max_upscale_factor = { 985 .argb8888 = 16000, 986 .nv12 = 16000, 987 .fp16 = 16000 988 }, 989 990 // 6:1 downscaling ratio: 1000/6 = 166.666 991 .max_downscale_factor = { 992 .argb8888 = 167, 993 .nv12 = 167, 994 .fp16 = 167 995 }, 996 64, 997 64 998 }; 999 1000 static const struct dc_debug_options debug_defaults_drv = { 1001 .disable_dmcu = true, 1002 .force_abm_enable = false, 1003 .timing_trace = false, 1004 .clock_trace = true, 1005 .disable_pplib_clock_request = false, 1006 .pipe_split_policy = MPC_SPLIT_DYNAMIC, 1007 .force_single_disp_pipe_split = false, 1008 .disable_dcc = DCC_ENABLE, 1009 .vsr_support = true, 1010 .performance_trace = false, 1011 .max_downscale_src_width = 4096,/*upto true 4K*/ 1012 .disable_pplib_wm_range = false, 1013 .scl_reset_length10 = true, 1014 .sanity_checks = false, 1015 .underflow_assert_delay_us = 0xFFFFFFFF, 1016 .dwb_fi_phase = -1, // -1 = disable, 1017 .dmub_command_table = true, 1018 .pstate_enabled = true, 1019 .use_max_lb = true, 1020 .enable_mem_low_power = { 1021 .bits = { 1022 .vga = true, 1023 .i2c = true, 1024 .dmcu = false, // This is previously known to cause hang on S3 cycles if enabled 1025 .dscl = true, 1026 .cm = true, 1027 .mpc = true, 1028 .optc = true, 1029 .vpg = true, 1030 .afmt = true, 1031 } 1032 }, 1033 .optimize_edp_link_rate = true, 1034 .enable_sw_cntl_psr = true, 1035 .apply_vendor_specific_lttpr_wa = true, 1036 }; 1037 1038 static const struct dc_debug_options debug_defaults_diags = { 1039 .disable_dmcu = true, 1040 .force_abm_enable = false, 1041 .timing_trace = true, 1042 .clock_trace = true, 1043 .disable_dpp_power_gate = true, 1044 .disable_hubp_power_gate = true, 1045 .disable_clock_gate = true, 1046 .disable_pplib_clock_request = true, 1047 .disable_pplib_wm_range = true, 1048 .disable_stutter = false, 1049 .scl_reset_length10 = true, 1050 .dwb_fi_phase = -1, // -1 = disable 1051 .dmub_command_table = true, 1052 .enable_tri_buf = true, 1053 .use_max_lb = true 1054 }; 1055 1056 static void dcn31_dpp_destroy(struct dpp **dpp) 1057 { 1058 kfree(TO_DCN20_DPP(*dpp)); 1059 *dpp = NULL; 1060 } 1061 1062 static struct dpp *dcn31_dpp_create( 1063 struct dc_context *ctx, 1064 uint32_t inst) 1065 { 1066 struct dcn3_dpp *dpp = 1067 kzalloc(sizeof(struct dcn3_dpp), GFP_KERNEL); 1068 1069 if (!dpp) 1070 return NULL; 1071 1072 if (dpp3_construct(dpp, ctx, inst, 1073 &dpp_regs[inst], &tf_shift, &tf_mask)) 1074 return &dpp->base; 1075 1076 BREAK_TO_DEBUGGER(); 1077 kfree(dpp); 1078 return NULL; 1079 } 1080 1081 static struct output_pixel_processor *dcn31_opp_create( 1082 struct dc_context *ctx, uint32_t inst) 1083 { 1084 struct dcn20_opp *opp = 1085 kzalloc(sizeof(struct dcn20_opp), GFP_KERNEL); 1086 1087 if (!opp) { 1088 BREAK_TO_DEBUGGER(); 1089 return NULL; 1090 } 1091 1092 dcn20_opp_construct(opp, ctx, inst, 1093 &opp_regs[inst], &opp_shift, &opp_mask); 1094 return &opp->base; 1095 } 1096 1097 static struct dce_aux *dcn31_aux_engine_create( 1098 struct dc_context *ctx, 1099 uint32_t inst) 1100 { 1101 struct aux_engine_dce110 *aux_engine = 1102 kzalloc(sizeof(struct aux_engine_dce110), GFP_KERNEL); 1103 1104 if (!aux_engine) 1105 return NULL; 1106 1107 dce110_aux_engine_construct(aux_engine, ctx, inst, 1108 SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD, 1109 &aux_engine_regs[inst], 1110 &aux_mask, 1111 &aux_shift, 1112 ctx->dc->caps.extended_aux_timeout_support); 1113 1114 return &aux_engine->base; 1115 } 1116 #define i2c_inst_regs(id) { I2C_HW_ENGINE_COMMON_REG_LIST_DCN30(id) } 1117 1118 static const struct dce_i2c_registers i2c_hw_regs[] = { 1119 i2c_inst_regs(1), 1120 i2c_inst_regs(2), 1121 i2c_inst_regs(3), 1122 i2c_inst_regs(4), 1123 i2c_inst_regs(5), 1124 }; 1125 1126 static const struct dce_i2c_shift i2c_shifts = { 1127 I2C_COMMON_MASK_SH_LIST_DCN30(__SHIFT) 1128 }; 1129 1130 static const struct dce_i2c_mask i2c_masks = { 1131 I2C_COMMON_MASK_SH_LIST_DCN30(_MASK) 1132 }; 1133 1134 static struct dce_i2c_hw *dcn31_i2c_hw_create( 1135 struct dc_context *ctx, 1136 uint32_t inst) 1137 { 1138 struct dce_i2c_hw *dce_i2c_hw = 1139 kzalloc(sizeof(struct dce_i2c_hw), GFP_KERNEL); 1140 1141 if (!dce_i2c_hw) 1142 return NULL; 1143 1144 dcn2_i2c_hw_construct(dce_i2c_hw, ctx, inst, 1145 &i2c_hw_regs[inst], &i2c_shifts, &i2c_masks); 1146 1147 return dce_i2c_hw; 1148 } 1149 static struct mpc *dcn31_mpc_create( 1150 struct dc_context *ctx, 1151 int num_mpcc, 1152 int num_rmu) 1153 { 1154 struct dcn30_mpc *mpc30 = kzalloc(sizeof(struct dcn30_mpc), 1155 GFP_KERNEL); 1156 1157 if (!mpc30) 1158 return NULL; 1159 1160 dcn30_mpc_construct(mpc30, ctx, 1161 &mpc_regs, 1162 &mpc_shift, 1163 &mpc_mask, 1164 num_mpcc, 1165 num_rmu); 1166 1167 return &mpc30->base; 1168 } 1169 1170 static struct hubbub *dcn31_hubbub_create(struct dc_context *ctx) 1171 { 1172 int i; 1173 1174 struct dcn20_hubbub *hubbub3 = kzalloc(sizeof(struct dcn20_hubbub), 1175 GFP_KERNEL); 1176 1177 if (!hubbub3) 1178 return NULL; 1179 1180 hubbub31_construct(hubbub3, ctx, 1181 &hubbub_reg, 1182 &hubbub_shift, 1183 &hubbub_mask, 1184 dcn3_1_ip.det_buffer_size_kbytes, 1185 dcn3_1_ip.pixel_chunk_size_kbytes, 1186 dcn3_1_ip.config_return_buffer_size_in_kbytes); 1187 1188 1189 for (i = 0; i < res_cap_dcn31.num_vmid; i++) { 1190 struct dcn20_vmid *vmid = &hubbub3->vmid[i]; 1191 1192 vmid->ctx = ctx; 1193 1194 vmid->regs = &vmid_regs[i]; 1195 vmid->shifts = &vmid_shifts; 1196 vmid->masks = &vmid_masks; 1197 } 1198 1199 return &hubbub3->base; 1200 } 1201 1202 static struct timing_generator *dcn31_timing_generator_create( 1203 struct dc_context *ctx, 1204 uint32_t instance) 1205 { 1206 struct optc *tgn10 = 1207 kzalloc(sizeof(struct optc), GFP_KERNEL); 1208 1209 if (!tgn10) 1210 return NULL; 1211 1212 tgn10->base.inst = instance; 1213 tgn10->base.ctx = ctx; 1214 1215 tgn10->tg_regs = &optc_regs[instance]; 1216 tgn10->tg_shift = &optc_shift; 1217 tgn10->tg_mask = &optc_mask; 1218 1219 dcn31_timing_generator_init(tgn10); 1220 1221 return &tgn10->base; 1222 } 1223 1224 static const struct encoder_feature_support link_enc_feature = { 1225 .max_hdmi_deep_color = COLOR_DEPTH_121212, 1226 .max_hdmi_pixel_clock = 600000, 1227 .hdmi_ycbcr420_supported = true, 1228 .dp_ycbcr420_supported = true, 1229 .fec_supported = true, 1230 .flags.bits.IS_HBR2_CAPABLE = true, 1231 .flags.bits.IS_HBR3_CAPABLE = true, 1232 .flags.bits.IS_TPS3_CAPABLE = true, 1233 .flags.bits.IS_TPS4_CAPABLE = true 1234 }; 1235 1236 static struct link_encoder *dcn31_link_encoder_create( 1237 const struct encoder_init_data *enc_init_data) 1238 { 1239 struct dcn20_link_encoder *enc20 = 1240 kzalloc(sizeof(struct dcn20_link_encoder), GFP_KERNEL); 1241 1242 if (!enc20) 1243 return NULL; 1244 1245 dcn31_link_encoder_construct(enc20, 1246 enc_init_data, 1247 &link_enc_feature, 1248 &link_enc_regs[enc_init_data->transmitter], 1249 &link_enc_aux_regs[enc_init_data->channel - 1], 1250 &link_enc_hpd_regs[enc_init_data->hpd_source], 1251 &le_shift, 1252 &le_mask); 1253 1254 return &enc20->enc10.base; 1255 } 1256 1257 /* Create a minimal link encoder object not associated with a particular 1258 * physical connector. 1259 * resource_funcs.link_enc_create_minimal 1260 */ 1261 static struct link_encoder *dcn31_link_enc_create_minimal( 1262 struct dc_context *ctx, enum engine_id eng_id) 1263 { 1264 struct dcn20_link_encoder *enc20; 1265 1266 if ((eng_id - ENGINE_ID_DIGA) > ctx->dc->res_pool->res_cap->num_dig_link_enc) 1267 return NULL; 1268 1269 enc20 = kzalloc(sizeof(struct dcn20_link_encoder), GFP_KERNEL); 1270 if (!enc20) 1271 return NULL; 1272 1273 dcn31_link_encoder_construct_minimal( 1274 enc20, 1275 ctx, 1276 &link_enc_feature, 1277 &link_enc_regs[eng_id - ENGINE_ID_DIGA], 1278 eng_id); 1279 1280 return &enc20->enc10.base; 1281 } 1282 1283 static struct panel_cntl *dcn31_panel_cntl_create(const struct panel_cntl_init_data *init_data) 1284 { 1285 struct dcn31_panel_cntl *panel_cntl = 1286 kzalloc(sizeof(struct dcn31_panel_cntl), GFP_KERNEL); 1287 1288 if (!panel_cntl) 1289 return NULL; 1290 1291 dcn31_panel_cntl_construct(panel_cntl, init_data); 1292 1293 return &panel_cntl->base; 1294 } 1295 1296 static void read_dce_straps( 1297 struct dc_context *ctx, 1298 struct resource_straps *straps) 1299 { 1300 generic_reg_get(ctx, regDC_PINSTRAPS + BASE(regDC_PINSTRAPS_BASE_IDX), 1301 FN(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO), &straps->dc_pinstraps_audio); 1302 1303 } 1304 1305 static struct audio *dcn31_create_audio( 1306 struct dc_context *ctx, unsigned int inst) 1307 { 1308 return dce_audio_create(ctx, inst, 1309 &audio_regs[inst], &audio_shift, &audio_mask); 1310 } 1311 1312 static struct vpg *dcn31_vpg_create( 1313 struct dc_context *ctx, 1314 uint32_t inst) 1315 { 1316 struct dcn31_vpg *vpg31 = kzalloc(sizeof(struct dcn31_vpg), GFP_KERNEL); 1317 1318 if (!vpg31) 1319 return NULL; 1320 1321 vpg31_construct(vpg31, ctx, inst, 1322 &vpg_regs[inst], 1323 &vpg_shift, 1324 &vpg_mask); 1325 1326 return &vpg31->base; 1327 } 1328 1329 static struct afmt *dcn31_afmt_create( 1330 struct dc_context *ctx, 1331 uint32_t inst) 1332 { 1333 struct dcn31_afmt *afmt31 = kzalloc(sizeof(struct dcn31_afmt), GFP_KERNEL); 1334 1335 if (!afmt31) 1336 return NULL; 1337 1338 afmt31_construct(afmt31, ctx, inst, 1339 &afmt_regs[inst], 1340 &afmt_shift, 1341 &afmt_mask); 1342 1343 // Light sleep by default, no need to power down here 1344 1345 return &afmt31->base; 1346 } 1347 1348 static struct apg *dcn31_apg_create( 1349 struct dc_context *ctx, 1350 uint32_t inst) 1351 { 1352 struct dcn31_apg *apg31 = kzalloc(sizeof(struct dcn31_apg), GFP_KERNEL); 1353 1354 if (!apg31) 1355 return NULL; 1356 1357 apg31_construct(apg31, ctx, inst, 1358 &apg_regs[inst], 1359 &apg_shift, 1360 &apg_mask); 1361 1362 return &apg31->base; 1363 } 1364 1365 static struct stream_encoder *dcn31_stream_encoder_create( 1366 enum engine_id eng_id, 1367 struct dc_context *ctx) 1368 { 1369 struct dcn10_stream_encoder *enc1; 1370 struct vpg *vpg; 1371 struct afmt *afmt; 1372 int vpg_inst; 1373 int afmt_inst; 1374 1375 /* Mapping of VPG, AFMT, DME register blocks to DIO block instance */ 1376 if (eng_id <= ENGINE_ID_DIGF) { 1377 vpg_inst = eng_id; 1378 afmt_inst = eng_id; 1379 } else 1380 return NULL; 1381 1382 enc1 = kzalloc(sizeof(struct dcn10_stream_encoder), GFP_KERNEL); 1383 vpg = dcn31_vpg_create(ctx, vpg_inst); 1384 afmt = dcn31_afmt_create(ctx, afmt_inst); 1385 1386 if (!enc1 || !vpg || !afmt) { 1387 kfree(enc1); 1388 kfree(vpg); 1389 kfree(afmt); 1390 return NULL; 1391 } 1392 1393 if (ctx->asic_id.chip_family == FAMILY_YELLOW_CARP && 1394 ctx->asic_id.hw_internal_rev == YELLOW_CARP_B0) { 1395 if ((eng_id == ENGINE_ID_DIGC) || (eng_id == ENGINE_ID_DIGD)) 1396 eng_id = eng_id + 3; // For B0 only. C->F, D->G. 1397 } 1398 1399 dcn30_dio_stream_encoder_construct(enc1, ctx, ctx->dc_bios, 1400 eng_id, vpg, afmt, 1401 &stream_enc_regs[eng_id], 1402 &se_shift, &se_mask); 1403 1404 return &enc1->base; 1405 } 1406 1407 static struct hpo_dp_stream_encoder *dcn31_hpo_dp_stream_encoder_create( 1408 enum engine_id eng_id, 1409 struct dc_context *ctx) 1410 { 1411 struct dcn31_hpo_dp_stream_encoder *hpo_dp_enc31; 1412 struct vpg *vpg; 1413 struct apg *apg; 1414 uint32_t hpo_dp_inst; 1415 uint32_t vpg_inst; 1416 uint32_t apg_inst; 1417 1418 ASSERT((eng_id >= ENGINE_ID_HPO_DP_0) && (eng_id <= ENGINE_ID_HPO_DP_3)); 1419 hpo_dp_inst = eng_id - ENGINE_ID_HPO_DP_0; 1420 1421 /* Mapping of VPG register blocks to HPO DP block instance: 1422 * VPG[6] -> HPO_DP[0] 1423 * VPG[7] -> HPO_DP[1] 1424 * VPG[8] -> HPO_DP[2] 1425 * VPG[9] -> HPO_DP[3] 1426 */ 1427 vpg_inst = hpo_dp_inst + 6; 1428 1429 /* Mapping of APG register blocks to HPO DP block instance: 1430 * APG[0] -> HPO_DP[0] 1431 * APG[1] -> HPO_DP[1] 1432 * APG[2] -> HPO_DP[2] 1433 * APG[3] -> HPO_DP[3] 1434 */ 1435 apg_inst = hpo_dp_inst; 1436 1437 /* allocate HPO stream encoder and create VPG sub-block */ 1438 hpo_dp_enc31 = kzalloc(sizeof(struct dcn31_hpo_dp_stream_encoder), GFP_KERNEL); 1439 vpg = dcn31_vpg_create(ctx, vpg_inst); 1440 apg = dcn31_apg_create(ctx, apg_inst); 1441 1442 if (!hpo_dp_enc31 || !vpg || !apg) { 1443 kfree(hpo_dp_enc31); 1444 kfree(vpg); 1445 kfree(apg); 1446 return NULL; 1447 } 1448 1449 dcn31_hpo_dp_stream_encoder_construct(hpo_dp_enc31, ctx, ctx->dc_bios, 1450 hpo_dp_inst, eng_id, vpg, apg, 1451 &hpo_dp_stream_enc_regs[hpo_dp_inst], 1452 &hpo_dp_se_shift, &hpo_dp_se_mask); 1453 1454 return &hpo_dp_enc31->base; 1455 } 1456 1457 static struct hpo_dp_link_encoder *dcn31_hpo_dp_link_encoder_create( 1458 uint8_t inst, 1459 struct dc_context *ctx) 1460 { 1461 struct dcn31_hpo_dp_link_encoder *hpo_dp_enc31; 1462 1463 /* allocate HPO link encoder */ 1464 hpo_dp_enc31 = kzalloc(sizeof(struct dcn31_hpo_dp_link_encoder), GFP_KERNEL); 1465 1466 hpo_dp_link_encoder31_construct(hpo_dp_enc31, ctx, inst, 1467 &hpo_dp_link_enc_regs[inst], 1468 &hpo_dp_le_shift, &hpo_dp_le_mask); 1469 1470 return &hpo_dp_enc31->base; 1471 } 1472 1473 static struct dce_hwseq *dcn31_hwseq_create( 1474 struct dc_context *ctx) 1475 { 1476 struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_KERNEL); 1477 1478 if (hws) { 1479 hws->ctx = ctx; 1480 hws->regs = &hwseq_reg; 1481 hws->shifts = &hwseq_shift; 1482 hws->masks = &hwseq_mask; 1483 /* DCN3.1 FPGA Workaround 1484 * Need to enable HPO DP Stream Encoder before setting OTG master enable. 1485 * To do so, move calling function enable_stream_timing to only be done AFTER calling 1486 * function core_link_enable_stream 1487 */ 1488 if (IS_FPGA_MAXIMUS_DC(ctx->dce_environment)) 1489 hws->wa.dp_hpo_and_otg_sequence = true; 1490 } 1491 return hws; 1492 } 1493 static const struct resource_create_funcs res_create_funcs = { 1494 .read_dce_straps = read_dce_straps, 1495 .create_audio = dcn31_create_audio, 1496 .create_stream_encoder = dcn31_stream_encoder_create, 1497 .create_hpo_dp_stream_encoder = dcn31_hpo_dp_stream_encoder_create, 1498 .create_hpo_dp_link_encoder = dcn31_hpo_dp_link_encoder_create, 1499 .create_hwseq = dcn31_hwseq_create, 1500 }; 1501 1502 static const struct resource_create_funcs res_create_maximus_funcs = { 1503 .read_dce_straps = NULL, 1504 .create_audio = NULL, 1505 .create_stream_encoder = NULL, 1506 .create_hpo_dp_stream_encoder = dcn31_hpo_dp_stream_encoder_create, 1507 .create_hpo_dp_link_encoder = dcn31_hpo_dp_link_encoder_create, 1508 .create_hwseq = dcn31_hwseq_create, 1509 }; 1510 1511 static void dcn31_resource_destruct(struct dcn31_resource_pool *pool) 1512 { 1513 unsigned int i; 1514 1515 for (i = 0; i < pool->base.stream_enc_count; i++) { 1516 if (pool->base.stream_enc[i] != NULL) { 1517 if (pool->base.stream_enc[i]->vpg != NULL) { 1518 kfree(DCN30_VPG_FROM_VPG(pool->base.stream_enc[i]->vpg)); 1519 pool->base.stream_enc[i]->vpg = NULL; 1520 } 1521 if (pool->base.stream_enc[i]->afmt != NULL) { 1522 kfree(DCN30_AFMT_FROM_AFMT(pool->base.stream_enc[i]->afmt)); 1523 pool->base.stream_enc[i]->afmt = NULL; 1524 } 1525 kfree(DCN10STRENC_FROM_STRENC(pool->base.stream_enc[i])); 1526 pool->base.stream_enc[i] = NULL; 1527 } 1528 } 1529 1530 for (i = 0; i < pool->base.hpo_dp_stream_enc_count; i++) { 1531 if (pool->base.hpo_dp_stream_enc[i] != NULL) { 1532 if (pool->base.hpo_dp_stream_enc[i]->vpg != NULL) { 1533 kfree(DCN30_VPG_FROM_VPG(pool->base.hpo_dp_stream_enc[i]->vpg)); 1534 pool->base.hpo_dp_stream_enc[i]->vpg = NULL; 1535 } 1536 if (pool->base.hpo_dp_stream_enc[i]->apg != NULL) { 1537 kfree(DCN31_APG_FROM_APG(pool->base.hpo_dp_stream_enc[i]->apg)); 1538 pool->base.hpo_dp_stream_enc[i]->apg = NULL; 1539 } 1540 kfree(DCN3_1_HPO_DP_STREAM_ENC_FROM_HPO_STREAM_ENC(pool->base.hpo_dp_stream_enc[i])); 1541 pool->base.hpo_dp_stream_enc[i] = NULL; 1542 } 1543 } 1544 1545 for (i = 0; i < pool->base.hpo_dp_link_enc_count; i++) { 1546 if (pool->base.hpo_dp_link_enc[i] != NULL) { 1547 kfree(DCN3_1_HPO_DP_LINK_ENC_FROM_HPO_LINK_ENC(pool->base.hpo_dp_link_enc[i])); 1548 pool->base.hpo_dp_link_enc[i] = NULL; 1549 } 1550 } 1551 1552 for (i = 0; i < pool->base.res_cap->num_dsc; i++) { 1553 if (pool->base.dscs[i] != NULL) 1554 dcn20_dsc_destroy(&pool->base.dscs[i]); 1555 } 1556 1557 if (pool->base.mpc != NULL) { 1558 kfree(TO_DCN20_MPC(pool->base.mpc)); 1559 pool->base.mpc = NULL; 1560 } 1561 if (pool->base.hubbub != NULL) { 1562 kfree(pool->base.hubbub); 1563 pool->base.hubbub = NULL; 1564 } 1565 for (i = 0; i < pool->base.pipe_count; i++) { 1566 if (pool->base.dpps[i] != NULL) 1567 dcn31_dpp_destroy(&pool->base.dpps[i]); 1568 1569 if (pool->base.ipps[i] != NULL) 1570 pool->base.ipps[i]->funcs->ipp_destroy(&pool->base.ipps[i]); 1571 1572 if (pool->base.hubps[i] != NULL) { 1573 kfree(TO_DCN20_HUBP(pool->base.hubps[i])); 1574 pool->base.hubps[i] = NULL; 1575 } 1576 1577 if (pool->base.irqs != NULL) { 1578 dal_irq_service_destroy(&pool->base.irqs); 1579 } 1580 } 1581 1582 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { 1583 if (pool->base.engines[i] != NULL) 1584 dce110_engine_destroy(&pool->base.engines[i]); 1585 if (pool->base.hw_i2cs[i] != NULL) { 1586 kfree(pool->base.hw_i2cs[i]); 1587 pool->base.hw_i2cs[i] = NULL; 1588 } 1589 if (pool->base.sw_i2cs[i] != NULL) { 1590 kfree(pool->base.sw_i2cs[i]); 1591 pool->base.sw_i2cs[i] = NULL; 1592 } 1593 } 1594 1595 for (i = 0; i < pool->base.res_cap->num_opp; i++) { 1596 if (pool->base.opps[i] != NULL) 1597 pool->base.opps[i]->funcs->opp_destroy(&pool->base.opps[i]); 1598 } 1599 1600 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { 1601 if (pool->base.timing_generators[i] != NULL) { 1602 kfree(DCN10TG_FROM_TG(pool->base.timing_generators[i])); 1603 pool->base.timing_generators[i] = NULL; 1604 } 1605 } 1606 1607 for (i = 0; i < pool->base.res_cap->num_dwb; i++) { 1608 if (pool->base.dwbc[i] != NULL) { 1609 kfree(TO_DCN30_DWBC(pool->base.dwbc[i])); 1610 pool->base.dwbc[i] = NULL; 1611 } 1612 if (pool->base.mcif_wb[i] != NULL) { 1613 kfree(TO_DCN30_MMHUBBUB(pool->base.mcif_wb[i])); 1614 pool->base.mcif_wb[i] = NULL; 1615 } 1616 } 1617 1618 for (i = 0; i < pool->base.audio_count; i++) { 1619 if (pool->base.audios[i]) 1620 dce_aud_destroy(&pool->base.audios[i]); 1621 } 1622 1623 for (i = 0; i < pool->base.clk_src_count; i++) { 1624 if (pool->base.clock_sources[i] != NULL) { 1625 dcn20_clock_source_destroy(&pool->base.clock_sources[i]); 1626 pool->base.clock_sources[i] = NULL; 1627 } 1628 } 1629 1630 for (i = 0; i < pool->base.res_cap->num_mpc_3dlut; i++) { 1631 if (pool->base.mpc_lut[i] != NULL) { 1632 dc_3dlut_func_release(pool->base.mpc_lut[i]); 1633 pool->base.mpc_lut[i] = NULL; 1634 } 1635 if (pool->base.mpc_shaper[i] != NULL) { 1636 dc_transfer_func_release(pool->base.mpc_shaper[i]); 1637 pool->base.mpc_shaper[i] = NULL; 1638 } 1639 } 1640 1641 if (pool->base.dp_clock_source != NULL) { 1642 dcn20_clock_source_destroy(&pool->base.dp_clock_source); 1643 pool->base.dp_clock_source = NULL; 1644 } 1645 1646 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { 1647 if (pool->base.multiple_abms[i] != NULL) 1648 dce_abm_destroy(&pool->base.multiple_abms[i]); 1649 } 1650 1651 if (pool->base.psr != NULL) 1652 dmub_psr_destroy(&pool->base.psr); 1653 1654 if (pool->base.dccg != NULL) 1655 dcn_dccg_destroy(&pool->base.dccg); 1656 } 1657 1658 static struct hubp *dcn31_hubp_create( 1659 struct dc_context *ctx, 1660 uint32_t inst) 1661 { 1662 struct dcn20_hubp *hubp2 = 1663 kzalloc(sizeof(struct dcn20_hubp), GFP_KERNEL); 1664 1665 if (!hubp2) 1666 return NULL; 1667 1668 if (hubp31_construct(hubp2, ctx, inst, 1669 &hubp_regs[inst], &hubp_shift, &hubp_mask)) 1670 return &hubp2->base; 1671 1672 BREAK_TO_DEBUGGER(); 1673 kfree(hubp2); 1674 return NULL; 1675 } 1676 1677 static bool dcn31_dwbc_create(struct dc_context *ctx, struct resource_pool *pool) 1678 { 1679 int i; 1680 uint32_t pipe_count = pool->res_cap->num_dwb; 1681 1682 for (i = 0; i < pipe_count; i++) { 1683 struct dcn30_dwbc *dwbc30 = kzalloc(sizeof(struct dcn30_dwbc), 1684 GFP_KERNEL); 1685 1686 if (!dwbc30) { 1687 dm_error("DC: failed to create dwbc30!\n"); 1688 return false; 1689 } 1690 1691 dcn30_dwbc_construct(dwbc30, ctx, 1692 &dwbc30_regs[i], 1693 &dwbc30_shift, 1694 &dwbc30_mask, 1695 i); 1696 1697 pool->dwbc[i] = &dwbc30->base; 1698 } 1699 return true; 1700 } 1701 1702 static bool dcn31_mmhubbub_create(struct dc_context *ctx, struct resource_pool *pool) 1703 { 1704 int i; 1705 uint32_t pipe_count = pool->res_cap->num_dwb; 1706 1707 for (i = 0; i < pipe_count; i++) { 1708 struct dcn30_mmhubbub *mcif_wb30 = kzalloc(sizeof(struct dcn30_mmhubbub), 1709 GFP_KERNEL); 1710 1711 if (!mcif_wb30) { 1712 dm_error("DC: failed to create mcif_wb30!\n"); 1713 return false; 1714 } 1715 1716 dcn30_mmhubbub_construct(mcif_wb30, ctx, 1717 &mcif_wb30_regs[i], 1718 &mcif_wb30_shift, 1719 &mcif_wb30_mask, 1720 i); 1721 1722 pool->mcif_wb[i] = &mcif_wb30->base; 1723 } 1724 return true; 1725 } 1726 1727 static struct display_stream_compressor *dcn31_dsc_create( 1728 struct dc_context *ctx, uint32_t inst) 1729 { 1730 struct dcn20_dsc *dsc = 1731 kzalloc(sizeof(struct dcn20_dsc), GFP_KERNEL); 1732 1733 if (!dsc) { 1734 BREAK_TO_DEBUGGER(); 1735 return NULL; 1736 } 1737 1738 dsc2_construct(dsc, ctx, inst, &dsc_regs[inst], &dsc_shift, &dsc_mask); 1739 return &dsc->base; 1740 } 1741 1742 static void dcn31_destroy_resource_pool(struct resource_pool **pool) 1743 { 1744 struct dcn31_resource_pool *dcn31_pool = TO_DCN31_RES_POOL(*pool); 1745 1746 dcn31_resource_destruct(dcn31_pool); 1747 kfree(dcn31_pool); 1748 *pool = NULL; 1749 } 1750 1751 static struct clock_source *dcn31_clock_source_create( 1752 struct dc_context *ctx, 1753 struct dc_bios *bios, 1754 enum clock_source_id id, 1755 const struct dce110_clk_src_regs *regs, 1756 bool dp_clk_src) 1757 { 1758 struct dce110_clk_src *clk_src = 1759 kzalloc(sizeof(struct dce110_clk_src), GFP_KERNEL); 1760 1761 if (!clk_src) 1762 return NULL; 1763 1764 if (dcn3_clk_src_construct(clk_src, ctx, bios, id, 1765 regs, &cs_shift, &cs_mask)) { 1766 clk_src->base.dp_clk_src = dp_clk_src; 1767 return &clk_src->base; 1768 } 1769 1770 BREAK_TO_DEBUGGER(); 1771 return NULL; 1772 } 1773 1774 static bool is_dual_plane(enum surface_pixel_format format) 1775 { 1776 return format >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN || format == SURFACE_PIXEL_FORMAT_GRPH_RGBE_ALPHA; 1777 } 1778 1779 static int dcn31_populate_dml_pipes_from_context( 1780 struct dc *dc, struct dc_state *context, 1781 display_e2e_pipe_params_st *pipes, 1782 bool fast_validate) 1783 { 1784 int i, pipe_cnt; 1785 struct resource_context *res_ctx = &context->res_ctx; 1786 struct pipe_ctx *pipe; 1787 bool upscaled = false; 1788 1789 dcn20_populate_dml_pipes_from_context(dc, context, pipes, fast_validate); 1790 1791 for (i = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) { 1792 struct dc_crtc_timing *timing; 1793 1794 if (!res_ctx->pipe_ctx[i].stream) 1795 continue; 1796 pipe = &res_ctx->pipe_ctx[i]; 1797 timing = &pipe->stream->timing; 1798 1799 if (pipe->plane_state && 1800 (pipe->plane_state->src_rect.height < pipe->plane_state->dst_rect.height || 1801 pipe->plane_state->src_rect.width < pipe->plane_state->dst_rect.width)) 1802 upscaled = true; 1803 1804 /* 1805 * Immediate flip can be set dynamically after enabling the plane. 1806 * We need to require support for immediate flip or underflow can be 1807 * intermittently experienced depending on peak b/w requirements. 1808 */ 1809 pipes[pipe_cnt].pipe.src.immediate_flip = true; 1810 1811 pipes[pipe_cnt].pipe.src.unbounded_req_mode = false; 1812 pipes[pipe_cnt].pipe.src.gpuvm = true; 1813 pipes[pipe_cnt].pipe.src.dcc_fraction_of_zs_req_luma = 0; 1814 pipes[pipe_cnt].pipe.src.dcc_fraction_of_zs_req_chroma = 0; 1815 pipes[pipe_cnt].pipe.dest.vfront_porch = timing->v_front_porch; 1816 pipes[pipe_cnt].pipe.src.dcc_rate = 3; 1817 pipes[pipe_cnt].dout.dsc_input_bpc = 0; 1818 1819 if (pipes[pipe_cnt].dout.dsc_enable) { 1820 switch (timing->display_color_depth) { 1821 case COLOR_DEPTH_888: 1822 pipes[pipe_cnt].dout.dsc_input_bpc = 8; 1823 break; 1824 case COLOR_DEPTH_101010: 1825 pipes[pipe_cnt].dout.dsc_input_bpc = 10; 1826 break; 1827 case COLOR_DEPTH_121212: 1828 pipes[pipe_cnt].dout.dsc_input_bpc = 12; 1829 break; 1830 default: 1831 ASSERT(0); 1832 break; 1833 } 1834 } 1835 1836 pipe_cnt++; 1837 } 1838 context->bw_ctx.dml.ip.det_buffer_size_kbytes = DCN3_1_DEFAULT_DET_SIZE; 1839 dc->config.enable_4to1MPC = false; 1840 if (pipe_cnt == 1 && pipe->plane_state && !dc->debug.disable_z9_mpc) { 1841 if (is_dual_plane(pipe->plane_state->format) 1842 && pipe->plane_state->src_rect.width <= 1920 && pipe->plane_state->src_rect.height <= 1080) { 1843 dc->config.enable_4to1MPC = true; 1844 } else if (!is_dual_plane(pipe->plane_state->format)) { 1845 context->bw_ctx.dml.ip.det_buffer_size_kbytes = 192; 1846 pipes[0].pipe.src.unbounded_req_mode = true; 1847 } 1848 } else if (context->stream_count >= dc->debug.crb_alloc_policy_min_disp_count 1849 && dc->debug.crb_alloc_policy > DET_SIZE_DEFAULT) { 1850 context->bw_ctx.dml.ip.det_buffer_size_kbytes = dc->debug.crb_alloc_policy * 64; 1851 } else if (context->stream_count >= 3 && upscaled) { 1852 context->bw_ctx.dml.ip.det_buffer_size_kbytes = 192; 1853 } 1854 1855 return pipe_cnt; 1856 } 1857 1858 void dcn31_update_soc_for_wm_a(struct dc *dc, struct dc_state *context) 1859 { 1860 if (dc->clk_mgr->bw_params->wm_table.entries[WM_A].valid) { 1861 context->bw_ctx.dml.soc.dram_clock_change_latency_us = dc->clk_mgr->bw_params->wm_table.entries[WM_A].pstate_latency_us; 1862 context->bw_ctx.dml.soc.sr_enter_plus_exit_time_us = dc->clk_mgr->bw_params->wm_table.entries[WM_A].sr_enter_plus_exit_time_us; 1863 context->bw_ctx.dml.soc.sr_exit_time_us = dc->clk_mgr->bw_params->wm_table.entries[WM_A].sr_exit_time_us; 1864 } 1865 } 1866 1867 static void dcn31_calculate_wm_and_dlg_fp( 1868 struct dc *dc, struct dc_state *context, 1869 display_e2e_pipe_params_st *pipes, 1870 int pipe_cnt, 1871 int vlevel) 1872 { 1873 int i, pipe_idx; 1874 double dcfclk = context->bw_ctx.dml.vba.DCFCLKState[vlevel][context->bw_ctx.dml.vba.maxMpcComb]; 1875 1876 if (context->bw_ctx.dml.soc.min_dcfclk > dcfclk) 1877 dcfclk = context->bw_ctx.dml.soc.min_dcfclk; 1878 1879 /* We don't recalculate clocks for 0 pipe configs, which can block 1880 * S0i3 as high clocks will block low power states 1881 * Override any clocks that can block S0i3 to min here 1882 */ 1883 if (pipe_cnt == 0) { 1884 context->bw_ctx.bw.dcn.clk.dcfclk_khz = dcfclk; // always should be vlevel 0 1885 return; 1886 } 1887 1888 pipes[0].clks_cfg.voltage = vlevel; 1889 pipes[0].clks_cfg.dcfclk_mhz = dcfclk; 1890 pipes[0].clks_cfg.socclk_mhz = context->bw_ctx.dml.soc.clock_limits[vlevel].socclk_mhz; 1891 1892 #if 0 // TODO 1893 /* Set B: 1894 * TODO 1895 */ 1896 if (dc->clk_mgr->bw_params->wm_table.nv_entries[WM_B].valid) { 1897 if (vlevel == 0) { 1898 pipes[0].clks_cfg.voltage = 1; 1899 pipes[0].clks_cfg.dcfclk_mhz = context->bw_ctx.dml.soc.clock_limits[0].dcfclk_mhz; 1900 } 1901 context->bw_ctx.dml.soc.dram_clock_change_latency_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_B].dml_input.pstate_latency_us; 1902 context->bw_ctx.dml.soc.sr_enter_plus_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_B].dml_input.sr_enter_plus_exit_time_us; 1903 context->bw_ctx.dml.soc.sr_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_B].dml_input.sr_exit_time_us; 1904 } 1905 context->bw_ctx.bw.dcn.watermarks.b.urgent_ns = get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 1906 context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 1907 context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 1908 context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.cstate_enter_plus_exit_z8_ns = get_wm_z8_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 1909 context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.cstate_exit_z8_ns = get_wm_z8_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 1910 context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 1911 context->bw_ctx.bw.dcn.watermarks.b.pte_meta_urgent_ns = get_wm_memory_trip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 1912 context->bw_ctx.bw.dcn.watermarks.b.frac_urg_bw_nom = get_fraction_of_urgent_bandwidth(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 1913 context->bw_ctx.bw.dcn.watermarks.b.frac_urg_bw_flip = get_fraction_of_urgent_bandwidth_imm_flip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 1914 context->bw_ctx.bw.dcn.watermarks.b.urgent_latency_ns = get_urgent_latency(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 1915 1916 pipes[0].clks_cfg.voltage = vlevel; 1917 pipes[0].clks_cfg.dcfclk_mhz = dcfclk; 1918 1919 /* Set C: 1920 * TODO 1921 */ 1922 if (dc->clk_mgr->bw_params->wm_table.nv_entries[WM_C].valid) { 1923 context->bw_ctx.dml.soc.dram_clock_change_latency_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_C].dml_input.pstate_latency_us; 1924 context->bw_ctx.dml.soc.sr_enter_plus_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_C].dml_input.sr_enter_plus_exit_time_us; 1925 context->bw_ctx.dml.soc.sr_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_C].dml_input.sr_exit_time_us; 1926 } 1927 context->bw_ctx.bw.dcn.watermarks.c.urgent_ns = get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 1928 context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 1929 context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 1930 context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.cstate_enter_plus_exit_z8_ns = get_wm_z8_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 1931 context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.cstate_exit_z8_ns = get_wm_z8_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 1932 context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 1933 context->bw_ctx.bw.dcn.watermarks.c.pte_meta_urgent_ns = get_wm_memory_trip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 1934 context->bw_ctx.bw.dcn.watermarks.c.frac_urg_bw_nom = get_fraction_of_urgent_bandwidth(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 1935 context->bw_ctx.bw.dcn.watermarks.c.frac_urg_bw_flip = get_fraction_of_urgent_bandwidth_imm_flip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 1936 context->bw_ctx.bw.dcn.watermarks.c.urgent_latency_ns = get_urgent_latency(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 1937 1938 /* Set D: 1939 * TODO 1940 */ 1941 if (dc->clk_mgr->bw_params->wm_table.nv_entries[WM_D].valid) { 1942 context->bw_ctx.dml.soc.dram_clock_change_latency_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_D].dml_input.pstate_latency_us; 1943 context->bw_ctx.dml.soc.sr_enter_plus_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_D].dml_input.sr_enter_plus_exit_time_us; 1944 context->bw_ctx.dml.soc.sr_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_D].dml_input.sr_exit_time_us; 1945 } 1946 context->bw_ctx.bw.dcn.watermarks.d.urgent_ns = get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 1947 context->bw_ctx.bw.dcn.watermarks.d.cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 1948 context->bw_ctx.bw.dcn.watermarks.d.cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 1949 context->bw_ctx.bw.dcn.watermarks.d.cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 1950 context->bw_ctx.bw.dcn.watermarks.d.cstate_pstate.cstate_enter_plus_exit_z8_ns = get_wm_z8_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 1951 context->bw_ctx.bw.dcn.watermarks.d.cstate_pstate.cstate_exit_z8_ns = get_wm_z8_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 1952 context->bw_ctx.bw.dcn.watermarks.d.pte_meta_urgent_ns = get_wm_memory_trip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 1953 context->bw_ctx.bw.dcn.watermarks.d.frac_urg_bw_nom = get_fraction_of_urgent_bandwidth(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 1954 context->bw_ctx.bw.dcn.watermarks.d.frac_urg_bw_flip = get_fraction_of_urgent_bandwidth_imm_flip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 1955 context->bw_ctx.bw.dcn.watermarks.d.urgent_latency_ns = get_urgent_latency(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 1956 #endif 1957 1958 /* Set A: 1959 * All clocks min required 1960 * 1961 * Set A calculated last so that following calculations are based on Set A 1962 */ 1963 dc->res_pool->funcs->update_soc_for_wm_a(dc, context); 1964 context->bw_ctx.bw.dcn.watermarks.a.urgent_ns = get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 1965 context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 1966 context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 1967 context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 1968 context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.cstate_enter_plus_exit_z8_ns = get_wm_z8_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 1969 context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.cstate_exit_z8_ns = get_wm_z8_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 1970 context->bw_ctx.bw.dcn.watermarks.a.pte_meta_urgent_ns = get_wm_memory_trip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 1971 context->bw_ctx.bw.dcn.watermarks.a.frac_urg_bw_nom = get_fraction_of_urgent_bandwidth(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 1972 context->bw_ctx.bw.dcn.watermarks.a.frac_urg_bw_flip = get_fraction_of_urgent_bandwidth_imm_flip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 1973 context->bw_ctx.bw.dcn.watermarks.a.urgent_latency_ns = get_urgent_latency(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 1974 /* TODO: remove: */ 1975 context->bw_ctx.bw.dcn.watermarks.b = context->bw_ctx.bw.dcn.watermarks.a; 1976 context->bw_ctx.bw.dcn.watermarks.c = context->bw_ctx.bw.dcn.watermarks.a; 1977 context->bw_ctx.bw.dcn.watermarks.d = context->bw_ctx.bw.dcn.watermarks.a; 1978 /* end remove*/ 1979 1980 for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) { 1981 if (!context->res_ctx.pipe_ctx[i].stream) 1982 continue; 1983 1984 pipes[pipe_idx].clks_cfg.dispclk_mhz = get_dispclk_calculated(&context->bw_ctx.dml, pipes, pipe_cnt); 1985 pipes[pipe_idx].clks_cfg.dppclk_mhz = get_dppclk_calculated(&context->bw_ctx.dml, pipes, pipe_cnt, pipe_idx); 1986 1987 if (dc->config.forced_clocks || dc->debug.max_disp_clk) { 1988 pipes[pipe_idx].clks_cfg.dispclk_mhz = context->bw_ctx.dml.soc.clock_limits[0].dispclk_mhz; 1989 pipes[pipe_idx].clks_cfg.dppclk_mhz = context->bw_ctx.dml.soc.clock_limits[0].dppclk_mhz; 1990 } 1991 if (dc->debug.min_disp_clk_khz > pipes[pipe_idx].clks_cfg.dispclk_mhz * 1000) 1992 pipes[pipe_idx].clks_cfg.dispclk_mhz = dc->debug.min_disp_clk_khz / 1000.0; 1993 if (dc->debug.min_dpp_clk_khz > pipes[pipe_idx].clks_cfg.dppclk_mhz * 1000) 1994 pipes[pipe_idx].clks_cfg.dppclk_mhz = dc->debug.min_dpp_clk_khz / 1000.0; 1995 1996 pipe_idx++; 1997 } 1998 1999 dcn20_calculate_dlg_params(dc, context, pipes, pipe_cnt, vlevel); 2000 } 2001 2002 void dcn31_calculate_wm_and_dlg( 2003 struct dc *dc, struct dc_state *context, 2004 display_e2e_pipe_params_st *pipes, 2005 int pipe_cnt, 2006 int vlevel) 2007 { 2008 DC_FP_START(); 2009 dcn31_calculate_wm_and_dlg_fp(dc, context, pipes, pipe_cnt, vlevel); 2010 DC_FP_END(); 2011 } 2012 2013 bool dcn31_validate_bandwidth(struct dc *dc, 2014 struct dc_state *context, 2015 bool fast_validate) 2016 { 2017 bool out = false; 2018 2019 BW_VAL_TRACE_SETUP(); 2020 2021 int vlevel = 0; 2022 int pipe_cnt = 0; 2023 display_e2e_pipe_params_st *pipes = kzalloc(dc->res_pool->pipe_count * sizeof(display_e2e_pipe_params_st), GFP_KERNEL); 2024 DC_LOGGER_INIT(dc->ctx->logger); 2025 2026 BW_VAL_TRACE_COUNT(); 2027 2028 out = dcn30_internal_validate_bw(dc, context, pipes, &pipe_cnt, &vlevel, fast_validate); 2029 2030 // Disable fast_validate to set min dcfclk in alculate_wm_and_dlg 2031 if (pipe_cnt == 0) 2032 fast_validate = false; 2033 2034 if (!out) 2035 goto validate_fail; 2036 2037 BW_VAL_TRACE_END_VOLTAGE_LEVEL(); 2038 2039 if (fast_validate) { 2040 BW_VAL_TRACE_SKIP(fast); 2041 goto validate_out; 2042 } 2043 2044 dc->res_pool->funcs->calculate_wm_and_dlg(dc, context, pipes, pipe_cnt, vlevel); 2045 2046 BW_VAL_TRACE_END_WATERMARKS(); 2047 2048 goto validate_out; 2049 2050 validate_fail: 2051 DC_LOG_WARNING("Mode Validation Warning: %s failed validation.\n", 2052 dml_get_status_message(context->bw_ctx.dml.vba.ValidationStatus[context->bw_ctx.dml.vba.soc.num_states])); 2053 2054 BW_VAL_TRACE_SKIP(fail); 2055 out = false; 2056 2057 validate_out: 2058 kfree(pipes); 2059 2060 BW_VAL_TRACE_FINISH(); 2061 2062 return out; 2063 } 2064 2065 static struct dc_cap_funcs cap_funcs = { 2066 .get_dcc_compression_cap = dcn20_get_dcc_compression_cap 2067 }; 2068 2069 static void dcn31_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params) 2070 { 2071 struct clk_limit_table *clk_table = &bw_params->clk_table; 2072 struct _vcs_dpi_voltage_scaling_st clock_limits[DC__VOLTAGE_STATES]; 2073 unsigned int i, closest_clk_lvl; 2074 int j; 2075 2076 // Default clock levels are used for diags, which may lead to overclocking. 2077 if (!IS_DIAG_DC(dc->ctx->dce_environment)) { 2078 int max_dispclk_mhz = 0, max_dppclk_mhz = 0; 2079 2080 dcn3_1_ip.max_num_otg = dc->res_pool->res_cap->num_timing_generator; 2081 dcn3_1_ip.max_num_dpp = dc->res_pool->pipe_count; 2082 dcn3_1_soc.num_chans = bw_params->num_channels; 2083 2084 ASSERT(clk_table->num_entries); 2085 2086 /* Prepass to find max clocks independent of voltage level. */ 2087 for (i = 0; i < clk_table->num_entries; ++i) { 2088 if (clk_table->entries[i].dispclk_mhz > max_dispclk_mhz) 2089 max_dispclk_mhz = clk_table->entries[i].dispclk_mhz; 2090 if (clk_table->entries[i].dppclk_mhz > max_dppclk_mhz) 2091 max_dppclk_mhz = clk_table->entries[i].dppclk_mhz; 2092 } 2093 2094 for (i = 0; i < clk_table->num_entries; i++) { 2095 /* loop backwards*/ 2096 for (closest_clk_lvl = 0, j = dcn3_1_soc.num_states - 1; j >= 0; j--) { 2097 if ((unsigned int) dcn3_1_soc.clock_limits[j].dcfclk_mhz <= clk_table->entries[i].dcfclk_mhz) { 2098 closest_clk_lvl = j; 2099 break; 2100 } 2101 } 2102 2103 clock_limits[i].state = i; 2104 2105 /* Clocks dependent on voltage level. */ 2106 clock_limits[i].dcfclk_mhz = clk_table->entries[i].dcfclk_mhz; 2107 clock_limits[i].fabricclk_mhz = clk_table->entries[i].fclk_mhz; 2108 clock_limits[i].socclk_mhz = clk_table->entries[i].socclk_mhz; 2109 clock_limits[i].dram_speed_mts = clk_table->entries[i].memclk_mhz * 2 * clk_table->entries[i].wck_ratio; 2110 2111 /* Clocks independent of voltage level. */ 2112 clock_limits[i].dispclk_mhz = max_dispclk_mhz ? max_dispclk_mhz : 2113 dcn3_1_soc.clock_limits[closest_clk_lvl].dispclk_mhz; 2114 2115 clock_limits[i].dppclk_mhz = max_dppclk_mhz ? max_dppclk_mhz : 2116 dcn3_1_soc.clock_limits[closest_clk_lvl].dppclk_mhz; 2117 2118 clock_limits[i].dram_bw_per_chan_gbps = dcn3_1_soc.clock_limits[closest_clk_lvl].dram_bw_per_chan_gbps; 2119 clock_limits[i].dscclk_mhz = dcn3_1_soc.clock_limits[closest_clk_lvl].dscclk_mhz; 2120 clock_limits[i].dtbclk_mhz = dcn3_1_soc.clock_limits[closest_clk_lvl].dtbclk_mhz; 2121 clock_limits[i].phyclk_d18_mhz = dcn3_1_soc.clock_limits[closest_clk_lvl].phyclk_d18_mhz; 2122 clock_limits[i].phyclk_mhz = dcn3_1_soc.clock_limits[closest_clk_lvl].phyclk_mhz; 2123 } 2124 for (i = 0; i < clk_table->num_entries; i++) 2125 dcn3_1_soc.clock_limits[i] = clock_limits[i]; 2126 if (clk_table->num_entries) { 2127 dcn3_1_soc.num_states = clk_table->num_entries; 2128 } 2129 } 2130 2131 dcn3_1_soc.dispclk_dppclk_vco_speed_mhz = dc->clk_mgr->dentist_vco_freq_khz / 1000.0; 2132 dc->dml.soc.dispclk_dppclk_vco_speed_mhz = dc->clk_mgr->dentist_vco_freq_khz / 1000.0; 2133 2134 if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) 2135 dml_init_instance(&dc->dml, &dcn3_1_soc, &dcn3_1_ip, DML_PROJECT_DCN31); 2136 else 2137 dml_init_instance(&dc->dml, &dcn3_1_soc, &dcn3_1_ip, DML_PROJECT_DCN31_FPGA); 2138 } 2139 2140 static struct resource_funcs dcn31_res_pool_funcs = { 2141 .destroy = dcn31_destroy_resource_pool, 2142 .link_enc_create = dcn31_link_encoder_create, 2143 .link_enc_create_minimal = dcn31_link_enc_create_minimal, 2144 .link_encs_assign = link_enc_cfg_link_encs_assign, 2145 .link_enc_unassign = link_enc_cfg_link_enc_unassign, 2146 .panel_cntl_create = dcn31_panel_cntl_create, 2147 .validate_bandwidth = dcn31_validate_bandwidth, 2148 .calculate_wm_and_dlg = dcn31_calculate_wm_and_dlg, 2149 .update_soc_for_wm_a = dcn31_update_soc_for_wm_a, 2150 .populate_dml_pipes = dcn31_populate_dml_pipes_from_context, 2151 .acquire_idle_pipe_for_layer = dcn20_acquire_idle_pipe_for_layer, 2152 .add_stream_to_ctx = dcn30_add_stream_to_ctx, 2153 .add_dsc_to_stream_resource = dcn20_add_dsc_to_stream_resource, 2154 .remove_stream_from_ctx = dcn20_remove_stream_from_ctx, 2155 .populate_dml_writeback_from_context = dcn30_populate_dml_writeback_from_context, 2156 .set_mcif_arb_params = dcn30_set_mcif_arb_params, 2157 .find_first_free_match_stream_enc_for_link = dcn10_find_first_free_match_stream_enc_for_link, 2158 .acquire_post_bldn_3dlut = dcn30_acquire_post_bldn_3dlut, 2159 .release_post_bldn_3dlut = dcn30_release_post_bldn_3dlut, 2160 .update_bw_bounding_box = dcn31_update_bw_bounding_box, 2161 .patch_unknown_plane_state = dcn20_patch_unknown_plane_state, 2162 }; 2163 2164 static struct clock_source *dcn30_clock_source_create( 2165 struct dc_context *ctx, 2166 struct dc_bios *bios, 2167 enum clock_source_id id, 2168 const struct dce110_clk_src_regs *regs, 2169 bool dp_clk_src) 2170 { 2171 struct dce110_clk_src *clk_src = 2172 kzalloc(sizeof(struct dce110_clk_src), GFP_KERNEL); 2173 2174 if (!clk_src) 2175 return NULL; 2176 2177 if (dcn3_clk_src_construct(clk_src, ctx, bios, id, 2178 regs, &cs_shift, &cs_mask)) { 2179 clk_src->base.dp_clk_src = dp_clk_src; 2180 return &clk_src->base; 2181 } 2182 2183 BREAK_TO_DEBUGGER(); 2184 return NULL; 2185 } 2186 2187 static bool dcn31_resource_construct( 2188 uint8_t num_virtual_links, 2189 struct dc *dc, 2190 struct dcn31_resource_pool *pool) 2191 { 2192 int i; 2193 struct dc_context *ctx = dc->ctx; 2194 struct irq_service_init_data init_data; 2195 2196 DC_FP_START(); 2197 2198 ctx->dc_bios->regs = &bios_regs; 2199 2200 pool->base.res_cap = &res_cap_dcn31; 2201 2202 pool->base.funcs = &dcn31_res_pool_funcs; 2203 2204 /************************************************* 2205 * Resource + asic cap harcoding * 2206 *************************************************/ 2207 pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE; 2208 pool->base.pipe_count = pool->base.res_cap->num_timing_generator; 2209 pool->base.mpcc_count = pool->base.res_cap->num_timing_generator; 2210 dc->caps.max_downscale_ratio = 600; 2211 dc->caps.i2c_speed_in_khz = 100; 2212 dc->caps.i2c_speed_in_khz_hdcp = 5; /*1.4 w/a applied by default*/ 2213 dc->caps.max_cursor_size = 256; 2214 dc->caps.min_horizontal_blanking_period = 80; 2215 dc->caps.dmdata_alloc_size = 2048; 2216 2217 dc->caps.max_slave_planes = 1; 2218 dc->caps.max_slave_yuv_planes = 1; 2219 dc->caps.max_slave_rgb_planes = 1; 2220 dc->caps.post_blend_color_processing = true; 2221 dc->caps.force_dp_tps4_for_cp2520 = true; 2222 dc->caps.dp_hpo = true; 2223 dc->caps.hdmi_frl_pcon_support = true; 2224 dc->caps.edp_dsc_support = true; 2225 dc->caps.extended_aux_timeout_support = true; 2226 dc->caps.dmcub_support = true; 2227 dc->caps.is_apu = true; 2228 2229 /* Color pipeline capabilities */ 2230 dc->caps.color.dpp.dcn_arch = 1; 2231 dc->caps.color.dpp.input_lut_shared = 0; 2232 dc->caps.color.dpp.icsc = 1; 2233 dc->caps.color.dpp.dgam_ram = 0; // must use gamma_corr 2234 dc->caps.color.dpp.dgam_rom_caps.srgb = 1; 2235 dc->caps.color.dpp.dgam_rom_caps.bt2020 = 1; 2236 dc->caps.color.dpp.dgam_rom_caps.gamma2_2 = 1; 2237 dc->caps.color.dpp.dgam_rom_caps.pq = 1; 2238 dc->caps.color.dpp.dgam_rom_caps.hlg = 1; 2239 dc->caps.color.dpp.post_csc = 1; 2240 dc->caps.color.dpp.gamma_corr = 1; 2241 dc->caps.color.dpp.dgam_rom_for_yuv = 0; 2242 2243 dc->caps.color.dpp.hw_3d_lut = 1; 2244 dc->caps.color.dpp.ogam_ram = 1; 2245 // no OGAM ROM on DCN301 2246 dc->caps.color.dpp.ogam_rom_caps.srgb = 0; 2247 dc->caps.color.dpp.ogam_rom_caps.bt2020 = 0; 2248 dc->caps.color.dpp.ogam_rom_caps.gamma2_2 = 0; 2249 dc->caps.color.dpp.ogam_rom_caps.pq = 0; 2250 dc->caps.color.dpp.ogam_rom_caps.hlg = 0; 2251 dc->caps.color.dpp.ocsc = 0; 2252 2253 dc->caps.color.mpc.gamut_remap = 1; 2254 dc->caps.color.mpc.num_3dluts = pool->base.res_cap->num_mpc_3dlut; //2 2255 dc->caps.color.mpc.ogam_ram = 1; 2256 dc->caps.color.mpc.ogam_rom_caps.srgb = 0; 2257 dc->caps.color.mpc.ogam_rom_caps.bt2020 = 0; 2258 dc->caps.color.mpc.ogam_rom_caps.gamma2_2 = 0; 2259 dc->caps.color.mpc.ogam_rom_caps.pq = 0; 2260 dc->caps.color.mpc.ogam_rom_caps.hlg = 0; 2261 dc->caps.color.mpc.ocsc = 1; 2262 2263 /* Use pipe context based otg sync logic */ 2264 dc->config.use_pipe_ctx_sync_logic = true; 2265 2266 /* read VBIOS LTTPR caps */ 2267 { 2268 if (ctx->dc_bios->funcs->get_lttpr_caps) { 2269 enum bp_result bp_query_result; 2270 uint8_t is_vbios_lttpr_enable = 0; 2271 2272 bp_query_result = ctx->dc_bios->funcs->get_lttpr_caps(ctx->dc_bios, &is_vbios_lttpr_enable); 2273 dc->caps.vbios_lttpr_enable = (bp_query_result == BP_RESULT_OK) && !!is_vbios_lttpr_enable; 2274 } 2275 2276 /* interop bit is implicit */ 2277 { 2278 dc->caps.vbios_lttpr_aware = true; 2279 } 2280 } 2281 2282 if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV) 2283 dc->debug = debug_defaults_drv; 2284 else if (dc->ctx->dce_environment == DCE_ENV_FPGA_MAXIMUS) { 2285 dc->debug = debug_defaults_diags; 2286 } else 2287 dc->debug = debug_defaults_diags; 2288 // Init the vm_helper 2289 if (dc->vm_helper) 2290 vm_helper_init(dc->vm_helper, 16); 2291 2292 /************************************************* 2293 * Create resources * 2294 *************************************************/ 2295 2296 /* Clock Sources for Pixel Clock*/ 2297 pool->base.clock_sources[DCN31_CLK_SRC_PLL0] = 2298 dcn30_clock_source_create(ctx, ctx->dc_bios, 2299 CLOCK_SOURCE_COMBO_PHY_PLL0, 2300 &clk_src_regs[0], false); 2301 pool->base.clock_sources[DCN31_CLK_SRC_PLL1] = 2302 dcn30_clock_source_create(ctx, ctx->dc_bios, 2303 CLOCK_SOURCE_COMBO_PHY_PLL1, 2304 &clk_src_regs[1], false); 2305 /*move phypllx_pixclk_resync to dmub next*/ 2306 if (dc->ctx->asic_id.hw_internal_rev == YELLOW_CARP_B0) { 2307 pool->base.clock_sources[DCN31_CLK_SRC_PLL2] = 2308 dcn30_clock_source_create(ctx, ctx->dc_bios, 2309 CLOCK_SOURCE_COMBO_PHY_PLL2, 2310 &clk_src_regs_b0[2], false); 2311 pool->base.clock_sources[DCN31_CLK_SRC_PLL3] = 2312 dcn30_clock_source_create(ctx, ctx->dc_bios, 2313 CLOCK_SOURCE_COMBO_PHY_PLL3, 2314 &clk_src_regs_b0[3], false); 2315 } else { 2316 pool->base.clock_sources[DCN31_CLK_SRC_PLL2] = 2317 dcn30_clock_source_create(ctx, ctx->dc_bios, 2318 CLOCK_SOURCE_COMBO_PHY_PLL2, 2319 &clk_src_regs[2], false); 2320 pool->base.clock_sources[DCN31_CLK_SRC_PLL3] = 2321 dcn30_clock_source_create(ctx, ctx->dc_bios, 2322 CLOCK_SOURCE_COMBO_PHY_PLL3, 2323 &clk_src_regs[3], false); 2324 } 2325 2326 pool->base.clock_sources[DCN31_CLK_SRC_PLL4] = 2327 dcn30_clock_source_create(ctx, ctx->dc_bios, 2328 CLOCK_SOURCE_COMBO_PHY_PLL4, 2329 &clk_src_regs[4], false); 2330 2331 pool->base.clk_src_count = DCN30_CLK_SRC_TOTAL; 2332 2333 /* todo: not reuse phy_pll registers */ 2334 pool->base.dp_clock_source = 2335 dcn31_clock_source_create(ctx, ctx->dc_bios, 2336 CLOCK_SOURCE_ID_DP_DTO, 2337 &clk_src_regs[0], true); 2338 2339 for (i = 0; i < pool->base.clk_src_count; i++) { 2340 if (pool->base.clock_sources[i] == NULL) { 2341 dm_error("DC: failed to create clock sources!\n"); 2342 BREAK_TO_DEBUGGER(); 2343 goto create_fail; 2344 } 2345 } 2346 2347 /* TODO: DCCG */ 2348 pool->base.dccg = dccg31_create(ctx, &dccg_regs, &dccg_shift, &dccg_mask); 2349 if (pool->base.dccg == NULL) { 2350 dm_error("DC: failed to create dccg!\n"); 2351 BREAK_TO_DEBUGGER(); 2352 goto create_fail; 2353 } 2354 2355 /* TODO: IRQ */ 2356 init_data.ctx = dc->ctx; 2357 pool->base.irqs = dal_irq_service_dcn31_create(&init_data); 2358 if (!pool->base.irqs) 2359 goto create_fail; 2360 2361 /* HUBBUB */ 2362 pool->base.hubbub = dcn31_hubbub_create(ctx); 2363 if (pool->base.hubbub == NULL) { 2364 BREAK_TO_DEBUGGER(); 2365 dm_error("DC: failed to create hubbub!\n"); 2366 goto create_fail; 2367 } 2368 2369 /* HUBPs, DPPs, OPPs and TGs */ 2370 for (i = 0; i < pool->base.pipe_count; i++) { 2371 pool->base.hubps[i] = dcn31_hubp_create(ctx, i); 2372 if (pool->base.hubps[i] == NULL) { 2373 BREAK_TO_DEBUGGER(); 2374 dm_error( 2375 "DC: failed to create hubps!\n"); 2376 goto create_fail; 2377 } 2378 2379 pool->base.dpps[i] = dcn31_dpp_create(ctx, i); 2380 if (pool->base.dpps[i] == NULL) { 2381 BREAK_TO_DEBUGGER(); 2382 dm_error( 2383 "DC: failed to create dpps!\n"); 2384 goto create_fail; 2385 } 2386 } 2387 2388 for (i = 0; i < pool->base.res_cap->num_opp; i++) { 2389 pool->base.opps[i] = dcn31_opp_create(ctx, i); 2390 if (pool->base.opps[i] == NULL) { 2391 BREAK_TO_DEBUGGER(); 2392 dm_error( 2393 "DC: failed to create output pixel processor!\n"); 2394 goto create_fail; 2395 } 2396 } 2397 2398 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { 2399 pool->base.timing_generators[i] = dcn31_timing_generator_create( 2400 ctx, i); 2401 if (pool->base.timing_generators[i] == NULL) { 2402 BREAK_TO_DEBUGGER(); 2403 dm_error("DC: failed to create tg!\n"); 2404 goto create_fail; 2405 } 2406 } 2407 pool->base.timing_generator_count = i; 2408 2409 /* PSR */ 2410 pool->base.psr = dmub_psr_create(ctx); 2411 if (pool->base.psr == NULL) { 2412 dm_error("DC: failed to create psr obj!\n"); 2413 BREAK_TO_DEBUGGER(); 2414 goto create_fail; 2415 } 2416 2417 /* ABM */ 2418 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { 2419 pool->base.multiple_abms[i] = dmub_abm_create(ctx, 2420 &abm_regs[i], 2421 &abm_shift, 2422 &abm_mask); 2423 if (pool->base.multiple_abms[i] == NULL) { 2424 dm_error("DC: failed to create abm for pipe %d!\n", i); 2425 BREAK_TO_DEBUGGER(); 2426 goto create_fail; 2427 } 2428 } 2429 2430 /* MPC and DSC */ 2431 pool->base.mpc = dcn31_mpc_create(ctx, pool->base.mpcc_count, pool->base.res_cap->num_mpc_3dlut); 2432 if (pool->base.mpc == NULL) { 2433 BREAK_TO_DEBUGGER(); 2434 dm_error("DC: failed to create mpc!\n"); 2435 goto create_fail; 2436 } 2437 2438 for (i = 0; i < pool->base.res_cap->num_dsc; i++) { 2439 pool->base.dscs[i] = dcn31_dsc_create(ctx, i); 2440 if (pool->base.dscs[i] == NULL) { 2441 BREAK_TO_DEBUGGER(); 2442 dm_error("DC: failed to create display stream compressor %d!\n", i); 2443 goto create_fail; 2444 } 2445 } 2446 2447 /* DWB and MMHUBBUB */ 2448 if (!dcn31_dwbc_create(ctx, &pool->base)) { 2449 BREAK_TO_DEBUGGER(); 2450 dm_error("DC: failed to create dwbc!\n"); 2451 goto create_fail; 2452 } 2453 2454 if (!dcn31_mmhubbub_create(ctx, &pool->base)) { 2455 BREAK_TO_DEBUGGER(); 2456 dm_error("DC: failed to create mcif_wb!\n"); 2457 goto create_fail; 2458 } 2459 2460 /* AUX and I2C */ 2461 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { 2462 pool->base.engines[i] = dcn31_aux_engine_create(ctx, i); 2463 if (pool->base.engines[i] == NULL) { 2464 BREAK_TO_DEBUGGER(); 2465 dm_error( 2466 "DC:failed to create aux engine!!\n"); 2467 goto create_fail; 2468 } 2469 pool->base.hw_i2cs[i] = dcn31_i2c_hw_create(ctx, i); 2470 if (pool->base.hw_i2cs[i] == NULL) { 2471 BREAK_TO_DEBUGGER(); 2472 dm_error( 2473 "DC:failed to create hw i2c!!\n"); 2474 goto create_fail; 2475 } 2476 pool->base.sw_i2cs[i] = NULL; 2477 } 2478 2479 if (dc->ctx->asic_id.chip_family == FAMILY_YELLOW_CARP && 2480 dc->ctx->asic_id.hw_internal_rev == YELLOW_CARP_B0 && 2481 !dc->debug.dpia_debug.bits.disable_dpia) { 2482 /* YELLOW CARP B0 has 4 DPIA's */ 2483 pool->base.usb4_dpia_count = 4; 2484 } 2485 2486 /* Audio, Stream Encoders including HPO and virtual, MPC 3D LUTs */ 2487 if (!resource_construct(num_virtual_links, dc, &pool->base, 2488 (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment) ? 2489 &res_create_funcs : &res_create_maximus_funcs))) 2490 goto create_fail; 2491 2492 /* HW Sequencer and Plane caps */ 2493 dcn31_hw_sequencer_construct(dc); 2494 2495 dc->caps.max_planes = pool->base.pipe_count; 2496 2497 for (i = 0; i < dc->caps.max_planes; ++i) 2498 dc->caps.planes[i] = plane_cap; 2499 2500 dc->cap_funcs = cap_funcs; 2501 2502 dc->dcn_ip->max_num_dpp = dcn3_1_ip.max_num_dpp; 2503 2504 DC_FP_END(); 2505 2506 return true; 2507 2508 create_fail: 2509 2510 DC_FP_END(); 2511 dcn31_resource_destruct(pool); 2512 2513 return false; 2514 } 2515 2516 struct resource_pool *dcn31_create_resource_pool( 2517 const struct dc_init_data *init_data, 2518 struct dc *dc) 2519 { 2520 struct dcn31_resource_pool *pool = 2521 kzalloc(sizeof(struct dcn31_resource_pool), GFP_KERNEL); 2522 2523 if (!pool) 2524 return NULL; 2525 2526 if (dcn31_resource_construct(init_data->num_virtual_links, dc, pool)) 2527 return &pool->base; 2528 2529 BREAK_TO_DEBUGGER(); 2530 kfree(pool); 2531 return NULL; 2532 } 2533