1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 27 #include "dm_services.h" 28 #include "dc.h" 29 30 #include "dcn31/dcn31_init.h" 31 32 #include "resource.h" 33 #include "include/irq_service_interface.h" 34 #include "dcn31_resource.h" 35 36 #include "dcn20/dcn20_resource.h" 37 #include "dcn30/dcn30_resource.h" 38 39 #include "dml/dcn30/dcn30_fpu.h" 40 41 #include "dcn10/dcn10_ipp.h" 42 #include "dcn30/dcn30_hubbub.h" 43 #include "dcn31/dcn31_hubbub.h" 44 #include "dcn30/dcn30_mpc.h" 45 #include "dcn31/dcn31_hubp.h" 46 #include "irq/dcn31/irq_service_dcn31.h" 47 #include "dcn30/dcn30_dpp.h" 48 #include "dcn31/dcn31_optc.h" 49 #include "dcn20/dcn20_hwseq.h" 50 #include "dcn30/dcn30_hwseq.h" 51 #include "dce110/dce110_hw_sequencer.h" 52 #include "dcn30/dcn30_opp.h" 53 #include "dcn20/dcn20_dsc.h" 54 #include "dcn30/dcn30_vpg.h" 55 #include "dcn30/dcn30_afmt.h" 56 #include "dcn30/dcn30_dio_stream_encoder.h" 57 #include "dcn31/dcn31_hpo_dp_stream_encoder.h" 58 #include "dcn31/dcn31_hpo_dp_link_encoder.h" 59 #include "dcn31/dcn31_apg.h" 60 #include "dcn31/dcn31_dio_link_encoder.h" 61 #include "dcn31/dcn31_vpg.h" 62 #include "dcn31/dcn31_afmt.h" 63 #include "dce/dce_clock_source.h" 64 #include "dce/dce_audio.h" 65 #include "dce/dce_hwseq.h" 66 #include "clk_mgr.h" 67 #include "virtual/virtual_stream_encoder.h" 68 #include "dce110/dce110_resource.h" 69 #include "dml/display_mode_vba.h" 70 #include "dml/dcn31/dcn31_fpu.h" 71 #include "dcn31/dcn31_dccg.h" 72 #include "dcn10/dcn10_resource.h" 73 #include "dcn31_panel_cntl.h" 74 75 #include "dcn30/dcn30_dwb.h" 76 #include "dcn30/dcn30_mmhubbub.h" 77 78 // TODO: change include headers /amd/include/asic_reg after upstream 79 #include "yellow_carp_offset.h" 80 #include "dcn/dcn_3_1_2_offset.h" 81 #include "dcn/dcn_3_1_2_sh_mask.h" 82 #include "nbio/nbio_7_2_0_offset.h" 83 #include "dpcs/dpcs_4_2_0_offset.h" 84 #include "dpcs/dpcs_4_2_0_sh_mask.h" 85 #include "mmhub/mmhub_2_3_0_offset.h" 86 #include "mmhub/mmhub_2_3_0_sh_mask.h" 87 88 89 #define regDCHUBBUB_DEBUG_CTRL_0 0x04d6 90 #define regDCHUBBUB_DEBUG_CTRL_0_BASE_IDX 2 91 #define DCHUBBUB_DEBUG_CTRL_0__DET_DEPTH__SHIFT 0x10 92 #define DCHUBBUB_DEBUG_CTRL_0__DET_DEPTH_MASK 0x01FF0000L 93 94 #include "reg_helper.h" 95 #include "dce/dmub_abm.h" 96 #include "dce/dmub_psr.h" 97 #include "dce/dce_aux.h" 98 #include "dce/dce_i2c.h" 99 100 #include "dml/dcn30/display_mode_vba_30.h" 101 #include "vm_helper.h" 102 #include "dcn20/dcn20_vmid.h" 103 104 #include "link_enc_cfg.h" 105 106 #define DC_LOGGER_INIT(logger) 107 108 enum dcn31_clk_src_array_id { 109 DCN31_CLK_SRC_PLL0, 110 DCN31_CLK_SRC_PLL1, 111 DCN31_CLK_SRC_PLL2, 112 DCN31_CLK_SRC_PLL3, 113 DCN31_CLK_SRC_PLL4, 114 DCN30_CLK_SRC_TOTAL 115 }; 116 117 /* begin ********************* 118 * macros to expend register list macro defined in HW object header file 119 */ 120 121 /* DCN */ 122 #define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg 123 124 #define BASE(seg) BASE_INNER(seg) 125 126 #define SR(reg_name)\ 127 .reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \ 128 reg ## reg_name 129 130 #define SRI(reg_name, block, id)\ 131 .reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 132 reg ## block ## id ## _ ## reg_name 133 134 #define SRI2(reg_name, block, id)\ 135 .reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \ 136 reg ## reg_name 137 138 #define SRIR(var_name, reg_name, block, id)\ 139 .var_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 140 reg ## block ## id ## _ ## reg_name 141 142 #define SRII(reg_name, block, id)\ 143 .reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 144 reg ## block ## id ## _ ## reg_name 145 146 #define SRII_MPC_RMU(reg_name, block, id)\ 147 .RMU##_##reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 148 reg ## block ## id ## _ ## reg_name 149 150 #define SRII_DWB(reg_name, temp_name, block, id)\ 151 .reg_name[id] = BASE(reg ## block ## id ## _ ## temp_name ## _BASE_IDX) + \ 152 reg ## block ## id ## _ ## temp_name 153 154 #define SF_DWB2(reg_name, block, id, field_name, post_fix) \ 155 .field_name = reg_name ## __ ## field_name ## post_fix 156 157 #define DCCG_SRII(reg_name, block, id)\ 158 .block ## _ ## reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 159 reg ## block ## id ## _ ## reg_name 160 161 #define VUPDATE_SRII(reg_name, block, id)\ 162 .reg_name[id] = BASE(reg ## reg_name ## _ ## block ## id ## _BASE_IDX) + \ 163 reg ## reg_name ## _ ## block ## id 164 165 /* NBIO */ 166 #define NBIO_BASE_INNER(seg) \ 167 NBIO_BASE__INST0_SEG ## seg 168 169 #define NBIO_BASE(seg) \ 170 NBIO_BASE_INNER(seg) 171 172 #define NBIO_SR(reg_name)\ 173 .reg_name = NBIO_BASE(regBIF_BX1_ ## reg_name ## _BASE_IDX) + \ 174 regBIF_BX1_ ## reg_name 175 176 /* MMHUB */ 177 #define MMHUB_BASE_INNER(seg) \ 178 MMHUB_BASE__INST0_SEG ## seg 179 180 #define MMHUB_BASE(seg) \ 181 MMHUB_BASE_INNER(seg) 182 183 #define MMHUB_SR(reg_name)\ 184 .reg_name = MMHUB_BASE(mm ## reg_name ## _BASE_IDX) + \ 185 mm ## reg_name 186 187 /* CLOCK */ 188 #define CLK_BASE_INNER(seg) \ 189 CLK_BASE__INST0_SEG ## seg 190 191 #define CLK_BASE(seg) \ 192 CLK_BASE_INNER(seg) 193 194 #define CLK_SRI(reg_name, block, inst)\ 195 .reg_name = CLK_BASE(reg ## block ## _ ## inst ## _ ## reg_name ## _BASE_IDX) + \ 196 reg ## block ## _ ## inst ## _ ## reg_name 197 198 199 static const struct bios_registers bios_regs = { 200 NBIO_SR(BIOS_SCRATCH_3), 201 NBIO_SR(BIOS_SCRATCH_6) 202 }; 203 204 #define clk_src_regs(index, pllid)\ 205 [index] = {\ 206 CS_COMMON_REG_LIST_DCN3_0(index, pllid),\ 207 } 208 209 static const struct dce110_clk_src_regs clk_src_regs[] = { 210 clk_src_regs(0, A), 211 clk_src_regs(1, B), 212 clk_src_regs(2, C), 213 clk_src_regs(3, D), 214 clk_src_regs(4, E) 215 }; 216 /*pll_id being rempped in dmub, in driver it is logical instance*/ 217 static const struct dce110_clk_src_regs clk_src_regs_b0[] = { 218 clk_src_regs(0, A), 219 clk_src_regs(1, B), 220 clk_src_regs(2, F), 221 clk_src_regs(3, G), 222 clk_src_regs(4, E) 223 }; 224 225 static const struct dce110_clk_src_shift cs_shift = { 226 CS_COMMON_MASK_SH_LIST_DCN2_0(__SHIFT) 227 }; 228 229 static const struct dce110_clk_src_mask cs_mask = { 230 CS_COMMON_MASK_SH_LIST_DCN2_0(_MASK) 231 }; 232 233 #define abm_regs(id)\ 234 [id] = {\ 235 ABM_DCN302_REG_LIST(id)\ 236 } 237 238 static const struct dce_abm_registers abm_regs[] = { 239 abm_regs(0), 240 abm_regs(1), 241 abm_regs(2), 242 abm_regs(3), 243 }; 244 245 static const struct dce_abm_shift abm_shift = { 246 ABM_MASK_SH_LIST_DCN30(__SHIFT) 247 }; 248 249 static const struct dce_abm_mask abm_mask = { 250 ABM_MASK_SH_LIST_DCN30(_MASK) 251 }; 252 253 #define audio_regs(id)\ 254 [id] = {\ 255 AUD_COMMON_REG_LIST(id)\ 256 } 257 258 static const struct dce_audio_registers audio_regs[] = { 259 audio_regs(0), 260 audio_regs(1), 261 audio_regs(2), 262 audio_regs(3), 263 audio_regs(4), 264 audio_regs(5), 265 audio_regs(6) 266 }; 267 268 #define DCE120_AUD_COMMON_MASK_SH_LIST(mask_sh)\ 269 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX, AZALIA_ENDPOINT_REG_INDEX, mask_sh),\ 270 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA, AZALIA_ENDPOINT_REG_DATA, mask_sh),\ 271 AUD_COMMON_MASK_SH_LIST_BASE(mask_sh) 272 273 static const struct dce_audio_shift audio_shift = { 274 DCE120_AUD_COMMON_MASK_SH_LIST(__SHIFT) 275 }; 276 277 static const struct dce_audio_mask audio_mask = { 278 DCE120_AUD_COMMON_MASK_SH_LIST(_MASK) 279 }; 280 281 #define vpg_regs(id)\ 282 [id] = {\ 283 VPG_DCN31_REG_LIST(id)\ 284 } 285 286 static const struct dcn31_vpg_registers vpg_regs[] = { 287 vpg_regs(0), 288 vpg_regs(1), 289 vpg_regs(2), 290 vpg_regs(3), 291 vpg_regs(4), 292 vpg_regs(5), 293 vpg_regs(6), 294 vpg_regs(7), 295 vpg_regs(8), 296 vpg_regs(9), 297 }; 298 299 static const struct dcn31_vpg_shift vpg_shift = { 300 DCN31_VPG_MASK_SH_LIST(__SHIFT) 301 }; 302 303 static const struct dcn31_vpg_mask vpg_mask = { 304 DCN31_VPG_MASK_SH_LIST(_MASK) 305 }; 306 307 #define afmt_regs(id)\ 308 [id] = {\ 309 AFMT_DCN31_REG_LIST(id)\ 310 } 311 312 static const struct dcn31_afmt_registers afmt_regs[] = { 313 afmt_regs(0), 314 afmt_regs(1), 315 afmt_regs(2), 316 afmt_regs(3), 317 afmt_regs(4), 318 afmt_regs(5) 319 }; 320 321 static const struct dcn31_afmt_shift afmt_shift = { 322 DCN31_AFMT_MASK_SH_LIST(__SHIFT) 323 }; 324 325 static const struct dcn31_afmt_mask afmt_mask = { 326 DCN31_AFMT_MASK_SH_LIST(_MASK) 327 }; 328 329 #define apg_regs(id)\ 330 [id] = {\ 331 APG_DCN31_REG_LIST(id)\ 332 } 333 334 static const struct dcn31_apg_registers apg_regs[] = { 335 apg_regs(0), 336 apg_regs(1), 337 apg_regs(2), 338 apg_regs(3) 339 }; 340 341 static const struct dcn31_apg_shift apg_shift = { 342 DCN31_APG_MASK_SH_LIST(__SHIFT) 343 }; 344 345 static const struct dcn31_apg_mask apg_mask = { 346 DCN31_APG_MASK_SH_LIST(_MASK) 347 }; 348 349 #define stream_enc_regs(id)\ 350 [id] = {\ 351 SE_DCN3_REG_LIST(id)\ 352 } 353 354 /* Some encoders won't be initialized here - but they're logical, not physical. */ 355 static const struct dcn10_stream_enc_registers stream_enc_regs[ENGINE_ID_COUNT] = { 356 stream_enc_regs(0), 357 stream_enc_regs(1), 358 stream_enc_regs(2), 359 stream_enc_regs(3), 360 stream_enc_regs(4) 361 }; 362 363 static const struct dcn10_stream_encoder_shift se_shift = { 364 SE_COMMON_MASK_SH_LIST_DCN30(__SHIFT) 365 }; 366 367 static const struct dcn10_stream_encoder_mask se_mask = { 368 SE_COMMON_MASK_SH_LIST_DCN30(_MASK) 369 }; 370 371 372 #define aux_regs(id)\ 373 [id] = {\ 374 DCN2_AUX_REG_LIST(id)\ 375 } 376 377 static const struct dcn10_link_enc_aux_registers link_enc_aux_regs[] = { 378 aux_regs(0), 379 aux_regs(1), 380 aux_regs(2), 381 aux_regs(3), 382 aux_regs(4) 383 }; 384 385 #define hpd_regs(id)\ 386 [id] = {\ 387 HPD_REG_LIST(id)\ 388 } 389 390 static const struct dcn10_link_enc_hpd_registers link_enc_hpd_regs[] = { 391 hpd_regs(0), 392 hpd_regs(1), 393 hpd_regs(2), 394 hpd_regs(3), 395 hpd_regs(4) 396 }; 397 398 #define link_regs(id, phyid)\ 399 [id] = {\ 400 LE_DCN31_REG_LIST(id), \ 401 UNIPHY_DCN2_REG_LIST(phyid), \ 402 DPCS_DCN31_REG_LIST(id), \ 403 } 404 405 static const struct dce110_aux_registers_shift aux_shift = { 406 DCN_AUX_MASK_SH_LIST(__SHIFT) 407 }; 408 409 static const struct dce110_aux_registers_mask aux_mask = { 410 DCN_AUX_MASK_SH_LIST(_MASK) 411 }; 412 413 static const struct dcn10_link_enc_registers link_enc_regs[] = { 414 link_regs(0, A), 415 link_regs(1, B), 416 link_regs(2, C), 417 link_regs(3, D), 418 link_regs(4, E) 419 }; 420 421 static const struct dcn10_link_enc_shift le_shift = { 422 LINK_ENCODER_MASK_SH_LIST_DCN31(__SHIFT), \ 423 DPCS_DCN31_MASK_SH_LIST(__SHIFT) 424 }; 425 426 static const struct dcn10_link_enc_mask le_mask = { 427 LINK_ENCODER_MASK_SH_LIST_DCN31(_MASK), \ 428 DPCS_DCN31_MASK_SH_LIST(_MASK) 429 }; 430 431 #define hpo_dp_stream_encoder_reg_list(id)\ 432 [id] = {\ 433 DCN3_1_HPO_DP_STREAM_ENC_REG_LIST(id)\ 434 } 435 436 static const struct dcn31_hpo_dp_stream_encoder_registers hpo_dp_stream_enc_regs[] = { 437 hpo_dp_stream_encoder_reg_list(0), 438 hpo_dp_stream_encoder_reg_list(1), 439 hpo_dp_stream_encoder_reg_list(2), 440 hpo_dp_stream_encoder_reg_list(3), 441 }; 442 443 static const struct dcn31_hpo_dp_stream_encoder_shift hpo_dp_se_shift = { 444 DCN3_1_HPO_DP_STREAM_ENC_MASK_SH_LIST(__SHIFT) 445 }; 446 447 static const struct dcn31_hpo_dp_stream_encoder_mask hpo_dp_se_mask = { 448 DCN3_1_HPO_DP_STREAM_ENC_MASK_SH_LIST(_MASK) 449 }; 450 451 #define hpo_dp_link_encoder_reg_list(id)\ 452 [id] = {\ 453 DCN3_1_HPO_DP_LINK_ENC_REG_LIST(id),\ 454 DCN3_1_RDPCSTX_REG_LIST(0),\ 455 DCN3_1_RDPCSTX_REG_LIST(1),\ 456 DCN3_1_RDPCSTX_REG_LIST(2),\ 457 DCN3_1_RDPCSTX_REG_LIST(3),\ 458 DCN3_1_RDPCSTX_REG_LIST(4)\ 459 } 460 461 static const struct dcn31_hpo_dp_link_encoder_registers hpo_dp_link_enc_regs[] = { 462 hpo_dp_link_encoder_reg_list(0), 463 hpo_dp_link_encoder_reg_list(1), 464 }; 465 466 static const struct dcn31_hpo_dp_link_encoder_shift hpo_dp_le_shift = { 467 DCN3_1_HPO_DP_LINK_ENC_MASK_SH_LIST(__SHIFT) 468 }; 469 470 static const struct dcn31_hpo_dp_link_encoder_mask hpo_dp_le_mask = { 471 DCN3_1_HPO_DP_LINK_ENC_MASK_SH_LIST(_MASK) 472 }; 473 474 #define dpp_regs(id)\ 475 [id] = {\ 476 DPP_REG_LIST_DCN30(id),\ 477 } 478 479 static const struct dcn3_dpp_registers dpp_regs[] = { 480 dpp_regs(0), 481 dpp_regs(1), 482 dpp_regs(2), 483 dpp_regs(3) 484 }; 485 486 static const struct dcn3_dpp_shift tf_shift = { 487 DPP_REG_LIST_SH_MASK_DCN30(__SHIFT) 488 }; 489 490 static const struct dcn3_dpp_mask tf_mask = { 491 DPP_REG_LIST_SH_MASK_DCN30(_MASK) 492 }; 493 494 #define opp_regs(id)\ 495 [id] = {\ 496 OPP_REG_LIST_DCN30(id),\ 497 } 498 499 static const struct dcn20_opp_registers opp_regs[] = { 500 opp_regs(0), 501 opp_regs(1), 502 opp_regs(2), 503 opp_regs(3) 504 }; 505 506 static const struct dcn20_opp_shift opp_shift = { 507 OPP_MASK_SH_LIST_DCN20(__SHIFT) 508 }; 509 510 static const struct dcn20_opp_mask opp_mask = { 511 OPP_MASK_SH_LIST_DCN20(_MASK) 512 }; 513 514 #define aux_engine_regs(id)\ 515 [id] = {\ 516 AUX_COMMON_REG_LIST0(id), \ 517 .AUXN_IMPCAL = 0, \ 518 .AUXP_IMPCAL = 0, \ 519 .AUX_RESET_MASK = DP_AUX0_AUX_CONTROL__AUX_RESET_MASK, \ 520 } 521 522 static const struct dce110_aux_registers aux_engine_regs[] = { 523 aux_engine_regs(0), 524 aux_engine_regs(1), 525 aux_engine_regs(2), 526 aux_engine_regs(3), 527 aux_engine_regs(4) 528 }; 529 530 #define dwbc_regs_dcn3(id)\ 531 [id] = {\ 532 DWBC_COMMON_REG_LIST_DCN30(id),\ 533 } 534 535 static const struct dcn30_dwbc_registers dwbc30_regs[] = { 536 dwbc_regs_dcn3(0), 537 }; 538 539 static const struct dcn30_dwbc_shift dwbc30_shift = { 540 DWBC_COMMON_MASK_SH_LIST_DCN30(__SHIFT) 541 }; 542 543 static const struct dcn30_dwbc_mask dwbc30_mask = { 544 DWBC_COMMON_MASK_SH_LIST_DCN30(_MASK) 545 }; 546 547 #define mcif_wb_regs_dcn3(id)\ 548 [id] = {\ 549 MCIF_WB_COMMON_REG_LIST_DCN30(id),\ 550 } 551 552 static const struct dcn30_mmhubbub_registers mcif_wb30_regs[] = { 553 mcif_wb_regs_dcn3(0) 554 }; 555 556 static const struct dcn30_mmhubbub_shift mcif_wb30_shift = { 557 MCIF_WB_COMMON_MASK_SH_LIST_DCN30(__SHIFT) 558 }; 559 560 static const struct dcn30_mmhubbub_mask mcif_wb30_mask = { 561 MCIF_WB_COMMON_MASK_SH_LIST_DCN30(_MASK) 562 }; 563 564 #define dsc_regsDCN20(id)\ 565 [id] = {\ 566 DSC_REG_LIST_DCN20(id)\ 567 } 568 569 static const struct dcn20_dsc_registers dsc_regs[] = { 570 dsc_regsDCN20(0), 571 dsc_regsDCN20(1), 572 dsc_regsDCN20(2) 573 }; 574 575 static const struct dcn20_dsc_shift dsc_shift = { 576 DSC_REG_LIST_SH_MASK_DCN20(__SHIFT) 577 }; 578 579 static const struct dcn20_dsc_mask dsc_mask = { 580 DSC_REG_LIST_SH_MASK_DCN20(_MASK) 581 }; 582 583 static const struct dcn30_mpc_registers mpc_regs = { 584 MPC_REG_LIST_DCN3_0(0), 585 MPC_REG_LIST_DCN3_0(1), 586 MPC_REG_LIST_DCN3_0(2), 587 MPC_REG_LIST_DCN3_0(3), 588 MPC_OUT_MUX_REG_LIST_DCN3_0(0), 589 MPC_OUT_MUX_REG_LIST_DCN3_0(1), 590 MPC_OUT_MUX_REG_LIST_DCN3_0(2), 591 MPC_OUT_MUX_REG_LIST_DCN3_0(3), 592 MPC_RMU_GLOBAL_REG_LIST_DCN3AG, 593 MPC_RMU_REG_LIST_DCN3AG(0), 594 MPC_RMU_REG_LIST_DCN3AG(1), 595 //MPC_RMU_REG_LIST_DCN3AG(2), 596 MPC_DWB_MUX_REG_LIST_DCN3_0(0), 597 }; 598 599 static const struct dcn30_mpc_shift mpc_shift = { 600 MPC_COMMON_MASK_SH_LIST_DCN30(__SHIFT) 601 }; 602 603 static const struct dcn30_mpc_mask mpc_mask = { 604 MPC_COMMON_MASK_SH_LIST_DCN30(_MASK) 605 }; 606 607 #define optc_regs(id)\ 608 [id] = {OPTC_COMMON_REG_LIST_DCN3_1(id)} 609 610 static const struct dcn_optc_registers optc_regs[] = { 611 optc_regs(0), 612 optc_regs(1), 613 optc_regs(2), 614 optc_regs(3) 615 }; 616 617 static const struct dcn_optc_shift optc_shift = { 618 OPTC_COMMON_MASK_SH_LIST_DCN3_1(__SHIFT) 619 }; 620 621 static const struct dcn_optc_mask optc_mask = { 622 OPTC_COMMON_MASK_SH_LIST_DCN3_1(_MASK) 623 }; 624 625 #define hubp_regs(id)\ 626 [id] = {\ 627 HUBP_REG_LIST_DCN30(id)\ 628 } 629 630 static const struct dcn_hubp2_registers hubp_regs[] = { 631 hubp_regs(0), 632 hubp_regs(1), 633 hubp_regs(2), 634 hubp_regs(3) 635 }; 636 637 638 static const struct dcn_hubp2_shift hubp_shift = { 639 HUBP_MASK_SH_LIST_DCN31(__SHIFT) 640 }; 641 642 static const struct dcn_hubp2_mask hubp_mask = { 643 HUBP_MASK_SH_LIST_DCN31(_MASK) 644 }; 645 static const struct dcn_hubbub_registers hubbub_reg = { 646 HUBBUB_REG_LIST_DCN31(0) 647 }; 648 649 static const struct dcn_hubbub_shift hubbub_shift = { 650 HUBBUB_MASK_SH_LIST_DCN31(__SHIFT) 651 }; 652 653 static const struct dcn_hubbub_mask hubbub_mask = { 654 HUBBUB_MASK_SH_LIST_DCN31(_MASK) 655 }; 656 657 static const struct dccg_registers dccg_regs = { 658 DCCG_REG_LIST_DCN31() 659 }; 660 661 static const struct dccg_shift dccg_shift = { 662 DCCG_MASK_SH_LIST_DCN31(__SHIFT) 663 }; 664 665 static const struct dccg_mask dccg_mask = { 666 DCCG_MASK_SH_LIST_DCN31(_MASK) 667 }; 668 669 670 #define SRII2(reg_name_pre, reg_name_post, id)\ 671 .reg_name_pre ## _ ## reg_name_post[id] = BASE(reg ## reg_name_pre \ 672 ## id ## _ ## reg_name_post ## _BASE_IDX) + \ 673 reg ## reg_name_pre ## id ## _ ## reg_name_post 674 675 676 #define HWSEQ_DCN31_REG_LIST()\ 677 SR(DCHUBBUB_GLOBAL_TIMER_CNTL), \ 678 SR(DCHUBBUB_ARB_HOSTVM_CNTL), \ 679 SR(DIO_MEM_PWR_CTRL), \ 680 SR(ODM_MEM_PWR_CTRL3), \ 681 SR(DMU_MEM_PWR_CNTL), \ 682 SR(MMHUBBUB_MEM_PWR_CNTL), \ 683 SR(DCCG_GATE_DISABLE_CNTL), \ 684 SR(DCCG_GATE_DISABLE_CNTL2), \ 685 SR(DCFCLK_CNTL),\ 686 SR(DC_MEM_GLOBAL_PWR_REQ_CNTL), \ 687 SRII(PIXEL_RATE_CNTL, OTG, 0), \ 688 SRII(PIXEL_RATE_CNTL, OTG, 1),\ 689 SRII(PIXEL_RATE_CNTL, OTG, 2),\ 690 SRII(PIXEL_RATE_CNTL, OTG, 3),\ 691 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 0),\ 692 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 1),\ 693 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 2),\ 694 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 3),\ 695 SR(MICROSECOND_TIME_BASE_DIV), \ 696 SR(MILLISECOND_TIME_BASE_DIV), \ 697 SR(DISPCLK_FREQ_CHANGE_CNTL), \ 698 SR(RBBMIF_TIMEOUT_DIS), \ 699 SR(RBBMIF_TIMEOUT_DIS_2), \ 700 SR(DCHUBBUB_CRC_CTRL), \ 701 SR(DPP_TOP0_DPP_CRC_CTRL), \ 702 SR(DPP_TOP0_DPP_CRC_VAL_B_A), \ 703 SR(DPP_TOP0_DPP_CRC_VAL_R_G), \ 704 SR(MPC_CRC_CTRL), \ 705 SR(MPC_CRC_RESULT_GB), \ 706 SR(MPC_CRC_RESULT_C), \ 707 SR(MPC_CRC_RESULT_AR), \ 708 SR(DOMAIN0_PG_CONFIG), \ 709 SR(DOMAIN1_PG_CONFIG), \ 710 SR(DOMAIN2_PG_CONFIG), \ 711 SR(DOMAIN3_PG_CONFIG), \ 712 SR(DOMAIN16_PG_CONFIG), \ 713 SR(DOMAIN17_PG_CONFIG), \ 714 SR(DOMAIN18_PG_CONFIG), \ 715 SR(DOMAIN0_PG_STATUS), \ 716 SR(DOMAIN1_PG_STATUS), \ 717 SR(DOMAIN2_PG_STATUS), \ 718 SR(DOMAIN3_PG_STATUS), \ 719 SR(DOMAIN16_PG_STATUS), \ 720 SR(DOMAIN17_PG_STATUS), \ 721 SR(DOMAIN18_PG_STATUS), \ 722 SR(D1VGA_CONTROL), \ 723 SR(D2VGA_CONTROL), \ 724 SR(D3VGA_CONTROL), \ 725 SR(D4VGA_CONTROL), \ 726 SR(D5VGA_CONTROL), \ 727 SR(D6VGA_CONTROL), \ 728 SR(DC_IP_REQUEST_CNTL), \ 729 SR(AZALIA_AUDIO_DTO), \ 730 SR(AZALIA_CONTROLLER_CLOCK_GATING), \ 731 SR(HPO_TOP_HW_CONTROL) 732 733 static const struct dce_hwseq_registers hwseq_reg = { 734 HWSEQ_DCN31_REG_LIST() 735 }; 736 737 #define HWSEQ_DCN31_MASK_SH_LIST(mask_sh)\ 738 HWSEQ_DCN_MASK_SH_LIST(mask_sh), \ 739 HWS_SF(, DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_REFDIV, mask_sh), \ 740 HWS_SF(, DCHUBBUB_ARB_HOSTVM_CNTL, DISABLE_HOSTVM_FORCE_ALLOW_PSTATE, mask_sh), \ 741 HWS_SF(, DOMAIN0_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ 742 HWS_SF(, DOMAIN0_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ 743 HWS_SF(, DOMAIN1_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ 744 HWS_SF(, DOMAIN1_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ 745 HWS_SF(, DOMAIN2_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ 746 HWS_SF(, DOMAIN2_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ 747 HWS_SF(, DOMAIN3_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ 748 HWS_SF(, DOMAIN3_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ 749 HWS_SF(, DOMAIN16_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ 750 HWS_SF(, DOMAIN16_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ 751 HWS_SF(, DOMAIN17_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ 752 HWS_SF(, DOMAIN17_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ 753 HWS_SF(, DOMAIN18_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ 754 HWS_SF(, DOMAIN18_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ 755 HWS_SF(, DOMAIN0_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ 756 HWS_SF(, DOMAIN1_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ 757 HWS_SF(, DOMAIN2_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ 758 HWS_SF(, DOMAIN3_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ 759 HWS_SF(, DOMAIN16_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ 760 HWS_SF(, DOMAIN17_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ 761 HWS_SF(, DOMAIN18_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ 762 HWS_SF(, DC_IP_REQUEST_CNTL, IP_REQUEST_EN, mask_sh), \ 763 HWS_SF(, AZALIA_AUDIO_DTO, AZALIA_AUDIO_DTO_MODULE, mask_sh), \ 764 HWS_SF(, HPO_TOP_CLOCK_CONTROL, HPO_HDMISTREAMCLK_G_GATE_DIS, mask_sh), \ 765 HWS_SF(, DMU_MEM_PWR_CNTL, DMCU_ERAM_MEM_PWR_FORCE, mask_sh), \ 766 HWS_SF(, ODM_MEM_PWR_CTRL3, ODM_MEM_UNASSIGNED_PWR_MODE, mask_sh), \ 767 HWS_SF(, ODM_MEM_PWR_CTRL3, ODM_MEM_VBLANK_PWR_MODE, mask_sh), \ 768 HWS_SF(, MMHUBBUB_MEM_PWR_CNTL, VGA_MEM_PWR_FORCE, mask_sh), \ 769 HWS_SF(, DIO_MEM_PWR_CTRL, I2C_LIGHT_SLEEP_FORCE, mask_sh), \ 770 HWS_SF(, HPO_TOP_HW_CONTROL, HPO_IO_EN, mask_sh) 771 772 static const struct dce_hwseq_shift hwseq_shift = { 773 HWSEQ_DCN31_MASK_SH_LIST(__SHIFT) 774 }; 775 776 static const struct dce_hwseq_mask hwseq_mask = { 777 HWSEQ_DCN31_MASK_SH_LIST(_MASK) 778 }; 779 #define vmid_regs(id)\ 780 [id] = {\ 781 DCN20_VMID_REG_LIST(id)\ 782 } 783 784 static const struct dcn_vmid_registers vmid_regs[] = { 785 vmid_regs(0), 786 vmid_regs(1), 787 vmid_regs(2), 788 vmid_regs(3), 789 vmid_regs(4), 790 vmid_regs(5), 791 vmid_regs(6), 792 vmid_regs(7), 793 vmid_regs(8), 794 vmid_regs(9), 795 vmid_regs(10), 796 vmid_regs(11), 797 vmid_regs(12), 798 vmid_regs(13), 799 vmid_regs(14), 800 vmid_regs(15) 801 }; 802 803 static const struct dcn20_vmid_shift vmid_shifts = { 804 DCN20_VMID_MASK_SH_LIST(__SHIFT) 805 }; 806 807 static const struct dcn20_vmid_mask vmid_masks = { 808 DCN20_VMID_MASK_SH_LIST(_MASK) 809 }; 810 811 static const struct resource_caps res_cap_dcn31 = { 812 .num_timing_generator = 4, 813 .num_opp = 4, 814 .num_video_plane = 4, 815 .num_audio = 5, 816 .num_stream_encoder = 5, 817 .num_dig_link_enc = 5, 818 .num_hpo_dp_stream_encoder = 4, 819 .num_hpo_dp_link_encoder = 2, 820 .num_pll = 5, 821 .num_dwb = 1, 822 .num_ddc = 5, 823 .num_vmid = 16, 824 .num_mpc_3dlut = 2, 825 .num_dsc = 3, 826 }; 827 828 static const struct dc_plane_cap plane_cap = { 829 .type = DC_PLANE_TYPE_DCN_UNIVERSAL, 830 .blends_with_above = true, 831 .blends_with_below = true, 832 .per_pixel_alpha = true, 833 834 .pixel_format_support = { 835 .argb8888 = true, 836 .nv12 = true, 837 .fp16 = true, 838 .p010 = true, 839 .ayuv = false, 840 }, 841 842 .max_upscale_factor = { 843 .argb8888 = 16000, 844 .nv12 = 16000, 845 .fp16 = 16000 846 }, 847 848 // 6:1 downscaling ratio: 1000/6 = 166.666 849 .max_downscale_factor = { 850 .argb8888 = 167, 851 .nv12 = 167, 852 .fp16 = 167 853 }, 854 64, 855 64 856 }; 857 858 static const struct dc_debug_options debug_defaults_drv = { 859 .disable_dmcu = true, 860 .force_abm_enable = false, 861 .timing_trace = false, 862 .clock_trace = true, 863 .disable_pplib_clock_request = false, 864 .pipe_split_policy = MPC_SPLIT_DYNAMIC, 865 .force_single_disp_pipe_split = false, 866 .disable_dcc = DCC_ENABLE, 867 .vsr_support = true, 868 .performance_trace = false, 869 .max_downscale_src_width = 4096,/*upto true 4K*/ 870 .disable_pplib_wm_range = false, 871 .scl_reset_length10 = true, 872 .sanity_checks = true, 873 .underflow_assert_delay_us = 0xFFFFFFFF, 874 .dwb_fi_phase = -1, // -1 = disable, 875 .dmub_command_table = true, 876 .pstate_enabled = true, 877 .use_max_lb = true, 878 .enable_mem_low_power = { 879 .bits = { 880 .vga = true, 881 .i2c = true, 882 .dmcu = false, // This is previously known to cause hang on S3 cycles if enabled 883 .dscl = true, 884 .cm = true, 885 .mpc = true, 886 .optc = true, 887 .vpg = true, 888 .afmt = true, 889 } 890 }, 891 .disable_z10 = true, 892 .enable_z9_disable_interface = true, /* Allow support for the PMFW interface for disable Z9*/ 893 .dml_hostvm_override = DML_HOSTVM_OVERRIDE_FALSE, 894 }; 895 896 static const struct dc_debug_options debug_defaults_diags = { 897 .disable_dmcu = true, 898 .force_abm_enable = false, 899 .timing_trace = true, 900 .clock_trace = true, 901 .disable_dpp_power_gate = true, 902 .disable_hubp_power_gate = true, 903 .disable_clock_gate = true, 904 .disable_pplib_clock_request = true, 905 .disable_pplib_wm_range = true, 906 .disable_stutter = false, 907 .scl_reset_length10 = true, 908 .dwb_fi_phase = -1, // -1 = disable 909 .dmub_command_table = true, 910 .enable_tri_buf = true, 911 .use_max_lb = true 912 }; 913 914 static const struct dc_panel_config panel_config_defaults = { 915 .psr = { 916 .disable_psr = false, 917 .disallow_psrsu = false, 918 }, 919 .ilr = { 920 .optimize_edp_link_rate = true, 921 }, 922 }; 923 924 static void dcn31_dpp_destroy(struct dpp **dpp) 925 { 926 kfree(TO_DCN20_DPP(*dpp)); 927 *dpp = NULL; 928 } 929 930 static struct dpp *dcn31_dpp_create( 931 struct dc_context *ctx, 932 uint32_t inst) 933 { 934 struct dcn3_dpp *dpp = 935 kzalloc(sizeof(struct dcn3_dpp), GFP_KERNEL); 936 937 if (!dpp) 938 return NULL; 939 940 if (dpp3_construct(dpp, ctx, inst, 941 &dpp_regs[inst], &tf_shift, &tf_mask)) 942 return &dpp->base; 943 944 BREAK_TO_DEBUGGER(); 945 kfree(dpp); 946 return NULL; 947 } 948 949 static struct output_pixel_processor *dcn31_opp_create( 950 struct dc_context *ctx, uint32_t inst) 951 { 952 struct dcn20_opp *opp = 953 kzalloc(sizeof(struct dcn20_opp), GFP_KERNEL); 954 955 if (!opp) { 956 BREAK_TO_DEBUGGER(); 957 return NULL; 958 } 959 960 dcn20_opp_construct(opp, ctx, inst, 961 &opp_regs[inst], &opp_shift, &opp_mask); 962 return &opp->base; 963 } 964 965 static struct dce_aux *dcn31_aux_engine_create( 966 struct dc_context *ctx, 967 uint32_t inst) 968 { 969 struct aux_engine_dce110 *aux_engine = 970 kzalloc(sizeof(struct aux_engine_dce110), GFP_KERNEL); 971 972 if (!aux_engine) 973 return NULL; 974 975 dce110_aux_engine_construct(aux_engine, ctx, inst, 976 SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD, 977 &aux_engine_regs[inst], 978 &aux_mask, 979 &aux_shift, 980 ctx->dc->caps.extended_aux_timeout_support); 981 982 return &aux_engine->base; 983 } 984 #define i2c_inst_regs(id) { I2C_HW_ENGINE_COMMON_REG_LIST_DCN30(id) } 985 986 static const struct dce_i2c_registers i2c_hw_regs[] = { 987 i2c_inst_regs(1), 988 i2c_inst_regs(2), 989 i2c_inst_regs(3), 990 i2c_inst_regs(4), 991 i2c_inst_regs(5), 992 }; 993 994 static const struct dce_i2c_shift i2c_shifts = { 995 I2C_COMMON_MASK_SH_LIST_DCN30(__SHIFT) 996 }; 997 998 static const struct dce_i2c_mask i2c_masks = { 999 I2C_COMMON_MASK_SH_LIST_DCN30(_MASK) 1000 }; 1001 1002 static struct dce_i2c_hw *dcn31_i2c_hw_create( 1003 struct dc_context *ctx, 1004 uint32_t inst) 1005 { 1006 struct dce_i2c_hw *dce_i2c_hw = 1007 kzalloc(sizeof(struct dce_i2c_hw), GFP_KERNEL); 1008 1009 if (!dce_i2c_hw) 1010 return NULL; 1011 1012 dcn2_i2c_hw_construct(dce_i2c_hw, ctx, inst, 1013 &i2c_hw_regs[inst], &i2c_shifts, &i2c_masks); 1014 1015 return dce_i2c_hw; 1016 } 1017 static struct mpc *dcn31_mpc_create( 1018 struct dc_context *ctx, 1019 int num_mpcc, 1020 int num_rmu) 1021 { 1022 struct dcn30_mpc *mpc30 = kzalloc(sizeof(struct dcn30_mpc), 1023 GFP_KERNEL); 1024 1025 if (!mpc30) 1026 return NULL; 1027 1028 dcn30_mpc_construct(mpc30, ctx, 1029 &mpc_regs, 1030 &mpc_shift, 1031 &mpc_mask, 1032 num_mpcc, 1033 num_rmu); 1034 1035 return &mpc30->base; 1036 } 1037 1038 static struct hubbub *dcn31_hubbub_create(struct dc_context *ctx) 1039 { 1040 int i; 1041 1042 struct dcn20_hubbub *hubbub3 = kzalloc(sizeof(struct dcn20_hubbub), 1043 GFP_KERNEL); 1044 1045 if (!hubbub3) 1046 return NULL; 1047 1048 hubbub31_construct(hubbub3, ctx, 1049 &hubbub_reg, 1050 &hubbub_shift, 1051 &hubbub_mask, 1052 dcn3_1_ip.det_buffer_size_kbytes, 1053 dcn3_1_ip.pixel_chunk_size_kbytes, 1054 dcn3_1_ip.config_return_buffer_size_in_kbytes); 1055 1056 1057 for (i = 0; i < res_cap_dcn31.num_vmid; i++) { 1058 struct dcn20_vmid *vmid = &hubbub3->vmid[i]; 1059 1060 vmid->ctx = ctx; 1061 1062 vmid->regs = &vmid_regs[i]; 1063 vmid->shifts = &vmid_shifts; 1064 vmid->masks = &vmid_masks; 1065 } 1066 1067 return &hubbub3->base; 1068 } 1069 1070 static struct timing_generator *dcn31_timing_generator_create( 1071 struct dc_context *ctx, 1072 uint32_t instance) 1073 { 1074 struct optc *tgn10 = 1075 kzalloc(sizeof(struct optc), GFP_KERNEL); 1076 1077 if (!tgn10) 1078 return NULL; 1079 1080 tgn10->base.inst = instance; 1081 tgn10->base.ctx = ctx; 1082 1083 tgn10->tg_regs = &optc_regs[instance]; 1084 tgn10->tg_shift = &optc_shift; 1085 tgn10->tg_mask = &optc_mask; 1086 1087 dcn31_timing_generator_init(tgn10); 1088 1089 return &tgn10->base; 1090 } 1091 1092 static const struct encoder_feature_support link_enc_feature = { 1093 .max_hdmi_deep_color = COLOR_DEPTH_121212, 1094 .max_hdmi_pixel_clock = 600000, 1095 .hdmi_ycbcr420_supported = true, 1096 .dp_ycbcr420_supported = true, 1097 .fec_supported = true, 1098 .flags.bits.IS_HBR2_CAPABLE = true, 1099 .flags.bits.IS_HBR3_CAPABLE = true, 1100 .flags.bits.IS_TPS3_CAPABLE = true, 1101 .flags.bits.IS_TPS4_CAPABLE = true 1102 }; 1103 1104 static struct link_encoder *dcn31_link_encoder_create( 1105 struct dc_context *ctx, 1106 const struct encoder_init_data *enc_init_data) 1107 { 1108 struct dcn20_link_encoder *enc20 = 1109 kzalloc(sizeof(struct dcn20_link_encoder), GFP_KERNEL); 1110 1111 if (!enc20) 1112 return NULL; 1113 1114 dcn31_link_encoder_construct(enc20, 1115 enc_init_data, 1116 &link_enc_feature, 1117 &link_enc_regs[enc_init_data->transmitter], 1118 &link_enc_aux_regs[enc_init_data->channel - 1], 1119 &link_enc_hpd_regs[enc_init_data->hpd_source], 1120 &le_shift, 1121 &le_mask); 1122 1123 return &enc20->enc10.base; 1124 } 1125 1126 /* Create a minimal link encoder object not associated with a particular 1127 * physical connector. 1128 * resource_funcs.link_enc_create_minimal 1129 */ 1130 static struct link_encoder *dcn31_link_enc_create_minimal( 1131 struct dc_context *ctx, enum engine_id eng_id) 1132 { 1133 struct dcn20_link_encoder *enc20; 1134 1135 if ((eng_id - ENGINE_ID_DIGA) > ctx->dc->res_pool->res_cap->num_dig_link_enc) 1136 return NULL; 1137 1138 enc20 = kzalloc(sizeof(struct dcn20_link_encoder), GFP_KERNEL); 1139 if (!enc20) 1140 return NULL; 1141 1142 dcn31_link_encoder_construct_minimal( 1143 enc20, 1144 ctx, 1145 &link_enc_feature, 1146 &link_enc_regs[eng_id - ENGINE_ID_DIGA], 1147 eng_id); 1148 1149 return &enc20->enc10.base; 1150 } 1151 1152 static struct panel_cntl *dcn31_panel_cntl_create(const struct panel_cntl_init_data *init_data) 1153 { 1154 struct dcn31_panel_cntl *panel_cntl = 1155 kzalloc(sizeof(struct dcn31_panel_cntl), GFP_KERNEL); 1156 1157 if (!panel_cntl) 1158 return NULL; 1159 1160 dcn31_panel_cntl_construct(panel_cntl, init_data); 1161 1162 return &panel_cntl->base; 1163 } 1164 1165 static void read_dce_straps( 1166 struct dc_context *ctx, 1167 struct resource_straps *straps) 1168 { 1169 generic_reg_get(ctx, regDC_PINSTRAPS + BASE(regDC_PINSTRAPS_BASE_IDX), 1170 FN(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO), &straps->dc_pinstraps_audio); 1171 1172 } 1173 1174 static struct audio *dcn31_create_audio( 1175 struct dc_context *ctx, unsigned int inst) 1176 { 1177 return dce_audio_create(ctx, inst, 1178 &audio_regs[inst], &audio_shift, &audio_mask); 1179 } 1180 1181 static struct vpg *dcn31_vpg_create( 1182 struct dc_context *ctx, 1183 uint32_t inst) 1184 { 1185 struct dcn31_vpg *vpg31 = kzalloc(sizeof(struct dcn31_vpg), GFP_KERNEL); 1186 1187 if (!vpg31) 1188 return NULL; 1189 1190 vpg31_construct(vpg31, ctx, inst, 1191 &vpg_regs[inst], 1192 &vpg_shift, 1193 &vpg_mask); 1194 1195 return &vpg31->base; 1196 } 1197 1198 static struct afmt *dcn31_afmt_create( 1199 struct dc_context *ctx, 1200 uint32_t inst) 1201 { 1202 struct dcn31_afmt *afmt31 = kzalloc(sizeof(struct dcn31_afmt), GFP_KERNEL); 1203 1204 if (!afmt31) 1205 return NULL; 1206 1207 afmt31_construct(afmt31, ctx, inst, 1208 &afmt_regs[inst], 1209 &afmt_shift, 1210 &afmt_mask); 1211 1212 // Light sleep by default, no need to power down here 1213 1214 return &afmt31->base; 1215 } 1216 1217 static struct apg *dcn31_apg_create( 1218 struct dc_context *ctx, 1219 uint32_t inst) 1220 { 1221 struct dcn31_apg *apg31 = kzalloc(sizeof(struct dcn31_apg), GFP_KERNEL); 1222 1223 if (!apg31) 1224 return NULL; 1225 1226 apg31_construct(apg31, ctx, inst, 1227 &apg_regs[inst], 1228 &apg_shift, 1229 &apg_mask); 1230 1231 return &apg31->base; 1232 } 1233 1234 static struct stream_encoder *dcn31_stream_encoder_create( 1235 enum engine_id eng_id, 1236 struct dc_context *ctx) 1237 { 1238 struct dcn10_stream_encoder *enc1; 1239 struct vpg *vpg; 1240 struct afmt *afmt; 1241 int vpg_inst; 1242 int afmt_inst; 1243 1244 /* Mapping of VPG, AFMT, DME register blocks to DIO block instance */ 1245 if (eng_id <= ENGINE_ID_DIGF) { 1246 vpg_inst = eng_id; 1247 afmt_inst = eng_id; 1248 } else 1249 return NULL; 1250 1251 enc1 = kzalloc(sizeof(struct dcn10_stream_encoder), GFP_KERNEL); 1252 vpg = dcn31_vpg_create(ctx, vpg_inst); 1253 afmt = dcn31_afmt_create(ctx, afmt_inst); 1254 1255 if (!enc1 || !vpg || !afmt) { 1256 kfree(enc1); 1257 kfree(vpg); 1258 kfree(afmt); 1259 return NULL; 1260 } 1261 1262 dcn30_dio_stream_encoder_construct(enc1, ctx, ctx->dc_bios, 1263 eng_id, vpg, afmt, 1264 &stream_enc_regs[eng_id], 1265 &se_shift, &se_mask); 1266 1267 return &enc1->base; 1268 } 1269 1270 static struct hpo_dp_stream_encoder *dcn31_hpo_dp_stream_encoder_create( 1271 enum engine_id eng_id, 1272 struct dc_context *ctx) 1273 { 1274 struct dcn31_hpo_dp_stream_encoder *hpo_dp_enc31; 1275 struct vpg *vpg; 1276 struct apg *apg; 1277 uint32_t hpo_dp_inst; 1278 uint32_t vpg_inst; 1279 uint32_t apg_inst; 1280 1281 ASSERT((eng_id >= ENGINE_ID_HPO_DP_0) && (eng_id <= ENGINE_ID_HPO_DP_3)); 1282 hpo_dp_inst = eng_id - ENGINE_ID_HPO_DP_0; 1283 1284 /* Mapping of VPG register blocks to HPO DP block instance: 1285 * VPG[6] -> HPO_DP[0] 1286 * VPG[7] -> HPO_DP[1] 1287 * VPG[8] -> HPO_DP[2] 1288 * VPG[9] -> HPO_DP[3] 1289 */ 1290 vpg_inst = hpo_dp_inst + 6; 1291 1292 /* Mapping of APG register blocks to HPO DP block instance: 1293 * APG[0] -> HPO_DP[0] 1294 * APG[1] -> HPO_DP[1] 1295 * APG[2] -> HPO_DP[2] 1296 * APG[3] -> HPO_DP[3] 1297 */ 1298 apg_inst = hpo_dp_inst; 1299 1300 /* allocate HPO stream encoder and create VPG sub-block */ 1301 hpo_dp_enc31 = kzalloc(sizeof(struct dcn31_hpo_dp_stream_encoder), GFP_KERNEL); 1302 vpg = dcn31_vpg_create(ctx, vpg_inst); 1303 apg = dcn31_apg_create(ctx, apg_inst); 1304 1305 if (!hpo_dp_enc31 || !vpg || !apg) { 1306 kfree(hpo_dp_enc31); 1307 kfree(vpg); 1308 kfree(apg); 1309 return NULL; 1310 } 1311 1312 dcn31_hpo_dp_stream_encoder_construct(hpo_dp_enc31, ctx, ctx->dc_bios, 1313 hpo_dp_inst, eng_id, vpg, apg, 1314 &hpo_dp_stream_enc_regs[hpo_dp_inst], 1315 &hpo_dp_se_shift, &hpo_dp_se_mask); 1316 1317 return &hpo_dp_enc31->base; 1318 } 1319 1320 static struct hpo_dp_link_encoder *dcn31_hpo_dp_link_encoder_create( 1321 uint8_t inst, 1322 struct dc_context *ctx) 1323 { 1324 struct dcn31_hpo_dp_link_encoder *hpo_dp_enc31; 1325 1326 /* allocate HPO link encoder */ 1327 hpo_dp_enc31 = kzalloc(sizeof(struct dcn31_hpo_dp_link_encoder), GFP_KERNEL); 1328 1329 hpo_dp_link_encoder31_construct(hpo_dp_enc31, ctx, inst, 1330 &hpo_dp_link_enc_regs[inst], 1331 &hpo_dp_le_shift, &hpo_dp_le_mask); 1332 1333 return &hpo_dp_enc31->base; 1334 } 1335 1336 static struct dce_hwseq *dcn31_hwseq_create( 1337 struct dc_context *ctx) 1338 { 1339 struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_KERNEL); 1340 1341 if (hws) { 1342 hws->ctx = ctx; 1343 hws->regs = &hwseq_reg; 1344 hws->shifts = &hwseq_shift; 1345 hws->masks = &hwseq_mask; 1346 /* DCN3.1 FPGA Workaround 1347 * Need to enable HPO DP Stream Encoder before setting OTG master enable. 1348 * To do so, move calling function enable_stream_timing to only be done AFTER calling 1349 * function core_link_enable_stream 1350 */ 1351 if (IS_FPGA_MAXIMUS_DC(ctx->dce_environment)) 1352 hws->wa.dp_hpo_and_otg_sequence = true; 1353 } 1354 return hws; 1355 } 1356 static const struct resource_create_funcs res_create_funcs = { 1357 .read_dce_straps = read_dce_straps, 1358 .create_audio = dcn31_create_audio, 1359 .create_stream_encoder = dcn31_stream_encoder_create, 1360 .create_hpo_dp_stream_encoder = dcn31_hpo_dp_stream_encoder_create, 1361 .create_hpo_dp_link_encoder = dcn31_hpo_dp_link_encoder_create, 1362 .create_hwseq = dcn31_hwseq_create, 1363 }; 1364 1365 static const struct resource_create_funcs res_create_maximus_funcs = { 1366 .read_dce_straps = NULL, 1367 .create_audio = NULL, 1368 .create_stream_encoder = NULL, 1369 .create_hpo_dp_stream_encoder = dcn31_hpo_dp_stream_encoder_create, 1370 .create_hpo_dp_link_encoder = dcn31_hpo_dp_link_encoder_create, 1371 .create_hwseq = dcn31_hwseq_create, 1372 }; 1373 1374 static void dcn31_resource_destruct(struct dcn31_resource_pool *pool) 1375 { 1376 unsigned int i; 1377 1378 for (i = 0; i < pool->base.stream_enc_count; i++) { 1379 if (pool->base.stream_enc[i] != NULL) { 1380 if (pool->base.stream_enc[i]->vpg != NULL) { 1381 kfree(DCN30_VPG_FROM_VPG(pool->base.stream_enc[i]->vpg)); 1382 pool->base.stream_enc[i]->vpg = NULL; 1383 } 1384 if (pool->base.stream_enc[i]->afmt != NULL) { 1385 kfree(DCN30_AFMT_FROM_AFMT(pool->base.stream_enc[i]->afmt)); 1386 pool->base.stream_enc[i]->afmt = NULL; 1387 } 1388 kfree(DCN10STRENC_FROM_STRENC(pool->base.stream_enc[i])); 1389 pool->base.stream_enc[i] = NULL; 1390 } 1391 } 1392 1393 for (i = 0; i < pool->base.hpo_dp_stream_enc_count; i++) { 1394 if (pool->base.hpo_dp_stream_enc[i] != NULL) { 1395 if (pool->base.hpo_dp_stream_enc[i]->vpg != NULL) { 1396 kfree(DCN30_VPG_FROM_VPG(pool->base.hpo_dp_stream_enc[i]->vpg)); 1397 pool->base.hpo_dp_stream_enc[i]->vpg = NULL; 1398 } 1399 if (pool->base.hpo_dp_stream_enc[i]->apg != NULL) { 1400 kfree(DCN31_APG_FROM_APG(pool->base.hpo_dp_stream_enc[i]->apg)); 1401 pool->base.hpo_dp_stream_enc[i]->apg = NULL; 1402 } 1403 kfree(DCN3_1_HPO_DP_STREAM_ENC_FROM_HPO_STREAM_ENC(pool->base.hpo_dp_stream_enc[i])); 1404 pool->base.hpo_dp_stream_enc[i] = NULL; 1405 } 1406 } 1407 1408 for (i = 0; i < pool->base.hpo_dp_link_enc_count; i++) { 1409 if (pool->base.hpo_dp_link_enc[i] != NULL) { 1410 kfree(DCN3_1_HPO_DP_LINK_ENC_FROM_HPO_LINK_ENC(pool->base.hpo_dp_link_enc[i])); 1411 pool->base.hpo_dp_link_enc[i] = NULL; 1412 } 1413 } 1414 1415 for (i = 0; i < pool->base.res_cap->num_dsc; i++) { 1416 if (pool->base.dscs[i] != NULL) 1417 dcn20_dsc_destroy(&pool->base.dscs[i]); 1418 } 1419 1420 if (pool->base.mpc != NULL) { 1421 kfree(TO_DCN20_MPC(pool->base.mpc)); 1422 pool->base.mpc = NULL; 1423 } 1424 if (pool->base.hubbub != NULL) { 1425 kfree(pool->base.hubbub); 1426 pool->base.hubbub = NULL; 1427 } 1428 for (i = 0; i < pool->base.pipe_count; i++) { 1429 if (pool->base.dpps[i] != NULL) 1430 dcn31_dpp_destroy(&pool->base.dpps[i]); 1431 1432 if (pool->base.ipps[i] != NULL) 1433 pool->base.ipps[i]->funcs->ipp_destroy(&pool->base.ipps[i]); 1434 1435 if (pool->base.hubps[i] != NULL) { 1436 kfree(TO_DCN20_HUBP(pool->base.hubps[i])); 1437 pool->base.hubps[i] = NULL; 1438 } 1439 1440 if (pool->base.irqs != NULL) { 1441 dal_irq_service_destroy(&pool->base.irqs); 1442 } 1443 } 1444 1445 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { 1446 if (pool->base.engines[i] != NULL) 1447 dce110_engine_destroy(&pool->base.engines[i]); 1448 if (pool->base.hw_i2cs[i] != NULL) { 1449 kfree(pool->base.hw_i2cs[i]); 1450 pool->base.hw_i2cs[i] = NULL; 1451 } 1452 if (pool->base.sw_i2cs[i] != NULL) { 1453 kfree(pool->base.sw_i2cs[i]); 1454 pool->base.sw_i2cs[i] = NULL; 1455 } 1456 } 1457 1458 for (i = 0; i < pool->base.res_cap->num_opp; i++) { 1459 if (pool->base.opps[i] != NULL) 1460 pool->base.opps[i]->funcs->opp_destroy(&pool->base.opps[i]); 1461 } 1462 1463 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { 1464 if (pool->base.timing_generators[i] != NULL) { 1465 kfree(DCN10TG_FROM_TG(pool->base.timing_generators[i])); 1466 pool->base.timing_generators[i] = NULL; 1467 } 1468 } 1469 1470 for (i = 0; i < pool->base.res_cap->num_dwb; i++) { 1471 if (pool->base.dwbc[i] != NULL) { 1472 kfree(TO_DCN30_DWBC(pool->base.dwbc[i])); 1473 pool->base.dwbc[i] = NULL; 1474 } 1475 if (pool->base.mcif_wb[i] != NULL) { 1476 kfree(TO_DCN30_MMHUBBUB(pool->base.mcif_wb[i])); 1477 pool->base.mcif_wb[i] = NULL; 1478 } 1479 } 1480 1481 for (i = 0; i < pool->base.audio_count; i++) { 1482 if (pool->base.audios[i]) 1483 dce_aud_destroy(&pool->base.audios[i]); 1484 } 1485 1486 for (i = 0; i < pool->base.clk_src_count; i++) { 1487 if (pool->base.clock_sources[i] != NULL) { 1488 dcn20_clock_source_destroy(&pool->base.clock_sources[i]); 1489 pool->base.clock_sources[i] = NULL; 1490 } 1491 } 1492 1493 for (i = 0; i < pool->base.res_cap->num_mpc_3dlut; i++) { 1494 if (pool->base.mpc_lut[i] != NULL) { 1495 dc_3dlut_func_release(pool->base.mpc_lut[i]); 1496 pool->base.mpc_lut[i] = NULL; 1497 } 1498 if (pool->base.mpc_shaper[i] != NULL) { 1499 dc_transfer_func_release(pool->base.mpc_shaper[i]); 1500 pool->base.mpc_shaper[i] = NULL; 1501 } 1502 } 1503 1504 if (pool->base.dp_clock_source != NULL) { 1505 dcn20_clock_source_destroy(&pool->base.dp_clock_source); 1506 pool->base.dp_clock_source = NULL; 1507 } 1508 1509 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { 1510 if (pool->base.multiple_abms[i] != NULL) 1511 dce_abm_destroy(&pool->base.multiple_abms[i]); 1512 } 1513 1514 if (pool->base.psr != NULL) 1515 dmub_psr_destroy(&pool->base.psr); 1516 1517 if (pool->base.dccg != NULL) 1518 dcn_dccg_destroy(&pool->base.dccg); 1519 } 1520 1521 static struct hubp *dcn31_hubp_create( 1522 struct dc_context *ctx, 1523 uint32_t inst) 1524 { 1525 struct dcn20_hubp *hubp2 = 1526 kzalloc(sizeof(struct dcn20_hubp), GFP_KERNEL); 1527 1528 if (!hubp2) 1529 return NULL; 1530 1531 if (hubp31_construct(hubp2, ctx, inst, 1532 &hubp_regs[inst], &hubp_shift, &hubp_mask)) 1533 return &hubp2->base; 1534 1535 BREAK_TO_DEBUGGER(); 1536 kfree(hubp2); 1537 return NULL; 1538 } 1539 1540 static bool dcn31_dwbc_create(struct dc_context *ctx, struct resource_pool *pool) 1541 { 1542 int i; 1543 uint32_t pipe_count = pool->res_cap->num_dwb; 1544 1545 for (i = 0; i < pipe_count; i++) { 1546 struct dcn30_dwbc *dwbc30 = kzalloc(sizeof(struct dcn30_dwbc), 1547 GFP_KERNEL); 1548 1549 if (!dwbc30) { 1550 dm_error("DC: failed to create dwbc30!\n"); 1551 return false; 1552 } 1553 1554 dcn30_dwbc_construct(dwbc30, ctx, 1555 &dwbc30_regs[i], 1556 &dwbc30_shift, 1557 &dwbc30_mask, 1558 i); 1559 1560 pool->dwbc[i] = &dwbc30->base; 1561 } 1562 return true; 1563 } 1564 1565 static bool dcn31_mmhubbub_create(struct dc_context *ctx, struct resource_pool *pool) 1566 { 1567 int i; 1568 uint32_t pipe_count = pool->res_cap->num_dwb; 1569 1570 for (i = 0; i < pipe_count; i++) { 1571 struct dcn30_mmhubbub *mcif_wb30 = kzalloc(sizeof(struct dcn30_mmhubbub), 1572 GFP_KERNEL); 1573 1574 if (!mcif_wb30) { 1575 dm_error("DC: failed to create mcif_wb30!\n"); 1576 return false; 1577 } 1578 1579 dcn30_mmhubbub_construct(mcif_wb30, ctx, 1580 &mcif_wb30_regs[i], 1581 &mcif_wb30_shift, 1582 &mcif_wb30_mask, 1583 i); 1584 1585 pool->mcif_wb[i] = &mcif_wb30->base; 1586 } 1587 return true; 1588 } 1589 1590 static struct display_stream_compressor *dcn31_dsc_create( 1591 struct dc_context *ctx, uint32_t inst) 1592 { 1593 struct dcn20_dsc *dsc = 1594 kzalloc(sizeof(struct dcn20_dsc), GFP_KERNEL); 1595 1596 if (!dsc) { 1597 BREAK_TO_DEBUGGER(); 1598 return NULL; 1599 } 1600 1601 dsc2_construct(dsc, ctx, inst, &dsc_regs[inst], &dsc_shift, &dsc_mask); 1602 return &dsc->base; 1603 } 1604 1605 static void dcn31_destroy_resource_pool(struct resource_pool **pool) 1606 { 1607 struct dcn31_resource_pool *dcn31_pool = TO_DCN31_RES_POOL(*pool); 1608 1609 dcn31_resource_destruct(dcn31_pool); 1610 kfree(dcn31_pool); 1611 *pool = NULL; 1612 } 1613 1614 static struct clock_source *dcn31_clock_source_create( 1615 struct dc_context *ctx, 1616 struct dc_bios *bios, 1617 enum clock_source_id id, 1618 const struct dce110_clk_src_regs *regs, 1619 bool dp_clk_src) 1620 { 1621 struct dce110_clk_src *clk_src = 1622 kzalloc(sizeof(struct dce110_clk_src), GFP_KERNEL); 1623 1624 if (!clk_src) 1625 return NULL; 1626 1627 if (dcn3_clk_src_construct(clk_src, ctx, bios, id, 1628 regs, &cs_shift, &cs_mask)) { 1629 clk_src->base.dp_clk_src = dp_clk_src; 1630 return &clk_src->base; 1631 } 1632 1633 kfree(clk_src); 1634 BREAK_TO_DEBUGGER(); 1635 return NULL; 1636 } 1637 1638 static bool is_dual_plane(enum surface_pixel_format format) 1639 { 1640 return format >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN || format == SURFACE_PIXEL_FORMAT_GRPH_RGBE_ALPHA; 1641 } 1642 1643 int dcn31x_populate_dml_pipes_from_context(struct dc *dc, 1644 struct dc_state *context, 1645 display_e2e_pipe_params_st *pipes, 1646 bool fast_validate) 1647 { 1648 uint32_t pipe_cnt; 1649 int i; 1650 1651 dc_assert_fp_enabled(); 1652 1653 pipe_cnt = dcn20_populate_dml_pipes_from_context(dc, context, pipes, fast_validate); 1654 1655 for (i = 0; i < pipe_cnt; i++) { 1656 pipes[i].pipe.src.gpuvm = 1; 1657 if (dc->debug.dml_hostvm_override == DML_HOSTVM_NO_OVERRIDE) { 1658 //pipes[pipe_cnt].pipe.src.hostvm = dc->res_pool->hubbub->riommu_active; 1659 pipes[i].pipe.src.hostvm = dc->vm_pa_config.is_hvm_enabled; 1660 } else if (dc->debug.dml_hostvm_override == DML_HOSTVM_OVERRIDE_FALSE) 1661 pipes[i].pipe.src.hostvm = false; 1662 else if (dc->debug.dml_hostvm_override == DML_HOSTVM_OVERRIDE_TRUE) 1663 pipes[i].pipe.src.hostvm = true; 1664 } 1665 return pipe_cnt; 1666 } 1667 1668 int dcn31_populate_dml_pipes_from_context( 1669 struct dc *dc, struct dc_state *context, 1670 display_e2e_pipe_params_st *pipes, 1671 bool fast_validate) 1672 { 1673 int i, pipe_cnt; 1674 struct resource_context *res_ctx = &context->res_ctx; 1675 struct pipe_ctx *pipe; 1676 bool upscaled = false; 1677 1678 DC_FP_START(); 1679 dcn31x_populate_dml_pipes_from_context(dc, context, pipes, fast_validate); 1680 DC_FP_END(); 1681 1682 for (i = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) { 1683 struct dc_crtc_timing *timing; 1684 1685 if (!res_ctx->pipe_ctx[i].stream) 1686 continue; 1687 pipe = &res_ctx->pipe_ctx[i]; 1688 timing = &pipe->stream->timing; 1689 if (pipe->plane_state && 1690 (pipe->plane_state->src_rect.height < pipe->plane_state->dst_rect.height || 1691 pipe->plane_state->src_rect.width < pipe->plane_state->dst_rect.width)) 1692 upscaled = true; 1693 1694 /* 1695 * Immediate flip can be set dynamically after enabling the plane. 1696 * We need to require support for immediate flip or underflow can be 1697 * intermittently experienced depending on peak b/w requirements. 1698 */ 1699 pipes[pipe_cnt].pipe.src.immediate_flip = true; 1700 pipes[pipe_cnt].pipe.src.unbounded_req_mode = false; 1701 pipes[pipe_cnt].pipe.src.gpuvm = true; 1702 pipes[pipe_cnt].pipe.dest.vfront_porch = timing->v_front_porch; 1703 pipes[pipe_cnt].pipe.src.dcc_rate = 3; 1704 pipes[pipe_cnt].dout.dsc_input_bpc = 0; 1705 DC_FP_START(); 1706 dcn31_zero_pipe_dcc_fraction(pipes, pipe_cnt); 1707 DC_FP_END(); 1708 1709 1710 if (pipes[pipe_cnt].dout.dsc_enable) { 1711 switch (timing->display_color_depth) { 1712 case COLOR_DEPTH_888: 1713 pipes[pipe_cnt].dout.dsc_input_bpc = 8; 1714 break; 1715 case COLOR_DEPTH_101010: 1716 pipes[pipe_cnt].dout.dsc_input_bpc = 10; 1717 break; 1718 case COLOR_DEPTH_121212: 1719 pipes[pipe_cnt].dout.dsc_input_bpc = 12; 1720 break; 1721 default: 1722 ASSERT(0); 1723 break; 1724 } 1725 } 1726 1727 pipe_cnt++; 1728 } 1729 context->bw_ctx.dml.ip.det_buffer_size_kbytes = DCN3_1_DEFAULT_DET_SIZE; 1730 dc->config.enable_4to1MPC = false; 1731 if (pipe_cnt == 1 && pipe->plane_state && !dc->debug.disable_z9_mpc) { 1732 if (is_dual_plane(pipe->plane_state->format) 1733 && pipe->plane_state->src_rect.width <= 1920 && pipe->plane_state->src_rect.height <= 1080) { 1734 dc->config.enable_4to1MPC = true; 1735 } else if (!is_dual_plane(pipe->plane_state->format) && pipe->plane_state->src_rect.width <= 5120) { 1736 /* Limit to 5k max to avoid forced pipe split when there is not enough detile for swath */ 1737 context->bw_ctx.dml.ip.det_buffer_size_kbytes = 192; 1738 pipes[0].pipe.src.unbounded_req_mode = true; 1739 } 1740 } else if (context->stream_count >= dc->debug.crb_alloc_policy_min_disp_count 1741 && dc->debug.crb_alloc_policy > DET_SIZE_DEFAULT) { 1742 context->bw_ctx.dml.ip.det_buffer_size_kbytes = dc->debug.crb_alloc_policy * 64; 1743 } else if (context->stream_count >= 3 && upscaled) { 1744 context->bw_ctx.dml.ip.det_buffer_size_kbytes = 192; 1745 } 1746 1747 return pipe_cnt; 1748 } 1749 1750 void dcn31_calculate_wm_and_dlg( 1751 struct dc *dc, struct dc_state *context, 1752 display_e2e_pipe_params_st *pipes, 1753 int pipe_cnt, 1754 int vlevel) 1755 { 1756 DC_FP_START(); 1757 dcn31_calculate_wm_and_dlg_fp(dc, context, pipes, pipe_cnt, vlevel); 1758 DC_FP_END(); 1759 } 1760 1761 void 1762 dcn31_populate_dml_writeback_from_context(struct dc *dc, 1763 struct resource_context *res_ctx, 1764 display_e2e_pipe_params_st *pipes) 1765 { 1766 DC_FP_START(); 1767 dcn30_populate_dml_writeback_from_context(dc, res_ctx, pipes); 1768 DC_FP_END(); 1769 } 1770 1771 void 1772 dcn31_set_mcif_arb_params(struct dc *dc, 1773 struct dc_state *context, 1774 display_e2e_pipe_params_st *pipes, 1775 int pipe_cnt) 1776 { 1777 DC_FP_START(); 1778 dcn30_set_mcif_arb_params(dc, context, pipes, pipe_cnt); 1779 DC_FP_END(); 1780 } 1781 1782 bool dcn31_validate_bandwidth(struct dc *dc, 1783 struct dc_state *context, 1784 bool fast_validate) 1785 { 1786 bool out = false; 1787 1788 BW_VAL_TRACE_SETUP(); 1789 1790 int vlevel = 0; 1791 int pipe_cnt = 0; 1792 display_e2e_pipe_params_st *pipes = kzalloc(dc->res_pool->pipe_count * sizeof(display_e2e_pipe_params_st), GFP_KERNEL); 1793 DC_LOGGER_INIT(dc->ctx->logger); 1794 1795 BW_VAL_TRACE_COUNT(); 1796 1797 DC_FP_START(); 1798 out = dcn30_internal_validate_bw(dc, context, pipes, &pipe_cnt, &vlevel, fast_validate); 1799 DC_FP_END(); 1800 1801 // Disable fast_validate to set min dcfclk in alculate_wm_and_dlg 1802 if (pipe_cnt == 0) 1803 fast_validate = false; 1804 1805 if (!out) 1806 goto validate_fail; 1807 1808 BW_VAL_TRACE_END_VOLTAGE_LEVEL(); 1809 1810 if (fast_validate) { 1811 BW_VAL_TRACE_SKIP(fast); 1812 goto validate_out; 1813 } 1814 1815 dc->res_pool->funcs->calculate_wm_and_dlg(dc, context, pipes, pipe_cnt, vlevel); 1816 1817 BW_VAL_TRACE_END_WATERMARKS(); 1818 1819 goto validate_out; 1820 1821 validate_fail: 1822 DC_LOG_WARNING("Mode Validation Warning: %s failed validation.\n", 1823 dml_get_status_message(context->bw_ctx.dml.vba.ValidationStatus[context->bw_ctx.dml.vba.soc.num_states])); 1824 1825 BW_VAL_TRACE_SKIP(fail); 1826 out = false; 1827 1828 validate_out: 1829 kfree(pipes); 1830 1831 BW_VAL_TRACE_FINISH(); 1832 1833 return out; 1834 } 1835 1836 static void dcn31_get_panel_config_defaults(struct dc_panel_config *panel_config) 1837 { 1838 *panel_config = panel_config_defaults; 1839 } 1840 1841 static struct dc_cap_funcs cap_funcs = { 1842 .get_dcc_compression_cap = dcn20_get_dcc_compression_cap 1843 }; 1844 1845 static struct resource_funcs dcn31_res_pool_funcs = { 1846 .destroy = dcn31_destroy_resource_pool, 1847 .link_enc_create = dcn31_link_encoder_create, 1848 .link_enc_create_minimal = dcn31_link_enc_create_minimal, 1849 .link_encs_assign = link_enc_cfg_link_encs_assign, 1850 .link_enc_unassign = link_enc_cfg_link_enc_unassign, 1851 .panel_cntl_create = dcn31_panel_cntl_create, 1852 .validate_bandwidth = dcn31_validate_bandwidth, 1853 .calculate_wm_and_dlg = dcn31_calculate_wm_and_dlg, 1854 .update_soc_for_wm_a = dcn31_update_soc_for_wm_a, 1855 .populate_dml_pipes = dcn31_populate_dml_pipes_from_context, 1856 .acquire_idle_pipe_for_layer = dcn20_acquire_idle_pipe_for_layer, 1857 .add_stream_to_ctx = dcn30_add_stream_to_ctx, 1858 .add_dsc_to_stream_resource = dcn20_add_dsc_to_stream_resource, 1859 .remove_stream_from_ctx = dcn20_remove_stream_from_ctx, 1860 .populate_dml_writeback_from_context = dcn31_populate_dml_writeback_from_context, 1861 .set_mcif_arb_params = dcn31_set_mcif_arb_params, 1862 .find_first_free_match_stream_enc_for_link = dcn10_find_first_free_match_stream_enc_for_link, 1863 .acquire_post_bldn_3dlut = dcn30_acquire_post_bldn_3dlut, 1864 .release_post_bldn_3dlut = dcn30_release_post_bldn_3dlut, 1865 .update_bw_bounding_box = dcn31_update_bw_bounding_box, 1866 .patch_unknown_plane_state = dcn20_patch_unknown_plane_state, 1867 .get_panel_config_defaults = dcn31_get_panel_config_defaults, 1868 }; 1869 1870 static struct clock_source *dcn30_clock_source_create( 1871 struct dc_context *ctx, 1872 struct dc_bios *bios, 1873 enum clock_source_id id, 1874 const struct dce110_clk_src_regs *regs, 1875 bool dp_clk_src) 1876 { 1877 struct dce110_clk_src *clk_src = 1878 kzalloc(sizeof(struct dce110_clk_src), GFP_KERNEL); 1879 1880 if (!clk_src) 1881 return NULL; 1882 1883 if (dcn31_clk_src_construct(clk_src, ctx, bios, id, 1884 regs, &cs_shift, &cs_mask)) { 1885 clk_src->base.dp_clk_src = dp_clk_src; 1886 return &clk_src->base; 1887 } 1888 1889 BREAK_TO_DEBUGGER(); 1890 return NULL; 1891 } 1892 1893 static bool dcn31_resource_construct( 1894 uint8_t num_virtual_links, 1895 struct dc *dc, 1896 struct dcn31_resource_pool *pool) 1897 { 1898 int i; 1899 struct dc_context *ctx = dc->ctx; 1900 struct irq_service_init_data init_data; 1901 1902 ctx->dc_bios->regs = &bios_regs; 1903 1904 pool->base.res_cap = &res_cap_dcn31; 1905 1906 pool->base.funcs = &dcn31_res_pool_funcs; 1907 1908 /************************************************* 1909 * Resource + asic cap harcoding * 1910 *************************************************/ 1911 pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE; 1912 pool->base.pipe_count = pool->base.res_cap->num_timing_generator; 1913 pool->base.mpcc_count = pool->base.res_cap->num_timing_generator; 1914 dc->caps.max_downscale_ratio = 600; 1915 dc->caps.i2c_speed_in_khz = 100; 1916 dc->caps.i2c_speed_in_khz_hdcp = 5; /*1.4 w/a applied by default*/ 1917 dc->caps.max_cursor_size = 256; 1918 dc->caps.min_horizontal_blanking_period = 80; 1919 dc->caps.dmdata_alloc_size = 2048; 1920 1921 dc->caps.max_slave_planes = 2; 1922 dc->caps.max_slave_yuv_planes = 2; 1923 dc->caps.max_slave_rgb_planes = 2; 1924 dc->caps.post_blend_color_processing = true; 1925 dc->caps.force_dp_tps4_for_cp2520 = true; 1926 if (dc->config.forceHBR2CP2520) 1927 dc->caps.force_dp_tps4_for_cp2520 = false; 1928 dc->caps.dp_hpo = true; 1929 dc->caps.dp_hdmi21_pcon_support = true; 1930 dc->caps.edp_dsc_support = true; 1931 dc->caps.extended_aux_timeout_support = true; 1932 dc->caps.dmcub_support = true; 1933 dc->caps.is_apu = true; 1934 dc->caps.zstate_support = true; 1935 1936 /* Color pipeline capabilities */ 1937 dc->caps.color.dpp.dcn_arch = 1; 1938 dc->caps.color.dpp.input_lut_shared = 0; 1939 dc->caps.color.dpp.icsc = 1; 1940 dc->caps.color.dpp.dgam_ram = 0; // must use gamma_corr 1941 dc->caps.color.dpp.dgam_rom_caps.srgb = 1; 1942 dc->caps.color.dpp.dgam_rom_caps.bt2020 = 1; 1943 dc->caps.color.dpp.dgam_rom_caps.gamma2_2 = 1; 1944 dc->caps.color.dpp.dgam_rom_caps.pq = 1; 1945 dc->caps.color.dpp.dgam_rom_caps.hlg = 1; 1946 dc->caps.color.dpp.post_csc = 1; 1947 dc->caps.color.dpp.gamma_corr = 1; 1948 dc->caps.color.dpp.dgam_rom_for_yuv = 0; 1949 1950 dc->caps.color.dpp.hw_3d_lut = 1; 1951 dc->caps.color.dpp.ogam_ram = 1; 1952 // no OGAM ROM on DCN301 1953 dc->caps.color.dpp.ogam_rom_caps.srgb = 0; 1954 dc->caps.color.dpp.ogam_rom_caps.bt2020 = 0; 1955 dc->caps.color.dpp.ogam_rom_caps.gamma2_2 = 0; 1956 dc->caps.color.dpp.ogam_rom_caps.pq = 0; 1957 dc->caps.color.dpp.ogam_rom_caps.hlg = 0; 1958 dc->caps.color.dpp.ocsc = 0; 1959 1960 dc->caps.color.mpc.gamut_remap = 1; 1961 dc->caps.color.mpc.num_3dluts = pool->base.res_cap->num_mpc_3dlut; //2 1962 dc->caps.color.mpc.ogam_ram = 1; 1963 dc->caps.color.mpc.ogam_rom_caps.srgb = 0; 1964 dc->caps.color.mpc.ogam_rom_caps.bt2020 = 0; 1965 dc->caps.color.mpc.ogam_rom_caps.gamma2_2 = 0; 1966 dc->caps.color.mpc.ogam_rom_caps.pq = 0; 1967 dc->caps.color.mpc.ogam_rom_caps.hlg = 0; 1968 dc->caps.color.mpc.ocsc = 1; 1969 1970 /* Use pipe context based otg sync logic */ 1971 dc->config.use_pipe_ctx_sync_logic = true; 1972 1973 /* read VBIOS LTTPR caps */ 1974 { 1975 if (ctx->dc_bios->funcs->get_lttpr_caps) { 1976 enum bp_result bp_query_result; 1977 uint8_t is_vbios_lttpr_enable = 0; 1978 1979 bp_query_result = ctx->dc_bios->funcs->get_lttpr_caps(ctx->dc_bios, &is_vbios_lttpr_enable); 1980 dc->caps.vbios_lttpr_enable = (bp_query_result == BP_RESULT_OK) && !!is_vbios_lttpr_enable; 1981 } 1982 1983 /* interop bit is implicit */ 1984 { 1985 dc->caps.vbios_lttpr_aware = true; 1986 } 1987 } 1988 1989 if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV) 1990 dc->debug = debug_defaults_drv; 1991 else if (dc->ctx->dce_environment == DCE_ENV_FPGA_MAXIMUS) { 1992 dc->debug = debug_defaults_diags; 1993 } else 1994 dc->debug = debug_defaults_diags; 1995 // Init the vm_helper 1996 if (dc->vm_helper) 1997 vm_helper_init(dc->vm_helper, 16); 1998 1999 /************************************************* 2000 * Create resources * 2001 *************************************************/ 2002 2003 /* Clock Sources for Pixel Clock*/ 2004 pool->base.clock_sources[DCN31_CLK_SRC_PLL0] = 2005 dcn30_clock_source_create(ctx, ctx->dc_bios, 2006 CLOCK_SOURCE_COMBO_PHY_PLL0, 2007 &clk_src_regs[0], false); 2008 pool->base.clock_sources[DCN31_CLK_SRC_PLL1] = 2009 dcn30_clock_source_create(ctx, ctx->dc_bios, 2010 CLOCK_SOURCE_COMBO_PHY_PLL1, 2011 &clk_src_regs[1], false); 2012 /*move phypllx_pixclk_resync to dmub next*/ 2013 if (dc->ctx->asic_id.hw_internal_rev == YELLOW_CARP_B0) { 2014 pool->base.clock_sources[DCN31_CLK_SRC_PLL2] = 2015 dcn30_clock_source_create(ctx, ctx->dc_bios, 2016 CLOCK_SOURCE_COMBO_PHY_PLL2, 2017 &clk_src_regs_b0[2], false); 2018 pool->base.clock_sources[DCN31_CLK_SRC_PLL3] = 2019 dcn30_clock_source_create(ctx, ctx->dc_bios, 2020 CLOCK_SOURCE_COMBO_PHY_PLL3, 2021 &clk_src_regs_b0[3], false); 2022 } else { 2023 pool->base.clock_sources[DCN31_CLK_SRC_PLL2] = 2024 dcn30_clock_source_create(ctx, ctx->dc_bios, 2025 CLOCK_SOURCE_COMBO_PHY_PLL2, 2026 &clk_src_regs[2], false); 2027 pool->base.clock_sources[DCN31_CLK_SRC_PLL3] = 2028 dcn30_clock_source_create(ctx, ctx->dc_bios, 2029 CLOCK_SOURCE_COMBO_PHY_PLL3, 2030 &clk_src_regs[3], false); 2031 } 2032 2033 pool->base.clock_sources[DCN31_CLK_SRC_PLL4] = 2034 dcn30_clock_source_create(ctx, ctx->dc_bios, 2035 CLOCK_SOURCE_COMBO_PHY_PLL4, 2036 &clk_src_regs[4], false); 2037 2038 pool->base.clk_src_count = DCN30_CLK_SRC_TOTAL; 2039 2040 /* todo: not reuse phy_pll registers */ 2041 pool->base.dp_clock_source = 2042 dcn31_clock_source_create(ctx, ctx->dc_bios, 2043 CLOCK_SOURCE_ID_DP_DTO, 2044 &clk_src_regs[0], true); 2045 2046 for (i = 0; i < pool->base.clk_src_count; i++) { 2047 if (pool->base.clock_sources[i] == NULL) { 2048 dm_error("DC: failed to create clock sources!\n"); 2049 BREAK_TO_DEBUGGER(); 2050 goto create_fail; 2051 } 2052 } 2053 2054 /* TODO: DCCG */ 2055 pool->base.dccg = dccg31_create(ctx, &dccg_regs, &dccg_shift, &dccg_mask); 2056 if (pool->base.dccg == NULL) { 2057 dm_error("DC: failed to create dccg!\n"); 2058 BREAK_TO_DEBUGGER(); 2059 goto create_fail; 2060 } 2061 2062 /* TODO: IRQ */ 2063 init_data.ctx = dc->ctx; 2064 pool->base.irqs = dal_irq_service_dcn31_create(&init_data); 2065 if (!pool->base.irqs) 2066 goto create_fail; 2067 2068 /* HUBBUB */ 2069 pool->base.hubbub = dcn31_hubbub_create(ctx); 2070 if (pool->base.hubbub == NULL) { 2071 BREAK_TO_DEBUGGER(); 2072 dm_error("DC: failed to create hubbub!\n"); 2073 goto create_fail; 2074 } 2075 2076 /* HUBPs, DPPs, OPPs and TGs */ 2077 for (i = 0; i < pool->base.pipe_count; i++) { 2078 pool->base.hubps[i] = dcn31_hubp_create(ctx, i); 2079 if (pool->base.hubps[i] == NULL) { 2080 BREAK_TO_DEBUGGER(); 2081 dm_error( 2082 "DC: failed to create hubps!\n"); 2083 goto create_fail; 2084 } 2085 2086 pool->base.dpps[i] = dcn31_dpp_create(ctx, i); 2087 if (pool->base.dpps[i] == NULL) { 2088 BREAK_TO_DEBUGGER(); 2089 dm_error( 2090 "DC: failed to create dpps!\n"); 2091 goto create_fail; 2092 } 2093 } 2094 2095 for (i = 0; i < pool->base.res_cap->num_opp; i++) { 2096 pool->base.opps[i] = dcn31_opp_create(ctx, i); 2097 if (pool->base.opps[i] == NULL) { 2098 BREAK_TO_DEBUGGER(); 2099 dm_error( 2100 "DC: failed to create output pixel processor!\n"); 2101 goto create_fail; 2102 } 2103 } 2104 2105 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { 2106 pool->base.timing_generators[i] = dcn31_timing_generator_create( 2107 ctx, i); 2108 if (pool->base.timing_generators[i] == NULL) { 2109 BREAK_TO_DEBUGGER(); 2110 dm_error("DC: failed to create tg!\n"); 2111 goto create_fail; 2112 } 2113 } 2114 pool->base.timing_generator_count = i; 2115 2116 /* PSR */ 2117 pool->base.psr = dmub_psr_create(ctx); 2118 if (pool->base.psr == NULL) { 2119 dm_error("DC: failed to create psr obj!\n"); 2120 BREAK_TO_DEBUGGER(); 2121 goto create_fail; 2122 } 2123 2124 /* ABM */ 2125 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { 2126 pool->base.multiple_abms[i] = dmub_abm_create(ctx, 2127 &abm_regs[i], 2128 &abm_shift, 2129 &abm_mask); 2130 if (pool->base.multiple_abms[i] == NULL) { 2131 dm_error("DC: failed to create abm for pipe %d!\n", i); 2132 BREAK_TO_DEBUGGER(); 2133 goto create_fail; 2134 } 2135 } 2136 2137 /* MPC and DSC */ 2138 pool->base.mpc = dcn31_mpc_create(ctx, pool->base.mpcc_count, pool->base.res_cap->num_mpc_3dlut); 2139 if (pool->base.mpc == NULL) { 2140 BREAK_TO_DEBUGGER(); 2141 dm_error("DC: failed to create mpc!\n"); 2142 goto create_fail; 2143 } 2144 2145 for (i = 0; i < pool->base.res_cap->num_dsc; i++) { 2146 pool->base.dscs[i] = dcn31_dsc_create(ctx, i); 2147 if (pool->base.dscs[i] == NULL) { 2148 BREAK_TO_DEBUGGER(); 2149 dm_error("DC: failed to create display stream compressor %d!\n", i); 2150 goto create_fail; 2151 } 2152 } 2153 2154 /* DWB and MMHUBBUB */ 2155 if (!dcn31_dwbc_create(ctx, &pool->base)) { 2156 BREAK_TO_DEBUGGER(); 2157 dm_error("DC: failed to create dwbc!\n"); 2158 goto create_fail; 2159 } 2160 2161 if (!dcn31_mmhubbub_create(ctx, &pool->base)) { 2162 BREAK_TO_DEBUGGER(); 2163 dm_error("DC: failed to create mcif_wb!\n"); 2164 goto create_fail; 2165 } 2166 2167 /* AUX and I2C */ 2168 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { 2169 pool->base.engines[i] = dcn31_aux_engine_create(ctx, i); 2170 if (pool->base.engines[i] == NULL) { 2171 BREAK_TO_DEBUGGER(); 2172 dm_error( 2173 "DC:failed to create aux engine!!\n"); 2174 goto create_fail; 2175 } 2176 pool->base.hw_i2cs[i] = dcn31_i2c_hw_create(ctx, i); 2177 if (pool->base.hw_i2cs[i] == NULL) { 2178 BREAK_TO_DEBUGGER(); 2179 dm_error( 2180 "DC:failed to create hw i2c!!\n"); 2181 goto create_fail; 2182 } 2183 pool->base.sw_i2cs[i] = NULL; 2184 } 2185 2186 if (dc->ctx->asic_id.chip_family == FAMILY_YELLOW_CARP && 2187 dc->ctx->asic_id.hw_internal_rev == YELLOW_CARP_B0 && 2188 !dc->debug.dpia_debug.bits.disable_dpia) { 2189 /* YELLOW CARP B0 has 4 DPIA's */ 2190 pool->base.usb4_dpia_count = 4; 2191 } 2192 2193 if (dc->ctx->asic_id.chip_family == AMDGPU_FAMILY_GC_11_0_1) 2194 pool->base.usb4_dpia_count = 4; 2195 2196 /* Audio, Stream Encoders including HPO and virtual, MPC 3D LUTs */ 2197 if (!resource_construct(num_virtual_links, dc, &pool->base, 2198 (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment) ? 2199 &res_create_funcs : &res_create_maximus_funcs))) 2200 goto create_fail; 2201 2202 /* HW Sequencer and Plane caps */ 2203 dcn31_hw_sequencer_construct(dc); 2204 2205 dc->caps.max_planes = pool->base.pipe_count; 2206 2207 for (i = 0; i < dc->caps.max_planes; ++i) 2208 dc->caps.planes[i] = plane_cap; 2209 2210 dc->cap_funcs = cap_funcs; 2211 2212 dc->dcn_ip->max_num_dpp = dcn3_1_ip.max_num_dpp; 2213 2214 return true; 2215 2216 create_fail: 2217 dcn31_resource_destruct(pool); 2218 2219 return false; 2220 } 2221 2222 struct resource_pool *dcn31_create_resource_pool( 2223 const struct dc_init_data *init_data, 2224 struct dc *dc) 2225 { 2226 struct dcn31_resource_pool *pool = 2227 kzalloc(sizeof(struct dcn31_resource_pool), GFP_KERNEL); 2228 2229 if (!pool) 2230 return NULL; 2231 2232 if (dcn31_resource_construct(init_data->num_virtual_links, dc, pool)) 2233 return &pool->base; 2234 2235 BREAK_TO_DEBUGGER(); 2236 kfree(pool); 2237 return NULL; 2238 } 2239