1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 27 #include "dm_services.h" 28 #include "dc.h" 29 30 #include "dcn31/dcn31_init.h" 31 32 #include "resource.h" 33 #include "include/irq_service_interface.h" 34 #include "dcn31_resource.h" 35 36 #include "dcn20/dcn20_resource.h" 37 #include "dcn30/dcn30_resource.h" 38 39 #include "dcn10/dcn10_ipp.h" 40 #include "dcn30/dcn30_hubbub.h" 41 #include "dcn31/dcn31_hubbub.h" 42 #include "dcn30/dcn30_mpc.h" 43 #include "dcn31/dcn31_hubp.h" 44 #include "irq/dcn31/irq_service_dcn31.h" 45 #include "dcn30/dcn30_dpp.h" 46 #include "dcn31/dcn31_optc.h" 47 #include "dcn20/dcn20_hwseq.h" 48 #include "dcn30/dcn30_hwseq.h" 49 #include "dce110/dce110_hw_sequencer.h" 50 #include "dcn30/dcn30_opp.h" 51 #include "dcn20/dcn20_dsc.h" 52 #include "dcn30/dcn30_vpg.h" 53 #include "dcn30/dcn30_afmt.h" 54 #include "dcn30/dcn30_dio_stream_encoder.h" 55 #include "dcn31/dcn31_hpo_dp_stream_encoder.h" 56 #include "dcn31/dcn31_hpo_dp_link_encoder.h" 57 #include "dcn31/dcn31_apg.h" 58 #include "dcn31/dcn31_dio_link_encoder.h" 59 #include "dcn31/dcn31_vpg.h" 60 #include "dcn31/dcn31_afmt.h" 61 #include "dce/dce_clock_source.h" 62 #include "dce/dce_audio.h" 63 #include "dce/dce_hwseq.h" 64 #include "clk_mgr.h" 65 #include "virtual/virtual_stream_encoder.h" 66 #include "dce110/dce110_resource.h" 67 #include "dml/display_mode_vba.h" 68 #include "dml/dcn31/dcn31_fpu.h" 69 #include "dcn31/dcn31_dccg.h" 70 #include "dcn10/dcn10_resource.h" 71 #include "dcn31_panel_cntl.h" 72 73 #include "dcn30/dcn30_dwb.h" 74 #include "dcn30/dcn30_mmhubbub.h" 75 76 // TODO: change include headers /amd/include/asic_reg after upstream 77 #include "yellow_carp_offset.h" 78 #include "dcn/dcn_3_1_2_offset.h" 79 #include "dcn/dcn_3_1_2_sh_mask.h" 80 #include "nbio/nbio_7_2_0_offset.h" 81 #include "dpcs/dpcs_4_2_0_offset.h" 82 #include "dpcs/dpcs_4_2_0_sh_mask.h" 83 #include "mmhub/mmhub_2_3_0_offset.h" 84 #include "mmhub/mmhub_2_3_0_sh_mask.h" 85 86 87 #define regDCHUBBUB_DEBUG_CTRL_0 0x04d6 88 #define regDCHUBBUB_DEBUG_CTRL_0_BASE_IDX 2 89 #define DCHUBBUB_DEBUG_CTRL_0__DET_DEPTH__SHIFT 0x10 90 #define DCHUBBUB_DEBUG_CTRL_0__DET_DEPTH_MASK 0x01FF0000L 91 92 #include "reg_helper.h" 93 #include "dce/dmub_abm.h" 94 #include "dce/dmub_psr.h" 95 #include "dce/dce_aux.h" 96 #include "dce/dce_i2c.h" 97 98 #include "dml/dcn30/display_mode_vba_30.h" 99 #include "vm_helper.h" 100 #include "dcn20/dcn20_vmid.h" 101 102 #include "link_enc_cfg.h" 103 104 #define DC_LOGGER_INIT(logger) 105 106 enum dcn31_clk_src_array_id { 107 DCN31_CLK_SRC_PLL0, 108 DCN31_CLK_SRC_PLL1, 109 DCN31_CLK_SRC_PLL2, 110 DCN31_CLK_SRC_PLL3, 111 DCN31_CLK_SRC_PLL4, 112 DCN30_CLK_SRC_TOTAL 113 }; 114 115 /* begin ********************* 116 * macros to expend register list macro defined in HW object header file 117 */ 118 119 /* DCN */ 120 /* TODO awful hack. fixup dcn20_dwb.h */ 121 #undef BASE_INNER 122 #define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg 123 124 #define BASE(seg) BASE_INNER(seg) 125 126 #define SR(reg_name)\ 127 .reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \ 128 reg ## reg_name 129 130 #define SRI(reg_name, block, id)\ 131 .reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 132 reg ## block ## id ## _ ## reg_name 133 134 #define SRI2(reg_name, block, id)\ 135 .reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \ 136 reg ## reg_name 137 138 #define SRIR(var_name, reg_name, block, id)\ 139 .var_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 140 reg ## block ## id ## _ ## reg_name 141 142 #define SRII(reg_name, block, id)\ 143 .reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 144 reg ## block ## id ## _ ## reg_name 145 146 #define SRII_MPC_RMU(reg_name, block, id)\ 147 .RMU##_##reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 148 reg ## block ## id ## _ ## reg_name 149 150 #define SRII_DWB(reg_name, temp_name, block, id)\ 151 .reg_name[id] = BASE(reg ## block ## id ## _ ## temp_name ## _BASE_IDX) + \ 152 reg ## block ## id ## _ ## temp_name 153 154 #define DCCG_SRII(reg_name, block, id)\ 155 .block ## _ ## reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 156 reg ## block ## id ## _ ## reg_name 157 158 #define VUPDATE_SRII(reg_name, block, id)\ 159 .reg_name[id] = BASE(reg ## reg_name ## _ ## block ## id ## _BASE_IDX) + \ 160 reg ## reg_name ## _ ## block ## id 161 162 /* NBIO */ 163 #define NBIO_BASE_INNER(seg) \ 164 NBIO_BASE__INST0_SEG ## seg 165 166 #define NBIO_BASE(seg) \ 167 NBIO_BASE_INNER(seg) 168 169 #define NBIO_SR(reg_name)\ 170 .reg_name = NBIO_BASE(regBIF_BX1_ ## reg_name ## _BASE_IDX) + \ 171 regBIF_BX1_ ## reg_name 172 173 /* MMHUB */ 174 #define MMHUB_BASE_INNER(seg) \ 175 MMHUB_BASE__INST0_SEG ## seg 176 177 #define MMHUB_BASE(seg) \ 178 MMHUB_BASE_INNER(seg) 179 180 #define MMHUB_SR(reg_name)\ 181 .reg_name = MMHUB_BASE(mm ## reg_name ## _BASE_IDX) + \ 182 mm ## reg_name 183 184 /* CLOCK */ 185 #define CLK_BASE_INNER(seg) \ 186 CLK_BASE__INST0_SEG ## seg 187 188 #define CLK_BASE(seg) \ 189 CLK_BASE_INNER(seg) 190 191 #define CLK_SRI(reg_name, block, inst)\ 192 .reg_name = CLK_BASE(reg ## block ## _ ## inst ## _ ## reg_name ## _BASE_IDX) + \ 193 reg ## block ## _ ## inst ## _ ## reg_name 194 195 196 static const struct bios_registers bios_regs = { 197 NBIO_SR(BIOS_SCRATCH_3), 198 NBIO_SR(BIOS_SCRATCH_6) 199 }; 200 201 #define clk_src_regs(index, pllid)\ 202 [index] = {\ 203 CS_COMMON_REG_LIST_DCN3_0(index, pllid),\ 204 } 205 206 static const struct dce110_clk_src_regs clk_src_regs[] = { 207 clk_src_regs(0, A), 208 clk_src_regs(1, B), 209 clk_src_regs(2, C), 210 clk_src_regs(3, D), 211 clk_src_regs(4, E) 212 }; 213 /*pll_id being rempped in dmub, in driver it is logical instance*/ 214 static const struct dce110_clk_src_regs clk_src_regs_b0[] = { 215 clk_src_regs(0, A), 216 clk_src_regs(1, B), 217 clk_src_regs(2, F), 218 clk_src_regs(3, G), 219 clk_src_regs(4, E) 220 }; 221 222 static const struct dce110_clk_src_shift cs_shift = { 223 CS_COMMON_MASK_SH_LIST_DCN2_0(__SHIFT) 224 }; 225 226 static const struct dce110_clk_src_mask cs_mask = { 227 CS_COMMON_MASK_SH_LIST_DCN2_0(_MASK) 228 }; 229 230 #define abm_regs(id)\ 231 [id] = {\ 232 ABM_DCN302_REG_LIST(id)\ 233 } 234 235 static const struct dce_abm_registers abm_regs[] = { 236 abm_regs(0), 237 abm_regs(1), 238 abm_regs(2), 239 abm_regs(3), 240 }; 241 242 static const struct dce_abm_shift abm_shift = { 243 ABM_MASK_SH_LIST_DCN30(__SHIFT) 244 }; 245 246 static const struct dce_abm_mask abm_mask = { 247 ABM_MASK_SH_LIST_DCN30(_MASK) 248 }; 249 250 #define audio_regs(id)\ 251 [id] = {\ 252 AUD_COMMON_REG_LIST(id)\ 253 } 254 255 static const struct dce_audio_registers audio_regs[] = { 256 audio_regs(0), 257 audio_regs(1), 258 audio_regs(2), 259 audio_regs(3), 260 audio_regs(4), 261 audio_regs(5), 262 audio_regs(6) 263 }; 264 265 #define DCE120_AUD_COMMON_MASK_SH_LIST(mask_sh)\ 266 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX, AZALIA_ENDPOINT_REG_INDEX, mask_sh),\ 267 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA, AZALIA_ENDPOINT_REG_DATA, mask_sh),\ 268 AUD_COMMON_MASK_SH_LIST_BASE(mask_sh) 269 270 static const struct dce_audio_shift audio_shift = { 271 DCE120_AUD_COMMON_MASK_SH_LIST(__SHIFT) 272 }; 273 274 static const struct dce_audio_mask audio_mask = { 275 DCE120_AUD_COMMON_MASK_SH_LIST(_MASK) 276 }; 277 278 #define vpg_regs(id)\ 279 [id] = {\ 280 VPG_DCN31_REG_LIST(id)\ 281 } 282 283 static const struct dcn31_vpg_registers vpg_regs[] = { 284 vpg_regs(0), 285 vpg_regs(1), 286 vpg_regs(2), 287 vpg_regs(3), 288 vpg_regs(4), 289 vpg_regs(5), 290 vpg_regs(6), 291 vpg_regs(7), 292 vpg_regs(8), 293 vpg_regs(9), 294 }; 295 296 static const struct dcn31_vpg_shift vpg_shift = { 297 DCN31_VPG_MASK_SH_LIST(__SHIFT) 298 }; 299 300 static const struct dcn31_vpg_mask vpg_mask = { 301 DCN31_VPG_MASK_SH_LIST(_MASK) 302 }; 303 304 #define afmt_regs(id)\ 305 [id] = {\ 306 AFMT_DCN31_REG_LIST(id)\ 307 } 308 309 static const struct dcn31_afmt_registers afmt_regs[] = { 310 afmt_regs(0), 311 afmt_regs(1), 312 afmt_regs(2), 313 afmt_regs(3), 314 afmt_regs(4), 315 afmt_regs(5) 316 }; 317 318 static const struct dcn31_afmt_shift afmt_shift = { 319 DCN31_AFMT_MASK_SH_LIST(__SHIFT) 320 }; 321 322 static const struct dcn31_afmt_mask afmt_mask = { 323 DCN31_AFMT_MASK_SH_LIST(_MASK) 324 }; 325 326 #define apg_regs(id)\ 327 [id] = {\ 328 APG_DCN31_REG_LIST(id)\ 329 } 330 331 static const struct dcn31_apg_registers apg_regs[] = { 332 apg_regs(0), 333 apg_regs(1), 334 apg_regs(2), 335 apg_regs(3) 336 }; 337 338 static const struct dcn31_apg_shift apg_shift = { 339 DCN31_APG_MASK_SH_LIST(__SHIFT) 340 }; 341 342 static const struct dcn31_apg_mask apg_mask = { 343 DCN31_APG_MASK_SH_LIST(_MASK) 344 }; 345 346 #define stream_enc_regs(id)\ 347 [id] = {\ 348 SE_DCN3_REG_LIST(id)\ 349 } 350 351 /* Some encoders won't be initialized here - but they're logical, not physical. */ 352 static const struct dcn10_stream_enc_registers stream_enc_regs[ENGINE_ID_COUNT] = { 353 stream_enc_regs(0), 354 stream_enc_regs(1), 355 stream_enc_regs(2), 356 stream_enc_regs(3), 357 stream_enc_regs(4) 358 }; 359 360 static const struct dcn10_stream_encoder_shift se_shift = { 361 SE_COMMON_MASK_SH_LIST_DCN30(__SHIFT) 362 }; 363 364 static const struct dcn10_stream_encoder_mask se_mask = { 365 SE_COMMON_MASK_SH_LIST_DCN30(_MASK) 366 }; 367 368 369 #define aux_regs(id)\ 370 [id] = {\ 371 DCN2_AUX_REG_LIST(id)\ 372 } 373 374 static const struct dcn10_link_enc_aux_registers link_enc_aux_regs[] = { 375 aux_regs(0), 376 aux_regs(1), 377 aux_regs(2), 378 aux_regs(3), 379 aux_regs(4) 380 }; 381 382 #define hpd_regs(id)\ 383 [id] = {\ 384 HPD_REG_LIST(id)\ 385 } 386 387 static const struct dcn10_link_enc_hpd_registers link_enc_hpd_regs[] = { 388 hpd_regs(0), 389 hpd_regs(1), 390 hpd_regs(2), 391 hpd_regs(3), 392 hpd_regs(4) 393 }; 394 395 #define link_regs(id, phyid)\ 396 [id] = {\ 397 LE_DCN31_REG_LIST(id), \ 398 UNIPHY_DCN2_REG_LIST(phyid), \ 399 DPCS_DCN31_REG_LIST(id), \ 400 } 401 402 static const struct dce110_aux_registers_shift aux_shift = { 403 DCN_AUX_MASK_SH_LIST(__SHIFT) 404 }; 405 406 static const struct dce110_aux_registers_mask aux_mask = { 407 DCN_AUX_MASK_SH_LIST(_MASK) 408 }; 409 410 static const struct dcn10_link_enc_registers link_enc_regs[] = { 411 link_regs(0, A), 412 link_regs(1, B), 413 link_regs(2, C), 414 link_regs(3, D), 415 link_regs(4, E) 416 }; 417 418 static const struct dcn10_link_enc_shift le_shift = { 419 LINK_ENCODER_MASK_SH_LIST_DCN31(__SHIFT), \ 420 DPCS_DCN31_MASK_SH_LIST(__SHIFT) 421 }; 422 423 static const struct dcn10_link_enc_mask le_mask = { 424 LINK_ENCODER_MASK_SH_LIST_DCN31(_MASK), \ 425 DPCS_DCN31_MASK_SH_LIST(_MASK) 426 }; 427 428 #define hpo_dp_stream_encoder_reg_list(id)\ 429 [id] = {\ 430 DCN3_1_HPO_DP_STREAM_ENC_REG_LIST(id)\ 431 } 432 433 static const struct dcn31_hpo_dp_stream_encoder_registers hpo_dp_stream_enc_regs[] = { 434 hpo_dp_stream_encoder_reg_list(0), 435 hpo_dp_stream_encoder_reg_list(1), 436 hpo_dp_stream_encoder_reg_list(2), 437 hpo_dp_stream_encoder_reg_list(3), 438 }; 439 440 static const struct dcn31_hpo_dp_stream_encoder_shift hpo_dp_se_shift = { 441 DCN3_1_HPO_DP_STREAM_ENC_MASK_SH_LIST(__SHIFT) 442 }; 443 444 static const struct dcn31_hpo_dp_stream_encoder_mask hpo_dp_se_mask = { 445 DCN3_1_HPO_DP_STREAM_ENC_MASK_SH_LIST(_MASK) 446 }; 447 448 #define hpo_dp_link_encoder_reg_list(id)\ 449 [id] = {\ 450 DCN3_1_HPO_DP_LINK_ENC_REG_LIST(id),\ 451 DCN3_1_RDPCSTX_REG_LIST(0),\ 452 DCN3_1_RDPCSTX_REG_LIST(1),\ 453 DCN3_1_RDPCSTX_REG_LIST(2),\ 454 DCN3_1_RDPCSTX_REG_LIST(3),\ 455 DCN3_1_RDPCSTX_REG_LIST(4)\ 456 } 457 458 static const struct dcn31_hpo_dp_link_encoder_registers hpo_dp_link_enc_regs[] = { 459 hpo_dp_link_encoder_reg_list(0), 460 hpo_dp_link_encoder_reg_list(1), 461 }; 462 463 static const struct dcn31_hpo_dp_link_encoder_shift hpo_dp_le_shift = { 464 DCN3_1_HPO_DP_LINK_ENC_MASK_SH_LIST(__SHIFT) 465 }; 466 467 static const struct dcn31_hpo_dp_link_encoder_mask hpo_dp_le_mask = { 468 DCN3_1_HPO_DP_LINK_ENC_MASK_SH_LIST(_MASK) 469 }; 470 471 #define dpp_regs(id)\ 472 [id] = {\ 473 DPP_REG_LIST_DCN30(id),\ 474 } 475 476 static const struct dcn3_dpp_registers dpp_regs[] = { 477 dpp_regs(0), 478 dpp_regs(1), 479 dpp_regs(2), 480 dpp_regs(3) 481 }; 482 483 static const struct dcn3_dpp_shift tf_shift = { 484 DPP_REG_LIST_SH_MASK_DCN30(__SHIFT) 485 }; 486 487 static const struct dcn3_dpp_mask tf_mask = { 488 DPP_REG_LIST_SH_MASK_DCN30(_MASK) 489 }; 490 491 #define opp_regs(id)\ 492 [id] = {\ 493 OPP_REG_LIST_DCN30(id),\ 494 } 495 496 static const struct dcn20_opp_registers opp_regs[] = { 497 opp_regs(0), 498 opp_regs(1), 499 opp_regs(2), 500 opp_regs(3) 501 }; 502 503 static const struct dcn20_opp_shift opp_shift = { 504 OPP_MASK_SH_LIST_DCN20(__SHIFT) 505 }; 506 507 static const struct dcn20_opp_mask opp_mask = { 508 OPP_MASK_SH_LIST_DCN20(_MASK) 509 }; 510 511 #define aux_engine_regs(id)\ 512 [id] = {\ 513 AUX_COMMON_REG_LIST0(id), \ 514 .AUXN_IMPCAL = 0, \ 515 .AUXP_IMPCAL = 0, \ 516 .AUX_RESET_MASK = DP_AUX0_AUX_CONTROL__AUX_RESET_MASK, \ 517 } 518 519 static const struct dce110_aux_registers aux_engine_regs[] = { 520 aux_engine_regs(0), 521 aux_engine_regs(1), 522 aux_engine_regs(2), 523 aux_engine_regs(3), 524 aux_engine_regs(4) 525 }; 526 527 #define dwbc_regs_dcn3(id)\ 528 [id] = {\ 529 DWBC_COMMON_REG_LIST_DCN30(id),\ 530 } 531 532 static const struct dcn30_dwbc_registers dwbc30_regs[] = { 533 dwbc_regs_dcn3(0), 534 }; 535 536 static const struct dcn30_dwbc_shift dwbc30_shift = { 537 DWBC_COMMON_MASK_SH_LIST_DCN30(__SHIFT) 538 }; 539 540 static const struct dcn30_dwbc_mask dwbc30_mask = { 541 DWBC_COMMON_MASK_SH_LIST_DCN30(_MASK) 542 }; 543 544 #define mcif_wb_regs_dcn3(id)\ 545 [id] = {\ 546 MCIF_WB_COMMON_REG_LIST_DCN30(id),\ 547 } 548 549 static const struct dcn30_mmhubbub_registers mcif_wb30_regs[] = { 550 mcif_wb_regs_dcn3(0) 551 }; 552 553 static const struct dcn30_mmhubbub_shift mcif_wb30_shift = { 554 MCIF_WB_COMMON_MASK_SH_LIST_DCN30(__SHIFT) 555 }; 556 557 static const struct dcn30_mmhubbub_mask mcif_wb30_mask = { 558 MCIF_WB_COMMON_MASK_SH_LIST_DCN30(_MASK) 559 }; 560 561 #define dsc_regsDCN20(id)\ 562 [id] = {\ 563 DSC_REG_LIST_DCN20(id)\ 564 } 565 566 static const struct dcn20_dsc_registers dsc_regs[] = { 567 dsc_regsDCN20(0), 568 dsc_regsDCN20(1), 569 dsc_regsDCN20(2) 570 }; 571 572 static const struct dcn20_dsc_shift dsc_shift = { 573 DSC_REG_LIST_SH_MASK_DCN20(__SHIFT) 574 }; 575 576 static const struct dcn20_dsc_mask dsc_mask = { 577 DSC_REG_LIST_SH_MASK_DCN20(_MASK) 578 }; 579 580 static const struct dcn30_mpc_registers mpc_regs = { 581 MPC_REG_LIST_DCN3_0(0), 582 MPC_REG_LIST_DCN3_0(1), 583 MPC_REG_LIST_DCN3_0(2), 584 MPC_REG_LIST_DCN3_0(3), 585 MPC_OUT_MUX_REG_LIST_DCN3_0(0), 586 MPC_OUT_MUX_REG_LIST_DCN3_0(1), 587 MPC_OUT_MUX_REG_LIST_DCN3_0(2), 588 MPC_OUT_MUX_REG_LIST_DCN3_0(3), 589 MPC_RMU_GLOBAL_REG_LIST_DCN3AG, 590 MPC_RMU_REG_LIST_DCN3AG(0), 591 MPC_RMU_REG_LIST_DCN3AG(1), 592 //MPC_RMU_REG_LIST_DCN3AG(2), 593 MPC_DWB_MUX_REG_LIST_DCN3_0(0), 594 }; 595 596 static const struct dcn30_mpc_shift mpc_shift = { 597 MPC_COMMON_MASK_SH_LIST_DCN30(__SHIFT) 598 }; 599 600 static const struct dcn30_mpc_mask mpc_mask = { 601 MPC_COMMON_MASK_SH_LIST_DCN30(_MASK) 602 }; 603 604 #define optc_regs(id)\ 605 [id] = {OPTC_COMMON_REG_LIST_DCN3_1(id)} 606 607 static const struct dcn_optc_registers optc_regs[] = { 608 optc_regs(0), 609 optc_regs(1), 610 optc_regs(2), 611 optc_regs(3) 612 }; 613 614 static const struct dcn_optc_shift optc_shift = { 615 OPTC_COMMON_MASK_SH_LIST_DCN3_1(__SHIFT) 616 }; 617 618 static const struct dcn_optc_mask optc_mask = { 619 OPTC_COMMON_MASK_SH_LIST_DCN3_1(_MASK) 620 }; 621 622 #define hubp_regs(id)\ 623 [id] = {\ 624 HUBP_REG_LIST_DCN30(id)\ 625 } 626 627 static const struct dcn_hubp2_registers hubp_regs[] = { 628 hubp_regs(0), 629 hubp_regs(1), 630 hubp_regs(2), 631 hubp_regs(3) 632 }; 633 634 635 static const struct dcn_hubp2_shift hubp_shift = { 636 HUBP_MASK_SH_LIST_DCN31(__SHIFT) 637 }; 638 639 static const struct dcn_hubp2_mask hubp_mask = { 640 HUBP_MASK_SH_LIST_DCN31(_MASK) 641 }; 642 static const struct dcn_hubbub_registers hubbub_reg = { 643 HUBBUB_REG_LIST_DCN31(0) 644 }; 645 646 static const struct dcn_hubbub_shift hubbub_shift = { 647 HUBBUB_MASK_SH_LIST_DCN31(__SHIFT) 648 }; 649 650 static const struct dcn_hubbub_mask hubbub_mask = { 651 HUBBUB_MASK_SH_LIST_DCN31(_MASK) 652 }; 653 654 static const struct dccg_registers dccg_regs = { 655 DCCG_REG_LIST_DCN31() 656 }; 657 658 static const struct dccg_shift dccg_shift = { 659 DCCG_MASK_SH_LIST_DCN31(__SHIFT) 660 }; 661 662 static const struct dccg_mask dccg_mask = { 663 DCCG_MASK_SH_LIST_DCN31(_MASK) 664 }; 665 666 667 #define SRII2(reg_name_pre, reg_name_post, id)\ 668 .reg_name_pre ## _ ## reg_name_post[id] = BASE(reg ## reg_name_pre \ 669 ## id ## _ ## reg_name_post ## _BASE_IDX) + \ 670 reg ## reg_name_pre ## id ## _ ## reg_name_post 671 672 673 #define HWSEQ_DCN31_REG_LIST()\ 674 SR(DCHUBBUB_GLOBAL_TIMER_CNTL), \ 675 SR(DCHUBBUB_ARB_HOSTVM_CNTL), \ 676 SR(DIO_MEM_PWR_CTRL), \ 677 SR(ODM_MEM_PWR_CTRL3), \ 678 SR(DMU_MEM_PWR_CNTL), \ 679 SR(MMHUBBUB_MEM_PWR_CNTL), \ 680 SR(DCCG_GATE_DISABLE_CNTL), \ 681 SR(DCCG_GATE_DISABLE_CNTL2), \ 682 SR(DCFCLK_CNTL),\ 683 SR(DC_MEM_GLOBAL_PWR_REQ_CNTL), \ 684 SRII(PIXEL_RATE_CNTL, OTG, 0), \ 685 SRII(PIXEL_RATE_CNTL, OTG, 1),\ 686 SRII(PIXEL_RATE_CNTL, OTG, 2),\ 687 SRII(PIXEL_RATE_CNTL, OTG, 3),\ 688 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 0),\ 689 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 1),\ 690 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 2),\ 691 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 3),\ 692 SR(MICROSECOND_TIME_BASE_DIV), \ 693 SR(MILLISECOND_TIME_BASE_DIV), \ 694 SR(DISPCLK_FREQ_CHANGE_CNTL), \ 695 SR(RBBMIF_TIMEOUT_DIS), \ 696 SR(RBBMIF_TIMEOUT_DIS_2), \ 697 SR(DCHUBBUB_CRC_CTRL), \ 698 SR(DPP_TOP0_DPP_CRC_CTRL), \ 699 SR(DPP_TOP0_DPP_CRC_VAL_B_A), \ 700 SR(DPP_TOP0_DPP_CRC_VAL_R_G), \ 701 SR(MPC_CRC_CTRL), \ 702 SR(MPC_CRC_RESULT_GB), \ 703 SR(MPC_CRC_RESULT_C), \ 704 SR(MPC_CRC_RESULT_AR), \ 705 SR(DOMAIN0_PG_CONFIG), \ 706 SR(DOMAIN1_PG_CONFIG), \ 707 SR(DOMAIN2_PG_CONFIG), \ 708 SR(DOMAIN3_PG_CONFIG), \ 709 SR(DOMAIN16_PG_CONFIG), \ 710 SR(DOMAIN17_PG_CONFIG), \ 711 SR(DOMAIN18_PG_CONFIG), \ 712 SR(DOMAIN0_PG_STATUS), \ 713 SR(DOMAIN1_PG_STATUS), \ 714 SR(DOMAIN2_PG_STATUS), \ 715 SR(DOMAIN3_PG_STATUS), \ 716 SR(DOMAIN16_PG_STATUS), \ 717 SR(DOMAIN17_PG_STATUS), \ 718 SR(DOMAIN18_PG_STATUS), \ 719 SR(D1VGA_CONTROL), \ 720 SR(D2VGA_CONTROL), \ 721 SR(D3VGA_CONTROL), \ 722 SR(D4VGA_CONTROL), \ 723 SR(D5VGA_CONTROL), \ 724 SR(D6VGA_CONTROL), \ 725 SR(DC_IP_REQUEST_CNTL), \ 726 SR(AZALIA_AUDIO_DTO), \ 727 SR(AZALIA_CONTROLLER_CLOCK_GATING), \ 728 SR(HPO_TOP_HW_CONTROL) 729 730 static const struct dce_hwseq_registers hwseq_reg = { 731 HWSEQ_DCN31_REG_LIST() 732 }; 733 734 #define HWSEQ_DCN31_MASK_SH_LIST(mask_sh)\ 735 HWSEQ_DCN_MASK_SH_LIST(mask_sh), \ 736 HWS_SF(, DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_REFDIV, mask_sh), \ 737 HWS_SF(, DCHUBBUB_ARB_HOSTVM_CNTL, DISABLE_HOSTVM_FORCE_ALLOW_PSTATE, mask_sh), \ 738 HWS_SF(, DOMAIN0_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ 739 HWS_SF(, DOMAIN0_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ 740 HWS_SF(, DOMAIN1_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ 741 HWS_SF(, DOMAIN1_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ 742 HWS_SF(, DOMAIN2_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ 743 HWS_SF(, DOMAIN2_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ 744 HWS_SF(, DOMAIN3_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ 745 HWS_SF(, DOMAIN3_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ 746 HWS_SF(, DOMAIN16_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ 747 HWS_SF(, DOMAIN16_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ 748 HWS_SF(, DOMAIN17_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ 749 HWS_SF(, DOMAIN17_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ 750 HWS_SF(, DOMAIN18_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ 751 HWS_SF(, DOMAIN18_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ 752 HWS_SF(, DOMAIN0_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ 753 HWS_SF(, DOMAIN1_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ 754 HWS_SF(, DOMAIN2_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ 755 HWS_SF(, DOMAIN3_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ 756 HWS_SF(, DOMAIN16_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ 757 HWS_SF(, DOMAIN17_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ 758 HWS_SF(, DOMAIN18_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ 759 HWS_SF(, DC_IP_REQUEST_CNTL, IP_REQUEST_EN, mask_sh), \ 760 HWS_SF(, AZALIA_AUDIO_DTO, AZALIA_AUDIO_DTO_MODULE, mask_sh), \ 761 HWS_SF(, HPO_TOP_CLOCK_CONTROL, HPO_HDMISTREAMCLK_G_GATE_DIS, mask_sh), \ 762 HWS_SF(, DMU_MEM_PWR_CNTL, DMCU_ERAM_MEM_PWR_FORCE, mask_sh), \ 763 HWS_SF(, ODM_MEM_PWR_CTRL3, ODM_MEM_UNASSIGNED_PWR_MODE, mask_sh), \ 764 HWS_SF(, ODM_MEM_PWR_CTRL3, ODM_MEM_VBLANK_PWR_MODE, mask_sh), \ 765 HWS_SF(, MMHUBBUB_MEM_PWR_CNTL, VGA_MEM_PWR_FORCE, mask_sh), \ 766 HWS_SF(, DIO_MEM_PWR_CTRL, I2C_LIGHT_SLEEP_FORCE, mask_sh), \ 767 HWS_SF(, HPO_TOP_HW_CONTROL, HPO_IO_EN, mask_sh) 768 769 static const struct dce_hwseq_shift hwseq_shift = { 770 HWSEQ_DCN31_MASK_SH_LIST(__SHIFT) 771 }; 772 773 static const struct dce_hwseq_mask hwseq_mask = { 774 HWSEQ_DCN31_MASK_SH_LIST(_MASK) 775 }; 776 #define vmid_regs(id)\ 777 [id] = {\ 778 DCN20_VMID_REG_LIST(id)\ 779 } 780 781 static const struct dcn_vmid_registers vmid_regs[] = { 782 vmid_regs(0), 783 vmid_regs(1), 784 vmid_regs(2), 785 vmid_regs(3), 786 vmid_regs(4), 787 vmid_regs(5), 788 vmid_regs(6), 789 vmid_regs(7), 790 vmid_regs(8), 791 vmid_regs(9), 792 vmid_regs(10), 793 vmid_regs(11), 794 vmid_regs(12), 795 vmid_regs(13), 796 vmid_regs(14), 797 vmid_regs(15) 798 }; 799 800 static const struct dcn20_vmid_shift vmid_shifts = { 801 DCN20_VMID_MASK_SH_LIST(__SHIFT) 802 }; 803 804 static const struct dcn20_vmid_mask vmid_masks = { 805 DCN20_VMID_MASK_SH_LIST(_MASK) 806 }; 807 808 static const struct resource_caps res_cap_dcn31 = { 809 .num_timing_generator = 4, 810 .num_opp = 4, 811 .num_video_plane = 4, 812 .num_audio = 5, 813 .num_stream_encoder = 5, 814 .num_dig_link_enc = 5, 815 .num_hpo_dp_stream_encoder = 4, 816 .num_hpo_dp_link_encoder = 2, 817 .num_pll = 5, 818 .num_dwb = 1, 819 .num_ddc = 5, 820 .num_vmid = 16, 821 .num_mpc_3dlut = 2, 822 .num_dsc = 3, 823 }; 824 825 static const struct dc_plane_cap plane_cap = { 826 .type = DC_PLANE_TYPE_DCN_UNIVERSAL, 827 .blends_with_above = true, 828 .blends_with_below = true, 829 .per_pixel_alpha = true, 830 831 .pixel_format_support = { 832 .argb8888 = true, 833 .nv12 = true, 834 .fp16 = true, 835 .p010 = true, 836 .ayuv = false, 837 }, 838 839 .max_upscale_factor = { 840 .argb8888 = 16000, 841 .nv12 = 16000, 842 .fp16 = 16000 843 }, 844 845 // 6:1 downscaling ratio: 1000/6 = 166.666 846 .max_downscale_factor = { 847 .argb8888 = 167, 848 .nv12 = 167, 849 .fp16 = 167 850 }, 851 64, 852 64 853 }; 854 855 static const struct dc_debug_options debug_defaults_drv = { 856 .disable_dmcu = true, 857 .force_abm_enable = false, 858 .timing_trace = false, 859 .clock_trace = true, 860 .disable_pplib_clock_request = false, 861 .pipe_split_policy = MPC_SPLIT_DYNAMIC, 862 .force_single_disp_pipe_split = false, 863 .disable_dcc = DCC_ENABLE, 864 .vsr_support = true, 865 .performance_trace = false, 866 .max_downscale_src_width = 4096,/*upto true 4K*/ 867 .disable_pplib_wm_range = false, 868 .scl_reset_length10 = true, 869 .sanity_checks = true, 870 .underflow_assert_delay_us = 0xFFFFFFFF, 871 .dwb_fi_phase = -1, // -1 = disable, 872 .dmub_command_table = true, 873 .pstate_enabled = true, 874 .use_max_lb = true, 875 .enable_mem_low_power = { 876 .bits = { 877 .vga = true, 878 .i2c = true, 879 .dmcu = false, // This is previously known to cause hang on S3 cycles if enabled 880 .dscl = true, 881 .cm = true, 882 .mpc = true, 883 .optc = true, 884 .vpg = true, 885 .afmt = true, 886 } 887 }, 888 .disable_z10 = true, 889 .optimize_edp_link_rate = true, 890 .enable_sw_cntl_psr = true, 891 .apply_vendor_specific_lttpr_wa = true, 892 .enable_z9_disable_interface = true, /* Allow support for the PMFW interface for disable Z9*/ 893 .dml_hostvm_override = DML_HOSTVM_OVERRIDE_FALSE, 894 }; 895 896 static const struct dc_debug_options debug_defaults_diags = { 897 .disable_dmcu = true, 898 .force_abm_enable = false, 899 .timing_trace = true, 900 .clock_trace = true, 901 .disable_dpp_power_gate = true, 902 .disable_hubp_power_gate = true, 903 .disable_clock_gate = true, 904 .disable_pplib_clock_request = true, 905 .disable_pplib_wm_range = true, 906 .disable_stutter = false, 907 .scl_reset_length10 = true, 908 .dwb_fi_phase = -1, // -1 = disable 909 .dmub_command_table = true, 910 .enable_tri_buf = true, 911 .use_max_lb = true 912 }; 913 914 static void dcn31_dpp_destroy(struct dpp **dpp) 915 { 916 kfree(TO_DCN20_DPP(*dpp)); 917 *dpp = NULL; 918 } 919 920 static struct dpp *dcn31_dpp_create( 921 struct dc_context *ctx, 922 uint32_t inst) 923 { 924 struct dcn3_dpp *dpp = 925 kzalloc(sizeof(struct dcn3_dpp), GFP_KERNEL); 926 927 if (!dpp) 928 return NULL; 929 930 if (dpp3_construct(dpp, ctx, inst, 931 &dpp_regs[inst], &tf_shift, &tf_mask)) 932 return &dpp->base; 933 934 BREAK_TO_DEBUGGER(); 935 kfree(dpp); 936 return NULL; 937 } 938 939 static struct output_pixel_processor *dcn31_opp_create( 940 struct dc_context *ctx, uint32_t inst) 941 { 942 struct dcn20_opp *opp = 943 kzalloc(sizeof(struct dcn20_opp), GFP_KERNEL); 944 945 if (!opp) { 946 BREAK_TO_DEBUGGER(); 947 return NULL; 948 } 949 950 dcn20_opp_construct(opp, ctx, inst, 951 &opp_regs[inst], &opp_shift, &opp_mask); 952 return &opp->base; 953 } 954 955 static struct dce_aux *dcn31_aux_engine_create( 956 struct dc_context *ctx, 957 uint32_t inst) 958 { 959 struct aux_engine_dce110 *aux_engine = 960 kzalloc(sizeof(struct aux_engine_dce110), GFP_KERNEL); 961 962 if (!aux_engine) 963 return NULL; 964 965 dce110_aux_engine_construct(aux_engine, ctx, inst, 966 SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD, 967 &aux_engine_regs[inst], 968 &aux_mask, 969 &aux_shift, 970 ctx->dc->caps.extended_aux_timeout_support); 971 972 return &aux_engine->base; 973 } 974 #define i2c_inst_regs(id) { I2C_HW_ENGINE_COMMON_REG_LIST_DCN30(id) } 975 976 static const struct dce_i2c_registers i2c_hw_regs[] = { 977 i2c_inst_regs(1), 978 i2c_inst_regs(2), 979 i2c_inst_regs(3), 980 i2c_inst_regs(4), 981 i2c_inst_regs(5), 982 }; 983 984 static const struct dce_i2c_shift i2c_shifts = { 985 I2C_COMMON_MASK_SH_LIST_DCN30(__SHIFT) 986 }; 987 988 static const struct dce_i2c_mask i2c_masks = { 989 I2C_COMMON_MASK_SH_LIST_DCN30(_MASK) 990 }; 991 992 static struct dce_i2c_hw *dcn31_i2c_hw_create( 993 struct dc_context *ctx, 994 uint32_t inst) 995 { 996 struct dce_i2c_hw *dce_i2c_hw = 997 kzalloc(sizeof(struct dce_i2c_hw), GFP_KERNEL); 998 999 if (!dce_i2c_hw) 1000 return NULL; 1001 1002 dcn2_i2c_hw_construct(dce_i2c_hw, ctx, inst, 1003 &i2c_hw_regs[inst], &i2c_shifts, &i2c_masks); 1004 1005 return dce_i2c_hw; 1006 } 1007 static struct mpc *dcn31_mpc_create( 1008 struct dc_context *ctx, 1009 int num_mpcc, 1010 int num_rmu) 1011 { 1012 struct dcn30_mpc *mpc30 = kzalloc(sizeof(struct dcn30_mpc), 1013 GFP_KERNEL); 1014 1015 if (!mpc30) 1016 return NULL; 1017 1018 dcn30_mpc_construct(mpc30, ctx, 1019 &mpc_regs, 1020 &mpc_shift, 1021 &mpc_mask, 1022 num_mpcc, 1023 num_rmu); 1024 1025 return &mpc30->base; 1026 } 1027 1028 static struct hubbub *dcn31_hubbub_create(struct dc_context *ctx) 1029 { 1030 int i; 1031 1032 struct dcn20_hubbub *hubbub3 = kzalloc(sizeof(struct dcn20_hubbub), 1033 GFP_KERNEL); 1034 1035 if (!hubbub3) 1036 return NULL; 1037 1038 hubbub31_construct(hubbub3, ctx, 1039 &hubbub_reg, 1040 &hubbub_shift, 1041 &hubbub_mask, 1042 dcn3_1_ip.det_buffer_size_kbytes, 1043 dcn3_1_ip.pixel_chunk_size_kbytes, 1044 dcn3_1_ip.config_return_buffer_size_in_kbytes); 1045 1046 1047 for (i = 0; i < res_cap_dcn31.num_vmid; i++) { 1048 struct dcn20_vmid *vmid = &hubbub3->vmid[i]; 1049 1050 vmid->ctx = ctx; 1051 1052 vmid->regs = &vmid_regs[i]; 1053 vmid->shifts = &vmid_shifts; 1054 vmid->masks = &vmid_masks; 1055 } 1056 1057 return &hubbub3->base; 1058 } 1059 1060 static struct timing_generator *dcn31_timing_generator_create( 1061 struct dc_context *ctx, 1062 uint32_t instance) 1063 { 1064 struct optc *tgn10 = 1065 kzalloc(sizeof(struct optc), GFP_KERNEL); 1066 1067 if (!tgn10) 1068 return NULL; 1069 1070 tgn10->base.inst = instance; 1071 tgn10->base.ctx = ctx; 1072 1073 tgn10->tg_regs = &optc_regs[instance]; 1074 tgn10->tg_shift = &optc_shift; 1075 tgn10->tg_mask = &optc_mask; 1076 1077 dcn31_timing_generator_init(tgn10); 1078 1079 return &tgn10->base; 1080 } 1081 1082 static const struct encoder_feature_support link_enc_feature = { 1083 .max_hdmi_deep_color = COLOR_DEPTH_121212, 1084 .max_hdmi_pixel_clock = 600000, 1085 .hdmi_ycbcr420_supported = true, 1086 .dp_ycbcr420_supported = true, 1087 .fec_supported = true, 1088 .flags.bits.IS_HBR2_CAPABLE = true, 1089 .flags.bits.IS_HBR3_CAPABLE = true, 1090 .flags.bits.IS_TPS3_CAPABLE = true, 1091 .flags.bits.IS_TPS4_CAPABLE = true 1092 }; 1093 1094 static struct link_encoder *dcn31_link_encoder_create( 1095 const struct encoder_init_data *enc_init_data) 1096 { 1097 struct dcn20_link_encoder *enc20 = 1098 kzalloc(sizeof(struct dcn20_link_encoder), GFP_KERNEL); 1099 1100 if (!enc20) 1101 return NULL; 1102 1103 dcn31_link_encoder_construct(enc20, 1104 enc_init_data, 1105 &link_enc_feature, 1106 &link_enc_regs[enc_init_data->transmitter], 1107 &link_enc_aux_regs[enc_init_data->channel - 1], 1108 &link_enc_hpd_regs[enc_init_data->hpd_source], 1109 &le_shift, 1110 &le_mask); 1111 1112 return &enc20->enc10.base; 1113 } 1114 1115 /* Create a minimal link encoder object not associated with a particular 1116 * physical connector. 1117 * resource_funcs.link_enc_create_minimal 1118 */ 1119 static struct link_encoder *dcn31_link_enc_create_minimal( 1120 struct dc_context *ctx, enum engine_id eng_id) 1121 { 1122 struct dcn20_link_encoder *enc20; 1123 1124 if ((eng_id - ENGINE_ID_DIGA) > ctx->dc->res_pool->res_cap->num_dig_link_enc) 1125 return NULL; 1126 1127 enc20 = kzalloc(sizeof(struct dcn20_link_encoder), GFP_KERNEL); 1128 if (!enc20) 1129 return NULL; 1130 1131 dcn31_link_encoder_construct_minimal( 1132 enc20, 1133 ctx, 1134 &link_enc_feature, 1135 &link_enc_regs[eng_id - ENGINE_ID_DIGA], 1136 eng_id); 1137 1138 return &enc20->enc10.base; 1139 } 1140 1141 static struct panel_cntl *dcn31_panel_cntl_create(const struct panel_cntl_init_data *init_data) 1142 { 1143 struct dcn31_panel_cntl *panel_cntl = 1144 kzalloc(sizeof(struct dcn31_panel_cntl), GFP_KERNEL); 1145 1146 if (!panel_cntl) 1147 return NULL; 1148 1149 dcn31_panel_cntl_construct(panel_cntl, init_data); 1150 1151 return &panel_cntl->base; 1152 } 1153 1154 static void read_dce_straps( 1155 struct dc_context *ctx, 1156 struct resource_straps *straps) 1157 { 1158 generic_reg_get(ctx, regDC_PINSTRAPS + BASE(regDC_PINSTRAPS_BASE_IDX), 1159 FN(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO), &straps->dc_pinstraps_audio); 1160 1161 } 1162 1163 static struct audio *dcn31_create_audio( 1164 struct dc_context *ctx, unsigned int inst) 1165 { 1166 return dce_audio_create(ctx, inst, 1167 &audio_regs[inst], &audio_shift, &audio_mask); 1168 } 1169 1170 static struct vpg *dcn31_vpg_create( 1171 struct dc_context *ctx, 1172 uint32_t inst) 1173 { 1174 struct dcn31_vpg *vpg31 = kzalloc(sizeof(struct dcn31_vpg), GFP_KERNEL); 1175 1176 if (!vpg31) 1177 return NULL; 1178 1179 vpg31_construct(vpg31, ctx, inst, 1180 &vpg_regs[inst], 1181 &vpg_shift, 1182 &vpg_mask); 1183 1184 return &vpg31->base; 1185 } 1186 1187 static struct afmt *dcn31_afmt_create( 1188 struct dc_context *ctx, 1189 uint32_t inst) 1190 { 1191 struct dcn31_afmt *afmt31 = kzalloc(sizeof(struct dcn31_afmt), GFP_KERNEL); 1192 1193 if (!afmt31) 1194 return NULL; 1195 1196 afmt31_construct(afmt31, ctx, inst, 1197 &afmt_regs[inst], 1198 &afmt_shift, 1199 &afmt_mask); 1200 1201 // Light sleep by default, no need to power down here 1202 1203 return &afmt31->base; 1204 } 1205 1206 static struct apg *dcn31_apg_create( 1207 struct dc_context *ctx, 1208 uint32_t inst) 1209 { 1210 struct dcn31_apg *apg31 = kzalloc(sizeof(struct dcn31_apg), GFP_KERNEL); 1211 1212 if (!apg31) 1213 return NULL; 1214 1215 apg31_construct(apg31, ctx, inst, 1216 &apg_regs[inst], 1217 &apg_shift, 1218 &apg_mask); 1219 1220 return &apg31->base; 1221 } 1222 1223 static struct stream_encoder *dcn31_stream_encoder_create( 1224 enum engine_id eng_id, 1225 struct dc_context *ctx) 1226 { 1227 struct dcn10_stream_encoder *enc1; 1228 struct vpg *vpg; 1229 struct afmt *afmt; 1230 int vpg_inst; 1231 int afmt_inst; 1232 1233 /* Mapping of VPG, AFMT, DME register blocks to DIO block instance */ 1234 if (eng_id <= ENGINE_ID_DIGF) { 1235 vpg_inst = eng_id; 1236 afmt_inst = eng_id; 1237 } else 1238 return NULL; 1239 1240 enc1 = kzalloc(sizeof(struct dcn10_stream_encoder), GFP_KERNEL); 1241 vpg = dcn31_vpg_create(ctx, vpg_inst); 1242 afmt = dcn31_afmt_create(ctx, afmt_inst); 1243 1244 if (!enc1 || !vpg || !afmt) { 1245 kfree(enc1); 1246 kfree(vpg); 1247 kfree(afmt); 1248 return NULL; 1249 } 1250 1251 if (ctx->asic_id.chip_family == FAMILY_YELLOW_CARP && 1252 ctx->asic_id.hw_internal_rev == YELLOW_CARP_B0) { 1253 if ((eng_id == ENGINE_ID_DIGC) || (eng_id == ENGINE_ID_DIGD)) 1254 eng_id = eng_id + 3; // For B0 only. C->F, D->G. 1255 } 1256 1257 dcn30_dio_stream_encoder_construct(enc1, ctx, ctx->dc_bios, 1258 eng_id, vpg, afmt, 1259 &stream_enc_regs[eng_id], 1260 &se_shift, &se_mask); 1261 1262 return &enc1->base; 1263 } 1264 1265 static struct hpo_dp_stream_encoder *dcn31_hpo_dp_stream_encoder_create( 1266 enum engine_id eng_id, 1267 struct dc_context *ctx) 1268 { 1269 struct dcn31_hpo_dp_stream_encoder *hpo_dp_enc31; 1270 struct vpg *vpg; 1271 struct apg *apg; 1272 uint32_t hpo_dp_inst; 1273 uint32_t vpg_inst; 1274 uint32_t apg_inst; 1275 1276 ASSERT((eng_id >= ENGINE_ID_HPO_DP_0) && (eng_id <= ENGINE_ID_HPO_DP_3)); 1277 hpo_dp_inst = eng_id - ENGINE_ID_HPO_DP_0; 1278 1279 /* Mapping of VPG register blocks to HPO DP block instance: 1280 * VPG[6] -> HPO_DP[0] 1281 * VPG[7] -> HPO_DP[1] 1282 * VPG[8] -> HPO_DP[2] 1283 * VPG[9] -> HPO_DP[3] 1284 */ 1285 vpg_inst = hpo_dp_inst + 6; 1286 1287 /* Mapping of APG register blocks to HPO DP block instance: 1288 * APG[0] -> HPO_DP[0] 1289 * APG[1] -> HPO_DP[1] 1290 * APG[2] -> HPO_DP[2] 1291 * APG[3] -> HPO_DP[3] 1292 */ 1293 apg_inst = hpo_dp_inst; 1294 1295 /* allocate HPO stream encoder and create VPG sub-block */ 1296 hpo_dp_enc31 = kzalloc(sizeof(struct dcn31_hpo_dp_stream_encoder), GFP_KERNEL); 1297 vpg = dcn31_vpg_create(ctx, vpg_inst); 1298 apg = dcn31_apg_create(ctx, apg_inst); 1299 1300 if (!hpo_dp_enc31 || !vpg || !apg) { 1301 kfree(hpo_dp_enc31); 1302 kfree(vpg); 1303 kfree(apg); 1304 return NULL; 1305 } 1306 1307 dcn31_hpo_dp_stream_encoder_construct(hpo_dp_enc31, ctx, ctx->dc_bios, 1308 hpo_dp_inst, eng_id, vpg, apg, 1309 &hpo_dp_stream_enc_regs[hpo_dp_inst], 1310 &hpo_dp_se_shift, &hpo_dp_se_mask); 1311 1312 return &hpo_dp_enc31->base; 1313 } 1314 1315 static struct hpo_dp_link_encoder *dcn31_hpo_dp_link_encoder_create( 1316 uint8_t inst, 1317 struct dc_context *ctx) 1318 { 1319 struct dcn31_hpo_dp_link_encoder *hpo_dp_enc31; 1320 1321 /* allocate HPO link encoder */ 1322 hpo_dp_enc31 = kzalloc(sizeof(struct dcn31_hpo_dp_link_encoder), GFP_KERNEL); 1323 1324 hpo_dp_link_encoder31_construct(hpo_dp_enc31, ctx, inst, 1325 &hpo_dp_link_enc_regs[inst], 1326 &hpo_dp_le_shift, &hpo_dp_le_mask); 1327 1328 return &hpo_dp_enc31->base; 1329 } 1330 1331 static struct dce_hwseq *dcn31_hwseq_create( 1332 struct dc_context *ctx) 1333 { 1334 struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_KERNEL); 1335 1336 if (hws) { 1337 hws->ctx = ctx; 1338 hws->regs = &hwseq_reg; 1339 hws->shifts = &hwseq_shift; 1340 hws->masks = &hwseq_mask; 1341 /* DCN3.1 FPGA Workaround 1342 * Need to enable HPO DP Stream Encoder before setting OTG master enable. 1343 * To do so, move calling function enable_stream_timing to only be done AFTER calling 1344 * function core_link_enable_stream 1345 */ 1346 if (IS_FPGA_MAXIMUS_DC(ctx->dce_environment)) 1347 hws->wa.dp_hpo_and_otg_sequence = true; 1348 } 1349 return hws; 1350 } 1351 static const struct resource_create_funcs res_create_funcs = { 1352 .read_dce_straps = read_dce_straps, 1353 .create_audio = dcn31_create_audio, 1354 .create_stream_encoder = dcn31_stream_encoder_create, 1355 .create_hpo_dp_stream_encoder = dcn31_hpo_dp_stream_encoder_create, 1356 .create_hpo_dp_link_encoder = dcn31_hpo_dp_link_encoder_create, 1357 .create_hwseq = dcn31_hwseq_create, 1358 }; 1359 1360 static const struct resource_create_funcs res_create_maximus_funcs = { 1361 .read_dce_straps = NULL, 1362 .create_audio = NULL, 1363 .create_stream_encoder = NULL, 1364 .create_hpo_dp_stream_encoder = dcn31_hpo_dp_stream_encoder_create, 1365 .create_hpo_dp_link_encoder = dcn31_hpo_dp_link_encoder_create, 1366 .create_hwseq = dcn31_hwseq_create, 1367 }; 1368 1369 static void dcn31_resource_destruct(struct dcn31_resource_pool *pool) 1370 { 1371 unsigned int i; 1372 1373 for (i = 0; i < pool->base.stream_enc_count; i++) { 1374 if (pool->base.stream_enc[i] != NULL) { 1375 if (pool->base.stream_enc[i]->vpg != NULL) { 1376 kfree(DCN30_VPG_FROM_VPG(pool->base.stream_enc[i]->vpg)); 1377 pool->base.stream_enc[i]->vpg = NULL; 1378 } 1379 if (pool->base.stream_enc[i]->afmt != NULL) { 1380 kfree(DCN30_AFMT_FROM_AFMT(pool->base.stream_enc[i]->afmt)); 1381 pool->base.stream_enc[i]->afmt = NULL; 1382 } 1383 kfree(DCN10STRENC_FROM_STRENC(pool->base.stream_enc[i])); 1384 pool->base.stream_enc[i] = NULL; 1385 } 1386 } 1387 1388 for (i = 0; i < pool->base.hpo_dp_stream_enc_count; i++) { 1389 if (pool->base.hpo_dp_stream_enc[i] != NULL) { 1390 if (pool->base.hpo_dp_stream_enc[i]->vpg != NULL) { 1391 kfree(DCN30_VPG_FROM_VPG(pool->base.hpo_dp_stream_enc[i]->vpg)); 1392 pool->base.hpo_dp_stream_enc[i]->vpg = NULL; 1393 } 1394 if (pool->base.hpo_dp_stream_enc[i]->apg != NULL) { 1395 kfree(DCN31_APG_FROM_APG(pool->base.hpo_dp_stream_enc[i]->apg)); 1396 pool->base.hpo_dp_stream_enc[i]->apg = NULL; 1397 } 1398 kfree(DCN3_1_HPO_DP_STREAM_ENC_FROM_HPO_STREAM_ENC(pool->base.hpo_dp_stream_enc[i])); 1399 pool->base.hpo_dp_stream_enc[i] = NULL; 1400 } 1401 } 1402 1403 for (i = 0; i < pool->base.hpo_dp_link_enc_count; i++) { 1404 if (pool->base.hpo_dp_link_enc[i] != NULL) { 1405 kfree(DCN3_1_HPO_DP_LINK_ENC_FROM_HPO_LINK_ENC(pool->base.hpo_dp_link_enc[i])); 1406 pool->base.hpo_dp_link_enc[i] = NULL; 1407 } 1408 } 1409 1410 for (i = 0; i < pool->base.res_cap->num_dsc; i++) { 1411 if (pool->base.dscs[i] != NULL) 1412 dcn20_dsc_destroy(&pool->base.dscs[i]); 1413 } 1414 1415 if (pool->base.mpc != NULL) { 1416 kfree(TO_DCN20_MPC(pool->base.mpc)); 1417 pool->base.mpc = NULL; 1418 } 1419 if (pool->base.hubbub != NULL) { 1420 kfree(pool->base.hubbub); 1421 pool->base.hubbub = NULL; 1422 } 1423 for (i = 0; i < pool->base.pipe_count; i++) { 1424 if (pool->base.dpps[i] != NULL) 1425 dcn31_dpp_destroy(&pool->base.dpps[i]); 1426 1427 if (pool->base.ipps[i] != NULL) 1428 pool->base.ipps[i]->funcs->ipp_destroy(&pool->base.ipps[i]); 1429 1430 if (pool->base.hubps[i] != NULL) { 1431 kfree(TO_DCN20_HUBP(pool->base.hubps[i])); 1432 pool->base.hubps[i] = NULL; 1433 } 1434 1435 if (pool->base.irqs != NULL) { 1436 dal_irq_service_destroy(&pool->base.irqs); 1437 } 1438 } 1439 1440 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { 1441 if (pool->base.engines[i] != NULL) 1442 dce110_engine_destroy(&pool->base.engines[i]); 1443 if (pool->base.hw_i2cs[i] != NULL) { 1444 kfree(pool->base.hw_i2cs[i]); 1445 pool->base.hw_i2cs[i] = NULL; 1446 } 1447 if (pool->base.sw_i2cs[i] != NULL) { 1448 kfree(pool->base.sw_i2cs[i]); 1449 pool->base.sw_i2cs[i] = NULL; 1450 } 1451 } 1452 1453 for (i = 0; i < pool->base.res_cap->num_opp; i++) { 1454 if (pool->base.opps[i] != NULL) 1455 pool->base.opps[i]->funcs->opp_destroy(&pool->base.opps[i]); 1456 } 1457 1458 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { 1459 if (pool->base.timing_generators[i] != NULL) { 1460 kfree(DCN10TG_FROM_TG(pool->base.timing_generators[i])); 1461 pool->base.timing_generators[i] = NULL; 1462 } 1463 } 1464 1465 for (i = 0; i < pool->base.res_cap->num_dwb; i++) { 1466 if (pool->base.dwbc[i] != NULL) { 1467 kfree(TO_DCN30_DWBC(pool->base.dwbc[i])); 1468 pool->base.dwbc[i] = NULL; 1469 } 1470 if (pool->base.mcif_wb[i] != NULL) { 1471 kfree(TO_DCN30_MMHUBBUB(pool->base.mcif_wb[i])); 1472 pool->base.mcif_wb[i] = NULL; 1473 } 1474 } 1475 1476 for (i = 0; i < pool->base.audio_count; i++) { 1477 if (pool->base.audios[i]) 1478 dce_aud_destroy(&pool->base.audios[i]); 1479 } 1480 1481 for (i = 0; i < pool->base.clk_src_count; i++) { 1482 if (pool->base.clock_sources[i] != NULL) { 1483 dcn20_clock_source_destroy(&pool->base.clock_sources[i]); 1484 pool->base.clock_sources[i] = NULL; 1485 } 1486 } 1487 1488 for (i = 0; i < pool->base.res_cap->num_mpc_3dlut; i++) { 1489 if (pool->base.mpc_lut[i] != NULL) { 1490 dc_3dlut_func_release(pool->base.mpc_lut[i]); 1491 pool->base.mpc_lut[i] = NULL; 1492 } 1493 if (pool->base.mpc_shaper[i] != NULL) { 1494 dc_transfer_func_release(pool->base.mpc_shaper[i]); 1495 pool->base.mpc_shaper[i] = NULL; 1496 } 1497 } 1498 1499 if (pool->base.dp_clock_source != NULL) { 1500 dcn20_clock_source_destroy(&pool->base.dp_clock_source); 1501 pool->base.dp_clock_source = NULL; 1502 } 1503 1504 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { 1505 if (pool->base.multiple_abms[i] != NULL) 1506 dce_abm_destroy(&pool->base.multiple_abms[i]); 1507 } 1508 1509 if (pool->base.psr != NULL) 1510 dmub_psr_destroy(&pool->base.psr); 1511 1512 if (pool->base.dccg != NULL) 1513 dcn_dccg_destroy(&pool->base.dccg); 1514 } 1515 1516 static struct hubp *dcn31_hubp_create( 1517 struct dc_context *ctx, 1518 uint32_t inst) 1519 { 1520 struct dcn20_hubp *hubp2 = 1521 kzalloc(sizeof(struct dcn20_hubp), GFP_KERNEL); 1522 1523 if (!hubp2) 1524 return NULL; 1525 1526 if (hubp31_construct(hubp2, ctx, inst, 1527 &hubp_regs[inst], &hubp_shift, &hubp_mask)) 1528 return &hubp2->base; 1529 1530 BREAK_TO_DEBUGGER(); 1531 kfree(hubp2); 1532 return NULL; 1533 } 1534 1535 static bool dcn31_dwbc_create(struct dc_context *ctx, struct resource_pool *pool) 1536 { 1537 int i; 1538 uint32_t pipe_count = pool->res_cap->num_dwb; 1539 1540 for (i = 0; i < pipe_count; i++) { 1541 struct dcn30_dwbc *dwbc30 = kzalloc(sizeof(struct dcn30_dwbc), 1542 GFP_KERNEL); 1543 1544 if (!dwbc30) { 1545 dm_error("DC: failed to create dwbc30!\n"); 1546 return false; 1547 } 1548 1549 dcn30_dwbc_construct(dwbc30, ctx, 1550 &dwbc30_regs[i], 1551 &dwbc30_shift, 1552 &dwbc30_mask, 1553 i); 1554 1555 pool->dwbc[i] = &dwbc30->base; 1556 } 1557 return true; 1558 } 1559 1560 static bool dcn31_mmhubbub_create(struct dc_context *ctx, struct resource_pool *pool) 1561 { 1562 int i; 1563 uint32_t pipe_count = pool->res_cap->num_dwb; 1564 1565 for (i = 0; i < pipe_count; i++) { 1566 struct dcn30_mmhubbub *mcif_wb30 = kzalloc(sizeof(struct dcn30_mmhubbub), 1567 GFP_KERNEL); 1568 1569 if (!mcif_wb30) { 1570 dm_error("DC: failed to create mcif_wb30!\n"); 1571 return false; 1572 } 1573 1574 dcn30_mmhubbub_construct(mcif_wb30, ctx, 1575 &mcif_wb30_regs[i], 1576 &mcif_wb30_shift, 1577 &mcif_wb30_mask, 1578 i); 1579 1580 pool->mcif_wb[i] = &mcif_wb30->base; 1581 } 1582 return true; 1583 } 1584 1585 static struct display_stream_compressor *dcn31_dsc_create( 1586 struct dc_context *ctx, uint32_t inst) 1587 { 1588 struct dcn20_dsc *dsc = 1589 kzalloc(sizeof(struct dcn20_dsc), GFP_KERNEL); 1590 1591 if (!dsc) { 1592 BREAK_TO_DEBUGGER(); 1593 return NULL; 1594 } 1595 1596 dsc2_construct(dsc, ctx, inst, &dsc_regs[inst], &dsc_shift, &dsc_mask); 1597 return &dsc->base; 1598 } 1599 1600 static void dcn31_destroy_resource_pool(struct resource_pool **pool) 1601 { 1602 struct dcn31_resource_pool *dcn31_pool = TO_DCN31_RES_POOL(*pool); 1603 1604 dcn31_resource_destruct(dcn31_pool); 1605 kfree(dcn31_pool); 1606 *pool = NULL; 1607 } 1608 1609 static struct clock_source *dcn31_clock_source_create( 1610 struct dc_context *ctx, 1611 struct dc_bios *bios, 1612 enum clock_source_id id, 1613 const struct dce110_clk_src_regs *regs, 1614 bool dp_clk_src) 1615 { 1616 struct dce110_clk_src *clk_src = 1617 kzalloc(sizeof(struct dce110_clk_src), GFP_KERNEL); 1618 1619 if (!clk_src) 1620 return NULL; 1621 1622 if (dcn3_clk_src_construct(clk_src, ctx, bios, id, 1623 regs, &cs_shift, &cs_mask)) { 1624 clk_src->base.dp_clk_src = dp_clk_src; 1625 return &clk_src->base; 1626 } 1627 1628 BREAK_TO_DEBUGGER(); 1629 return NULL; 1630 } 1631 1632 static bool is_dual_plane(enum surface_pixel_format format) 1633 { 1634 return format >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN || format == SURFACE_PIXEL_FORMAT_GRPH_RGBE_ALPHA; 1635 } 1636 1637 int dcn31_populate_dml_pipes_from_context( 1638 struct dc *dc, struct dc_state *context, 1639 display_e2e_pipe_params_st *pipes, 1640 bool fast_validate) 1641 { 1642 int i, pipe_cnt; 1643 struct resource_context *res_ctx = &context->res_ctx; 1644 struct pipe_ctx *pipe; 1645 bool upscaled = false; 1646 1647 DC_FP_START(); 1648 dcn20_populate_dml_pipes_from_context(dc, context, pipes, fast_validate); 1649 DC_FP_END(); 1650 1651 for (i = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) { 1652 struct dc_crtc_timing *timing; 1653 1654 if (!res_ctx->pipe_ctx[i].stream) 1655 continue; 1656 pipe = &res_ctx->pipe_ctx[i]; 1657 timing = &pipe->stream->timing; 1658 1659 if (pipe->plane_state && 1660 (pipe->plane_state->src_rect.height < pipe->plane_state->dst_rect.height || 1661 pipe->plane_state->src_rect.width < pipe->plane_state->dst_rect.width)) 1662 upscaled = true; 1663 1664 /* 1665 * Immediate flip can be set dynamically after enabling the plane. 1666 * We need to require support for immediate flip or underflow can be 1667 * intermittently experienced depending on peak b/w requirements. 1668 */ 1669 pipes[pipe_cnt].pipe.src.immediate_flip = true; 1670 pipes[pipe_cnt].pipe.src.unbounded_req_mode = false; 1671 pipes[pipe_cnt].pipe.src.gpuvm = true; 1672 pipes[pipe_cnt].pipe.src.dcc_fraction_of_zs_req_luma = 0; 1673 pipes[pipe_cnt].pipe.src.dcc_fraction_of_zs_req_chroma = 0; 1674 pipes[pipe_cnt].pipe.dest.vfront_porch = timing->v_front_porch; 1675 pipes[pipe_cnt].pipe.src.dcc_rate = 3; 1676 pipes[pipe_cnt].dout.dsc_input_bpc = 0; 1677 1678 if (dc->debug.dml_hostvm_override == DML_HOSTVM_NO_OVERRIDE) 1679 pipes[pipe_cnt].pipe.src.hostvm = dc->res_pool->hubbub->riommu_active; 1680 else if (dc->debug.dml_hostvm_override == DML_HOSTVM_OVERRIDE_FALSE) 1681 pipes[pipe_cnt].pipe.src.hostvm = false; 1682 else if (dc->debug.dml_hostvm_override == DML_HOSTVM_OVERRIDE_TRUE) 1683 pipes[pipe_cnt].pipe.src.hostvm = true; 1684 1685 if (pipes[pipe_cnt].dout.dsc_enable) { 1686 switch (timing->display_color_depth) { 1687 case COLOR_DEPTH_888: 1688 pipes[pipe_cnt].dout.dsc_input_bpc = 8; 1689 break; 1690 case COLOR_DEPTH_101010: 1691 pipes[pipe_cnt].dout.dsc_input_bpc = 10; 1692 break; 1693 case COLOR_DEPTH_121212: 1694 pipes[pipe_cnt].dout.dsc_input_bpc = 12; 1695 break; 1696 default: 1697 ASSERT(0); 1698 break; 1699 } 1700 } 1701 1702 pipe_cnt++; 1703 } 1704 context->bw_ctx.dml.ip.det_buffer_size_kbytes = DCN3_1_DEFAULT_DET_SIZE; 1705 dc->config.enable_4to1MPC = false; 1706 if (pipe_cnt == 1 && pipe->plane_state && !dc->debug.disable_z9_mpc) { 1707 if (is_dual_plane(pipe->plane_state->format) 1708 && pipe->plane_state->src_rect.width <= 1920 && pipe->plane_state->src_rect.height <= 1080) { 1709 dc->config.enable_4to1MPC = true; 1710 } else if (!is_dual_plane(pipe->plane_state->format) && pipe->plane_state->src_rect.width <= 5120) { 1711 /* Limit to 5k max to avoid forced pipe split when there is not enough detile for swath */ 1712 context->bw_ctx.dml.ip.det_buffer_size_kbytes = 192; 1713 pipes[0].pipe.src.unbounded_req_mode = true; 1714 } 1715 } else if (context->stream_count >= dc->debug.crb_alloc_policy_min_disp_count 1716 && dc->debug.crb_alloc_policy > DET_SIZE_DEFAULT) { 1717 context->bw_ctx.dml.ip.det_buffer_size_kbytes = dc->debug.crb_alloc_policy * 64; 1718 } else if (context->stream_count >= 3 && upscaled) { 1719 context->bw_ctx.dml.ip.det_buffer_size_kbytes = 192; 1720 } 1721 1722 return pipe_cnt; 1723 } 1724 1725 void dcn31_update_soc_for_wm_a(struct dc *dc, struct dc_state *context) 1726 { 1727 if (dc->clk_mgr->bw_params->wm_table.entries[WM_A].valid) { 1728 context->bw_ctx.dml.soc.dram_clock_change_latency_us = dc->clk_mgr->bw_params->wm_table.entries[WM_A].pstate_latency_us; 1729 context->bw_ctx.dml.soc.sr_enter_plus_exit_time_us = dc->clk_mgr->bw_params->wm_table.entries[WM_A].sr_enter_plus_exit_time_us; 1730 context->bw_ctx.dml.soc.sr_exit_time_us = dc->clk_mgr->bw_params->wm_table.entries[WM_A].sr_exit_time_us; 1731 } 1732 } 1733 1734 void dcn31_calculate_wm_and_dlg( 1735 struct dc *dc, struct dc_state *context, 1736 display_e2e_pipe_params_st *pipes, 1737 int pipe_cnt, 1738 int vlevel) 1739 { 1740 DC_FP_START(); 1741 dcn31_calculate_wm_and_dlg_fp(dc, context, pipes, pipe_cnt, vlevel); 1742 DC_FP_END(); 1743 } 1744 1745 void 1746 dcn31_populate_dml_writeback_from_context(struct dc *dc, 1747 struct resource_context *res_ctx, 1748 display_e2e_pipe_params_st *pipes) 1749 { 1750 DC_FP_START(); 1751 dcn30_populate_dml_writeback_from_context(dc, res_ctx, pipes); 1752 DC_FP_END(); 1753 } 1754 1755 void 1756 dcn31_set_mcif_arb_params(struct dc *dc, 1757 struct dc_state *context, 1758 display_e2e_pipe_params_st *pipes, 1759 int pipe_cnt) 1760 { 1761 DC_FP_START(); 1762 dcn30_set_mcif_arb_params(dc, context, pipes, pipe_cnt); 1763 DC_FP_END(); 1764 } 1765 1766 bool dcn31_validate_bandwidth(struct dc *dc, 1767 struct dc_state *context, 1768 bool fast_validate) 1769 { 1770 bool out = false; 1771 1772 BW_VAL_TRACE_SETUP(); 1773 1774 int vlevel = 0; 1775 int pipe_cnt = 0; 1776 display_e2e_pipe_params_st *pipes = kzalloc(dc->res_pool->pipe_count * sizeof(display_e2e_pipe_params_st), GFP_KERNEL); 1777 DC_LOGGER_INIT(dc->ctx->logger); 1778 1779 BW_VAL_TRACE_COUNT(); 1780 1781 DC_FP_START(); 1782 out = dcn30_internal_validate_bw(dc, context, pipes, &pipe_cnt, &vlevel, fast_validate); 1783 DC_FP_END(); 1784 1785 // Disable fast_validate to set min dcfclk in alculate_wm_and_dlg 1786 if (pipe_cnt == 0) 1787 fast_validate = false; 1788 1789 if (!out) 1790 goto validate_fail; 1791 1792 BW_VAL_TRACE_END_VOLTAGE_LEVEL(); 1793 1794 if (fast_validate) { 1795 BW_VAL_TRACE_SKIP(fast); 1796 goto validate_out; 1797 } 1798 1799 dc->res_pool->funcs->calculate_wm_and_dlg(dc, context, pipes, pipe_cnt, vlevel); 1800 1801 BW_VAL_TRACE_END_WATERMARKS(); 1802 1803 goto validate_out; 1804 1805 validate_fail: 1806 DC_LOG_WARNING("Mode Validation Warning: %s failed validation.\n", 1807 dml_get_status_message(context->bw_ctx.dml.vba.ValidationStatus[context->bw_ctx.dml.vba.soc.num_states])); 1808 1809 BW_VAL_TRACE_SKIP(fail); 1810 out = false; 1811 1812 validate_out: 1813 kfree(pipes); 1814 1815 BW_VAL_TRACE_FINISH(); 1816 1817 return out; 1818 } 1819 1820 static struct dc_cap_funcs cap_funcs = { 1821 .get_dcc_compression_cap = dcn20_get_dcc_compression_cap 1822 }; 1823 1824 static struct resource_funcs dcn31_res_pool_funcs = { 1825 .destroy = dcn31_destroy_resource_pool, 1826 .link_enc_create = dcn31_link_encoder_create, 1827 .link_enc_create_minimal = dcn31_link_enc_create_minimal, 1828 .link_encs_assign = link_enc_cfg_link_encs_assign, 1829 .link_enc_unassign = link_enc_cfg_link_enc_unassign, 1830 .panel_cntl_create = dcn31_panel_cntl_create, 1831 .validate_bandwidth = dcn31_validate_bandwidth, 1832 .calculate_wm_and_dlg = dcn31_calculate_wm_and_dlg, 1833 .update_soc_for_wm_a = dcn31_update_soc_for_wm_a, 1834 .populate_dml_pipes = dcn31_populate_dml_pipes_from_context, 1835 .acquire_idle_pipe_for_layer = dcn20_acquire_idle_pipe_for_layer, 1836 .add_stream_to_ctx = dcn30_add_stream_to_ctx, 1837 .add_dsc_to_stream_resource = dcn20_add_dsc_to_stream_resource, 1838 .remove_stream_from_ctx = dcn20_remove_stream_from_ctx, 1839 .populate_dml_writeback_from_context = dcn31_populate_dml_writeback_from_context, 1840 .set_mcif_arb_params = dcn31_set_mcif_arb_params, 1841 .find_first_free_match_stream_enc_for_link = dcn10_find_first_free_match_stream_enc_for_link, 1842 .acquire_post_bldn_3dlut = dcn30_acquire_post_bldn_3dlut, 1843 .release_post_bldn_3dlut = dcn30_release_post_bldn_3dlut, 1844 .update_bw_bounding_box = dcn31_update_bw_bounding_box, 1845 .patch_unknown_plane_state = dcn20_patch_unknown_plane_state, 1846 }; 1847 1848 static struct clock_source *dcn30_clock_source_create( 1849 struct dc_context *ctx, 1850 struct dc_bios *bios, 1851 enum clock_source_id id, 1852 const struct dce110_clk_src_regs *regs, 1853 bool dp_clk_src) 1854 { 1855 struct dce110_clk_src *clk_src = 1856 kzalloc(sizeof(struct dce110_clk_src), GFP_KERNEL); 1857 1858 if (!clk_src) 1859 return NULL; 1860 1861 if (dcn31_clk_src_construct(clk_src, ctx, bios, id, 1862 regs, &cs_shift, &cs_mask)) { 1863 clk_src->base.dp_clk_src = dp_clk_src; 1864 return &clk_src->base; 1865 } 1866 1867 BREAK_TO_DEBUGGER(); 1868 return NULL; 1869 } 1870 1871 static bool dcn31_resource_construct( 1872 uint8_t num_virtual_links, 1873 struct dc *dc, 1874 struct dcn31_resource_pool *pool) 1875 { 1876 int i; 1877 struct dc_context *ctx = dc->ctx; 1878 struct irq_service_init_data init_data; 1879 1880 DC_FP_START(); 1881 1882 ctx->dc_bios->regs = &bios_regs; 1883 1884 pool->base.res_cap = &res_cap_dcn31; 1885 1886 pool->base.funcs = &dcn31_res_pool_funcs; 1887 1888 /************************************************* 1889 * Resource + asic cap harcoding * 1890 *************************************************/ 1891 pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE; 1892 pool->base.pipe_count = pool->base.res_cap->num_timing_generator; 1893 pool->base.mpcc_count = pool->base.res_cap->num_timing_generator; 1894 dc->caps.max_downscale_ratio = 600; 1895 dc->caps.i2c_speed_in_khz = 100; 1896 dc->caps.i2c_speed_in_khz_hdcp = 5; /*1.4 w/a applied by default*/ 1897 dc->caps.max_cursor_size = 256; 1898 dc->caps.min_horizontal_blanking_period = 80; 1899 dc->caps.dmdata_alloc_size = 2048; 1900 1901 dc->caps.max_slave_planes = 2; 1902 dc->caps.max_slave_yuv_planes = 2; 1903 dc->caps.max_slave_rgb_planes = 2; 1904 dc->caps.post_blend_color_processing = true; 1905 dc->caps.force_dp_tps4_for_cp2520 = true; 1906 dc->caps.dp_hpo = true; 1907 dc->caps.hdmi_frl_pcon_support = true; 1908 dc->caps.edp_dsc_support = true; 1909 dc->caps.extended_aux_timeout_support = true; 1910 dc->caps.dmcub_support = true; 1911 dc->caps.is_apu = true; 1912 dc->caps.zstate_support = true; 1913 1914 /* Color pipeline capabilities */ 1915 dc->caps.color.dpp.dcn_arch = 1; 1916 dc->caps.color.dpp.input_lut_shared = 0; 1917 dc->caps.color.dpp.icsc = 1; 1918 dc->caps.color.dpp.dgam_ram = 0; // must use gamma_corr 1919 dc->caps.color.dpp.dgam_rom_caps.srgb = 1; 1920 dc->caps.color.dpp.dgam_rom_caps.bt2020 = 1; 1921 dc->caps.color.dpp.dgam_rom_caps.gamma2_2 = 1; 1922 dc->caps.color.dpp.dgam_rom_caps.pq = 1; 1923 dc->caps.color.dpp.dgam_rom_caps.hlg = 1; 1924 dc->caps.color.dpp.post_csc = 1; 1925 dc->caps.color.dpp.gamma_corr = 1; 1926 dc->caps.color.dpp.dgam_rom_for_yuv = 0; 1927 1928 dc->caps.color.dpp.hw_3d_lut = 1; 1929 dc->caps.color.dpp.ogam_ram = 1; 1930 // no OGAM ROM on DCN301 1931 dc->caps.color.dpp.ogam_rom_caps.srgb = 0; 1932 dc->caps.color.dpp.ogam_rom_caps.bt2020 = 0; 1933 dc->caps.color.dpp.ogam_rom_caps.gamma2_2 = 0; 1934 dc->caps.color.dpp.ogam_rom_caps.pq = 0; 1935 dc->caps.color.dpp.ogam_rom_caps.hlg = 0; 1936 dc->caps.color.dpp.ocsc = 0; 1937 1938 dc->caps.color.mpc.gamut_remap = 1; 1939 dc->caps.color.mpc.num_3dluts = pool->base.res_cap->num_mpc_3dlut; //2 1940 dc->caps.color.mpc.ogam_ram = 1; 1941 dc->caps.color.mpc.ogam_rom_caps.srgb = 0; 1942 dc->caps.color.mpc.ogam_rom_caps.bt2020 = 0; 1943 dc->caps.color.mpc.ogam_rom_caps.gamma2_2 = 0; 1944 dc->caps.color.mpc.ogam_rom_caps.pq = 0; 1945 dc->caps.color.mpc.ogam_rom_caps.hlg = 0; 1946 dc->caps.color.mpc.ocsc = 1; 1947 1948 /* Use pipe context based otg sync logic */ 1949 dc->config.use_pipe_ctx_sync_logic = true; 1950 1951 /* read VBIOS LTTPR caps */ 1952 { 1953 if (ctx->dc_bios->funcs->get_lttpr_caps) { 1954 enum bp_result bp_query_result; 1955 uint8_t is_vbios_lttpr_enable = 0; 1956 1957 bp_query_result = ctx->dc_bios->funcs->get_lttpr_caps(ctx->dc_bios, &is_vbios_lttpr_enable); 1958 dc->caps.vbios_lttpr_enable = (bp_query_result == BP_RESULT_OK) && !!is_vbios_lttpr_enable; 1959 } 1960 1961 /* interop bit is implicit */ 1962 { 1963 dc->caps.vbios_lttpr_aware = true; 1964 } 1965 } 1966 1967 if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV) 1968 dc->debug = debug_defaults_drv; 1969 else if (dc->ctx->dce_environment == DCE_ENV_FPGA_MAXIMUS) { 1970 dc->debug = debug_defaults_diags; 1971 } else 1972 dc->debug = debug_defaults_diags; 1973 // Init the vm_helper 1974 if (dc->vm_helper) 1975 vm_helper_init(dc->vm_helper, 16); 1976 1977 /************************************************* 1978 * Create resources * 1979 *************************************************/ 1980 1981 /* Clock Sources for Pixel Clock*/ 1982 pool->base.clock_sources[DCN31_CLK_SRC_PLL0] = 1983 dcn30_clock_source_create(ctx, ctx->dc_bios, 1984 CLOCK_SOURCE_COMBO_PHY_PLL0, 1985 &clk_src_regs[0], false); 1986 pool->base.clock_sources[DCN31_CLK_SRC_PLL1] = 1987 dcn30_clock_source_create(ctx, ctx->dc_bios, 1988 CLOCK_SOURCE_COMBO_PHY_PLL1, 1989 &clk_src_regs[1], false); 1990 /*move phypllx_pixclk_resync to dmub next*/ 1991 if (dc->ctx->asic_id.hw_internal_rev == YELLOW_CARP_B0) { 1992 pool->base.clock_sources[DCN31_CLK_SRC_PLL2] = 1993 dcn30_clock_source_create(ctx, ctx->dc_bios, 1994 CLOCK_SOURCE_COMBO_PHY_PLL2, 1995 &clk_src_regs_b0[2], false); 1996 pool->base.clock_sources[DCN31_CLK_SRC_PLL3] = 1997 dcn30_clock_source_create(ctx, ctx->dc_bios, 1998 CLOCK_SOURCE_COMBO_PHY_PLL3, 1999 &clk_src_regs_b0[3], false); 2000 } else { 2001 pool->base.clock_sources[DCN31_CLK_SRC_PLL2] = 2002 dcn30_clock_source_create(ctx, ctx->dc_bios, 2003 CLOCK_SOURCE_COMBO_PHY_PLL2, 2004 &clk_src_regs[2], false); 2005 pool->base.clock_sources[DCN31_CLK_SRC_PLL3] = 2006 dcn30_clock_source_create(ctx, ctx->dc_bios, 2007 CLOCK_SOURCE_COMBO_PHY_PLL3, 2008 &clk_src_regs[3], false); 2009 } 2010 2011 pool->base.clock_sources[DCN31_CLK_SRC_PLL4] = 2012 dcn30_clock_source_create(ctx, ctx->dc_bios, 2013 CLOCK_SOURCE_COMBO_PHY_PLL4, 2014 &clk_src_regs[4], false); 2015 2016 pool->base.clk_src_count = DCN30_CLK_SRC_TOTAL; 2017 2018 /* todo: not reuse phy_pll registers */ 2019 pool->base.dp_clock_source = 2020 dcn31_clock_source_create(ctx, ctx->dc_bios, 2021 CLOCK_SOURCE_ID_DP_DTO, 2022 &clk_src_regs[0], true); 2023 2024 for (i = 0; i < pool->base.clk_src_count; i++) { 2025 if (pool->base.clock_sources[i] == NULL) { 2026 dm_error("DC: failed to create clock sources!\n"); 2027 BREAK_TO_DEBUGGER(); 2028 goto create_fail; 2029 } 2030 } 2031 2032 /* TODO: DCCG */ 2033 pool->base.dccg = dccg31_create(ctx, &dccg_regs, &dccg_shift, &dccg_mask); 2034 if (pool->base.dccg == NULL) { 2035 dm_error("DC: failed to create dccg!\n"); 2036 BREAK_TO_DEBUGGER(); 2037 goto create_fail; 2038 } 2039 2040 /* TODO: IRQ */ 2041 init_data.ctx = dc->ctx; 2042 pool->base.irqs = dal_irq_service_dcn31_create(&init_data); 2043 if (!pool->base.irqs) 2044 goto create_fail; 2045 2046 /* HUBBUB */ 2047 pool->base.hubbub = dcn31_hubbub_create(ctx); 2048 if (pool->base.hubbub == NULL) { 2049 BREAK_TO_DEBUGGER(); 2050 dm_error("DC: failed to create hubbub!\n"); 2051 goto create_fail; 2052 } 2053 2054 /* HUBPs, DPPs, OPPs and TGs */ 2055 for (i = 0; i < pool->base.pipe_count; i++) { 2056 pool->base.hubps[i] = dcn31_hubp_create(ctx, i); 2057 if (pool->base.hubps[i] == NULL) { 2058 BREAK_TO_DEBUGGER(); 2059 dm_error( 2060 "DC: failed to create hubps!\n"); 2061 goto create_fail; 2062 } 2063 2064 pool->base.dpps[i] = dcn31_dpp_create(ctx, i); 2065 if (pool->base.dpps[i] == NULL) { 2066 BREAK_TO_DEBUGGER(); 2067 dm_error( 2068 "DC: failed to create dpps!\n"); 2069 goto create_fail; 2070 } 2071 } 2072 2073 for (i = 0; i < pool->base.res_cap->num_opp; i++) { 2074 pool->base.opps[i] = dcn31_opp_create(ctx, i); 2075 if (pool->base.opps[i] == NULL) { 2076 BREAK_TO_DEBUGGER(); 2077 dm_error( 2078 "DC: failed to create output pixel processor!\n"); 2079 goto create_fail; 2080 } 2081 } 2082 2083 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { 2084 pool->base.timing_generators[i] = dcn31_timing_generator_create( 2085 ctx, i); 2086 if (pool->base.timing_generators[i] == NULL) { 2087 BREAK_TO_DEBUGGER(); 2088 dm_error("DC: failed to create tg!\n"); 2089 goto create_fail; 2090 } 2091 } 2092 pool->base.timing_generator_count = i; 2093 2094 /* PSR */ 2095 pool->base.psr = dmub_psr_create(ctx); 2096 if (pool->base.psr == NULL) { 2097 dm_error("DC: failed to create psr obj!\n"); 2098 BREAK_TO_DEBUGGER(); 2099 goto create_fail; 2100 } 2101 2102 /* ABM */ 2103 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { 2104 pool->base.multiple_abms[i] = dmub_abm_create(ctx, 2105 &abm_regs[i], 2106 &abm_shift, 2107 &abm_mask); 2108 if (pool->base.multiple_abms[i] == NULL) { 2109 dm_error("DC: failed to create abm for pipe %d!\n", i); 2110 BREAK_TO_DEBUGGER(); 2111 goto create_fail; 2112 } 2113 } 2114 2115 /* MPC and DSC */ 2116 pool->base.mpc = dcn31_mpc_create(ctx, pool->base.mpcc_count, pool->base.res_cap->num_mpc_3dlut); 2117 if (pool->base.mpc == NULL) { 2118 BREAK_TO_DEBUGGER(); 2119 dm_error("DC: failed to create mpc!\n"); 2120 goto create_fail; 2121 } 2122 2123 for (i = 0; i < pool->base.res_cap->num_dsc; i++) { 2124 pool->base.dscs[i] = dcn31_dsc_create(ctx, i); 2125 if (pool->base.dscs[i] == NULL) { 2126 BREAK_TO_DEBUGGER(); 2127 dm_error("DC: failed to create display stream compressor %d!\n", i); 2128 goto create_fail; 2129 } 2130 } 2131 2132 /* DWB and MMHUBBUB */ 2133 if (!dcn31_dwbc_create(ctx, &pool->base)) { 2134 BREAK_TO_DEBUGGER(); 2135 dm_error("DC: failed to create dwbc!\n"); 2136 goto create_fail; 2137 } 2138 2139 if (!dcn31_mmhubbub_create(ctx, &pool->base)) { 2140 BREAK_TO_DEBUGGER(); 2141 dm_error("DC: failed to create mcif_wb!\n"); 2142 goto create_fail; 2143 } 2144 2145 /* AUX and I2C */ 2146 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { 2147 pool->base.engines[i] = dcn31_aux_engine_create(ctx, i); 2148 if (pool->base.engines[i] == NULL) { 2149 BREAK_TO_DEBUGGER(); 2150 dm_error( 2151 "DC:failed to create aux engine!!\n"); 2152 goto create_fail; 2153 } 2154 pool->base.hw_i2cs[i] = dcn31_i2c_hw_create(ctx, i); 2155 if (pool->base.hw_i2cs[i] == NULL) { 2156 BREAK_TO_DEBUGGER(); 2157 dm_error( 2158 "DC:failed to create hw i2c!!\n"); 2159 goto create_fail; 2160 } 2161 pool->base.sw_i2cs[i] = NULL; 2162 } 2163 2164 if (dc->ctx->asic_id.chip_family == FAMILY_YELLOW_CARP && 2165 dc->ctx->asic_id.hw_internal_rev == YELLOW_CARP_B0 && 2166 !dc->debug.dpia_debug.bits.disable_dpia) { 2167 /* YELLOW CARP B0 has 4 DPIA's */ 2168 pool->base.usb4_dpia_count = 4; 2169 } 2170 2171 /* Audio, Stream Encoders including HPO and virtual, MPC 3D LUTs */ 2172 if (!resource_construct(num_virtual_links, dc, &pool->base, 2173 (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment) ? 2174 &res_create_funcs : &res_create_maximus_funcs))) 2175 goto create_fail; 2176 2177 /* HW Sequencer and Plane caps */ 2178 dcn31_hw_sequencer_construct(dc); 2179 2180 dc->caps.max_planes = pool->base.pipe_count; 2181 2182 for (i = 0; i < dc->caps.max_planes; ++i) 2183 dc->caps.planes[i] = plane_cap; 2184 2185 dc->cap_funcs = cap_funcs; 2186 2187 dc->dcn_ip->max_num_dpp = dcn3_1_ip.max_num_dpp; 2188 2189 DC_FP_END(); 2190 2191 return true; 2192 2193 create_fail: 2194 2195 DC_FP_END(); 2196 dcn31_resource_destruct(pool); 2197 2198 return false; 2199 } 2200 2201 struct resource_pool *dcn31_create_resource_pool( 2202 const struct dc_init_data *init_data, 2203 struct dc *dc) 2204 { 2205 struct dcn31_resource_pool *pool = 2206 kzalloc(sizeof(struct dcn31_resource_pool), GFP_KERNEL); 2207 2208 if (!pool) 2209 return NULL; 2210 2211 if (dcn31_resource_construct(init_data->num_virtual_links, dc, pool)) 2212 return &pool->base; 2213 2214 BREAK_TO_DEBUGGER(); 2215 kfree(pool); 2216 return NULL; 2217 } 2218