1 /* 2 * Copyright 2012-15 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #include "dcn31_optc.h" 27 28 #include "dcn30/dcn30_optc.h" 29 #include "reg_helper.h" 30 #include "dc.h" 31 #include "dcn_calc_math.h" 32 33 #define REG(reg)\ 34 optc1->tg_regs->reg 35 36 #define CTX \ 37 optc1->base.ctx 38 39 #undef FN 40 #define FN(reg_name, field_name) \ 41 optc1->tg_shift->field_name, optc1->tg_mask->field_name 42 43 #define STATIC_SCREEN_EVENT_MASK_DRR_DOUBLE_BUFFER_UPDATE_EN 0x2000 /*bit 13*/ 44 static void optc31_set_odm_combine(struct timing_generator *optc, int *opp_id, int opp_cnt, 45 struct dc_crtc_timing *timing) 46 { 47 struct optc *optc1 = DCN10TG_FROM_TG(optc); 48 int mpcc_hactive = (timing->h_addressable + timing->h_border_left + timing->h_border_right) 49 / opp_cnt; 50 uint32_t memory_mask = 0; 51 int mem_count_per_opp = (mpcc_hactive + 2559) / 2560; 52 53 /* Assume less than 6 pipes */ 54 if (opp_cnt == 4) { 55 if (mem_count_per_opp == 1) 56 memory_mask = 0xf; 57 else { 58 ASSERT(mem_count_per_opp == 2); 59 memory_mask = 0xff; 60 } 61 } else if (mem_count_per_opp == 1) 62 memory_mask = 0x1 << (opp_id[0] * 2) | 0x1 << (opp_id[1] * 2); 63 else if (mem_count_per_opp == 2) 64 memory_mask = 0x3 << (opp_id[0] * 2) | 0x3 << (opp_id[1] * 2); 65 else if (mem_count_per_opp == 3) 66 memory_mask = 0x77; 67 else if (mem_count_per_opp == 4) 68 memory_mask = 0xff; 69 70 if (REG(OPTC_MEMORY_CONFIG)) 71 REG_SET(OPTC_MEMORY_CONFIG, 0, 72 OPTC_MEM_SEL, memory_mask); 73 74 if (opp_cnt == 2) { 75 REG_SET_3(OPTC_DATA_SOURCE_SELECT, 0, 76 OPTC_NUM_OF_INPUT_SEGMENT, 1, 77 OPTC_SEG0_SRC_SEL, opp_id[0], 78 OPTC_SEG1_SRC_SEL, opp_id[1]); 79 } else if (opp_cnt == 4) { 80 REG_SET_5(OPTC_DATA_SOURCE_SELECT, 0, 81 OPTC_NUM_OF_INPUT_SEGMENT, 3, 82 OPTC_SEG0_SRC_SEL, opp_id[0], 83 OPTC_SEG1_SRC_SEL, opp_id[1], 84 OPTC_SEG2_SRC_SEL, opp_id[2], 85 OPTC_SEG3_SRC_SEL, opp_id[3]); 86 } 87 88 REG_UPDATE(OPTC_WIDTH_CONTROL, 89 OPTC_SEGMENT_WIDTH, mpcc_hactive); 90 91 REG_SET(OTG_H_TIMING_CNTL, 0, OTG_H_TIMING_DIV_MODE, opp_cnt - 1); 92 optc1->opp_count = opp_cnt; 93 } 94 95 /* 96 * Enable CRTC - call ASIC Control Object to enable Timing generator. 97 */ 98 static bool optc31_enable_crtc(struct timing_generator *optc) 99 { 100 struct optc *optc1 = DCN10TG_FROM_TG(optc); 101 102 /* opp instance for OTG, 1 to 1 mapping and odm will adjust */ 103 REG_UPDATE(OPTC_DATA_SOURCE_SELECT, 104 OPTC_SEG0_SRC_SEL, optc->inst); 105 106 /* VTG enable first is for HW workaround */ 107 REG_UPDATE(CONTROL, 108 VTG0_ENABLE, 1); 109 110 REG_SEQ_START(); 111 112 /* Enable CRTC */ 113 REG_UPDATE_2(OTG_CONTROL, 114 OTG_DISABLE_POINT_CNTL, 2, 115 OTG_MASTER_EN, 1); 116 117 REG_SEQ_SUBMIT(); 118 REG_SEQ_WAIT_DONE(); 119 120 return true; 121 } 122 123 /* disable_crtc - call ASIC Control Object to disable Timing generator. */ 124 static bool optc31_disable_crtc(struct timing_generator *optc) 125 { 126 struct optc *optc1 = DCN10TG_FROM_TG(optc); 127 /* disable otg request until end of the first line 128 * in the vertical blank region 129 */ 130 REG_UPDATE(OTG_CONTROL, 131 OTG_MASTER_EN, 0); 132 133 REG_UPDATE(CONTROL, 134 VTG0_ENABLE, 0); 135 136 /* CRTC disabled, so disable clock. */ 137 REG_WAIT(OTG_CLOCK_CONTROL, 138 OTG_BUSY, 0, 139 1, 100000); 140 optc1_clear_optc_underflow(optc); 141 142 return true; 143 } 144 145 bool optc31_immediate_disable_crtc(struct timing_generator *optc) 146 { 147 struct optc *optc1 = DCN10TG_FROM_TG(optc); 148 149 REG_UPDATE_2(OTG_CONTROL, 150 OTG_DISABLE_POINT_CNTL, 0, 151 OTG_MASTER_EN, 0); 152 153 REG_UPDATE(CONTROL, 154 VTG0_ENABLE, 0); 155 156 /* CRTC disabled, so disable clock. */ 157 REG_WAIT(OTG_CLOCK_CONTROL, 158 OTG_BUSY, 0, 159 1, 100000); 160 161 /* clear the false state */ 162 optc1_clear_optc_underflow(optc); 163 164 return true; 165 } 166 167 void optc31_set_drr( 168 struct timing_generator *optc, 169 const struct drr_params *params) 170 { 171 struct optc *optc1 = DCN10TG_FROM_TG(optc); 172 173 if (params != NULL && 174 params->vertical_total_max > 0 && 175 params->vertical_total_min > 0) { 176 177 if (params->vertical_total_mid != 0) { 178 179 REG_SET(OTG_V_TOTAL_MID, 0, 180 OTG_V_TOTAL_MID, params->vertical_total_mid - 1); 181 182 REG_UPDATE_2(OTG_V_TOTAL_CONTROL, 183 OTG_VTOTAL_MID_REPLACING_MAX_EN, 1, 184 OTG_VTOTAL_MID_FRAME_NUM, 185 (uint8_t)params->vertical_total_mid_frame_num); 186 187 } 188 189 optc->funcs->set_vtotal_min_max(optc, params->vertical_total_min - 1, params->vertical_total_max - 1); 190 191 /* 192 * MIN_MASK_EN is gone and MASK is now always enabled. 193 * 194 * To get it to it work with manual trigger we need to make sure 195 * we program the correct bit. 196 */ 197 REG_UPDATE_4(OTG_V_TOTAL_CONTROL, 198 OTG_V_TOTAL_MIN_SEL, 1, 199 OTG_V_TOTAL_MAX_SEL, 1, 200 OTG_FORCE_LOCK_ON_EVENT, 0, 201 OTG_SET_V_TOTAL_MIN_MASK, (1 << 1)); /* TRIGA */ 202 203 // Setup manual flow control for EOF via TRIG_A 204 optc->funcs->setup_manual_trigger(optc); 205 } else { 206 REG_UPDATE_4(OTG_V_TOTAL_CONTROL, 207 OTG_SET_V_TOTAL_MIN_MASK, 0, 208 OTG_V_TOTAL_MIN_SEL, 0, 209 OTG_V_TOTAL_MAX_SEL, 0, 210 OTG_FORCE_LOCK_ON_EVENT, 0); 211 212 optc->funcs->set_vtotal_min_max(optc, 0, 0); 213 } 214 } 215 216 void optc3_init_odm(struct timing_generator *optc) 217 { 218 struct optc *optc1 = DCN10TG_FROM_TG(optc); 219 220 REG_SET_5(OPTC_DATA_SOURCE_SELECT, 0, 221 OPTC_NUM_OF_INPUT_SEGMENT, 0, 222 OPTC_SEG0_SRC_SEL, optc->inst, 223 OPTC_SEG1_SRC_SEL, 0xf, 224 OPTC_SEG2_SRC_SEL, 0xf, 225 OPTC_SEG3_SRC_SEL, 0xf 226 ); 227 228 REG_SET(OTG_H_TIMING_CNTL, 0, 229 OTG_H_TIMING_DIV_MODE, 0); 230 231 REG_SET(OPTC_MEMORY_CONFIG, 0, 232 OPTC_MEM_SEL, 0); 233 optc1->opp_count = 1; 234 } 235 void optc31_set_static_screen_control( 236 struct timing_generator *optc, 237 uint32_t event_triggers, 238 uint32_t num_frames) 239 { 240 struct optc *optc1 = DCN10TG_FROM_TG(optc); 241 uint32_t framecount; 242 uint32_t events; 243 244 if (num_frames > 0xFF) 245 num_frames = 0xFF; 246 REG_GET_2(OTG_STATIC_SCREEN_CONTROL, 247 OTG_STATIC_SCREEN_EVENT_MASK, &events, 248 OTG_STATIC_SCREEN_FRAME_COUNT, &framecount); 249 250 if (events == event_triggers && num_frames == framecount) 251 return; 252 if ((event_triggers & STATIC_SCREEN_EVENT_MASK_DRR_DOUBLE_BUFFER_UPDATE_EN) 253 != 0) 254 event_triggers = event_triggers & 255 ~STATIC_SCREEN_EVENT_MASK_DRR_DOUBLE_BUFFER_UPDATE_EN; 256 257 REG_UPDATE_2(OTG_STATIC_SCREEN_CONTROL, 258 OTG_STATIC_SCREEN_EVENT_MASK, event_triggers, 259 OTG_STATIC_SCREEN_FRAME_COUNT, num_frames); 260 } 261 262 static struct timing_generator_funcs dcn31_tg_funcs = { 263 .validate_timing = optc1_validate_timing, 264 .program_timing = optc1_program_timing, 265 .setup_vertical_interrupt0 = optc1_setup_vertical_interrupt0, 266 .setup_vertical_interrupt1 = optc1_setup_vertical_interrupt1, 267 .setup_vertical_interrupt2 = optc1_setup_vertical_interrupt2, 268 .program_global_sync = optc1_program_global_sync, 269 .enable_crtc = optc31_enable_crtc, 270 .disable_crtc = optc31_disable_crtc, 271 .immediate_disable_crtc = optc31_immediate_disable_crtc, 272 /* used by enable_timing_synchronization. Not need for FPGA */ 273 .is_counter_moving = optc1_is_counter_moving, 274 .get_position = optc1_get_position, 275 .get_frame_count = optc1_get_vblank_counter, 276 .get_scanoutpos = optc1_get_crtc_scanoutpos, 277 .get_otg_active_size = optc1_get_otg_active_size, 278 .set_early_control = optc1_set_early_control, 279 /* used by enable_timing_synchronization. Not need for FPGA */ 280 .wait_for_state = optc1_wait_for_state, 281 .set_blank_color = optc3_program_blank_color, 282 .did_triggered_reset_occur = optc1_did_triggered_reset_occur, 283 .triplebuffer_lock = optc3_triplebuffer_lock, 284 .triplebuffer_unlock = optc2_triplebuffer_unlock, 285 .enable_reset_trigger = optc1_enable_reset_trigger, 286 .enable_crtc_reset = optc1_enable_crtc_reset, 287 .disable_reset_trigger = optc1_disable_reset_trigger, 288 .lock = optc3_lock, 289 .unlock = optc1_unlock, 290 .lock_doublebuffer_enable = optc3_lock_doublebuffer_enable, 291 .lock_doublebuffer_disable = optc3_lock_doublebuffer_disable, 292 .enable_optc_clock = optc1_enable_optc_clock, 293 .set_drr = optc31_set_drr, 294 .get_last_used_drr_vtotal = optc2_get_last_used_drr_vtotal, 295 .set_vtotal_min_max = optc1_set_vtotal_min_max, 296 .set_static_screen_control = optc31_set_static_screen_control, 297 .program_stereo = optc1_program_stereo, 298 .is_stereo_left_eye = optc1_is_stereo_left_eye, 299 .tg_init = optc3_tg_init, 300 .is_tg_enabled = optc1_is_tg_enabled, 301 .is_optc_underflow_occurred = optc1_is_optc_underflow_occurred, 302 .clear_optc_underflow = optc1_clear_optc_underflow, 303 .setup_global_swap_lock = NULL, 304 .get_crc = optc1_get_crc, 305 .configure_crc = optc2_configure_crc, 306 .set_dsc_config = optc3_set_dsc_config, 307 .get_dsc_status = optc2_get_dsc_status, 308 .set_dwb_source = NULL, 309 .set_odm_bypass = optc3_set_odm_bypass, 310 .set_odm_combine = optc31_set_odm_combine, 311 .get_optc_source = optc2_get_optc_source, 312 .set_out_mux = optc3_set_out_mux, 313 .set_drr_trigger_window = optc3_set_drr_trigger_window, 314 .set_vtotal_change_limit = optc3_set_vtotal_change_limit, 315 .set_gsl = optc2_set_gsl, 316 .set_gsl_source_select = optc2_set_gsl_source_select, 317 .set_vtg_params = optc1_set_vtg_params, 318 .program_manual_trigger = optc2_program_manual_trigger, 319 .setup_manual_trigger = optc2_setup_manual_trigger, 320 .get_hw_timing = optc1_get_hw_timing, 321 .init_odm = optc3_init_odm, 322 }; 323 324 void dcn31_timing_generator_init(struct optc *optc1) 325 { 326 optc1->base.funcs = &dcn31_tg_funcs; 327 328 optc1->max_h_total = optc1->tg_mask->OTG_H_TOTAL + 1; 329 optc1->max_v_total = optc1->tg_mask->OTG_V_TOTAL + 1; 330 331 optc1->min_h_blank = 32; 332 optc1->min_v_blank = 3; 333 optc1->min_v_blank_interlace = 5; 334 optc1->min_h_sync_width = 4; 335 optc1->min_v_sync_width = 1; 336 } 337 338