1 /* 2 * Copyright 2012-15 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #include "dcn31_optc.h" 27 28 #include "dcn30/dcn30_optc.h" 29 #include "reg_helper.h" 30 #include "dc.h" 31 #include "dcn_calc_math.h" 32 33 #define REG(reg)\ 34 optc1->tg_regs->reg 35 36 #define CTX \ 37 optc1->base.ctx 38 39 #undef FN 40 #define FN(reg_name, field_name) \ 41 optc1->tg_shift->field_name, optc1->tg_mask->field_name 42 43 static void optc31_set_odm_combine(struct timing_generator *optc, int *opp_id, int opp_cnt, 44 struct dc_crtc_timing *timing) 45 { 46 struct optc *optc1 = DCN10TG_FROM_TG(optc); 47 int mpcc_hactive = (timing->h_addressable + timing->h_border_left + timing->h_border_right) 48 / opp_cnt; 49 uint32_t memory_mask = 0; 50 int mem_count_per_opp = (mpcc_hactive + 2559) / 2560; 51 52 /* Assume less than 6 pipes */ 53 if (opp_cnt == 4) { 54 if (mem_count_per_opp == 1) 55 memory_mask = 0xf; 56 else { 57 ASSERT(mem_count_per_opp == 2); 58 memory_mask = 0xff; 59 } 60 } else if (mem_count_per_opp == 1) 61 memory_mask = 0x1 << (opp_id[0] * 2) | 0x1 << (opp_id[1] * 2); 62 else if (mem_count_per_opp == 2) 63 memory_mask = 0x3 << (opp_id[0] * 2) | 0x3 << (opp_id[1] * 2); 64 else if (mem_count_per_opp == 3) 65 memory_mask = 0x77; 66 else if (mem_count_per_opp == 4) 67 memory_mask = 0xff; 68 69 if (REG(OPTC_MEMORY_CONFIG)) 70 REG_SET(OPTC_MEMORY_CONFIG, 0, 71 OPTC_MEM_SEL, memory_mask); 72 73 if (opp_cnt == 2) { 74 REG_SET_3(OPTC_DATA_SOURCE_SELECT, 0, 75 OPTC_NUM_OF_INPUT_SEGMENT, 1, 76 OPTC_SEG0_SRC_SEL, opp_id[0], 77 OPTC_SEG1_SRC_SEL, opp_id[1]); 78 } else if (opp_cnt == 4) { 79 REG_SET_5(OPTC_DATA_SOURCE_SELECT, 0, 80 OPTC_NUM_OF_INPUT_SEGMENT, 3, 81 OPTC_SEG0_SRC_SEL, opp_id[0], 82 OPTC_SEG1_SRC_SEL, opp_id[1], 83 OPTC_SEG2_SRC_SEL, opp_id[2], 84 OPTC_SEG3_SRC_SEL, opp_id[3]); 85 } 86 87 REG_UPDATE(OPTC_WIDTH_CONTROL, 88 OPTC_SEGMENT_WIDTH, mpcc_hactive); 89 90 REG_SET(OTG_H_TIMING_CNTL, 0, OTG_H_TIMING_DIV_MODE, opp_cnt - 1); 91 optc1->opp_count = opp_cnt; 92 } 93 94 /* 95 * Enable CRTC - call ASIC Control Object to enable Timing generator. 96 */ 97 static bool optc31_enable_crtc(struct timing_generator *optc) 98 { 99 struct optc *optc1 = DCN10TG_FROM_TG(optc); 100 101 /* opp instance for OTG, 1 to 1 mapping and odm will adjust */ 102 REG_UPDATE(OPTC_DATA_SOURCE_SELECT, 103 OPTC_SEG0_SRC_SEL, optc->inst); 104 105 /* VTG enable first is for HW workaround */ 106 REG_UPDATE(CONTROL, 107 VTG0_ENABLE, 1); 108 109 REG_SEQ_START(); 110 111 /* Enable CRTC */ 112 REG_UPDATE_2(OTG_CONTROL, 113 OTG_DISABLE_POINT_CNTL, 2, 114 OTG_MASTER_EN, 1); 115 116 REG_SEQ_SUBMIT(); 117 REG_SEQ_WAIT_DONE(); 118 119 return true; 120 } 121 122 /* disable_crtc - call ASIC Control Object to disable Timing generator. */ 123 static bool optc31_disable_crtc(struct timing_generator *optc) 124 { 125 struct optc *optc1 = DCN10TG_FROM_TG(optc); 126 /* disable otg request until end of the first line 127 * in the vertical blank region 128 */ 129 REG_UPDATE(OTG_CONTROL, 130 OTG_MASTER_EN, 0); 131 132 REG_UPDATE(CONTROL, 133 VTG0_ENABLE, 0); 134 135 /* CRTC disabled, so disable clock. */ 136 REG_WAIT(OTG_CLOCK_CONTROL, 137 OTG_BUSY, 0, 138 1, 100000); 139 optc1_clear_optc_underflow(optc); 140 141 return true; 142 } 143 144 static bool optc31_immediate_disable_crtc(struct timing_generator *optc) 145 { 146 struct optc *optc1 = DCN10TG_FROM_TG(optc); 147 148 REG_UPDATE_2(OTG_CONTROL, 149 OTG_DISABLE_POINT_CNTL, 0, 150 OTG_MASTER_EN, 0); 151 152 REG_UPDATE(CONTROL, 153 VTG0_ENABLE, 0); 154 155 /* CRTC disabled, so disable clock. */ 156 REG_WAIT(OTG_CLOCK_CONTROL, 157 OTG_BUSY, 0, 158 1, 100000); 159 160 /* clear the false state */ 161 optc1_clear_optc_underflow(optc); 162 163 return true; 164 } 165 166 void optc31_set_drr( 167 struct timing_generator *optc, 168 const struct drr_params *params) 169 { 170 struct optc *optc1 = DCN10TG_FROM_TG(optc); 171 172 if (params != NULL && 173 params->vertical_total_max > 0 && 174 params->vertical_total_min > 0) { 175 176 if (params->vertical_total_mid != 0) { 177 178 REG_SET(OTG_V_TOTAL_MID, 0, 179 OTG_V_TOTAL_MID, params->vertical_total_mid - 1); 180 181 REG_UPDATE_2(OTG_V_TOTAL_CONTROL, 182 OTG_VTOTAL_MID_REPLACING_MAX_EN, 1, 183 OTG_VTOTAL_MID_FRAME_NUM, 184 (uint8_t)params->vertical_total_mid_frame_num); 185 186 } 187 188 optc->funcs->set_vtotal_min_max(optc, params->vertical_total_min - 1, params->vertical_total_max - 1); 189 190 /* 191 * MIN_MASK_EN is gone and MASK is now always enabled. 192 * 193 * To get it to it work with manual trigger we need to make sure 194 * we program the correct bit. 195 */ 196 REG_UPDATE_4(OTG_V_TOTAL_CONTROL, 197 OTG_V_TOTAL_MIN_SEL, 1, 198 OTG_V_TOTAL_MAX_SEL, 1, 199 OTG_FORCE_LOCK_ON_EVENT, 0, 200 OTG_SET_V_TOTAL_MIN_MASK, (1 << 1)); /* TRIGA */ 201 202 // Setup manual flow control for EOF via TRIG_A 203 optc->funcs->setup_manual_trigger(optc); 204 205 } else { 206 REG_UPDATE_4(OTG_V_TOTAL_CONTROL, 207 OTG_SET_V_TOTAL_MIN_MASK, 0, 208 OTG_V_TOTAL_MIN_SEL, 0, 209 OTG_V_TOTAL_MAX_SEL, 0, 210 OTG_FORCE_LOCK_ON_EVENT, 0); 211 212 optc->funcs->set_vtotal_min_max(optc, 0, 0); 213 } 214 } 215 216 void optc3_init_odm(struct timing_generator *optc) 217 { 218 struct optc *optc1 = DCN10TG_FROM_TG(optc); 219 220 REG_SET_5(OPTC_DATA_SOURCE_SELECT, 0, 221 OPTC_NUM_OF_INPUT_SEGMENT, 0, 222 OPTC_SEG0_SRC_SEL, optc->inst, 223 OPTC_SEG1_SRC_SEL, 0xf, 224 OPTC_SEG2_SRC_SEL, 0xf, 225 OPTC_SEG3_SRC_SEL, 0xf 226 ); 227 228 REG_SET(OTG_H_TIMING_CNTL, 0, 229 OTG_H_TIMING_DIV_MODE, 0); 230 231 REG_SET(OPTC_MEMORY_CONFIG, 0, 232 OPTC_MEM_SEL, 0); 233 optc1->opp_count = 1; 234 } 235 236 static struct timing_generator_funcs dcn31_tg_funcs = { 237 .validate_timing = optc1_validate_timing, 238 .program_timing = optc1_program_timing, 239 .setup_vertical_interrupt0 = optc1_setup_vertical_interrupt0, 240 .setup_vertical_interrupt1 = optc1_setup_vertical_interrupt1, 241 .setup_vertical_interrupt2 = optc1_setup_vertical_interrupt2, 242 .program_global_sync = optc1_program_global_sync, 243 .enable_crtc = optc31_enable_crtc, 244 .disable_crtc = optc31_disable_crtc, 245 .immediate_disable_crtc = optc31_immediate_disable_crtc, 246 /* used by enable_timing_synchronization. Not need for FPGA */ 247 .is_counter_moving = optc1_is_counter_moving, 248 .get_position = optc1_get_position, 249 .get_frame_count = optc1_get_vblank_counter, 250 .get_scanoutpos = optc1_get_crtc_scanoutpos, 251 .get_otg_active_size = optc1_get_otg_active_size, 252 .set_early_control = optc1_set_early_control, 253 /* used by enable_timing_synchronization. Not need for FPGA */ 254 .wait_for_state = optc1_wait_for_state, 255 .set_blank_color = optc3_program_blank_color, 256 .did_triggered_reset_occur = optc1_did_triggered_reset_occur, 257 .triplebuffer_lock = optc3_triplebuffer_lock, 258 .triplebuffer_unlock = optc2_triplebuffer_unlock, 259 .enable_reset_trigger = optc1_enable_reset_trigger, 260 .enable_crtc_reset = optc1_enable_crtc_reset, 261 .disable_reset_trigger = optc1_disable_reset_trigger, 262 .lock = optc3_lock, 263 .is_locked = optc1_is_locked, 264 .unlock = optc1_unlock, 265 .lock_doublebuffer_enable = optc3_lock_doublebuffer_enable, 266 .lock_doublebuffer_disable = optc3_lock_doublebuffer_disable, 267 .enable_optc_clock = optc1_enable_optc_clock, 268 .set_drr = optc31_set_drr, 269 .set_vtotal_min_max = optc1_set_vtotal_min_max, 270 .set_static_screen_control = optc1_set_static_screen_control, 271 .program_stereo = optc1_program_stereo, 272 .is_stereo_left_eye = optc1_is_stereo_left_eye, 273 .tg_init = optc3_tg_init, 274 .is_tg_enabled = optc1_is_tg_enabled, 275 .is_optc_underflow_occurred = optc1_is_optc_underflow_occurred, 276 .clear_optc_underflow = optc1_clear_optc_underflow, 277 .setup_global_swap_lock = NULL, 278 .get_crc = optc1_get_crc, 279 .configure_crc = optc2_configure_crc, 280 .set_dsc_config = optc3_set_dsc_config, 281 .get_dsc_status = optc2_get_dsc_status, 282 .set_dwb_source = NULL, 283 .set_odm_bypass = optc3_set_odm_bypass, 284 .set_odm_combine = optc31_set_odm_combine, 285 .get_optc_source = optc2_get_optc_source, 286 .set_out_mux = optc3_set_out_mux, 287 .set_drr_trigger_window = optc3_set_drr_trigger_window, 288 .set_vtotal_change_limit = optc3_set_vtotal_change_limit, 289 .set_gsl = optc2_set_gsl, 290 .set_gsl_source_select = optc2_set_gsl_source_select, 291 .set_vtg_params = optc1_set_vtg_params, 292 .program_manual_trigger = optc2_program_manual_trigger, 293 .setup_manual_trigger = optc2_setup_manual_trigger, 294 .get_hw_timing = optc1_get_hw_timing, 295 .init_odm = optc3_init_odm, 296 }; 297 298 void dcn31_timing_generator_init(struct optc *optc1) 299 { 300 optc1->base.funcs = &dcn31_tg_funcs; 301 302 optc1->max_h_total = optc1->tg_mask->OTG_H_TOTAL + 1; 303 optc1->max_v_total = optc1->tg_mask->OTG_V_TOTAL + 1; 304 305 optc1->min_h_blank = 32; 306 optc1->min_v_blank = 3; 307 optc1->min_v_blank_interlace = 5; 308 optc1->min_h_sync_width = 4; 309 optc1->min_v_sync_width = 1; 310 } 311 312