1 /*
2  * Copyright 2012-15 Advanced Micro Devices, Inc.
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice shall be included in
12  * all copies or substantial portions of the Software.
13  *
14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20  * OTHER DEALINGS IN THE SOFTWARE.
21  *
22  * Authors: AMD
23  *
24  */
25 
26 #include "dcn31_optc.h"
27 
28 #include "dcn30/dcn30_optc.h"
29 #include "reg_helper.h"
30 #include "dc.h"
31 #include "dcn_calc_math.h"
32 
33 #define REG(reg)\
34 	optc1->tg_regs->reg
35 
36 #define CTX \
37 	optc1->base.ctx
38 
39 #undef FN
40 #define FN(reg_name, field_name) \
41 	optc1->tg_shift->field_name, optc1->tg_mask->field_name
42 
43 static void optc31_set_odm_combine(struct timing_generator *optc, int *opp_id, int opp_cnt,
44 		struct dc_crtc_timing *timing)
45 {
46 	struct optc *optc1 = DCN10TG_FROM_TG(optc);
47 	int mpcc_hactive = (timing->h_addressable + timing->h_border_left + timing->h_border_right)
48 			/ opp_cnt;
49 	uint32_t memory_mask = 0;
50 	int mem_count_per_opp = (mpcc_hactive + 2559) / 2560;
51 
52 	/* Assume less than 6 pipes */
53 	if (opp_cnt == 4) {
54 		if (mem_count_per_opp == 1)
55 			memory_mask = 0xf;
56 		else {
57 			ASSERT(mem_count_per_opp == 2);
58 			memory_mask = 0xff;
59 		}
60 	} else if (mem_count_per_opp == 1)
61 		memory_mask = 0x1 << (opp_id[0] * 2) | 0x1 << (opp_id[1] * 2);
62 	else if (mem_count_per_opp == 2)
63 		memory_mask = 0x3 << (opp_id[0] * 2) | 0x3 << (opp_id[1] * 2);
64 	else if (mem_count_per_opp == 3)
65 		memory_mask = 0x77;
66 	else if (mem_count_per_opp == 4)
67 		memory_mask = 0xff;
68 
69 	if (REG(OPTC_MEMORY_CONFIG))
70 		REG_SET(OPTC_MEMORY_CONFIG, 0,
71 			OPTC_MEM_SEL, memory_mask);
72 
73 	if (opp_cnt == 2) {
74 		REG_SET_3(OPTC_DATA_SOURCE_SELECT, 0,
75 				OPTC_NUM_OF_INPUT_SEGMENT, 1,
76 				OPTC_SEG0_SRC_SEL, opp_id[0],
77 				OPTC_SEG1_SRC_SEL, opp_id[1]);
78 	} else if (opp_cnt == 4) {
79 		REG_SET_5(OPTC_DATA_SOURCE_SELECT, 0,
80 				OPTC_NUM_OF_INPUT_SEGMENT, 3,
81 				OPTC_SEG0_SRC_SEL, opp_id[0],
82 				OPTC_SEG1_SRC_SEL, opp_id[1],
83 				OPTC_SEG2_SRC_SEL, opp_id[2],
84 				OPTC_SEG3_SRC_SEL, opp_id[3]);
85 	}
86 
87 	REG_UPDATE(OPTC_WIDTH_CONTROL,
88 			OPTC_SEGMENT_WIDTH, mpcc_hactive);
89 
90 	REG_SET(OTG_H_TIMING_CNTL, 0, OTG_H_TIMING_DIV_MODE, opp_cnt - 1);
91 	optc1->opp_count = opp_cnt;
92 }
93 
94 /**
95  * Enable CRTC
96  * Enable CRTC - call ASIC Control Object to enable Timing generator.
97  */
98 static bool optc31_enable_crtc(struct timing_generator *optc)
99 {
100 	struct optc *optc1 = DCN10TG_FROM_TG(optc);
101 
102 	/* opp instance for OTG, 1 to 1 mapping and odm will adjust */
103 	REG_UPDATE(OPTC_DATA_SOURCE_SELECT,
104 			OPTC_SEG0_SRC_SEL, optc->inst);
105 
106 	/* VTG enable first is for HW workaround */
107 	REG_UPDATE(CONTROL,
108 			VTG0_ENABLE, 1);
109 
110 	REG_SEQ_START();
111 
112 	/* Enable CRTC */
113 	REG_UPDATE_2(OTG_CONTROL,
114 			OTG_DISABLE_POINT_CNTL, 2,
115 			OTG_MASTER_EN, 1);
116 
117 	REG_SEQ_SUBMIT();
118 	REG_SEQ_WAIT_DONE();
119 
120 	return true;
121 }
122 
123 /* disable_crtc - call ASIC Control Object to disable Timing generator. */
124 static bool optc31_disable_crtc(struct timing_generator *optc)
125 {
126 	struct optc *optc1 = DCN10TG_FROM_TG(optc);
127 
128 	/* disable otg request until end of the first line
129 	 * in the vertical blank region
130 	 */
131 	REG_UPDATE(OTG_CONTROL,
132 			OTG_MASTER_EN, 0);
133 
134 	REG_UPDATE(CONTROL,
135 			VTG0_ENABLE, 0);
136 
137 	/* CRTC disabled, so disable  clock. */
138 	REG_WAIT(OTG_CLOCK_CONTROL,
139 			OTG_BUSY, 0,
140 			1, 100000);
141 
142 	return true;
143 }
144 
145 static bool optc31_immediate_disable_crtc(struct timing_generator *optc)
146 {
147 	struct optc *optc1 = DCN10TG_FROM_TG(optc);
148 
149 	REG_UPDATE_2(OTG_CONTROL,
150 			OTG_DISABLE_POINT_CNTL, 0,
151 			OTG_MASTER_EN, 0);
152 
153 	REG_UPDATE(CONTROL,
154 			VTG0_ENABLE, 0);
155 
156 	/* CRTC disabled, so disable  clock. */
157 	REG_WAIT(OTG_CLOCK_CONTROL,
158 			OTG_BUSY, 0,
159 			1, 100000);
160 
161 	return true;
162 }
163 
164 void optc31_set_drr(
165 	struct timing_generator *optc,
166 	const struct drr_params *params)
167 {
168 	struct optc *optc1 = DCN10TG_FROM_TG(optc);
169 
170 	if (params != NULL &&
171 		params->vertical_total_max > 0 &&
172 		params->vertical_total_min > 0) {
173 
174 		if (params->vertical_total_mid != 0) {
175 
176 			REG_SET(OTG_V_TOTAL_MID, 0,
177 				OTG_V_TOTAL_MID, params->vertical_total_mid - 1);
178 
179 			REG_UPDATE_2(OTG_V_TOTAL_CONTROL,
180 					OTG_VTOTAL_MID_REPLACING_MAX_EN, 1,
181 					OTG_VTOTAL_MID_FRAME_NUM,
182 					(uint8_t)params->vertical_total_mid_frame_num);
183 
184 		}
185 
186 		optc->funcs->set_vtotal_min_max(optc, params->vertical_total_min - 1, params->vertical_total_max - 1);
187 
188 		/*
189 		 * MIN_MASK_EN is gone and MASK is now always enabled.
190 		 *
191 		 * To get it to it work with manual trigger we need to make sure
192 		 * we program the correct bit.
193 		 */
194 		REG_UPDATE_4(OTG_V_TOTAL_CONTROL,
195 				OTG_V_TOTAL_MIN_SEL, 1,
196 				OTG_V_TOTAL_MAX_SEL, 1,
197 				OTG_FORCE_LOCK_ON_EVENT, 0,
198 				OTG_SET_V_TOTAL_MIN_MASK, (1 << 1)); /* TRIGA */
199 
200 		// Setup manual flow control for EOF via TRIG_A
201 		optc->funcs->setup_manual_trigger(optc);
202 
203 	} else {
204 		REG_UPDATE_4(OTG_V_TOTAL_CONTROL,
205 				OTG_SET_V_TOTAL_MIN_MASK, 0,
206 				OTG_V_TOTAL_MIN_SEL, 0,
207 				OTG_V_TOTAL_MAX_SEL, 0,
208 				OTG_FORCE_LOCK_ON_EVENT, 0);
209 
210 		optc->funcs->set_vtotal_min_max(optc, 0, 0);
211 	}
212 }
213 
214 static struct timing_generator_funcs dcn31_tg_funcs = {
215 		.validate_timing = optc1_validate_timing,
216 		.program_timing = optc1_program_timing,
217 		.setup_vertical_interrupt0 = optc1_setup_vertical_interrupt0,
218 		.setup_vertical_interrupt1 = optc1_setup_vertical_interrupt1,
219 		.setup_vertical_interrupt2 = optc1_setup_vertical_interrupt2,
220 		.program_global_sync = optc1_program_global_sync,
221 		.enable_crtc = optc31_enable_crtc,
222 		.disable_crtc = optc31_disable_crtc,
223 		.immediate_disable_crtc = optc31_immediate_disable_crtc,
224 		/* used by enable_timing_synchronization. Not need for FPGA */
225 		.is_counter_moving = optc1_is_counter_moving,
226 		.get_position = optc1_get_position,
227 		.get_frame_count = optc1_get_vblank_counter,
228 		.get_scanoutpos = optc1_get_crtc_scanoutpos,
229 		.get_otg_active_size = optc1_get_otg_active_size,
230 		.set_early_control = optc1_set_early_control,
231 		/* used by enable_timing_synchronization. Not need for FPGA */
232 		.wait_for_state = optc1_wait_for_state,
233 		.set_blank_color = optc3_program_blank_color,
234 		.did_triggered_reset_occur = optc1_did_triggered_reset_occur,
235 		.triplebuffer_lock = optc3_triplebuffer_lock,
236 		.triplebuffer_unlock = optc2_triplebuffer_unlock,
237 		.enable_reset_trigger = optc1_enable_reset_trigger,
238 		.enable_crtc_reset = optc1_enable_crtc_reset,
239 		.disable_reset_trigger = optc1_disable_reset_trigger,
240 		.lock = optc3_lock,
241 		.is_locked = optc1_is_locked,
242 		.unlock = optc1_unlock,
243 		.lock_doublebuffer_enable = optc3_lock_doublebuffer_enable,
244 		.lock_doublebuffer_disable = optc3_lock_doublebuffer_disable,
245 		.enable_optc_clock = optc1_enable_optc_clock,
246 		.set_drr = optc31_set_drr,
247 		.set_vtotal_min_max = optc1_set_vtotal_min_max,
248 		.set_static_screen_control = optc1_set_static_screen_control,
249 		.program_stereo = optc1_program_stereo,
250 		.is_stereo_left_eye = optc1_is_stereo_left_eye,
251 		.tg_init = optc3_tg_init,
252 		.is_tg_enabled = optc1_is_tg_enabled,
253 		.is_optc_underflow_occurred = optc1_is_optc_underflow_occurred,
254 		.clear_optc_underflow = optc1_clear_optc_underflow,
255 		.setup_global_swap_lock = NULL,
256 		.get_crc = optc1_get_crc,
257 		.configure_crc = optc2_configure_crc,
258 		.set_dsc_config = optc3_set_dsc_config,
259 		.get_dsc_status = optc2_get_dsc_status,
260 		.set_dwb_source = NULL,
261 		.set_odm_bypass = optc3_set_odm_bypass,
262 		.set_odm_combine = optc31_set_odm_combine,
263 		.get_optc_source = optc2_get_optc_source,
264 		.set_out_mux = optc3_set_out_mux,
265 		.set_drr_trigger_window = optc3_set_drr_trigger_window,
266 		.set_vtotal_change_limit = optc3_set_vtotal_change_limit,
267 		.set_gsl = optc2_set_gsl,
268 		.set_gsl_source_select = optc2_set_gsl_source_select,
269 		.set_vtg_params = optc1_set_vtg_params,
270 		.program_manual_trigger = optc2_program_manual_trigger,
271 		.setup_manual_trigger = optc2_setup_manual_trigger,
272 		.get_hw_timing = optc1_get_hw_timing,
273 };
274 
275 void dcn31_timing_generator_init(struct optc *optc1)
276 {
277 	optc1->base.funcs = &dcn31_tg_funcs;
278 
279 	optc1->max_h_total = optc1->tg_mask->OTG_H_TOTAL + 1;
280 	optc1->max_v_total = optc1->tg_mask->OTG_V_TOTAL + 1;
281 
282 	optc1->min_h_blank = 32;
283 	optc1->min_v_blank = 3;
284 	optc1->min_v_blank_interlace = 5;
285 	optc1->min_h_sync_width = 4;
286 	optc1->min_v_sync_width = 1;
287 }
288 
289